1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Texas Instruments' J721E DDRSS driver
4 *
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
6 */
7
8 #include <common.h>
9 #include <clk.h>
10 #include <dm.h>
11 #include <hang.h>
12 #include <log.h>
13 #include <ram.h>
14 #include <asm/io.h>
15 #include <power-domain.h>
16 #include <wait_bit.h>
17 #include <dm/device_compat.h>
18
19 #include "lpddr4_obj_if.h"
20 #include "lpddr4_if.h"
21 #include "lpddr4_structs_if.h"
22 #include "lpddr4_ctl_regs.h"
23
24 #define SRAM_MAX 512
25
26 #define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS 0x80
27 #define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS 0xc0
28
29 struct j721e_ddrss_desc {
30 struct udevice *dev;
31 void __iomem *ddrss_ss_cfg;
32 void __iomem *ddrss_ctrl_mmr;
33 struct power_domain ddrcfg_pwrdmn;
34 struct power_domain ddrdata_pwrdmn;
35 struct clk ddr_clk;
36 struct clk osc_clk;
37 u32 ddr_freq1;
38 u32 ddr_freq2;
39 u32 ddr_fhs_cnt;
40 };
41
42 static LPDDR4_OBJ *driverdt;
43 static lpddr4_config config;
44 static lpddr4_privatedata pd;
45
46 static struct j721e_ddrss_desc *ddrss;
47
48 #define TH_MACRO_EXP(fld, str) (fld##str)
49
50 #define TH_FLD_MASK(fld) TH_MACRO_EXP(fld, _MASK)
51 #define TH_FLD_SHIFT(fld) TH_MACRO_EXP(fld, _SHIFT)
52 #define TH_FLD_WIDTH(fld) TH_MACRO_EXP(fld, _WIDTH)
53 #define TH_FLD_WOCLR(fld) TH_MACRO_EXP(fld, _WOCLR)
54 #define TH_FLD_WOSET(fld) TH_MACRO_EXP(fld, _WOSET)
55
56 #define str(s) #s
57 #define xstr(s) str(s)
58
59 #define CTL_SHIFT 11
60 #define PHY_SHIFT 11
61 #define PI_SHIFT 10
62
63 #define TH_OFFSET_FROM_REG(REG, SHIFT, offset) do {\
64 char *i, *pstr= xstr(REG); offset = 0;\
65 for (i = &pstr[SHIFT]; *i != '\0'; ++i) {\
66 offset = offset * 10 + (*i - '0'); }\
67 } while (0)
68
j721e_lpddr4_ack_freq_upd_req(void)69 static void j721e_lpddr4_ack_freq_upd_req(void)
70 {
71 unsigned int req_type, counter;
72
73 debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
74
75 for (counter = 0; counter < ddrss->ddr_fhs_cnt; counter++) {
76 if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
77 CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
78 true, 10000, false)) {
79 printf("Timeout during frequency handshake\n");
80 hang();
81 }
82
83 req_type = readl(ddrss->ddrss_ctrl_mmr +
84 CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS) & 0x03;
85
86 debug("%s: received freq change req: req type = %d, req no. = %d \n",
87 __func__, req_type, counter);
88
89 if (req_type == 1)
90 clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
91 else if (req_type == 2)
92 clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq2);
93 else if (req_type == 0)
94 /* Put DDR pll in bypass mode */
95 clk_set_rate(&ddrss->ddr_clk,
96 clk_get_rate(&ddrss->osc_clk));
97 else
98 printf("%s: Invalid freq request type\n", __func__);
99
100 writel(0x1, ddrss->ddrss_ctrl_mmr +
101 CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS);
102 if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
103 CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
104 false, 10, false)) {
105 printf("Timeout during frequency handshake\n");
106 hang();
107 }
108 writel(0x0, ddrss->ddrss_ctrl_mmr +
109 CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS);
110 }
111 }
112
j721e_lpddr4_info_handler(const lpddr4_privatedata * pd,lpddr4_infotype infotype)113 static void j721e_lpddr4_info_handler(const lpddr4_privatedata * pd,
114 lpddr4_infotype infotype)
115 {
116 if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE) {
117 j721e_lpddr4_ack_freq_upd_req();
118 }
119 }
120
j721e_ddrss_power_on(struct j721e_ddrss_desc * ddrss)121 static int j721e_ddrss_power_on(struct j721e_ddrss_desc *ddrss)
122 {
123 int ret;
124
125 debug("%s(ddrss=%p)\n", __func__, ddrss);
126
127 ret = power_domain_on(&ddrss->ddrcfg_pwrdmn);
128 if (ret) {
129 dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
130 return ret;
131 }
132
133 ret = power_domain_on(&ddrss->ddrdata_pwrdmn);
134 if (ret) {
135 dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
136 return ret;
137 }
138
139 return 0;
140 }
141
j721e_ddrss_ofdata_to_priv(struct udevice * dev)142 static int j721e_ddrss_ofdata_to_priv(struct udevice *dev)
143 {
144 struct j721e_ddrss_desc *ddrss = dev_get_priv(dev);
145 phys_addr_t reg;
146 int ret;
147
148 debug("%s(dev=%p)\n", __func__, dev);
149
150 reg = dev_read_addr_name(dev, "cfg");
151 if (reg == FDT_ADDR_T_NONE) {
152 dev_err(dev, "No reg property for DDRSS wrapper logic\n");
153 return -EINVAL;
154 }
155 ddrss->ddrss_ss_cfg = (void *)reg;
156
157 reg = dev_read_addr_name(dev, "ctrl_mmr_lp4");
158 if (reg == FDT_ADDR_T_NONE) {
159 dev_err(dev, "No reg property for CTRL MMR\n");
160 return -EINVAL;
161 }
162 ddrss->ddrss_ctrl_mmr = (void *)reg;
163
164 ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0);
165 if (ret) {
166 dev_err(dev, "power_domain_get() failed: %d\n", ret);
167 return ret;
168 }
169
170 ret = power_domain_get_by_index(dev, &ddrss->ddrdata_pwrdmn, 1);
171 if (ret) {
172 dev_err(dev, "power_domain_get() failed: %d\n", ret);
173 return ret;
174 }
175
176 ret = clk_get_by_index(dev, 0, &ddrss->ddr_clk);
177 if (ret)
178 dev_err(dev, "clk get failed%d\n", ret);
179
180 ret = clk_get_by_index(dev, 1, &ddrss->osc_clk);
181 if (ret)
182 dev_err(dev, "clk get failed for osc clk %d\n", ret);
183
184 ret = dev_read_u32(dev, "ti,ddr-freq1", &ddrss->ddr_freq1);
185 if (ret)
186 dev_err(dev, "ddr freq1 not populated %d\n", ret);
187
188 ret = dev_read_u32(dev, "ti,ddr-freq2", &ddrss->ddr_freq2);
189 if (ret)
190 dev_err(dev, "ddr freq2 not populated %d\n", ret);
191
192 ret = dev_read_u32(dev, "ti,ddr-fhs-cnt", &ddrss->ddr_fhs_cnt);
193 if (ret)
194 dev_err(dev, "ddr fhs cnt not populated %d\n", ret);
195
196 /* Put DDR pll in bypass mode */
197 ret = clk_set_rate(&ddrss->ddr_clk, clk_get_rate(&ddrss->osc_clk));
198 if (ret)
199 dev_err(dev, "ddr clk bypass failed\n");
200
201 return ret;
202 }
203
j721e_lpddr4_probe(void)204 void j721e_lpddr4_probe(void)
205 {
206 uint32_t status = 0U;
207 uint16_t configsize = 0U;
208
209 status = driverdt->probe(&config, &configsize);
210
211 if ((status != 0) || (configsize != sizeof(lpddr4_privatedata))
212 || (configsize > SRAM_MAX)) {
213 printf("LPDDR4_Probe: FAIL\n");
214 hang();
215 } else {
216 debug("LPDDR4_Probe: PASS\n");
217 }
218 }
219
j721e_lpddr4_init(void)220 void j721e_lpddr4_init(void)
221 {
222 uint32_t status = 0U;
223
224 if ((sizeof(pd) != sizeof(lpddr4_privatedata))
225 || (sizeof(pd) > SRAM_MAX)) {
226 printf("LPDDR4_Init: FAIL\n");
227 hang();
228 }
229
230 config.ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ss_cfg;
231 config.infohandler = (lpddr4_infocallback) j721e_lpddr4_info_handler;
232
233 status = driverdt->init(&pd, &config);
234
235 if ((status > 0U) ||
236 (pd.ctlbase != (struct lpddr4_ctlregs_s *)config.ctlbase) ||
237 (pd.ctlinterrupthandler != config.ctlinterrupthandler) ||
238 (pd.phyindepinterrupthandler != config.phyindepinterrupthandler)) {
239 printf("LPDDR4_Init: FAIL\n");
240 hang();
241 } else {
242 debug("LPDDR4_Init: PASS\n");
243 }
244 }
245
populate_data_array_from_dt(lpddr4_reginitdata * reginit_data)246 void populate_data_array_from_dt(lpddr4_reginitdata * reginit_data)
247 {
248 int ret, i;
249
250 ret = dev_read_u32_array(ddrss->dev, "ti,ctl-data",
251 (u32 *) reginit_data->denalictlreg,
252 LPDDR4_CTL_REG_COUNT);
253 if (ret)
254 printf("Error reading ctrl data\n");
255
256 for (i = 0; i < LPDDR4_CTL_REG_COUNT; i++)
257 reginit_data->updatectlreg[i] = true;
258
259 ret = dev_read_u32_array(ddrss->dev, "ti,pi-data",
260 (u32 *) reginit_data->denaliphyindepreg,
261 LPDDR4_PHY_INDEP_REG_COUNT);
262 if (ret)
263 printf("Error reading PI data\n");
264
265 for (i = 0; i < LPDDR4_PHY_INDEP_REG_COUNT; i++)
266 reginit_data->updatephyindepreg[i] = true;
267
268 ret = dev_read_u32_array(ddrss->dev, "ti,phy-data",
269 (u32 *) reginit_data->denaliphyreg,
270 LPDDR4_PHY_REG_COUNT);
271 if (ret)
272 printf("Error reading PHY data\n");
273
274 for (i = 0; i < LPDDR4_PHY_REG_COUNT; i++)
275 reginit_data->updatephyreg[i] = true;
276 }
277
j721e_lpddr4_hardware_reg_init(void)278 void j721e_lpddr4_hardware_reg_init(void)
279 {
280 uint32_t status = 0U;
281 lpddr4_reginitdata reginitdata;
282
283 populate_data_array_from_dt(®initdata);
284
285 status = driverdt->writectlconfig(&pd, ®initdata);
286 if (!status) {
287 status = driverdt->writephyindepconfig(&pd, ®initdata);
288 }
289 if (!status) {
290 status = driverdt->writephyconfig(&pd, ®initdata);
291 }
292 if (status) {
293 printf(" ERROR: LPDDR4_HardwareRegInit failed!!\n");
294 hang();
295 }
296
297 return;
298 }
299
j721e_lpddr4_start(void)300 void j721e_lpddr4_start(void)
301 {
302 uint32_t status = 0U;
303 uint32_t regval = 0U;
304 uint32_t offset = 0U;
305
306 TH_OFFSET_FROM_REG(LPDDR4__START__REG, CTL_SHIFT, offset);
307
308 status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, ®val);
309 if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 0U)) {
310 printf("LPDDR4_StartTest: FAIL\n");
311 hang();
312 }
313
314 status = driverdt->start(&pd);
315 if (status > 0U) {
316 printf("LPDDR4_StartTest: FAIL\n");
317 hang();
318 }
319
320 status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, ®val);
321 if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 1U)) {
322 printf("LPDDR4_Start: FAIL\n");
323 hang();
324 } else {
325 debug("LPDDR4_Start: PASS\n");
326 }
327 }
328
j721e_ddrss_probe(struct udevice * dev)329 static int j721e_ddrss_probe(struct udevice *dev)
330 {
331 int ret;
332 ddrss = dev_get_priv(dev);
333
334 debug("%s(dev=%p)\n", __func__, dev);
335
336 ret = j721e_ddrss_ofdata_to_priv(dev);
337 if (ret)
338 return ret;
339
340 ddrss->dev = dev;
341 ret = j721e_ddrss_power_on(ddrss);
342 if (ret)
343 return ret;
344
345 driverdt = lpddr4_getinstance();
346 j721e_lpddr4_probe();
347 j721e_lpddr4_init();
348 j721e_lpddr4_hardware_reg_init();
349 j721e_lpddr4_start();
350
351 return ret;
352 }
353
j721e_ddrss_get_info(struct udevice * dev,struct ram_info * info)354 static int j721e_ddrss_get_info(struct udevice *dev, struct ram_info *info)
355 {
356 return 0;
357 }
358
359 static struct ram_ops j721e_ddrss_ops = {
360 .get_info = j721e_ddrss_get_info,
361 };
362
363 static const struct udevice_id j721e_ddrss_ids[] = {
364 {.compatible = "ti,j721e-ddrss"},
365 {}
366 };
367
368 U_BOOT_DRIVER(j721e_ddrss) = {
369 .name = "j721e_ddrss",
370 .id = UCLASS_RAM,
371 .of_match = j721e_ddrss_ids,
372 .ops = &j721e_ddrss_ops,
373 .probe = j721e_ddrss_probe,
374 .priv_auto_alloc_size = sizeof(struct j721e_ddrss_desc),
375 };
376