1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2009, 2011, 2016 Freescale Semiconductor, Inc.
4 *
5 * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
6 *
7 * Author: Tor Krill tor@excito.com
8 */
9
10 #include <common.h>
11 #include <env.h>
12 #include <log.h>
13 #include <pci.h>
14 #include <usb.h>
15 #include <asm/io.h>
16 #include <linux/delay.h>
17 #include <usb/ehci-ci.h>
18 #include <hwconfig.h>
19 #include <fsl_usb.h>
20 #include <fdt_support.h>
21 #include <dm.h>
22
23 #include "ehci.h"
24
25 DECLARE_GLOBAL_DATA_PTR;
26
27 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
28 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
29 #endif
30
31 #if CONFIG_IS_ENABLED(DM_USB)
32 struct ehci_fsl_priv {
33 struct ehci_ctrl ehci;
34 fdt_addr_t hcd_base;
35 char *phy_type;
36 };
37 #endif
38
39 static void set_txfifothresh(struct usb_ehci *, u32);
40 #if CONFIG_IS_ENABLED(DM_USB)
41 static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci,
42 struct ehci_hccr *hccr, struct ehci_hcor *hcor);
43 #else
44 static int ehci_fsl_init(int index, struct usb_ehci *ehci,
45 struct ehci_hccr *hccr, struct ehci_hcor *hcor);
46 #endif
47
48 /* Check USB PHY clock valid */
usb_phy_clk_valid(struct usb_ehci * ehci)49 static int usb_phy_clk_valid(struct usb_ehci *ehci)
50 {
51 if (!((in_be32(&ehci->control) & PHY_CLK_VALID) ||
52 in_be32(&ehci->prictrl))) {
53 printf("USB PHY clock invalid!\n");
54 return 0;
55 } else {
56 return 1;
57 }
58 }
59
60 #if CONFIG_IS_ENABLED(DM_USB)
ehci_fsl_ofdata_to_platdata(struct udevice * dev)61 static int ehci_fsl_ofdata_to_platdata(struct udevice *dev)
62 {
63 struct ehci_fsl_priv *priv = dev_get_priv(dev);
64 const void *prop;
65
66 prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy_type",
67 NULL);
68 if (prop) {
69 priv->phy_type = (char *)prop;
70 debug("phy_type %s\n", priv->phy_type);
71 }
72
73 return 0;
74 }
75
ehci_fsl_init_after_reset(struct ehci_ctrl * ctrl)76 static int ehci_fsl_init_after_reset(struct ehci_ctrl *ctrl)
77 {
78 struct usb_ehci *ehci = NULL;
79 struct ehci_fsl_priv *priv = container_of(ctrl, struct ehci_fsl_priv,
80 ehci);
81 #ifdef CONFIG_PPC
82 ehci = (struct usb_ehci *)lower_32_bits(priv->hcd_base);
83 #else
84 ehci = (struct usb_ehci *)priv->hcd_base;
85 #endif
86
87 if (ehci_fsl_init(priv, ehci, priv->ehci.hccr, priv->ehci.hcor) < 0)
88 return -ENXIO;
89
90 return 0;
91 }
92
93 static const struct ehci_ops fsl_ehci_ops = {
94 .init_after_reset = ehci_fsl_init_after_reset,
95 };
96
ehci_fsl_probe(struct udevice * dev)97 static int ehci_fsl_probe(struct udevice *dev)
98 {
99 struct ehci_fsl_priv *priv = dev_get_priv(dev);
100 struct usb_ehci *ehci = NULL;
101 struct ehci_hccr *hccr;
102 struct ehci_hcor *hcor;
103 struct ehci_ctrl *ehci_ctrl = &priv->ehci;
104
105 /*
106 * Get the base address for EHCI controller from the device node
107 */
108 priv->hcd_base = devfdt_get_addr(dev);
109 if (priv->hcd_base == FDT_ADDR_T_NONE) {
110 debug("Can't get the EHCI register base address\n");
111 return -ENXIO;
112 }
113 #ifdef CONFIG_PPC
114 ehci = (struct usb_ehci *)lower_32_bits(priv->hcd_base);
115 #else
116 ehci = (struct usb_ehci *)priv->hcd_base;
117 #endif
118 hccr = (struct ehci_hccr *)(&ehci->caplength);
119 hcor = (struct ehci_hcor *)
120 ((void *)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
121
122 ehci_ctrl->has_fsl_erratum_a005275 = has_erratum_a005275();
123
124 if (ehci_fsl_init(priv, ehci, hccr, hcor) < 0)
125 return -ENXIO;
126
127 debug("ehci-fsl: init hccr %p and hcor %p hc_length %d\n",
128 (void *)hccr, (void *)hcor,
129 HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
130
131 return ehci_register(dev, hccr, hcor, &fsl_ehci_ops, 0, USB_INIT_HOST);
132 }
133
134 static const struct udevice_id ehci_usb_ids[] = {
135 { .compatible = "fsl-usb2-mph", },
136 { .compatible = "fsl-usb2-dr", },
137 { }
138 };
139
140 U_BOOT_DRIVER(ehci_fsl) = {
141 .name = "ehci_fsl",
142 .id = UCLASS_USB,
143 .of_match = ehci_usb_ids,
144 .ofdata_to_platdata = ehci_fsl_ofdata_to_platdata,
145 .probe = ehci_fsl_probe,
146 .remove = ehci_deregister,
147 .ops = &ehci_usb_ops,
148 .platdata_auto_alloc_size = sizeof(struct usb_platdata),
149 .priv_auto_alloc_size = sizeof(struct ehci_fsl_priv),
150 .flags = DM_FLAG_ALLOC_PRIV_DMA,
151 };
152 #else
153 /*
154 * Create the appropriate control structures to manage
155 * a new EHCI host controller.
156 *
157 * Excerpts from linux ehci fsl driver.
158 */
ehci_hcd_init(int index,enum usb_init_type init,struct ehci_hccr ** hccr,struct ehci_hcor ** hcor)159 int ehci_hcd_init(int index, enum usb_init_type init,
160 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
161 {
162 struct ehci_ctrl *ehci_ctrl = container_of(hccr,
163 struct ehci_ctrl, hccr);
164 struct usb_ehci *ehci = NULL;
165
166 switch (index) {
167 case 0:
168 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
169 break;
170 case 1:
171 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR;
172 break;
173 default:
174 printf("ERROR: wrong controller index!!\n");
175 return -EINVAL;
176 };
177
178 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
179 *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
180 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
181
182 ehci_ctrl->has_fsl_erratum_a005275 = has_erratum_a005275();
183
184 return ehci_fsl_init(index, ehci, *hccr, *hcor);
185 }
186
187 /*
188 * Destroy the appropriate control structures corresponding
189 * the the EHCI host controller.
190 */
ehci_hcd_stop(int index)191 int ehci_hcd_stop(int index)
192 {
193 return 0;
194 }
195 #endif
196
197 #if CONFIG_IS_ENABLED(DM_USB)
ehci_fsl_init(struct ehci_fsl_priv * priv,struct usb_ehci * ehci,struct ehci_hccr * hccr,struct ehci_hcor * hcor)198 static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci,
199 struct ehci_hccr *hccr, struct ehci_hcor *hcor)
200 #else
201 static int ehci_fsl_init(int index, struct usb_ehci *ehci,
202 struct ehci_hccr *hccr, struct ehci_hcor *hcor)
203 #endif
204 {
205 const char *phy_type = NULL;
206 #if !CONFIG_IS_ENABLED(DM_USB)
207 size_t len;
208 char current_usb_controller[5];
209 #endif
210 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
211 char usb_phy[5];
212
213 usb_phy[0] = '\0';
214 #endif
215 if (has_erratum_a007075()) {
216 /*
217 * A 5ms delay is needed after applying soft-reset to the
218 * controller to let external ULPI phy come out of reset.
219 * This delay needs to be added before re-initializing
220 * the controller after soft-resetting completes
221 */
222 mdelay(5);
223 }
224
225 /* Set to Host mode */
226 setbits_le32(&ehci->usbmode, CM_HOST);
227
228 out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
229 out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
230
231 /* Init phy */
232 #if CONFIG_IS_ENABLED(DM_USB)
233 if (priv->phy_type)
234 phy_type = priv->phy_type;
235 #else
236 memset(current_usb_controller, '\0', 5);
237 snprintf(current_usb_controller, sizeof(current_usb_controller),
238 "usb%d", index+1);
239
240 if (hwconfig_sub(current_usb_controller, "phy_type"))
241 phy_type = hwconfig_subarg(current_usb_controller,
242 "phy_type", &len);
243 #endif
244 else
245 phy_type = env_get("usb_phy_type");
246
247 if (!phy_type) {
248 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
249 /* if none specified assume internal UTMI */
250 strcpy(usb_phy, "utmi");
251 phy_type = usb_phy;
252 #else
253 printf("WARNING: USB phy type not defined !!\n");
254 return -1;
255 #endif
256 }
257
258 if (!strncmp(phy_type, "utmi", 4)) {
259 #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
260 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
261 PHY_CLK_SEL_UTMI);
262 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
263 UTMI_PHY_EN);
264 udelay(1000); /* delay required for PHY Clk to appear */
265 #endif
266 out_le32(&(hcor)->or_portsc[0], PORT_PTS_UTMI);
267 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
268 USB_EN);
269 } else {
270 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
271 PHY_CLK_SEL_ULPI);
272 clrsetbits_be32(&ehci->control, UTMI_PHY_EN |
273 CONTROL_REGISTER_W1C_MASK, USB_EN);
274 udelay(1000); /* delay required for PHY Clk to appear */
275 if (!usb_phy_clk_valid(ehci))
276 return -EINVAL;
277 out_le32(&(hcor)->or_portsc[0], PORT_PTS_ULPI);
278 }
279
280 out_be32(&ehci->prictrl, 0x0000000c);
281 out_be32(&ehci->age_cnt_limit, 0x00000040);
282 out_be32(&ehci->sictrl, 0x00000001);
283
284 in_le32(&ehci->usbmode);
285
286 if (has_erratum_a007798())
287 set_txfifothresh(ehci, TXFIFOTHRESH);
288
289 if (has_erratum_a004477()) {
290 /*
291 * When reset is issued while any ULPI transaction is ongoing
292 * then it may result to corruption of ULPI Function Control
293 * Register which eventually causes phy clock to enter low
294 * power mode which stops the clock. Thus delay is required
295 * before reset to let ongoing ULPI transaction complete.
296 */
297 udelay(1);
298 }
299 return 0;
300 }
301
302 /*
303 * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register
304 * to counter DDR latencies in writing data into Tx buffer.
305 * This prevents Tx buffer from getting underrun
306 */
set_txfifothresh(struct usb_ehci * ehci,u32 txfifo_thresh)307 static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh)
308 {
309 u32 cmd;
310 cmd = ehci_readl(&ehci->txfilltuning);
311 cmd &= ~TXFIFO_THRESH_MASK;
312 cmd |= TXFIFO_THRESH(txfifo_thresh);
313 ehci_writel(&ehci->txfilltuning, cmd);
314 }
315