1 // SPDX-License-Identifier: GPL-2.0
2 /*-
3 * Copyright (c) 2007-2008, Juniper Networks, Inc.
4 * Copyright (c) 2008, Excito Elektronik i Skåne AB
5 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
6 *
7 * All rights reserved.
8 */
9 #include <common.h>
10 #include <cpu_func.h>
11 #include <dm.h>
12 #include <errno.h>
13 #include <log.h>
14 #include <asm/byteorder.h>
15 #include <asm/cache.h>
16 #include <asm/unaligned.h>
17 #include <usb.h>
18 #include <asm/io.h>
19 #include <malloc.h>
20 #include <memalign.h>
21 #include <watchdog.h>
22 #include <dm/device_compat.h>
23 #include <linux/compiler.h>
24 #include <linux/delay.h>
25
26 #include "ehci.h"
27
28 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
29 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
30 #endif
31
32 /*
33 * EHCI spec page 20 says that the HC may take up to 16 uFrames (= 4ms) to halt.
34 * Let's time out after 8 to have a little safety margin on top of that.
35 */
36 #define HCHALT_TIMEOUT (8 * 1000)
37
38 #if !CONFIG_IS_ENABLED(DM_USB)
39 static struct ehci_ctrl ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
40 #endif
41
42 #define ALIGN_END_ADDR(type, ptr, size) \
43 ((unsigned long)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
44
45 static struct descriptor {
46 struct usb_hub_descriptor hub;
47 struct usb_device_descriptor device;
48 struct usb_linux_config_descriptor config;
49 struct usb_linux_interface_descriptor interface;
50 struct usb_endpoint_descriptor endpoint;
51 } __attribute__ ((packed)) descriptor = {
52 {
53 0x8, /* bDescLength */
54 0x29, /* bDescriptorType: hub descriptor */
55 2, /* bNrPorts -- runtime modified */
56 0, /* wHubCharacteristics */
57 10, /* bPwrOn2PwrGood */
58 0, /* bHubCntrCurrent */
59 { /* Device removable */
60 } /* at most 7 ports! XXX */
61 },
62 {
63 0x12, /* bLength */
64 1, /* bDescriptorType: UDESC_DEVICE */
65 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
66 9, /* bDeviceClass: UDCLASS_HUB */
67 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
68 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */
69 64, /* bMaxPacketSize: 64 bytes */
70 0x0000, /* idVendor */
71 0x0000, /* idProduct */
72 cpu_to_le16(0x0100), /* bcdDevice */
73 1, /* iManufacturer */
74 2, /* iProduct */
75 0, /* iSerialNumber */
76 1 /* bNumConfigurations: 1 */
77 },
78 {
79 0x9,
80 2, /* bDescriptorType: UDESC_CONFIG */
81 cpu_to_le16(0x19),
82 1, /* bNumInterface */
83 1, /* bConfigurationValue */
84 0, /* iConfiguration */
85 0x40, /* bmAttributes: UC_SELF_POWER */
86 0 /* bMaxPower */
87 },
88 {
89 0x9, /* bLength */
90 4, /* bDescriptorType: UDESC_INTERFACE */
91 0, /* bInterfaceNumber */
92 0, /* bAlternateSetting */
93 1, /* bNumEndpoints */
94 9, /* bInterfaceClass: UICLASS_HUB */
95 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
96 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
97 0 /* iInterface */
98 },
99 {
100 0x7, /* bLength */
101 5, /* bDescriptorType: UDESC_ENDPOINT */
102 0x81, /* bEndpointAddress:
103 * UE_DIR_IN | EHCI_INTR_ENDPT
104 */
105 3, /* bmAttributes: UE_INTERRUPT */
106 8, /* wMaxPacketSize */
107 255 /* bInterval */
108 },
109 };
110
111 #if defined(CONFIG_EHCI_IS_TDI)
112 #define ehci_is_TDI() (1)
113 #else
114 #define ehci_is_TDI() (0)
115 #endif
116
ehci_get_ctrl(struct usb_device * udev)117 static struct ehci_ctrl *ehci_get_ctrl(struct usb_device *udev)
118 {
119 #if CONFIG_IS_ENABLED(DM_USB)
120 return dev_get_priv(usb_get_bus(udev->dev));
121 #else
122 return udev->controller;
123 #endif
124 }
125
ehci_get_port_speed(struct ehci_ctrl * ctrl,uint32_t reg)126 static int ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg)
127 {
128 return PORTSC_PSPD(reg);
129 }
130
ehci_set_usbmode(struct ehci_ctrl * ctrl)131 static void ehci_set_usbmode(struct ehci_ctrl *ctrl)
132 {
133 uint32_t tmp;
134 uint32_t *reg_ptr;
135
136 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + USBMODE);
137 tmp = ehci_readl(reg_ptr);
138 tmp |= USBMODE_CM_HC;
139 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
140 tmp |= USBMODE_BE;
141 #else
142 tmp &= ~USBMODE_BE;
143 #endif
144 ehci_writel(reg_ptr, tmp);
145 }
146
ehci_powerup_fixup(struct ehci_ctrl * ctrl,uint32_t * status_reg,uint32_t * reg)147 static void ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
148 uint32_t *reg)
149 {
150 mdelay(50);
151 }
152
ehci_get_portsc_register(struct ehci_ctrl * ctrl,int port)153 static uint32_t *ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port)
154 {
155 int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams));
156
157 if (port < 0 || port >= max_ports) {
158 /* Printing the message would cause a scan failure! */
159 debug("The request port(%u) exceeds maximum port number\n",
160 port);
161 return NULL;
162 }
163
164 return (uint32_t *)&ctrl->hcor->or_portsc[port];
165 }
166
handshake(uint32_t * ptr,uint32_t mask,uint32_t done,int usec)167 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
168 {
169 uint32_t result;
170 do {
171 result = ehci_readl(ptr);
172 udelay(5);
173 if (result == ~(uint32_t)0)
174 return -1;
175 result &= mask;
176 if (result == done)
177 return 0;
178 usec--;
179 } while (usec > 0);
180 return -1;
181 }
182
ehci_reset(struct ehci_ctrl * ctrl)183 static int ehci_reset(struct ehci_ctrl *ctrl)
184 {
185 uint32_t cmd;
186 int ret = 0;
187
188 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
189 cmd = (cmd & ~CMD_RUN) | CMD_RESET;
190 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
191 ret = handshake((uint32_t *)&ctrl->hcor->or_usbcmd,
192 CMD_RESET, 0, 250 * 1000);
193 if (ret < 0) {
194 printf("EHCI fail to reset\n");
195 goto out;
196 }
197
198 if (ehci_is_TDI())
199 ctrl->ops.set_usb_mode(ctrl);
200
201 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
202 cmd = ehci_readl(&ctrl->hcor->or_txfilltuning);
203 cmd &= ~TXFIFO_THRESH_MASK;
204 cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
205 ehci_writel(&ctrl->hcor->or_txfilltuning, cmd);
206 #endif
207 out:
208 return ret;
209 }
210
ehci_shutdown(struct ehci_ctrl * ctrl)211 static int ehci_shutdown(struct ehci_ctrl *ctrl)
212 {
213 int i, ret = 0;
214 uint32_t cmd, reg;
215 int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams));
216
217 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
218 /* If not run, directly return */
219 if (!(cmd & CMD_RUN))
220 return 0;
221 cmd &= ~(CMD_PSE | CMD_ASE);
222 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
223 ret = handshake(&ctrl->hcor->or_usbsts, STS_ASS | STS_PSS, 0,
224 100 * 1000);
225
226 if (!ret) {
227 for (i = 0; i < max_ports; i++) {
228 reg = ehci_readl(&ctrl->hcor->or_portsc[i]);
229 reg |= EHCI_PS_SUSP;
230 ehci_writel(&ctrl->hcor->or_portsc[i], reg);
231 }
232
233 cmd &= ~CMD_RUN;
234 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
235 ret = handshake(&ctrl->hcor->or_usbsts, STS_HALT, STS_HALT,
236 HCHALT_TIMEOUT);
237 }
238
239 if (ret)
240 puts("EHCI failed to shut down host controller.\n");
241
242 return ret;
243 }
244
ehci_td_buffer(struct qTD * td,void * buf,size_t sz)245 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
246 {
247 uint32_t delta, next;
248 unsigned long addr = (unsigned long)buf;
249 int idx;
250
251 if (addr != ALIGN(addr, ARCH_DMA_MINALIGN))
252 debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf);
253
254 flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN));
255
256 idx = 0;
257 while (idx < QT_BUFFER_CNT) {
258 td->qt_buffer[idx] = cpu_to_hc32(virt_to_phys((void *)addr));
259 td->qt_buffer_hi[idx] = 0;
260 next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1);
261 delta = next - addr;
262 if (delta >= sz)
263 break;
264 sz -= delta;
265 addr = next;
266 idx++;
267 }
268
269 if (idx == QT_BUFFER_CNT) {
270 printf("out of buffer pointers (%zu bytes left)\n", sz);
271 return -1;
272 }
273
274 return 0;
275 }
276
ehci_encode_speed(enum usb_device_speed speed)277 static inline u8 ehci_encode_speed(enum usb_device_speed speed)
278 {
279 #define QH_HIGH_SPEED 2
280 #define QH_FULL_SPEED 0
281 #define QH_LOW_SPEED 1
282 if (speed == USB_SPEED_HIGH)
283 return QH_HIGH_SPEED;
284 if (speed == USB_SPEED_LOW)
285 return QH_LOW_SPEED;
286 return QH_FULL_SPEED;
287 }
288
ehci_update_endpt2_dev_n_port(struct usb_device * udev,struct QH * qh)289 static void ehci_update_endpt2_dev_n_port(struct usb_device *udev,
290 struct QH *qh)
291 {
292 uint8_t portnr = 0;
293 uint8_t hubaddr = 0;
294
295 if (udev->speed != USB_SPEED_LOW && udev->speed != USB_SPEED_FULL)
296 return;
297
298 usb_find_usb2_hub_address_port(udev, &hubaddr, &portnr);
299
300 qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(portnr) |
301 QH_ENDPT2_HUBADDR(hubaddr));
302 }
303
ehci_enable_async(struct ehci_ctrl * ctrl)304 static int ehci_enable_async(struct ehci_ctrl *ctrl)
305 {
306 u32 cmd;
307 int ret;
308
309 /* Enable async. schedule. */
310 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
311 if (cmd & CMD_ASE)
312 return 0;
313
314 cmd |= CMD_ASE;
315 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
316
317 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS,
318 100 * 1000);
319 if (ret < 0)
320 printf("EHCI fail timeout STS_ASS set\n");
321
322 return ret;
323 }
324
ehci_disable_async(struct ehci_ctrl * ctrl)325 static int ehci_disable_async(struct ehci_ctrl *ctrl)
326 {
327 u32 cmd;
328 int ret;
329
330 if (ctrl->async_locked)
331 return 0;
332
333 /* Disable async schedule. */
334 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
335 if (!(cmd & CMD_ASE))
336 return 0;
337
338 cmd &= ~CMD_ASE;
339 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
340
341 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0,
342 100 * 1000);
343 if (ret < 0)
344 printf("EHCI fail timeout STS_ASS reset\n");
345
346 return ret;
347 }
348
349 static int
ehci_submit_async(struct usb_device * dev,unsigned long pipe,void * buffer,int length,struct devrequest * req)350 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
351 int length, struct devrequest *req)
352 {
353 ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
354 struct qTD *qtd;
355 int qtd_count = 0;
356 int qtd_counter = 0;
357 volatile struct qTD *vtd;
358 unsigned long ts;
359 uint32_t *tdp;
360 uint32_t endpt, maxpacket, token, usbsts, qhtoken;
361 uint32_t c, toggle;
362 int timeout;
363 int ret = 0;
364 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
365
366 debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
367 buffer, length, req);
368 if (req != NULL)
369 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
370 req->request, req->request,
371 req->requesttype, req->requesttype,
372 le16_to_cpu(req->value), le16_to_cpu(req->value),
373 le16_to_cpu(req->index));
374
375 #define PKT_ALIGN 512
376 /*
377 * The USB transfer is split into qTD transfers. Eeach qTD transfer is
378 * described by a transfer descriptor (the qTD). The qTDs form a linked
379 * list with a queue head (QH).
380 *
381 * Each qTD transfer starts with a new USB packet, i.e. a packet cannot
382 * have its beginning in a qTD transfer and its end in the following
383 * one, so the qTD transfer lengths have to be chosen accordingly.
384 *
385 * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to
386 * single pages. The first data buffer can start at any offset within a
387 * page (not considering the cache-line alignment issues), while the
388 * following buffers must be page-aligned. There is no alignment
389 * constraint on the size of a qTD transfer.
390 */
391 if (req != NULL)
392 /* 1 qTD will be needed for SETUP, and 1 for ACK. */
393 qtd_count += 1 + 1;
394 if (length > 0 || req == NULL) {
395 /*
396 * Determine the qTD transfer size that will be used for the
397 * data payload (not considering the first qTD transfer, which
398 * may be longer or shorter, and the final one, which may be
399 * shorter).
400 *
401 * In order to keep each packet within a qTD transfer, the qTD
402 * transfer size is aligned to PKT_ALIGN, which is a multiple of
403 * wMaxPacketSize (except in some cases for interrupt transfers,
404 * see comment in submit_int_msg()).
405 *
406 * By default, i.e. if the input buffer is aligned to PKT_ALIGN,
407 * QT_BUFFER_CNT full pages will be used.
408 */
409 int xfr_sz = QT_BUFFER_CNT;
410 /*
411 * However, if the input buffer is not aligned to PKT_ALIGN, the
412 * qTD transfer size will be one page shorter, and the first qTD
413 * data buffer of each transfer will be page-unaligned.
414 */
415 if ((unsigned long)buffer & (PKT_ALIGN - 1))
416 xfr_sz--;
417 /* Convert the qTD transfer size to bytes. */
418 xfr_sz *= EHCI_PAGE_SIZE;
419 /*
420 * Approximate by excess the number of qTDs that will be
421 * required for the data payload. The exact formula is way more
422 * complicated and saves at most 2 qTDs, i.e. a total of 128
423 * bytes.
424 */
425 qtd_count += 2 + length / xfr_sz;
426 }
427 /*
428 * Threshold value based on the worst-case total size of the allocated qTDs for
429 * a mass-storage transfer of 65535 blocks of 512 bytes.
430 */
431 #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024
432 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI
433 #endif
434 qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD));
435 if (qtd == NULL) {
436 printf("unable to allocate TDs\n");
437 return -1;
438 }
439
440 memset(qh, 0, sizeof(struct QH));
441 memset(qtd, 0, qtd_count * sizeof(*qtd));
442
443 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
444
445 /*
446 * Setup QH (3.6 in ehci-r10.pdf)
447 *
448 * qh_link ................. 03-00 H
449 * qh_endpt1 ............... 07-04 H
450 * qh_endpt2 ............... 0B-08 H
451 * - qh_curtd
452 * qh_overlay.qt_next ...... 13-10 H
453 * - qh_overlay.qt_altnext
454 */
455 qh->qh_link = cpu_to_hc32(virt_to_phys(&ctrl->qh_list) | QH_LINK_TYPE_QH);
456 c = (dev->speed != USB_SPEED_HIGH) && !usb_pipeendpoint(pipe);
457 maxpacket = usb_maxpacket(dev, pipe);
458 endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
459 QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) |
460 QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) |
461 QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
462 QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
463
464 /* Force FS for fsl HS quirk */
465 if (!ctrl->has_fsl_erratum_a005275)
466 endpt |= QH_ENDPT1_EPS(ehci_encode_speed(dev->speed));
467 else
468 endpt |= QH_ENDPT1_EPS(ehci_encode_speed(QH_FULL_SPEED));
469
470 qh->qh_endpt1 = cpu_to_hc32(endpt);
471 endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
472 qh->qh_endpt2 = cpu_to_hc32(endpt);
473 ehci_update_endpt2_dev_n_port(dev, qh);
474 qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
475 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
476
477 tdp = &qh->qh_overlay.qt_next;
478 if (req != NULL) {
479 /*
480 * Setup request qTD (3.5 in ehci-r10.pdf)
481 *
482 * qt_next ................ 03-00 H
483 * qt_altnext ............. 07-04 H
484 * qt_token ............... 0B-08 H
485 *
486 * [ buffer, buffer_hi ] loaded with "req".
487 */
488 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
489 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
490 token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) |
491 QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
492 QT_TOKEN_PID(QT_TOKEN_PID_SETUP) |
493 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
494 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
495 if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) {
496 printf("unable to construct SETUP TD\n");
497 goto fail;
498 }
499 /* Update previous qTD! */
500 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
501 tdp = &qtd[qtd_counter++].qt_next;
502 toggle = 1;
503 }
504
505 if (length > 0 || req == NULL) {
506 uint8_t *buf_ptr = buffer;
507 int left_length = length;
508
509 do {
510 /*
511 * Determine the size of this qTD transfer. By default,
512 * QT_BUFFER_CNT full pages can be used.
513 */
514 int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE;
515 /*
516 * However, if the input buffer is not page-aligned, the
517 * portion of the first page before the buffer start
518 * offset within that page is unusable.
519 */
520 xfr_bytes -= (unsigned long)buf_ptr & (EHCI_PAGE_SIZE - 1);
521 /*
522 * In order to keep each packet within a qTD transfer,
523 * align the qTD transfer size to PKT_ALIGN.
524 */
525 xfr_bytes &= ~(PKT_ALIGN - 1);
526 /*
527 * This transfer may be shorter than the available qTD
528 * transfer size that has just been computed.
529 */
530 xfr_bytes = min(xfr_bytes, left_length);
531
532 /*
533 * Setup request qTD (3.5 in ehci-r10.pdf)
534 *
535 * qt_next ................ 03-00 H
536 * qt_altnext ............. 07-04 H
537 * qt_token ............... 0B-08 H
538 *
539 * [ buffer, buffer_hi ] loaded with "buffer".
540 */
541 qtd[qtd_counter].qt_next =
542 cpu_to_hc32(QT_NEXT_TERMINATE);
543 qtd[qtd_counter].qt_altnext =
544 cpu_to_hc32(QT_NEXT_TERMINATE);
545 token = QT_TOKEN_DT(toggle) |
546 QT_TOKEN_TOTALBYTES(xfr_bytes) |
547 QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) |
548 QT_TOKEN_CERR(3) |
549 QT_TOKEN_PID(usb_pipein(pipe) ?
550 QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) |
551 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
552 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
553 if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr,
554 xfr_bytes)) {
555 printf("unable to construct DATA TD\n");
556 goto fail;
557 }
558 /* Update previous qTD! */
559 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
560 tdp = &qtd[qtd_counter++].qt_next;
561 /*
562 * Data toggle has to be adjusted since the qTD transfer
563 * size is not always an even multiple of
564 * wMaxPacketSize.
565 */
566 if ((xfr_bytes / maxpacket) & 1)
567 toggle ^= 1;
568 buf_ptr += xfr_bytes;
569 left_length -= xfr_bytes;
570 } while (left_length > 0);
571 }
572
573 if (req != NULL) {
574 /*
575 * Setup request qTD (3.5 in ehci-r10.pdf)
576 *
577 * qt_next ................ 03-00 H
578 * qt_altnext ............. 07-04 H
579 * qt_token ............... 0B-08 H
580 */
581 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
582 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
583 token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) |
584 QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
585 QT_TOKEN_PID(usb_pipein(pipe) ?
586 QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) |
587 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
588 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
589 /* Update previous qTD! */
590 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
591 tdp = &qtd[qtd_counter++].qt_next;
592 }
593
594 ctrl->qh_list.qh_link = cpu_to_hc32(virt_to_phys(qh) | QH_LINK_TYPE_QH);
595
596 /* Flush dcache */
597 flush_dcache_range((unsigned long)&ctrl->qh_list,
598 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
599 flush_dcache_range((unsigned long)qh, ALIGN_END_ADDR(struct QH, qh, 1));
600 flush_dcache_range((unsigned long)qtd,
601 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
602
603 usbsts = ehci_readl(&ctrl->hcor->or_usbsts);
604 ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f));
605
606 ret = ehci_enable_async(ctrl);
607 if (ret)
608 goto fail;
609
610 /* Wait for TDs to be processed. */
611 ts = get_timer(0);
612 vtd = &qtd[qtd_counter - 1];
613 timeout = USB_TIMEOUT_MS(pipe);
614 do {
615 /* Invalidate dcache */
616 invalidate_dcache_range((unsigned long)&ctrl->qh_list,
617 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
618 invalidate_dcache_range((unsigned long)qh,
619 ALIGN_END_ADDR(struct QH, qh, 1));
620 invalidate_dcache_range((unsigned long)qtd,
621 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
622
623 token = hc32_to_cpu(vtd->qt_token);
624 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
625 break;
626 WATCHDOG_RESET();
627 } while (get_timer(ts) < timeout);
628 qhtoken = hc32_to_cpu(qh->qh_overlay.qt_token);
629
630 ctrl->qh_list.qh_link = cpu_to_hc32(virt_to_phys(&ctrl->qh_list) | QH_LINK_TYPE_QH);
631 flush_dcache_range((unsigned long)&ctrl->qh_list,
632 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
633
634 /*
635 * Invalidate the memory area occupied by buffer
636 * Don't try to fix the buffer alignment, if it isn't properly
637 * aligned it's upper layer's fault so let invalidate_dcache_range()
638 * vow about it. But we have to fix the length as it's actual
639 * transfer length and can be unaligned. This is potentially
640 * dangerous operation, it's responsibility of the calling
641 * code to make sure enough space is reserved.
642 */
643 if (buffer != NULL && length > 0)
644 invalidate_dcache_range((unsigned long)buffer,
645 ALIGN((unsigned long)buffer + length, ARCH_DMA_MINALIGN));
646
647 /* Check that the TD processing happened */
648 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
649 printf("EHCI timed out on TD - token=%#x\n", token);
650
651 ret = ehci_disable_async(ctrl);
652 if (ret)
653 goto fail;
654
655 if (!(QT_TOKEN_GET_STATUS(qhtoken) & QT_TOKEN_STATUS_ACTIVE)) {
656 debug("TOKEN=%#x\n", qhtoken);
657 switch (QT_TOKEN_GET_STATUS(qhtoken) &
658 ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) {
659 case 0:
660 toggle = QT_TOKEN_GET_DT(qhtoken);
661 usb_settoggle(dev, usb_pipeendpoint(pipe),
662 usb_pipeout(pipe), toggle);
663 dev->status = 0;
664 break;
665 case QT_TOKEN_STATUS_HALTED:
666 dev->status = USB_ST_STALLED;
667 break;
668 case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR:
669 case QT_TOKEN_STATUS_DATBUFERR:
670 dev->status = USB_ST_BUF_ERR;
671 break;
672 case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET:
673 case QT_TOKEN_STATUS_BABBLEDET:
674 dev->status = USB_ST_BABBLE_DET;
675 break;
676 default:
677 dev->status = USB_ST_CRC_ERR;
678 if (QT_TOKEN_GET_STATUS(qhtoken) & QT_TOKEN_STATUS_HALTED)
679 dev->status |= USB_ST_STALLED;
680 break;
681 }
682 dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(qhtoken);
683 } else {
684 dev->act_len = 0;
685 #ifndef CONFIG_USB_EHCI_FARADAY
686 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
687 dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts),
688 ehci_readl(&ctrl->hcor->or_portsc[0]),
689 ehci_readl(&ctrl->hcor->or_portsc[1]));
690 #endif
691 }
692
693 free(qtd);
694 return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
695
696 fail:
697 free(qtd);
698 return -1;
699 }
700
ehci_submit_root(struct usb_device * dev,unsigned long pipe,void * buffer,int length,struct devrequest * req)701 static int ehci_submit_root(struct usb_device *dev, unsigned long pipe,
702 void *buffer, int length, struct devrequest *req)
703 {
704 uint8_t tmpbuf[4];
705 u16 typeReq;
706 void *srcptr = NULL;
707 int len, srclen;
708 uint32_t reg;
709 uint32_t *status_reg;
710 int port = le16_to_cpu(req->index) & 0xff;
711 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
712
713 srclen = 0;
714
715 debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
716 req->request, req->request,
717 req->requesttype, req->requesttype,
718 le16_to_cpu(req->value), le16_to_cpu(req->index));
719
720 typeReq = req->request | req->requesttype << 8;
721
722 switch (typeReq) {
723 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
724 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
725 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
726 status_reg = ctrl->ops.get_portsc_register(ctrl, port - 1);
727 if (!status_reg)
728 return -1;
729 break;
730 default:
731 status_reg = NULL;
732 break;
733 }
734
735 switch (typeReq) {
736 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
737 switch (le16_to_cpu(req->value) >> 8) {
738 case USB_DT_DEVICE:
739 debug("USB_DT_DEVICE request\n");
740 srcptr = &descriptor.device;
741 srclen = descriptor.device.bLength;
742 break;
743 case USB_DT_CONFIG:
744 debug("USB_DT_CONFIG config\n");
745 srcptr = &descriptor.config;
746 srclen = descriptor.config.bLength +
747 descriptor.interface.bLength +
748 descriptor.endpoint.bLength;
749 break;
750 case USB_DT_STRING:
751 debug("USB_DT_STRING config\n");
752 switch (le16_to_cpu(req->value) & 0xff) {
753 case 0: /* Language */
754 srcptr = "\4\3\1\0";
755 srclen = 4;
756 break;
757 case 1: /* Vendor */
758 srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
759 srclen = 14;
760 break;
761 case 2: /* Product */
762 srcptr = "\52\3E\0H\0C\0I\0 "
763 "\0H\0o\0s\0t\0 "
764 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
765 srclen = 42;
766 break;
767 default:
768 debug("unknown value DT_STRING %x\n",
769 le16_to_cpu(req->value));
770 goto unknown;
771 }
772 break;
773 default:
774 debug("unknown value %x\n", le16_to_cpu(req->value));
775 goto unknown;
776 }
777 break;
778 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
779 switch (le16_to_cpu(req->value) >> 8) {
780 case USB_DT_HUB:
781 debug("USB_DT_HUB config\n");
782 srcptr = &descriptor.hub;
783 srclen = descriptor.hub.bLength;
784 break;
785 default:
786 debug("unknown value %x\n", le16_to_cpu(req->value));
787 goto unknown;
788 }
789 break;
790 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
791 debug("USB_REQ_SET_ADDRESS\n");
792 ctrl->rootdev = le16_to_cpu(req->value);
793 break;
794 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
795 debug("USB_REQ_SET_CONFIGURATION\n");
796 /* Nothing to do */
797 break;
798 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
799 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
800 tmpbuf[1] = 0;
801 srcptr = tmpbuf;
802 srclen = 2;
803 break;
804 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
805 memset(tmpbuf, 0, 4);
806 reg = ehci_readl(status_reg);
807 if (reg & EHCI_PS_CS)
808 tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
809 if (reg & EHCI_PS_PE)
810 tmpbuf[0] |= USB_PORT_STAT_ENABLE;
811 if (reg & EHCI_PS_SUSP)
812 tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
813 if (reg & EHCI_PS_OCA)
814 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
815 if (reg & EHCI_PS_PR)
816 tmpbuf[0] |= USB_PORT_STAT_RESET;
817 if (reg & EHCI_PS_PP)
818 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
819
820 if (ehci_is_TDI()) {
821 switch (ctrl->ops.get_port_speed(ctrl, reg)) {
822 case PORTSC_PSPD_FS:
823 break;
824 case PORTSC_PSPD_LS:
825 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
826 break;
827 case PORTSC_PSPD_HS:
828 default:
829 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
830 break;
831 }
832 } else {
833 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
834 }
835
836 if (reg & EHCI_PS_CSC)
837 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
838 if (reg & EHCI_PS_PEC)
839 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
840 if (reg & EHCI_PS_OCC)
841 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
842 if (ctrl->portreset & (1 << port))
843 tmpbuf[2] |= USB_PORT_STAT_C_RESET;
844
845 srcptr = tmpbuf;
846 srclen = 4;
847 break;
848 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
849 reg = ehci_readl(status_reg);
850 reg &= ~EHCI_PS_CLEAR;
851 switch (le16_to_cpu(req->value)) {
852 case USB_PORT_FEAT_ENABLE:
853 reg |= EHCI_PS_PE;
854 ehci_writel(status_reg, reg);
855 break;
856 case USB_PORT_FEAT_POWER:
857 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) {
858 reg |= EHCI_PS_PP;
859 ehci_writel(status_reg, reg);
860 }
861 break;
862 case USB_PORT_FEAT_RESET:
863 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
864 !ehci_is_TDI() &&
865 EHCI_PS_IS_LOWSPEED(reg)) {
866 /* Low speed device, give up ownership. */
867 debug("port %d low speed --> companion\n",
868 port - 1);
869 reg |= EHCI_PS_PO;
870 ehci_writel(status_reg, reg);
871 return -ENXIO;
872 } else {
873 int ret;
874
875 /* Disable chirp for HS erratum */
876 if (ctrl->has_fsl_erratum_a005275)
877 reg |= PORTSC_FSL_PFSC;
878
879 reg |= EHCI_PS_PR;
880 reg &= ~EHCI_PS_PE;
881 ehci_writel(status_reg, reg);
882 /*
883 * caller must wait, then call GetPortStatus
884 * usb 2.0 specification say 50 ms resets on
885 * root
886 */
887 ctrl->ops.powerup_fixup(ctrl, status_reg, ®);
888
889 ehci_writel(status_reg, reg & ~EHCI_PS_PR);
890 /*
891 * A host controller must terminate the reset
892 * and stabilize the state of the port within
893 * 2 milliseconds
894 */
895 ret = handshake(status_reg, EHCI_PS_PR, 0,
896 2 * 1000);
897 if (!ret) {
898 reg = ehci_readl(status_reg);
899 if ((reg & (EHCI_PS_PE | EHCI_PS_CS))
900 == EHCI_PS_CS && !ehci_is_TDI()) {
901 debug("port %d full speed --> companion\n", port - 1);
902 reg &= ~EHCI_PS_CLEAR;
903 reg |= EHCI_PS_PO;
904 ehci_writel(status_reg, reg);
905 return -ENXIO;
906 } else {
907 ctrl->portreset |= 1 << port;
908 }
909 } else {
910 printf("port(%d) reset error\n",
911 port - 1);
912 }
913 }
914 break;
915 case USB_PORT_FEAT_TEST:
916 ehci_shutdown(ctrl);
917 reg &= ~(0xf << 16);
918 reg |= ((le16_to_cpu(req->index) >> 8) & 0xf) << 16;
919 ehci_writel(status_reg, reg);
920 break;
921 default:
922 debug("unknown feature %x\n", le16_to_cpu(req->value));
923 goto unknown;
924 }
925 /* unblock posted writes */
926 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
927 break;
928 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
929 reg = ehci_readl(status_reg);
930 reg &= ~EHCI_PS_CLEAR;
931 switch (le16_to_cpu(req->value)) {
932 case USB_PORT_FEAT_ENABLE:
933 reg &= ~EHCI_PS_PE;
934 break;
935 case USB_PORT_FEAT_C_ENABLE:
936 reg |= EHCI_PS_PE;
937 break;
938 case USB_PORT_FEAT_POWER:
939 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams)))
940 reg &= ~EHCI_PS_PP;
941 break;
942 case USB_PORT_FEAT_C_CONNECTION:
943 reg |= EHCI_PS_CSC;
944 break;
945 case USB_PORT_FEAT_OVER_CURRENT:
946 reg |= EHCI_PS_OCC;
947 break;
948 case USB_PORT_FEAT_C_RESET:
949 ctrl->portreset &= ~(1 << port);
950 break;
951 default:
952 debug("unknown feature %x\n", le16_to_cpu(req->value));
953 goto unknown;
954 }
955 ehci_writel(status_reg, reg);
956 /* unblock posted write */
957 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
958 break;
959 default:
960 debug("Unknown request\n");
961 goto unknown;
962 }
963
964 mdelay(1);
965 len = min3(srclen, (int)le16_to_cpu(req->length), length);
966 if (srcptr != NULL && len > 0)
967 memcpy(buffer, srcptr, len);
968 else
969 debug("Len is 0\n");
970
971 dev->act_len = len;
972 dev->status = 0;
973 return 0;
974
975 unknown:
976 debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
977 req->requesttype, req->request, le16_to_cpu(req->value),
978 le16_to_cpu(req->index), le16_to_cpu(req->length));
979
980 dev->act_len = 0;
981 dev->status = USB_ST_STALLED;
982 return -1;
983 }
984
985 static const struct ehci_ops default_ehci_ops = {
986 .set_usb_mode = ehci_set_usbmode,
987 .get_port_speed = ehci_get_port_speed,
988 .powerup_fixup = ehci_powerup_fixup,
989 .get_portsc_register = ehci_get_portsc_register,
990 };
991
ehci_setup_ops(struct ehci_ctrl * ctrl,const struct ehci_ops * ops)992 static void ehci_setup_ops(struct ehci_ctrl *ctrl, const struct ehci_ops *ops)
993 {
994 if (!ops) {
995 ctrl->ops = default_ehci_ops;
996 } else {
997 ctrl->ops = *ops;
998 if (!ctrl->ops.set_usb_mode)
999 ctrl->ops.set_usb_mode = ehci_set_usbmode;
1000 if (!ctrl->ops.get_port_speed)
1001 ctrl->ops.get_port_speed = ehci_get_port_speed;
1002 if (!ctrl->ops.powerup_fixup)
1003 ctrl->ops.powerup_fixup = ehci_powerup_fixup;
1004 if (!ctrl->ops.get_portsc_register)
1005 ctrl->ops.get_portsc_register =
1006 ehci_get_portsc_register;
1007 }
1008 }
1009
1010 #if !CONFIG_IS_ENABLED(DM_USB)
ehci_set_controller_priv(int index,void * priv,const struct ehci_ops * ops)1011 void ehci_set_controller_priv(int index, void *priv, const struct ehci_ops *ops)
1012 {
1013 struct ehci_ctrl *ctrl = &ehcic[index];
1014
1015 ctrl->priv = priv;
1016 ehci_setup_ops(ctrl, ops);
1017 }
1018
ehci_get_controller_priv(int index)1019 void *ehci_get_controller_priv(int index)
1020 {
1021 return ehcic[index].priv;
1022 }
1023 #endif
1024
ehci_common_init(struct ehci_ctrl * ctrl,uint tweaks)1025 static int ehci_common_init(struct ehci_ctrl *ctrl, uint tweaks)
1026 {
1027 struct QH *qh_list;
1028 struct QH *periodic;
1029 uint32_t reg;
1030 uint32_t cmd;
1031 int i;
1032
1033 /* Set the high address word (aka segment) for 64-bit controller */
1034 if (ehci_readl(&ctrl->hccr->cr_hccparams) & 1)
1035 ehci_writel(&ctrl->hcor->or_ctrldssegment, 0);
1036
1037 qh_list = &ctrl->qh_list;
1038
1039 /* Set head of reclaim list */
1040 memset(qh_list, 0, sizeof(*qh_list));
1041 qh_list->qh_link = cpu_to_hc32(virt_to_phys(qh_list) | QH_LINK_TYPE_QH);
1042 qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
1043 QH_ENDPT1_EPS(USB_SPEED_HIGH));
1044 qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1045 qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1046 qh_list->qh_overlay.qt_token =
1047 cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
1048
1049 flush_dcache_range((unsigned long)qh_list,
1050 ALIGN_END_ADDR(struct QH, qh_list, 1));
1051
1052 /* Set async. queue head pointer. */
1053 ehci_writel(&ctrl->hcor->or_asynclistaddr, virt_to_phys(qh_list));
1054
1055 /*
1056 * Set up periodic list
1057 * Step 1: Parent QH for all periodic transfers.
1058 */
1059 ctrl->periodic_schedules = 0;
1060 periodic = &ctrl->periodic_queue;
1061 memset(periodic, 0, sizeof(*periodic));
1062 periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
1063 periodic->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1064 periodic->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1065
1066 flush_dcache_range((unsigned long)periodic,
1067 ALIGN_END_ADDR(struct QH, periodic, 1));
1068
1069 /*
1070 * Step 2: Setup frame-list: Every microframe, USB tries the same list.
1071 * In particular, device specifications on polling frequency
1072 * are disregarded. Keyboards seem to send NAK/NYet reliably
1073 * when polled with an empty buffer.
1074 *
1075 * Split Transactions will be spread across microframes using
1076 * S-mask and C-mask.
1077 */
1078 if (ctrl->periodic_list == NULL)
1079 ctrl->periodic_list = memalign(4096, 1024 * 4);
1080
1081 if (!ctrl->periodic_list)
1082 return -ENOMEM;
1083 for (i = 0; i < 1024; i++) {
1084 ctrl->periodic_list[i] = cpu_to_hc32((unsigned long)periodic
1085 | QH_LINK_TYPE_QH);
1086 }
1087
1088 flush_dcache_range((unsigned long)ctrl->periodic_list,
1089 ALIGN_END_ADDR(uint32_t, ctrl->periodic_list,
1090 1024));
1091
1092 /* Set periodic list base address */
1093 ehci_writel(&ctrl->hcor->or_periodiclistbase,
1094 (unsigned long)ctrl->periodic_list);
1095
1096 reg = ehci_readl(&ctrl->hccr->cr_hcsparams);
1097 descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
1098 debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
1099 /* Port Indicators */
1100 if (HCS_INDICATOR(reg))
1101 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1102 | 0x80, &descriptor.hub.wHubCharacteristics);
1103 /* Port Power Control */
1104 if (HCS_PPC(reg))
1105 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1106 | 0x01, &descriptor.hub.wHubCharacteristics);
1107
1108 /* Start the host controller. */
1109 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
1110 /*
1111 * Philips, Intel, and maybe others need CMD_RUN before the
1112 * root hub will detect new devices (why?); NEC doesn't
1113 */
1114 cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
1115 cmd |= CMD_RUN;
1116 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
1117
1118 if (!(tweaks & EHCI_TWEAK_NO_INIT_CF)) {
1119 /* take control over the ports */
1120 cmd = ehci_readl(&ctrl->hcor->or_configflag);
1121 cmd |= FLAG_CF;
1122 ehci_writel(&ctrl->hcor->or_configflag, cmd);
1123 }
1124
1125 /* unblock posted write */
1126 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
1127 mdelay(5);
1128 reg = HC_VERSION(ehci_readl(&ctrl->hccr->cr_capbase));
1129 printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
1130
1131 return 0;
1132 }
1133
1134 #if !CONFIG_IS_ENABLED(DM_USB)
usb_lowlevel_stop(int index)1135 int usb_lowlevel_stop(int index)
1136 {
1137 ehci_shutdown(&ehcic[index]);
1138 return ehci_hcd_stop(index);
1139 }
1140
usb_lowlevel_init(int index,enum usb_init_type init,void ** controller)1141 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1142 {
1143 struct ehci_ctrl *ctrl = &ehcic[index];
1144 uint tweaks = 0;
1145 int rc;
1146
1147 /**
1148 * Set ops to default_ehci_ops, ehci_hcd_init should call
1149 * ehci_set_controller_priv to change any of these function pointers.
1150 */
1151 ctrl->ops = default_ehci_ops;
1152
1153 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
1154 if (rc)
1155 return rc;
1156 if (!ctrl->hccr || !ctrl->hcor)
1157 return -1;
1158 if (init == USB_INIT_DEVICE)
1159 goto done;
1160
1161 /* EHCI spec section 4.1 */
1162 if (ehci_reset(ctrl))
1163 return -1;
1164
1165 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
1166 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
1167 if (rc)
1168 return rc;
1169 #endif
1170 #ifdef CONFIG_USB_EHCI_FARADAY
1171 tweaks |= EHCI_TWEAK_NO_INIT_CF;
1172 #endif
1173 rc = ehci_common_init(ctrl, tweaks);
1174 if (rc)
1175 return rc;
1176
1177 ctrl->rootdev = 0;
1178 done:
1179 *controller = &ehcic[index];
1180 return 0;
1181 }
1182 #endif
1183
_ehci_submit_bulk_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int length)1184 static int _ehci_submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
1185 void *buffer, int length)
1186 {
1187
1188 if (usb_pipetype(pipe) != PIPE_BULK) {
1189 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
1190 return -1;
1191 }
1192 return ehci_submit_async(dev, pipe, buffer, length, NULL);
1193 }
1194
_ehci_submit_control_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int length,struct devrequest * setup)1195 static int _ehci_submit_control_msg(struct usb_device *dev, unsigned long pipe,
1196 void *buffer, int length,
1197 struct devrequest *setup)
1198 {
1199 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1200
1201 if (usb_pipetype(pipe) != PIPE_CONTROL) {
1202 debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
1203 return -1;
1204 }
1205
1206 if (usb_pipedevice(pipe) == ctrl->rootdev) {
1207 if (!ctrl->rootdev)
1208 dev->speed = USB_SPEED_HIGH;
1209 return ehci_submit_root(dev, pipe, buffer, length, setup);
1210 }
1211 return ehci_submit_async(dev, pipe, buffer, length, setup);
1212 }
1213
1214 struct int_queue {
1215 int elementsize;
1216 unsigned long pipe;
1217 struct QH *first;
1218 struct QH *current;
1219 struct QH *last;
1220 struct qTD *tds;
1221 };
1222
1223 #define NEXT_QH(qh) (struct QH *)((unsigned long)hc32_to_cpu((qh)->qh_link) & ~0x1f)
1224
1225 static int
enable_periodic(struct ehci_ctrl * ctrl)1226 enable_periodic(struct ehci_ctrl *ctrl)
1227 {
1228 uint32_t cmd;
1229 struct ehci_hcor *hcor = ctrl->hcor;
1230 int ret;
1231
1232 cmd = ehci_readl(&hcor->or_usbcmd);
1233 cmd |= CMD_PSE;
1234 ehci_writel(&hcor->or_usbcmd, cmd);
1235
1236 ret = handshake((uint32_t *)&hcor->or_usbsts,
1237 STS_PSS, STS_PSS, 100 * 1000);
1238 if (ret < 0) {
1239 printf("EHCI failed: timeout when enabling periodic list\n");
1240 return -ETIMEDOUT;
1241 }
1242 udelay(1000);
1243 return 0;
1244 }
1245
1246 static int
disable_periodic(struct ehci_ctrl * ctrl)1247 disable_periodic(struct ehci_ctrl *ctrl)
1248 {
1249 uint32_t cmd;
1250 struct ehci_hcor *hcor = ctrl->hcor;
1251 int ret;
1252
1253 cmd = ehci_readl(&hcor->or_usbcmd);
1254 cmd &= ~CMD_PSE;
1255 ehci_writel(&hcor->or_usbcmd, cmd);
1256
1257 ret = handshake((uint32_t *)&hcor->or_usbsts,
1258 STS_PSS, 0, 100 * 1000);
1259 if (ret < 0) {
1260 printf("EHCI failed: timeout when disabling periodic list\n");
1261 return -ETIMEDOUT;
1262 }
1263 return 0;
1264 }
1265
_ehci_create_int_queue(struct usb_device * dev,unsigned long pipe,int queuesize,int elementsize,void * buffer,int interval)1266 static struct int_queue *_ehci_create_int_queue(struct usb_device *dev,
1267 unsigned long pipe, int queuesize, int elementsize,
1268 void *buffer, int interval)
1269 {
1270 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1271 struct int_queue *result = NULL;
1272 uint32_t i, toggle;
1273
1274 /*
1275 * Interrupt transfers requiring several transactions are not supported
1276 * because bInterval is ignored.
1277 *
1278 * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
1279 * <= PKT_ALIGN if several qTDs are required, while the USB
1280 * specification does not constrain this for interrupt transfers. That
1281 * means that ehci_submit_async() would support interrupt transfers
1282 * requiring several transactions only as long as the transfer size does
1283 * not require more than a single qTD.
1284 */
1285 if (elementsize > usb_maxpacket(dev, pipe)) {
1286 printf("%s: xfers requiring several transactions are not supported.\n",
1287 __func__);
1288 return NULL;
1289 }
1290
1291 debug("Enter create_int_queue\n");
1292 if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
1293 debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
1294 return NULL;
1295 }
1296
1297 /* limit to 4 full pages worth of data -
1298 * we can safely fit them in a single TD,
1299 * no matter the alignment
1300 */
1301 if (elementsize >= 16384) {
1302 debug("too large elements for interrupt transfers\n");
1303 return NULL;
1304 }
1305
1306 result = malloc(sizeof(*result));
1307 if (!result) {
1308 debug("ehci intr queue: out of memory\n");
1309 goto fail1;
1310 }
1311 result->elementsize = elementsize;
1312 result->pipe = pipe;
1313 result->first = memalign(USB_DMA_MINALIGN,
1314 sizeof(struct QH) * queuesize);
1315 if (!result->first) {
1316 debug("ehci intr queue: out of memory\n");
1317 goto fail2;
1318 }
1319 result->current = result->first;
1320 result->last = result->first + queuesize - 1;
1321 result->tds = memalign(USB_DMA_MINALIGN,
1322 sizeof(struct qTD) * queuesize);
1323 if (!result->tds) {
1324 debug("ehci intr queue: out of memory\n");
1325 goto fail3;
1326 }
1327 memset(result->first, 0, sizeof(struct QH) * queuesize);
1328 memset(result->tds, 0, sizeof(struct qTD) * queuesize);
1329
1330 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
1331
1332 for (i = 0; i < queuesize; i++) {
1333 struct QH *qh = result->first + i;
1334 struct qTD *td = result->tds + i;
1335 void **buf = &qh->buffer;
1336
1337 qh->qh_link = cpu_to_hc32((unsigned long)(qh+1) | QH_LINK_TYPE_QH);
1338 if (i == queuesize - 1)
1339 qh->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
1340
1341 qh->qh_overlay.qt_next = cpu_to_hc32((unsigned long)td);
1342 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1343 qh->qh_endpt1 =
1344 cpu_to_hc32((0 << 28) | /* No NAK reload (ehci 4.9) */
1345 (usb_maxpacket(dev, pipe) << 16) | /* MPS */
1346 (1 << 14) |
1347 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
1348 (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */
1349 (usb_pipedevice(pipe) << 0));
1350 qh->qh_endpt2 = cpu_to_hc32((1 << 30) | /* 1 Tx per mframe */
1351 (1 << 0)); /* S-mask: microframe 0 */
1352 if (dev->speed == USB_SPEED_LOW ||
1353 dev->speed == USB_SPEED_FULL) {
1354 /* C-mask: microframes 2-4 */
1355 qh->qh_endpt2 |= cpu_to_hc32((0x1c << 8));
1356 }
1357 ehci_update_endpt2_dev_n_port(dev, qh);
1358
1359 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1360 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1361 debug("communication direction is '%s'\n",
1362 usb_pipein(pipe) ? "in" : "out");
1363 td->qt_token = cpu_to_hc32(
1364 QT_TOKEN_DT(toggle) |
1365 (elementsize << 16) |
1366 ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */
1367 0x80); /* active */
1368 td->qt_buffer[0] =
1369 cpu_to_hc32((unsigned long)buffer + i * elementsize);
1370 td->qt_buffer[1] =
1371 cpu_to_hc32((td->qt_buffer[0] + 0x1000) & ~0xfff);
1372 td->qt_buffer[2] =
1373 cpu_to_hc32((td->qt_buffer[0] + 0x2000) & ~0xfff);
1374 td->qt_buffer[3] =
1375 cpu_to_hc32((td->qt_buffer[0] + 0x3000) & ~0xfff);
1376 td->qt_buffer[4] =
1377 cpu_to_hc32((td->qt_buffer[0] + 0x4000) & ~0xfff);
1378
1379 *buf = buffer + i * elementsize;
1380 toggle ^= 1;
1381 }
1382
1383 flush_dcache_range((unsigned long)buffer,
1384 ALIGN_END_ADDR(char, buffer,
1385 queuesize * elementsize));
1386 flush_dcache_range((unsigned long)result->first,
1387 ALIGN_END_ADDR(struct QH, result->first,
1388 queuesize));
1389 flush_dcache_range((unsigned long)result->tds,
1390 ALIGN_END_ADDR(struct qTD, result->tds,
1391 queuesize));
1392
1393 if (ctrl->periodic_schedules > 0) {
1394 if (disable_periodic(ctrl) < 0) {
1395 debug("FATAL: periodic should never fail, but did");
1396 goto fail3;
1397 }
1398 }
1399
1400 /* hook up to periodic list */
1401 struct QH *list = &ctrl->periodic_queue;
1402 result->last->qh_link = list->qh_link;
1403 list->qh_link = cpu_to_hc32((unsigned long)result->first | QH_LINK_TYPE_QH);
1404
1405 flush_dcache_range((unsigned long)result->last,
1406 ALIGN_END_ADDR(struct QH, result->last, 1));
1407 flush_dcache_range((unsigned long)list,
1408 ALIGN_END_ADDR(struct QH, list, 1));
1409
1410 if (enable_periodic(ctrl) < 0) {
1411 debug("FATAL: periodic should never fail, but did");
1412 goto fail3;
1413 }
1414 ctrl->periodic_schedules++;
1415
1416 debug("Exit create_int_queue\n");
1417 return result;
1418 fail3:
1419 free(result->tds);
1420 fail2:
1421 free(result->first);
1422 free(result);
1423 fail1:
1424 return NULL;
1425 }
1426
_ehci_poll_int_queue(struct usb_device * dev,struct int_queue * queue)1427 static void *_ehci_poll_int_queue(struct usb_device *dev,
1428 struct int_queue *queue)
1429 {
1430 struct QH *cur = queue->current;
1431 struct qTD *cur_td;
1432 uint32_t token, toggle;
1433 unsigned long pipe = queue->pipe;
1434
1435 /* depleted queue */
1436 if (cur == NULL) {
1437 debug("Exit poll_int_queue with completed queue\n");
1438 return NULL;
1439 }
1440 /* still active */
1441 cur_td = &queue->tds[queue->current - queue->first];
1442 invalidate_dcache_range((unsigned long)cur_td,
1443 ALIGN_END_ADDR(struct qTD, cur_td, 1));
1444 token = hc32_to_cpu(cur_td->qt_token);
1445 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE) {
1446 debug("Exit poll_int_queue with no completed intr transfer. token is %x\n", token);
1447 return NULL;
1448 }
1449
1450 toggle = QT_TOKEN_GET_DT(token);
1451 usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), toggle);
1452
1453 if (!(cur->qh_link & QH_LINK_TERMINATE))
1454 queue->current++;
1455 else
1456 queue->current = NULL;
1457
1458 invalidate_dcache_range((unsigned long)cur->buffer,
1459 ALIGN_END_ADDR(char, cur->buffer,
1460 queue->elementsize));
1461
1462 debug("Exit poll_int_queue with completed intr transfer. token is %x at %p (first at %p)\n",
1463 token, cur, queue->first);
1464 return cur->buffer;
1465 }
1466
1467 /* Do not free buffers associated with QHs, they're owned by someone else */
_ehci_destroy_int_queue(struct usb_device * dev,struct int_queue * queue)1468 static int _ehci_destroy_int_queue(struct usb_device *dev,
1469 struct int_queue *queue)
1470 {
1471 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1472 int result = -1;
1473 unsigned long timeout;
1474
1475 if (disable_periodic(ctrl) < 0) {
1476 debug("FATAL: periodic should never fail, but did");
1477 goto out;
1478 }
1479 ctrl->periodic_schedules--;
1480
1481 struct QH *cur = &ctrl->periodic_queue;
1482 timeout = get_timer(0) + 500; /* abort after 500ms */
1483 while (!(cur->qh_link & cpu_to_hc32(QH_LINK_TERMINATE))) {
1484 debug("considering %p, with qh_link %x\n", cur, cur->qh_link);
1485 if (NEXT_QH(cur) == queue->first) {
1486 debug("found candidate. removing from chain\n");
1487 cur->qh_link = queue->last->qh_link;
1488 flush_dcache_range((unsigned long)cur,
1489 ALIGN_END_ADDR(struct QH, cur, 1));
1490 result = 0;
1491 break;
1492 }
1493 cur = NEXT_QH(cur);
1494 if (get_timer(0) > timeout) {
1495 printf("Timeout destroying interrupt endpoint queue\n");
1496 result = -1;
1497 goto out;
1498 }
1499 }
1500
1501 if (ctrl->periodic_schedules > 0) {
1502 result = enable_periodic(ctrl);
1503 if (result < 0)
1504 debug("FATAL: periodic should never fail, but did");
1505 }
1506
1507 out:
1508 free(queue->tds);
1509 free(queue->first);
1510 free(queue);
1511
1512 return result;
1513 }
1514
_ehci_submit_int_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int length,int interval,bool nonblock)1515 static int _ehci_submit_int_msg(struct usb_device *dev, unsigned long pipe,
1516 void *buffer, int length, int interval,
1517 bool nonblock)
1518 {
1519 void *backbuffer;
1520 struct int_queue *queue;
1521 unsigned long timeout;
1522 int result = 0, ret;
1523
1524 debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
1525 dev, pipe, buffer, length, interval);
1526
1527 queue = _ehci_create_int_queue(dev, pipe, 1, length, buffer, interval);
1528 if (!queue)
1529 return -1;
1530
1531 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1532 while ((backbuffer = _ehci_poll_int_queue(dev, queue)) == NULL)
1533 if (get_timer(0) > timeout) {
1534 printf("Timeout poll on interrupt endpoint\n");
1535 result = -ETIMEDOUT;
1536 break;
1537 }
1538
1539 if (backbuffer != buffer) {
1540 debug("got wrong buffer back (%p instead of %p)\n",
1541 backbuffer, buffer);
1542 return -EINVAL;
1543 }
1544
1545 ret = _ehci_destroy_int_queue(dev, queue);
1546 if (ret < 0)
1547 return ret;
1548
1549 /* everything worked out fine */
1550 return result;
1551 }
1552
_ehci_lock_async(struct ehci_ctrl * ctrl,int lock)1553 static int _ehci_lock_async(struct ehci_ctrl *ctrl, int lock)
1554 {
1555 ctrl->async_locked = lock;
1556
1557 if (lock)
1558 return 0;
1559
1560 return ehci_disable_async(ctrl);
1561 }
1562
1563 #if !CONFIG_IS_ENABLED(DM_USB)
submit_bulk_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int length)1564 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
1565 void *buffer, int length)
1566 {
1567 return _ehci_submit_bulk_msg(dev, pipe, buffer, length);
1568 }
1569
submit_control_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int length,struct devrequest * setup)1570 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1571 int length, struct devrequest *setup)
1572 {
1573 return _ehci_submit_control_msg(dev, pipe, buffer, length, setup);
1574 }
1575
submit_int_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int length,int interval,bool nonblock)1576 int submit_int_msg(struct usb_device *dev, unsigned long pipe,
1577 void *buffer, int length, int interval, bool nonblock)
1578 {
1579 return _ehci_submit_int_msg(dev, pipe, buffer, length, interval,
1580 nonblock);
1581 }
1582
create_int_queue(struct usb_device * dev,unsigned long pipe,int queuesize,int elementsize,void * buffer,int interval)1583 struct int_queue *create_int_queue(struct usb_device *dev,
1584 unsigned long pipe, int queuesize, int elementsize,
1585 void *buffer, int interval)
1586 {
1587 return _ehci_create_int_queue(dev, pipe, queuesize, elementsize,
1588 buffer, interval);
1589 }
1590
poll_int_queue(struct usb_device * dev,struct int_queue * queue)1591 void *poll_int_queue(struct usb_device *dev, struct int_queue *queue)
1592 {
1593 return _ehci_poll_int_queue(dev, queue);
1594 }
1595
destroy_int_queue(struct usb_device * dev,struct int_queue * queue)1596 int destroy_int_queue(struct usb_device *dev, struct int_queue *queue)
1597 {
1598 return _ehci_destroy_int_queue(dev, queue);
1599 }
1600
usb_lock_async(struct usb_device * dev,int lock)1601 int usb_lock_async(struct usb_device *dev, int lock)
1602 {
1603 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1604
1605 return _ehci_lock_async(ctrl, lock);
1606 }
1607 #endif
1608
1609 #if CONFIG_IS_ENABLED(DM_USB)
ehci_submit_control_msg(struct udevice * dev,struct usb_device * udev,unsigned long pipe,void * buffer,int length,struct devrequest * setup)1610 static int ehci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1611 unsigned long pipe, void *buffer, int length,
1612 struct devrequest *setup)
1613 {
1614 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1615 dev->name, udev, udev->dev->name, udev->portnr);
1616
1617 return _ehci_submit_control_msg(udev, pipe, buffer, length, setup);
1618 }
1619
ehci_submit_bulk_msg(struct udevice * dev,struct usb_device * udev,unsigned long pipe,void * buffer,int length)1620 static int ehci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1621 unsigned long pipe, void *buffer, int length)
1622 {
1623 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1624 return _ehci_submit_bulk_msg(udev, pipe, buffer, length);
1625 }
1626
ehci_submit_int_msg(struct udevice * dev,struct usb_device * udev,unsigned long pipe,void * buffer,int length,int interval,bool nonblock)1627 static int ehci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1628 unsigned long pipe, void *buffer, int length,
1629 int interval, bool nonblock)
1630 {
1631 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1632 return _ehci_submit_int_msg(udev, pipe, buffer, length, interval,
1633 nonblock);
1634 }
1635
ehci_create_int_queue(struct udevice * dev,struct usb_device * udev,unsigned long pipe,int queuesize,int elementsize,void * buffer,int interval)1636 static struct int_queue *ehci_create_int_queue(struct udevice *dev,
1637 struct usb_device *udev, unsigned long pipe, int queuesize,
1638 int elementsize, void *buffer, int interval)
1639 {
1640 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1641 return _ehci_create_int_queue(udev, pipe, queuesize, elementsize,
1642 buffer, interval);
1643 }
1644
ehci_poll_int_queue(struct udevice * dev,struct usb_device * udev,struct int_queue * queue)1645 static void *ehci_poll_int_queue(struct udevice *dev, struct usb_device *udev,
1646 struct int_queue *queue)
1647 {
1648 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1649 return _ehci_poll_int_queue(udev, queue);
1650 }
1651
ehci_destroy_int_queue(struct udevice * dev,struct usb_device * udev,struct int_queue * queue)1652 static int ehci_destroy_int_queue(struct udevice *dev, struct usb_device *udev,
1653 struct int_queue *queue)
1654 {
1655 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1656 return _ehci_destroy_int_queue(udev, queue);
1657 }
1658
ehci_get_max_xfer_size(struct udevice * dev,size_t * size)1659 static int ehci_get_max_xfer_size(struct udevice *dev, size_t *size)
1660 {
1661 /*
1662 * EHCD can handle any transfer length as long as there is enough
1663 * free heap space left, hence set the theoretical max number here.
1664 */
1665 *size = SIZE_MAX;
1666
1667 return 0;
1668 }
1669
ehci_lock_async(struct udevice * dev,int lock)1670 static int ehci_lock_async(struct udevice *dev, int lock)
1671 {
1672 struct ehci_ctrl *ctrl = dev_get_priv(dev);
1673
1674 return _ehci_lock_async(ctrl, lock);
1675 }
1676
ehci_register(struct udevice * dev,struct ehci_hccr * hccr,struct ehci_hcor * hcor,const struct ehci_ops * ops,uint tweaks,enum usb_init_type init)1677 int ehci_register(struct udevice *dev, struct ehci_hccr *hccr,
1678 struct ehci_hcor *hcor, const struct ehci_ops *ops,
1679 uint tweaks, enum usb_init_type init)
1680 {
1681 struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
1682 struct ehci_ctrl *ctrl = dev_get_priv(dev);
1683 int ret = -1;
1684
1685 debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p, init=%d\n", __func__,
1686 dev->name, ctrl, hccr, hcor, init);
1687
1688 if (!ctrl || !hccr || !hcor)
1689 goto err;
1690
1691 priv->desc_before_addr = true;
1692
1693 ehci_setup_ops(ctrl, ops);
1694 ctrl->hccr = hccr;
1695 ctrl->hcor = hcor;
1696 ctrl->priv = ctrl;
1697
1698 ctrl->init = init;
1699 if (ctrl->init == USB_INIT_DEVICE)
1700 goto done;
1701
1702 ret = ehci_reset(ctrl);
1703 if (ret)
1704 goto err;
1705
1706 if (ctrl->ops.init_after_reset) {
1707 ret = ctrl->ops.init_after_reset(ctrl);
1708 if (ret)
1709 goto err;
1710 }
1711
1712 ret = ehci_common_init(ctrl, tweaks);
1713 if (ret)
1714 goto err;
1715 done:
1716 return 0;
1717 err:
1718 free(ctrl);
1719 debug("%s: failed, ret=%d\n", __func__, ret);
1720 return ret;
1721 }
1722
ehci_deregister(struct udevice * dev)1723 int ehci_deregister(struct udevice *dev)
1724 {
1725 struct ehci_ctrl *ctrl = dev_get_priv(dev);
1726
1727 if (ctrl->init == USB_INIT_DEVICE)
1728 return 0;
1729
1730 ehci_shutdown(ctrl);
1731
1732 return 0;
1733 }
1734
1735 struct dm_usb_ops ehci_usb_ops = {
1736 .control = ehci_submit_control_msg,
1737 .bulk = ehci_submit_bulk_msg,
1738 .interrupt = ehci_submit_int_msg,
1739 .create_int_queue = ehci_create_int_queue,
1740 .poll_int_queue = ehci_poll_int_queue,
1741 .destroy_int_queue = ehci_destroy_int_queue,
1742 .get_max_xfer_size = ehci_get_max_xfer_size,
1743 .lock_async = ehci_lock_async,
1744 };
1745
1746 #endif
1747
1748 #ifdef CONFIG_PHY
ehci_setup_phy(struct udevice * dev,struct phy * phy,int index)1749 int ehci_setup_phy(struct udevice *dev, struct phy *phy, int index)
1750 {
1751 int ret;
1752
1753 if (!phy)
1754 return 0;
1755
1756 ret = generic_phy_get_by_index(dev, index, phy);
1757 if (ret) {
1758 if (ret != -ENOENT) {
1759 dev_err(dev, "failed to get usb phy\n");
1760 return ret;
1761 }
1762 } else {
1763 ret = generic_phy_init(phy);
1764 if (ret) {
1765 dev_err(dev, "failed to init usb phy\n");
1766 return ret;
1767 }
1768
1769 ret = generic_phy_power_on(phy);
1770 if (ret) {
1771 dev_err(dev, "failed to power on usb phy\n");
1772 return generic_phy_exit(phy);
1773 }
1774 }
1775
1776 return 0;
1777 }
1778
ehci_shutdown_phy(struct udevice * dev,struct phy * phy)1779 int ehci_shutdown_phy(struct udevice *dev, struct phy *phy)
1780 {
1781 int ret = 0;
1782
1783 if (!phy)
1784 return 0;
1785
1786 if (generic_phy_valid(phy)) {
1787 ret = generic_phy_power_off(phy);
1788 if (ret) {
1789 dev_err(dev, "failed to power off usb phy\n");
1790 return ret;
1791 }
1792
1793 ret = generic_phy_exit(phy);
1794 if (ret) {
1795 dev_err(dev, "failed to power off usb phy\n");
1796 return ret;
1797 }
1798 }
1799
1800 return 0;
1801 }
1802 #else
ehci_setup_phy(struct udevice * dev,struct phy * phy,int index)1803 int ehci_setup_phy(struct udevice *dev, struct phy *phy, int index)
1804 {
1805 return 0;
1806 }
1807
ehci_shutdown_phy(struct udevice * dev,struct phy * phy)1808 int ehci_shutdown_phy(struct udevice *dev, struct phy *phy)
1809 {
1810 return 0;
1811 }
1812 #endif
1813