1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2011-2012 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __CONFIG_H 7 #define __CONFIG_H 8 9 #include <linux/stringify.h> 10 11 /* 12 * B4860 QDS board configuration file 13 */ 14 #ifdef CONFIG_RAMBOOT_PBL 15 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg 16 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg 17 #ifndef CONFIG_MTD_RAW_NAND 18 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 19 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 20 #else 21 #define CONFIG_SPL_FLUSH_IMAGE 22 #define CONFIG_SPL_PAD_TO 0x40000 23 #define CONFIG_SPL_MAX_SIZE 0x28000 24 #define RESET_VECTOR_OFFSET 0x27FFC 25 #define BOOT_PAGE_OFFSET 0x27000 26 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 27 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 28 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 29 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 30 #ifdef CONFIG_SPL_BUILD 31 #define CONFIG_SPL_SKIP_RELOCATE 32 #define CONFIG_SPL_COMMON_INIT_DDR 33 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 34 #endif 35 #endif 36 #endif 37 38 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 39 /* Set 1M boot space */ 40 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 42 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 43 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 44 #endif 45 46 /* High Level Configuration Options */ 47 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 48 49 #ifndef CONFIG_RESET_VECTOR_ADDRESS 50 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 51 #endif 52 53 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 54 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 55 #define CONFIG_PCIE1 /* PCIE controller 1 */ 56 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 57 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 58 59 #ifndef CONFIG_ARCH_B4420 60 #define CONFIG_SYS_SRIO 61 #define CONFIG_SRIO1 /* SRIO port 1 */ 62 #define CONFIG_SRIO2 /* SRIO port 2 */ 63 #define CONFIG_SRIO_PCIE_BOOT_MASTER 64 #endif 65 66 /* I2C bus multiplexer */ 67 #define I2C_MUX_PCA_ADDR 0x77 68 69 /* VSC Crossbar switches */ 70 #define CONFIG_VSC_CROSSBAR 71 #define I2C_CH_DEFAULT 0x8 72 #define I2C_CH_VSC3316 0xc 73 #define I2C_CH_VSC3308 0xd 74 75 #define VSC3316_TX_ADDRESS 0x70 76 #define VSC3316_RX_ADDRESS 0x71 77 #define VSC3308_TX_ADDRESS 0x02 78 #define VSC3308_RX_ADDRESS 0x03 79 80 /* IDT clock synthesizers */ 81 #define CONFIG_IDT8T49N222A 82 #define I2C_CH_IDT 0x9 83 84 #define IDT_SERDES1_ADDRESS 0x6E 85 #define IDT_SERDES2_ADDRESS 0x6C 86 87 /* Voltage monitor on channel 2*/ 88 #define I2C_MUX_CH_VOL_MONITOR 0xa 89 #define I2C_VOL_MONITOR_ADDR 0x40 90 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 91 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 92 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 93 94 #define CONFIG_ZM7300 95 #define I2C_MUX_CH_DPM 0xa 96 #define I2C_DPM_ADDR 0x28 97 98 #define CONFIG_ENV_OVERWRITE 99 100 #if defined(CONFIG_SPIFLASH) 101 #elif defined(CONFIG_SDCARD) 102 #define CONFIG_SYS_MMC_ENV_DEV 0 103 #endif 104 105 #ifndef __ASSEMBLY__ 106 unsigned long get_board_sys_clk(void); 107 unsigned long get_board_ddr_clk(void); 108 #endif 109 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 110 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 111 112 /* 113 * These can be toggled for performance analysis, otherwise use default. 114 */ 115 #define CONFIG_SYS_CACHE_STASHING 116 #define CONFIG_BTB /* toggle branch predition */ 117 #define CONFIG_DDR_ECC 118 #ifdef CONFIG_DDR_ECC 119 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 120 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 121 #endif 122 123 #define CONFIG_ENABLE_36BIT_PHYS 124 125 #ifdef CONFIG_PHYS_64BIT 126 #define CONFIG_ADDR_MAP 127 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 128 #endif 129 130 #if 0 131 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 132 #endif 133 134 /* 135 * Config the L3 Cache as L3 SRAM 136 */ 137 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 138 #define CONFIG_SYS_L3_SIZE 256 << 10 139 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 140 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 141 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 142 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 143 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 144 145 #ifdef CONFIG_PHYS_64BIT 146 #define CONFIG_SYS_DCSRBAR 0xf0000000 147 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 148 #endif 149 150 /* EEPROM */ 151 #define CONFIG_ID_EEPROM 152 #define CONFIG_SYS_I2C_EEPROM_NXID 153 #define CONFIG_SYS_EEPROM_BUS_NUM 0 154 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 155 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 156 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 157 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 158 159 /* 160 * DDR Setup 161 */ 162 #define CONFIG_VERY_BIG_RAM 163 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 164 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 165 166 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 167 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 168 169 #define CONFIG_DDR_SPD 170 #define CONFIG_SYS_DDR_RAW_TIMING 171 172 #define CONFIG_SYS_SPD_BUS_NUM 0 173 #define SPD_EEPROM_ADDRESS1 0x51 174 #define SPD_EEPROM_ADDRESS2 0x53 175 176 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 177 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 178 179 /* 180 * IFC Definitions 181 */ 182 #define CONFIG_SYS_FLASH_BASE 0xe0000000 183 #ifdef CONFIG_PHYS_64BIT 184 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 185 #else 186 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 187 #endif 188 189 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 190 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 191 + 0x8000000) | \ 192 CSPR_PORT_SIZE_16 | \ 193 CSPR_MSEL_NOR | \ 194 CSPR_V) 195 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 196 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 197 CSPR_PORT_SIZE_16 | \ 198 CSPR_MSEL_NOR | \ 199 CSPR_V) 200 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 201 /* NOR Flash Timing Params */ 202 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 203 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ 204 FTIM0_NOR_TEADC(0x04) | \ 205 FTIM0_NOR_TEAHC(0x20)) 206 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 207 FTIM1_NOR_TRAD_NOR(0x1A) |\ 208 FTIM1_NOR_TSEQRAD_NOR(0x13)) 209 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ 210 FTIM2_NOR_TCH(0x0E) | \ 211 FTIM2_NOR_TWPH(0x0E) | \ 212 FTIM2_NOR_TWP(0x1c)) 213 #define CONFIG_SYS_NOR_FTIM3 0x0 214 215 #define CONFIG_SYS_FLASH_QUIET_TEST 216 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 217 218 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 219 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 220 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 221 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 222 223 #define CONFIG_SYS_FLASH_EMPTY_INFO 224 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 225 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 226 227 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 228 #define CONFIG_FSL_QIXIS_V2 229 #define QIXIS_BASE 0xffdf0000 230 #ifdef CONFIG_PHYS_64BIT 231 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 232 #else 233 #define QIXIS_BASE_PHYS QIXIS_BASE 234 #endif 235 #define QIXIS_LBMAP_SWITCH 0x01 236 #define QIXIS_LBMAP_MASK 0x0f 237 #define QIXIS_LBMAP_SHIFT 0 238 #define QIXIS_LBMAP_DFLTBANK 0x00 239 #define QIXIS_LBMAP_ALTBANK 0x02 240 #define QIXIS_RST_CTL_RESET 0x31 241 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 242 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 243 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 244 245 #define CONFIG_SYS_CSPR3_EXT (0xf) 246 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 247 | CSPR_PORT_SIZE_8 \ 248 | CSPR_MSEL_GPCM \ 249 | CSPR_V) 250 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) 251 #define CONFIG_SYS_CSOR3 0x0 252 /* QIXIS Timing parameters for IFC CS3 */ 253 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 254 FTIM0_GPCM_TEADC(0x0e) | \ 255 FTIM0_GPCM_TEAHC(0x0e)) 256 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 257 FTIM1_GPCM_TRAD(0x1f)) 258 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 259 FTIM2_GPCM_TCH(0x8) | \ 260 FTIM2_GPCM_TWP(0x1f)) 261 #define CONFIG_SYS_CS3_FTIM3 0x0 262 263 /* NAND Flash on IFC */ 264 #define CONFIG_NAND_FSL_IFC 265 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 266 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 267 #define CONFIG_SYS_NAND_BASE 0xff800000 268 #ifdef CONFIG_PHYS_64BIT 269 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 270 #else 271 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 272 #endif 273 274 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 275 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 276 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 277 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 278 | CSPR_V) 279 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 280 281 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 282 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 283 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 284 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 285 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 286 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 287 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 288 289 #define CONFIG_SYS_NAND_ONFI_DETECTION 290 291 /* ONFI NAND Flash mode0 Timing Params */ 292 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 293 FTIM0_NAND_TWP(0x18) | \ 294 FTIM0_NAND_TWCHT(0x07) | \ 295 FTIM0_NAND_TWH(0x0a)) 296 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 297 FTIM1_NAND_TWBE(0x39) | \ 298 FTIM1_NAND_TRR(0x0e) | \ 299 FTIM1_NAND_TRP(0x18)) 300 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 301 FTIM2_NAND_TREH(0x0a) | \ 302 FTIM2_NAND_TWHRE(0x1e)) 303 #define CONFIG_SYS_NAND_FTIM3 0x0 304 305 #define CONFIG_SYS_NAND_DDR_LAW 11 306 307 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 308 #define CONFIG_SYS_MAX_NAND_DEVICE 1 309 310 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 311 312 #if defined(CONFIG_MTD_RAW_NAND) 313 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 314 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 315 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 316 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 317 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 318 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 319 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 320 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 321 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 322 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 323 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 324 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 325 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 326 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 327 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 328 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 329 #else 330 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 331 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 332 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 333 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 334 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 335 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 336 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 337 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 338 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 339 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 340 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 341 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 342 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 343 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 344 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 345 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 346 #endif 347 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 348 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 349 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 350 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 351 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 352 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 353 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 354 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 355 356 #ifdef CONFIG_SPL_BUILD 357 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 358 #else 359 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 360 #endif 361 362 #if defined(CONFIG_RAMBOOT_PBL) 363 #define CONFIG_SYS_RAMBOOT 364 #endif 365 366 #define CONFIG_HWCONFIG 367 368 /* define to use L1 as initial stack */ 369 #define CONFIG_L1_INIT_RAM 370 #define CONFIG_SYS_INIT_RAM_LOCK 371 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 372 #ifdef CONFIG_PHYS_64BIT 373 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 374 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 375 /* The assembler doesn't like typecast */ 376 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 377 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 378 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 379 #else 380 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 381 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 382 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 383 #endif 384 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 385 386 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 387 GENERATED_GBL_DATA_SIZE) 388 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 389 390 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 391 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 392 393 /* Serial Port - controlled on board with jumper J8 394 * open - index 2 395 * shorted - index 1 396 */ 397 #define CONFIG_SYS_NS16550_SERIAL 398 #define CONFIG_SYS_NS16550_REG_SIZE 1 399 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 400 401 #define CONFIG_SYS_BAUDRATE_TABLE \ 402 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 403 404 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 405 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 406 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 407 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 408 409 /* I2C */ 410 #define CONFIG_SYS_I2C 411 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 412 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 413 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 414 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ 415 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 416 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 417 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 418 419 /* 420 * RTC configuration 421 */ 422 #define RTC 423 #define CONFIG_RTC_DS3231 1 424 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 425 426 /* 427 * RapidIO 428 */ 429 #ifdef CONFIG_SYS_SRIO 430 #ifdef CONFIG_SRIO1 431 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 432 #ifdef CONFIG_PHYS_64BIT 433 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 434 #else 435 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 436 #endif 437 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 438 #endif 439 440 #ifdef CONFIG_SRIO2 441 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 442 #ifdef CONFIG_PHYS_64BIT 443 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 444 #else 445 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 446 #endif 447 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 448 #endif 449 #endif 450 451 /* 452 * for slave u-boot IMAGE instored in master memory space, 453 * PHYS must be aligned based on the SIZE 454 */ 455 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 456 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 457 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 458 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 459 /* 460 * for slave UCODE and ENV instored in master memory space, 461 * PHYS must be aligned based on the SIZE 462 */ 463 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 464 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 465 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 466 467 /* slave core release by master*/ 468 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 469 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 470 471 /* 472 * SRIO_PCIE_BOOT - SLAVE 473 */ 474 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 475 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 476 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 477 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 478 #endif 479 480 /* 481 * eSPI - Enhanced SPI 482 */ 483 484 /* 485 * MAPLE 486 */ 487 #ifdef CONFIG_PHYS_64BIT 488 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull 489 #else 490 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000 491 #endif 492 493 /* 494 * General PCI 495 * Memory space is mapped 1-1, but I/O space must start from 0. 496 */ 497 498 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 499 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 500 #ifdef CONFIG_PHYS_64BIT 501 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 502 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 503 #else 504 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 505 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 506 #endif 507 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 508 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 509 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 510 #ifdef CONFIG_PHYS_64BIT 511 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 512 #else 513 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 514 #endif 515 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 516 517 /* Qman/Bman */ 518 #ifndef CONFIG_NOBQFMAN 519 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 520 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 521 #ifdef CONFIG_PHYS_64BIT 522 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 523 #else 524 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 525 #endif 526 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 527 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 528 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 529 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 530 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 531 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 532 CONFIG_SYS_BMAN_CENA_SIZE) 533 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 534 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 535 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 536 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 537 #ifdef CONFIG_PHYS_64BIT 538 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 539 #else 540 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 541 #endif 542 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 543 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 544 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 545 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 546 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 547 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 548 CONFIG_SYS_QMAN_CENA_SIZE) 549 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 550 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 551 552 #define CONFIG_SYS_DPAA_FMAN 553 554 #define CONFIG_SYS_DPAA_RMAN 555 556 /* Default address of microcode for the Linux Fman driver */ 557 #if defined(CONFIG_SPIFLASH) 558 /* 559 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 560 * env, so we got 0x110000. 561 */ 562 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 563 #elif defined(CONFIG_SDCARD) 564 /* 565 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 566 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 567 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 568 */ 569 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130) 570 #elif defined(CONFIG_MTD_RAW_NAND) 571 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE) 572 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 573 /* 574 * Slave has no ucode locally, it can fetch this from remote. When implementing 575 * in two corenet boards, slave's ucode could be stored in master's memory 576 * space, the address can be mapped from slave TLB->slave LAW-> 577 * slave SRIO or PCIE outbound window->master inbound window-> 578 * master LAW->the ucode address in master's memory space. 579 */ 580 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 581 #else 582 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 583 #endif 584 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 585 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 586 #endif /* CONFIG_NOBQFMAN */ 587 588 #ifdef CONFIG_SYS_DPAA_FMAN 589 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 590 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 591 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 592 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 593 #endif 594 595 #ifdef CONFIG_PCI 596 #define CONFIG_PCI_INDIRECT_BRIDGE 597 598 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 599 #endif /* CONFIG_PCI */ 600 601 #ifdef CONFIG_FMAN_ENET 602 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10 603 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11 604 605 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */ 606 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ 607 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/ 608 609 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 610 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 611 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 612 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 613 614 #define CONFIG_ETHPRIME "FM1@DTSEC1" 615 #endif 616 617 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR 618 619 /* 620 * Environment 621 */ 622 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 623 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 624 625 /* 626 * USB 627 */ 628 #define CONFIG_HAS_FSL_DR_USB 629 630 #ifdef CONFIG_HAS_FSL_DR_USB 631 #ifdef CONFIG_USB_EHCI_HCD 632 #define CONFIG_USB_EHCI_FSL 633 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 634 #endif 635 #endif 636 637 /* 638 * Miscellaneous configurable options 639 */ 640 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 641 642 /* 643 * For booting Linux, the board info and command line data 644 * have to be in the first 64 MB of memory, since this is 645 * the maximum mapped by the Linux kernel during initialization. 646 */ 647 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 648 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 649 650 #ifdef CONFIG_CMD_KGDB 651 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 652 #endif 653 654 /* 655 * Environment Configuration 656 */ 657 #define CONFIG_ROOTPATH "/opt/nfsroot" 658 #define CONFIG_BOOTFILE "uImage" 659 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 660 661 /* default location for tftp and bootm */ 662 #define CONFIG_LOADADDR 1000000 663 664 #define __USB_PHY_TYPE ulpi 665 666 #ifdef CONFIG_ARCH_B4860 667 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \ 668 "bank_intlv=cs0_cs1;" \ 669 "en_cpc:cpc2;" 670 #else 671 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;" 672 #endif 673 674 #define CONFIG_EXTRA_ENV_SETTINGS \ 675 HWCONFIG \ 676 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 677 "netdev=eth0\0" \ 678 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 679 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 680 "tftpflash=tftpboot $loadaddr $uboot && " \ 681 "protect off $ubootaddr +$filesize && " \ 682 "erase $ubootaddr +$filesize && " \ 683 "cp.b $loadaddr $ubootaddr $filesize && " \ 684 "protect on $ubootaddr +$filesize && " \ 685 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 686 "consoledev=ttyS0\0" \ 687 "ramdiskaddr=2000000\0" \ 688 "ramdiskfile=b4860qds/ramdisk.uboot\0" \ 689 "fdtaddr=1e00000\0" \ 690 "fdtfile=b4860qds/b4860qds.dtb\0" \ 691 "bdev=sda3\0" 692 693 /* For emulation this causes u-boot to jump to the start of the proof point 694 app code automatically */ 695 #define CONFIG_PROOF_POINTS \ 696 "setenv bootargs root=/dev/$bdev rw " \ 697 "console=$consoledev,$baudrate $othbootargs;" \ 698 "cpu 1 release 0x29000000 - - -;" \ 699 "cpu 2 release 0x29000000 - - -;" \ 700 "cpu 3 release 0x29000000 - - -;" \ 701 "cpu 4 release 0x29000000 - - -;" \ 702 "cpu 5 release 0x29000000 - - -;" \ 703 "cpu 6 release 0x29000000 - - -;" \ 704 "cpu 7 release 0x29000000 - - -;" \ 705 "go 0x29000000" 706 707 #define CONFIG_HVBOOT \ 708 "setenv bootargs config-addr=0x60000000; " \ 709 "bootm 0x01000000 - 0x00f00000" 710 711 #define CONFIG_ALU \ 712 "setenv bootargs root=/dev/$bdev rw " \ 713 "console=$consoledev,$baudrate $othbootargs;" \ 714 "cpu 1 release 0x01000000 - - -;" \ 715 "cpu 2 release 0x01000000 - - -;" \ 716 "cpu 3 release 0x01000000 - - -;" \ 717 "cpu 4 release 0x01000000 - - -;" \ 718 "cpu 5 release 0x01000000 - - -;" \ 719 "cpu 6 release 0x01000000 - - -;" \ 720 "cpu 7 release 0x01000000 - - -;" \ 721 "go 0x01000000" 722 723 #define CONFIG_LINUX \ 724 "setenv bootargs root=/dev/ram rw " \ 725 "console=$consoledev,$baudrate $othbootargs;" \ 726 "setenv ramdiskaddr 0x02000000;" \ 727 "setenv fdtaddr 0x01e00000;" \ 728 "setenv loadaddr 0x1000000;" \ 729 "bootm $loadaddr $ramdiskaddr $fdtaddr" 730 731 #define CONFIG_HDBOOT \ 732 "setenv bootargs root=/dev/$bdev rw " \ 733 "console=$consoledev,$baudrate $othbootargs;" \ 734 "tftp $loadaddr $bootfile;" \ 735 "tftp $fdtaddr $fdtfile;" \ 736 "bootm $loadaddr - $fdtaddr" 737 738 #define CONFIG_NFSBOOTCOMMAND \ 739 "setenv bootargs root=/dev/nfs rw " \ 740 "nfsroot=$serverip:$rootpath " \ 741 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 742 "console=$consoledev,$baudrate $othbootargs;" \ 743 "tftp $loadaddr $bootfile;" \ 744 "tftp $fdtaddr $fdtfile;" \ 745 "bootm $loadaddr - $fdtaddr" 746 747 #define CONFIG_RAMBOOTCOMMAND \ 748 "setenv bootargs root=/dev/ram rw " \ 749 "console=$consoledev,$baudrate $othbootargs;" \ 750 "tftp $ramdiskaddr $ramdiskfile;" \ 751 "tftp $loadaddr $bootfile;" \ 752 "tftp $fdtaddr $fdtfile;" \ 753 "bootm $loadaddr $ramdiskaddr $fdtaddr" 754 755 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 756 757 #include <asm/fsl_secure_boot.h> 758 759 #endif /* __CONFIG_H */ 760