1 /*
2 * (C) Copyright 2015
3 * Kamil Lulko, <rev13@wp.pl>
4 *
5 * (C) Copyright 2014
6 * STMicroelectronics
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11 #include <common.h>
12 #include <asm/io.h>
13 #include <asm/arch/stm32.h>
14
15 #define RCC_CR_HSION (1 << 0)
16 #define RCC_CR_HSEON (1 << 16)
17 #define RCC_CR_HSERDY (1 << 17)
18 #define RCC_CR_HSEBYP (1 << 18)
19 #define RCC_CR_CSSON (1 << 19)
20 #define RCC_CR_PLLON (1 << 24)
21 #define RCC_CR_PLLRDY (1 << 25)
22
23 #define RCC_PLLCFGR_PLLM_MASK 0x3F
24 #define RCC_PLLCFGR_PLLN_MASK 0x7FC0
25 #define RCC_PLLCFGR_PLLP_MASK 0x30000
26 #define RCC_PLLCFGR_PLLQ_MASK 0xF000000
27 #define RCC_PLLCFGR_PLLSRC (1 << 22)
28 #define RCC_PLLCFGR_PLLN_SHIFT 6
29 #define RCC_PLLCFGR_PLLP_SHIFT 16
30 #define RCC_PLLCFGR_PLLQ_SHIFT 24
31
32 #define RCC_CFGR_AHB_PSC_MASK 0xF0
33 #define RCC_CFGR_APB1_PSC_MASK 0x1C00
34 #define RCC_CFGR_APB2_PSC_MASK 0xE000
35 #define RCC_CFGR_SW0 (1 << 0)
36 #define RCC_CFGR_SW1 (1 << 1)
37 #define RCC_CFGR_SW_MASK 0x3
38 #define RCC_CFGR_SW_HSI 0
39 #define RCC_CFGR_SW_HSE RCC_CFGR_SW0
40 #define RCC_CFGR_SW_PLL RCC_CFGR_SW1
41 #define RCC_CFGR_SWS0 (1 << 2)
42 #define RCC_CFGR_SWS1 (1 << 3)
43 #define RCC_CFGR_SWS_MASK 0xC
44 #define RCC_CFGR_SWS_HSI 0
45 #define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
46 #define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
47 #define RCC_CFGR_HPRE_SHIFT 4
48 #define RCC_CFGR_PPRE1_SHIFT 10
49 #define RCC_CFGR_PPRE2_SHIFT 13
50
51 #define RCC_APB1ENR_PWREN (1 << 28)
52
53 #define PWR_CR_VOS0 (1 << 14)
54 #define PWR_CR_VOS1 (1 << 15)
55 #define PWR_CR_VOS_MASK 0xC000
56 #define PWR_CR_VOS_SCALE_MODE_1 (PWR_CR_VOS0 | PWR_CR_VOS1)
57 #define PWR_CR_VOS_SCALE_MODE_2 (PWR_CR_VOS1)
58 #define PWR_CR_VOS_SCALE_MODE_3 (PWR_CR_VOS0)
59
60 #define FLASH_ACR_WS(n) n
61 #define FLASH_ACR_PRFTEN (1 << 8)
62 #define FLASH_ACR_ICEN (1 << 9)
63 #define FLASH_ACR_DCEN (1 << 10)
64
65 struct pll_psc {
66 u8 pll_m;
67 u16 pll_n;
68 u8 pll_p;
69 u8 pll_q;
70 u8 ahb_psc;
71 u8 apb1_psc;
72 u8 apb2_psc;
73 };
74
75 #define AHB_PSC_1 0
76 #define AHB_PSC_2 0x8
77 #define AHB_PSC_4 0x9
78 #define AHB_PSC_8 0xA
79 #define AHB_PSC_16 0xB
80 #define AHB_PSC_64 0xC
81 #define AHB_PSC_128 0xD
82 #define AHB_PSC_256 0xE
83 #define AHB_PSC_512 0xF
84
85 #define APB_PSC_1 0
86 #define APB_PSC_2 0x4
87 #define APB_PSC_4 0x5
88 #define APB_PSC_8 0x6
89 #define APB_PSC_16 0x7
90
91 #if !defined(CONFIG_STM32_HSE_HZ)
92 #error "CONFIG_STM32_HSE_HZ not defined!"
93 #else
94 #if (CONFIG_STM32_HSE_HZ == 8000000)
95 struct pll_psc pll_psc_168 = {
96 .pll_m = 8,
97 .pll_n = 336,
98 .pll_p = 2,
99 .pll_q = 7,
100 .ahb_psc = AHB_PSC_1,
101 .apb1_psc = APB_PSC_4,
102 .apb2_psc = APB_PSC_2
103 };
104 #else
105 #error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
106 #endif
107 #endif
108
configure_clocks(void)109 int configure_clocks(void)
110 {
111 /* Reset RCC configuration */
112 setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);
113 writel(0, &STM32_RCC->cfgr); /* Reset CFGR */
114 clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON
115 | RCC_CR_PLLON));
116 writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */
117 clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP);
118 writel(0, &STM32_RCC->cir); /* Disable all interrupts */
119
120 /* Configure for HSE+PLL operation */
121 setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON);
122 while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY))
123 ;
124
125 /* Enable high performance mode, System frequency up to 168 MHz */
126 setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN);
127 writel(PWR_CR_VOS_SCALE_MODE_1, &STM32_PWR->cr);
128
129 setbits_le32(&STM32_RCC->cfgr, ((
130 pll_psc_168.ahb_psc << RCC_CFGR_HPRE_SHIFT)
131 | (pll_psc_168.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
132 | (pll_psc_168.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
133
134 writel(pll_psc_168.pll_m
135 | (pll_psc_168.pll_n << RCC_PLLCFGR_PLLN_SHIFT)
136 | (((pll_psc_168.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT)
137 | (pll_psc_168.pll_q << RCC_PLLCFGR_PLLQ_SHIFT),
138 &STM32_RCC->pllcfgr);
139 setbits_le32(&STM32_RCC->pllcfgr, RCC_PLLCFGR_PLLSRC);
140
141 setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON);
142
143 while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
144 ;
145
146 /* 5 wait states, Prefetch enabled, D-Cache enabled, I-Cache enabled */
147 writel(FLASH_ACR_WS(5) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN
148 | FLASH_ACR_DCEN, &STM32_FLASH->acr);
149
150 clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
151 setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
152
153 while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) !=
154 RCC_CFGR_SWS_PLL)
155 ;
156
157 return 0;
158 }
159
clock_get(enum clock clck)160 unsigned long clock_get(enum clock clck)
161 {
162 u32 sysclk = 0;
163 u32 shift = 0;
164 /* Prescaler table lookups for clock computation */
165 u8 ahb_psc_table[16] = {
166 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
167 };
168 u8 apb_psc_table[8] = {
169 0, 0, 0, 0, 1, 2, 3, 4
170 };
171
172 if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
173 RCC_CFGR_SWS_PLL) {
174 u16 pllm, plln, pllp;
175 pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
176 plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
177 >> RCC_PLLCFGR_PLLN_SHIFT);
178 pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
179 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
180 sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
181 }
182
183 switch (clck) {
184 case CLOCK_CORE:
185 return sysclk;
186 break;
187 case CLOCK_AHB:
188 shift = ahb_psc_table[(
189 (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
190 >> RCC_CFGR_HPRE_SHIFT)];
191 return sysclk >>= shift;
192 break;
193 case CLOCK_APB1:
194 shift = apb_psc_table[(
195 (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
196 >> RCC_CFGR_PPRE1_SHIFT)];
197 return sysclk >>= shift;
198 break;
199 case CLOCK_APB2:
200 shift = apb_psc_table[(
201 (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
202 >> RCC_CFGR_PPRE2_SHIFT)];
203 return sysclk >>= shift;
204 break;
205 default:
206 return 0;
207 break;
208 }
209 }
210