1 /*
2 * Copyright (C) 2006 Atmel Corporation
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6 #ifndef __ASM_AVR32_ARCH_CLK_H__
7 #define __ASM_AVR32_ARCH_CLK_H__
8
9 #include <asm/arch/chip-features.h>
10 #include <asm/arch/portmux.h>
11
12 #ifdef CONFIG_PLL
13 #define PLL0_RATE ((CONFIG_SYS_OSC0_HZ / CONFIG_SYS_PLL0_DIV) \
14 * CONFIG_SYS_PLL0_MUL)
15 #define MAIN_CLK_RATE PLL0_RATE
16 #else
17 #define MAIN_CLK_RATE (CONFIG_SYS_OSC0_HZ)
18 #endif
19
get_cpu_clk_rate(void)20 static inline unsigned long get_cpu_clk_rate(void)
21 {
22 return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_CPU;
23 }
get_hsb_clk_rate(void)24 static inline unsigned long get_hsb_clk_rate(void)
25 {
26 return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB;
27 }
get_pba_clk_rate(void)28 static inline unsigned long get_pba_clk_rate(void)
29 {
30 return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBA;
31 }
get_pbb_clk_rate(void)32 static inline unsigned long get_pbb_clk_rate(void)
33 {
34 return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBB;
35 }
36
37 /* Accessors for specific devices. More will be added as needed. */
get_sdram_clk_rate(void)38 static inline unsigned long get_sdram_clk_rate(void)
39 {
40 return get_hsb_clk_rate();
41 }
42 #ifdef AT32AP700x_CHIP_HAS_USART
get_usart_clk_rate(unsigned int dev_id)43 static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
44 {
45 return get_pba_clk_rate();
46 }
47 #endif
48 #ifdef AT32AP700x_CHIP_HAS_MACB
get_macb_pclk_rate(unsigned int dev_id)49 static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
50 {
51 return get_pbb_clk_rate();
52 }
get_macb_hclk_rate(unsigned int dev_id)53 static inline unsigned long get_macb_hclk_rate(unsigned int dev_id)
54 {
55 return get_hsb_clk_rate();
56 }
57 #endif
58 #ifdef AT32AP700x_CHIP_HAS_MMCI
get_mci_clk_rate(void)59 static inline unsigned long get_mci_clk_rate(void)
60 {
61 return get_pbb_clk_rate();
62 }
63 #endif
64 #ifdef AT32AP700x_CHIP_HAS_SPI
get_spi_clk_rate(unsigned int dev_id)65 static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
66 {
67 return get_pba_clk_rate();
68 }
69 #endif
70 #ifdef AT32AP700x_CHIP_HAS_LCDC
get_lcdc_clk_rate(unsigned int dev_id)71 static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id)
72 {
73 return get_hsb_clk_rate();
74 }
75 #endif
76
77 extern void clk_init(void);
78
79 /* Board code may need the SDRAM base clock as a compile-time constant */
80 #define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB)
81
82 /* Generic clock control */
83 enum gclk_parent {
84 GCLK_PARENT_OSC0 = 0,
85 GCLK_PARENT_OSC1 = 1,
86 GCLK_PARENT_PLL0 = 2,
87 GCLK_PARENT_PLL1 = 3,
88 };
89
90 /* Some generic clocks have specific roles */
91 #define GCLK_DAC_SAMPLE_CLK 6
92 #define GCLK_LCDC_PIXCLK 7
93
94 extern unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent,
95 unsigned long rate, unsigned long parent_rate);
96
97 /**
98 * gclk_set_rate - configure and enable a generic clock
99 * @id: Which GCLK[id] to enable
100 * @parent: Parent clock feeding the GCLK
101 * @rate: Target rate of the GCLK in Hz
102 *
103 * Returns the actual GCLK rate in Hz, after rounding to the nearest
104 * supported rate.
105 *
106 * All three parameters are usually constant, hence the inline.
107 */
gclk_set_rate(unsigned int id,enum gclk_parent parent,unsigned long rate)108 static inline unsigned long gclk_set_rate(unsigned int id,
109 enum gclk_parent parent, unsigned long rate)
110 {
111 unsigned long parent_rate;
112
113 if (id > 7)
114 return 0;
115
116 switch (parent) {
117 case GCLK_PARENT_OSC0:
118 parent_rate = CONFIG_SYS_OSC0_HZ;
119 break;
120 #ifdef CONFIG_SYS_OSC1_HZ
121 case GCLK_PARENT_OSC1:
122 parent_rate = CONFIG_SYS_OSC1_HZ;
123 break;
124 #endif
125 #ifdef PLL0_RATE
126 case GCLK_PARENT_PLL0:
127 parent_rate = PLL0_RATE;
128 break;
129 #endif
130 #ifdef PLL1_RATE
131 case GCLK_PARENT_PLL1:
132 parent_rate = PLL1_RATE;
133 break;
134 #endif
135 default:
136 parent_rate = 0;
137 break;
138 }
139
140 return __gclk_set_rate(id, parent, rate, parent_rate);
141 }
142
143 /**
144 * gclk_enable_output - enable output on a GCLK pin
145 * @id: Which GCLK[id] pin to enable
146 * @drive_strength: Drive strength of external GCLK pin, if applicable
147 */
gclk_enable_output(unsigned int id,unsigned long drive_strength)148 static inline void gclk_enable_output(unsigned int id,
149 unsigned long drive_strength)
150 {
151 switch (id) {
152 case 0:
153 portmux_select_peripheral(PORTMUX_PORT_A, 1 << 30,
154 PORTMUX_FUNC_A, drive_strength);
155 break;
156 case 1:
157 portmux_select_peripheral(PORTMUX_PORT_A, 1 << 31,
158 PORTMUX_FUNC_A, drive_strength);
159 break;
160 case 2:
161 portmux_select_peripheral(PORTMUX_PORT_B, 1 << 19,
162 PORTMUX_FUNC_A, drive_strength);
163 break;
164 case 3:
165 portmux_select_peripheral(PORTMUX_PORT_B, 1 << 29,
166 PORTMUX_FUNC_A, drive_strength);
167 break;
168 case 4:
169 portmux_select_peripheral(PORTMUX_PORT_B, 1 << 30,
170 PORTMUX_FUNC_A, drive_strength);
171 break;
172 }
173 }
174
175 #endif /* __ASM_AVR32_ARCH_CLK_H__ */
176