1 /*
2  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef _QUARK_H_
8 #define _QUARK_H_
9 
10 /* Message Bus Ports */
11 #define MSG_PORT_MEM_ARBITER	0x00
12 #define MSG_PORT_HOST_BRIDGE	0x03
13 #define MSG_PORT_RMU		0x04
14 #define MSG_PORT_MEM_MGR	0x05
15 #define MSG_PORT_SOC_UNIT	0x31
16 
17 /* Port 0x00: Memory Arbiter Message Port Registers */
18 
19 /* Enhanced Configuration Space */
20 #define AEC_CTRL		0x00
21 
22 /* Port 0x03: Host Bridge Message Port Registers */
23 
24 /* Host Miscellaneous Controls 2 */
25 #define HMISC2			0x03
26 
27 #define HMISC2_SEGE		0x00000002
28 #define HMISC2_SEGF		0x00000004
29 #define HMISC2_SEGAB		0x00000010
30 
31 /* Host Memory I/O Boundary */
32 #define HM_BOUND		0x08
33 
34 /* Extended Configuration Space */
35 #define HEC_REG			0x09
36 
37 /* Port 0x04: Remote Management Unit Message Port Registers */
38 
39 /* ACPI PBLK Base Address Register */
40 #define PBLK_BA			0x70
41 
42 /* SPI DMA Base Address Register */
43 #define SPI_DMA_BA		0x7a
44 
45 /* Port 0x05: Memory Manager Message Port Registers */
46 
47 /* eSRAM Block Page Control */
48 #define ESRAM_BLK_CTRL		0x82
49 #define ESRAM_BLOCK_MODE	0x10000000
50 
51 /* DRAM */
52 #define DRAM_BASE		0x00000000
53 #define DRAM_MAX_SIZE		0x80000000
54 
55 /* eSRAM */
56 #define ESRAM_SIZE		0x80000
57 
58 /* Memory BAR Enable */
59 #define MEM_BAR_EN		0x00000001
60 
61 /* I/O BAR Enable */
62 #define IO_BAR_EN		0x80000000
63 
64 /* 64KiB of RMU binary in flash */
65 #define RMU_BINARY_SIZE		0x10000
66 
67 /* Legacy Bridge PCI Configuration Registers */
68 #define LB_GBA			0x44
69 #define LB_PM1BLK		0x48
70 #define LB_GPE0BLK		0x4c
71 #define LB_ACTL			0x58
72 #define LB_PABCDRC		0x60
73 #define LB_PEFGHRC		0x64
74 #define LB_WDTBA		0x84
75 #define LB_BCE			0xd4
76 #define LB_BC			0xd8
77 #define LB_RCBA			0xf0
78 
79 #ifndef __ASSEMBLY__
80 
81 /* Root Complex Register Block */
82 struct quark_rcba {
83 	u32	rctl;
84 	u32	esd;
85 	u32	rsvd1[3150];
86 	u16	rmu_ir;
87 	u16	d23_ir;
88 	u16	core_ir;
89 	u16	d20d21_ir;
90 };
91 
92 #endif /* __ASSEMBLY__ */
93 
94 #endif /* _QUARK_H_ */
95