1 /*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7 *
8 * (C) Copyright 2005-2009
9 * Modified for InterControl digsyMTC MPC5200 board by
10 * Frank Bodammer, GCD Hard- & Software GmbH,
11 * frank.bodammer@gcd-solutions.de
12 *
13 * (C) Copyright 2009
14 * Grzegorz Bernacki, Semihalf, gjb@semihalf.com
15 *
16 * SPDX-License-Identifier: GPL-2.0+
17 */
18
19 #include <common.h>
20 #include <mpc5xxx.h>
21 #include <net.h>
22 #include <pci.h>
23 #include <asm/processor.h>
24 #include <asm/io.h>
25 #include "eeprom.h"
26 #if defined(CONFIG_DIGSY_REV5)
27 #include "is45s16800a2.h"
28 #include <mtd/cfi_flash.h>
29 #include <flash.h>
30 #else
31 #include "is42s16800a-7t.h"
32 #endif
33 #include <libfdt.h>
34 #include <fdt_support.h>
35 #include <i2c.h>
36 #include <mb862xx.h>
37
38 DECLARE_GLOBAL_DATA_PTR;
39
40 extern int usb_cpu_init(void);
41
42 #if defined(CONFIG_DIGSY_REV5)
43 /*
44 * The M29W128GH needs a specail reset command function,
45 * details see the doc/README.cfi file
46 */
flash_cmd_reset(flash_info_t * info)47 void flash_cmd_reset(flash_info_t *info)
48 {
49 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
50 }
51 #endif
52
53 #ifndef CONFIG_SYS_RAMBOOT
sdram_start(int hi_addr)54 static void sdram_start(int hi_addr)
55 {
56 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
57 long control = SDRAM_CONTROL | hi_addr_bit;
58
59 /* unlock mode register */
60 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
61
62 /* precharge all banks */
63 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
64
65 /* auto refresh */
66 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
67
68 /* set mode register */
69 out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
70
71 /* normal operation */
72 out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
73 }
74 #endif
75
76 /*
77 * ATTENTION: Although partially referenced initdram does NOT make real use
78 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
79 * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
80 */
81
initdram(int board_type)82 phys_size_t initdram(int board_type)
83 {
84 ulong dramsize = 0;
85 ulong dramsize2 = 0;
86 uint svr, pvr;
87 #ifndef CONFIG_SYS_RAMBOOT
88 ulong test1, test2;
89
90 /* setup SDRAM chip selects */
91 out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001C); /* 512MB at 0x0 */
92 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
93
94 /* setup config registers */
95 out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
96 out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
97
98 /* find RAM size using SDRAM CS0 only */
99 sdram_start(0);
100 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
101 sdram_start(1);
102 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
103 if (test1 > test2) {
104 sdram_start(0);
105 dramsize = test1;
106 } else {
107 dramsize = test2;
108 }
109
110 /* memory smaller than 1MB is impossible */
111 if (dramsize < (1 << 20))
112 dramsize = 0;
113
114 /* set SDRAM CS0 size according to the amount of RAM found */
115 if (dramsize > 0) {
116 out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
117 (0x13 + __builtin_ffs(dramsize >> 20) - 1));
118 } else {
119 out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
120 }
121
122 /* let SDRAM CS1 start right after CS0 */
123 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize + 0x0000001C);
124
125 /* find RAM size using SDRAM CS1 only */
126 test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
127 0x08000000);
128 dramsize2 = test1;
129
130 /* memory smaller than 1MB is impossible */
131 if (dramsize2 < (1 << 20))
132 dramsize2 = 0;
133
134 /* set SDRAM CS1 size according to the amount of RAM found */
135 if (dramsize2 > 0) {
136 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, (dramsize |
137 (0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
138 } else {
139 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */
140 }
141
142 #else /* CONFIG_SYS_RAMBOOT */
143
144 /* retrieve size of memory connected to SDRAM CS0 */
145 dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
146 if (dramsize >= 0x13)
147 dramsize = (1 << (dramsize - 0x13)) << 20;
148 else
149 dramsize = 0;
150
151 /* retrieve size of memory connected to SDRAM CS1 */
152 dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
153 if (dramsize2 >= 0x13)
154 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
155 else
156 dramsize2 = 0;
157
158 #endif /* CONFIG_SYS_RAMBOOT */
159
160 /*
161 * On MPC5200B we need to set the special configuration delay in the
162 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
163 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
164 *
165 * "The SDelay should be written to a value of 0x00000004. It is
166 * required to account for changes caused by normal wafer processing
167 * parameters."
168 */
169 svr = get_svr();
170 pvr = get_pvr();
171 if ((SVR_MJREV(svr) >= 2) &&
172 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
173 out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
174
175 return dramsize + dramsize2;
176 }
177
checkboard(void)178 int checkboard(void)
179 {
180 char buf[64];
181 int i = getenv_f("serial#", buf, sizeof(buf));
182
183 puts ("Board: InterControl digsyMTC");
184 #if defined(CONFIG_DIGSY_REV5)
185 puts (" rev5");
186 #endif
187 if (i > 0) {
188 puts(", ");
189 puts(buf);
190 }
191 putc('\n');
192
193 return 0;
194 }
195
196 #if defined(CONFIG_VIDEO)
197
198 #define GPIO_USB1_0 0x00010000 /* Power-On pin */
199 #define GPIO_USB1_9 0x08 /* PX_~EN pin */
200
201 #define GPIO_EE_DO 0x10 /* PSC6_0 (DO) pin */
202 #define GPIO_EE_CTS 0x20 /* PSC6_1 (CTS) pin */
203 #define GPIO_EE_DI 0x10000000 /* PSC6_2 (DI) pin */
204 #define GPIO_EE_CLK 0x20000000 /* PSC6_3 (CLK) pin */
205
206 #define GPT_GPIO_ON 0x00000034 /* GPT as simple GPIO, high */
207
exbo_hw_init(void)208 static void exbo_hw_init(void)
209 {
210 struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
211 struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
212 struct mpc5xxx_wu_gpio *wu_gpio =
213 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
214
215 /* configure IrDA pins (PSC6 port) as gpios */
216 gpio->port_config &= 0xFF8FFFFF;
217
218 /* Init for USB1_0, EE_CLK and EE_DI - Low */
219 setbits_be32(&gpio->simple_ddr,
220 GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
221 clrbits_be32(&gpio->simple_ode,
222 GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
223 clrbits_be32(&gpio->simple_dvo,
224 GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
225 setbits_be32(&gpio->simple_gpioe,
226 GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
227
228 /* Init for EE_DO, EE_CTS - Input */
229 clrbits_8(&wu_gpio->ddr, GPIO_EE_DO | GPIO_EE_CTS);
230 setbits_8(&wu_gpio->enable, GPIO_EE_DO | GPIO_EE_CTS);
231
232 /* Init for PX_~EN (USB1_9) - High */
233 clrbits_8(&gpio->sint_ode, GPIO_USB1_9);
234 setbits_8(&gpio->sint_ddr, GPIO_USB1_9);
235 clrbits_8(&gpio->sint_inten, GPIO_USB1_9);
236 setbits_8(&gpio->sint_dvo, GPIO_USB1_9);
237 setbits_8(&gpio->sint_gpioe, GPIO_USB1_9);
238
239 /* Init for ~OE Switch (GPIO3) - Timer_0 GPIO High */
240 out_be32(&gpt[0].emsr, GPT_GPIO_ON);
241 /* Init for S Switch (GPIO4) - Timer_1 GPIO High */
242 out_be32(&gpt[1].emsr, GPT_GPIO_ON);
243
244 /* Power-On camera supply */
245 setbits_be32(&gpio->simple_dvo, GPIO_USB1_0);
246 }
247 #else
exbo_hw_init(void)248 static inline void exbo_hw_init(void) {}
249 #endif /* CONFIG_VIDEO */
250
board_early_init_r(void)251 int board_early_init_r(void)
252 {
253 #ifdef CONFIG_MPC52XX_SPI
254 struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt*)MPC5XXX_GPT;
255 #endif
256 /*
257 * Now, when we are in RAM, enable flash write access for detection
258 * process. Note that CS_BOOT cannot be cleared when executing in
259 * flash.
260 */
261 /* disable CS_BOOT */
262 clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
263 /* enable CS1 */
264 setbits_be32((void *)MPC5XXX_ADDECR, (1 << 17));
265 /* enable CS0 */
266 setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
267
268 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
269 /* Low level USB init, required for proper kernel operation */
270 usb_cpu_init();
271 #endif
272 #ifdef CONFIG_MPC52XX_SPI
273 /* GPT 6 Output Enable */
274 out_be32(&gpt[6].emsr, 0x00000034);
275 /* GPT 7 Output Enable */
276 out_be32(&gpt[7].emsr, 0x00000034);
277 #endif
278
279 return (0);
280 }
281
board_get_enetaddr(uchar * enet)282 void board_get_enetaddr (uchar * enet)
283 {
284 ushort read = 0;
285 ushort addr_of_eth_addr = 0;
286 ushort len_sys = 0;
287 ushort len_sys_cfg = 0;
288
289 /* check identification word */
290 eeprom_read(EEPROM_ADDR, EEPROM_ADDR_IDENT, (uchar *)&read, 2);
291 if (read != EEPROM_IDENT)
292 return;
293
294 /* calculate offset of config area */
295 eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYS, (uchar *)&len_sys, 2);
296 eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYSCFG,
297 (uchar *)&len_sys_cfg, 2);
298 addr_of_eth_addr = (len_sys + len_sys_cfg + EEPROM_ADDR_ETHADDR) << 1;
299 if (addr_of_eth_addr >= EEPROM_LEN)
300 return;
301
302 eeprom_read(EEPROM_ADDR, addr_of_eth_addr, enet, 6);
303 }
304
misc_init_r(void)305 int misc_init_r(void)
306 {
307 pci_dev_t devbusfn;
308 uchar enetaddr[6];
309
310 /* check if graphic extension board is present */
311 devbusfn = pci_find_device(PCI_VENDOR_ID_FUJITSU,
312 PCI_DEVICE_ID_CORAL_PA, 0);
313 if (devbusfn != -1)
314 exbo_hw_init();
315
316 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
317 board_get_enetaddr(enetaddr);
318 eth_setenv_enetaddr("ethaddr", enetaddr);
319 }
320
321 return 0;
322 }
323
324 #ifdef CONFIG_PCI
325 static struct pci_controller hose;
326
327 extern void pci_mpc5xxx_init(struct pci_controller *);
328
pci_init_board(void)329 void pci_init_board(void)
330 {
331 pci_mpc5xxx_init(&hose);
332 }
333 #endif
334
335 #ifdef CONFIG_CMD_IDE
336
337 #ifdef CONFIG_IDE_RESET
338
init_ide_reset(void)339 void init_ide_reset(void)
340 {
341 debug ("init_ide_reset\n");
342
343 /* set gpio output value to 1 */
344 setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
345 /* open drain output */
346 setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
347 /* direction output */
348 setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
349 /* enable gpio */
350 setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
351
352 }
353
ide_set_reset(int idereset)354 void ide_set_reset(int idereset)
355 {
356 debug ("ide_reset(%d)\n", idereset);
357
358 /* set gpio output value to 0 */
359 clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
360 /* open drain output */
361 setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
362 /* direction output */
363 setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
364 /* enable gpio */
365 setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
366
367 udelay(10000);
368
369 /* set gpio output value to 1 */
370 setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
371 /* open drain output */
372 setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
373 /* direction output */
374 setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
375 /* enable gpio */
376 setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
377 }
378 #endif /* CONFIG_IDE_RESET */
379 #endif /* CONFIG_CMD_IDE */
380
381 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
ft_delete_node(void * fdt,const char * compat)382 static void ft_delete_node(void *fdt, const char *compat)
383 {
384 int off = -1;
385 int ret;
386
387 off = fdt_node_offset_by_compatible(fdt, -1, compat);
388 if (off < 0) {
389 printf("Could not find %s node.\n", compat);
390 return;
391 }
392
393 ret = fdt_del_node(fdt, off);
394 if (ret < 0)
395 printf("Could not delete %s node.\n", compat);
396 }
397 #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
ft_adapt_flash_base(void * blob)398 static void ft_adapt_flash_base(void *blob)
399 {
400 flash_info_t *dev = &flash_info[0];
401 int off;
402 struct fdt_property *prop;
403 int len;
404 u32 *reg, *reg2;
405
406 off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
407 if (off < 0) {
408 printf("Could not find fsl,mpc5200b-lpb node.\n");
409 return;
410 }
411
412 /* found compatible property */
413 prop = fdt_get_property_w(blob, off, "ranges", &len);
414 if (prop) {
415 reg = reg2 = (u32 *)&prop->data[0];
416
417 reg[2] = dev->start[0];
418 reg[3] = dev->size;
419 fdt_setprop(blob, off, "ranges", reg2, len);
420 } else
421 printf("Could not find ranges\n");
422 }
423
424 extern ulong flash_get_size (phys_addr_t base, int banknum);
425
426 /* Update the Flash Baseaddr settings */
update_flash_size(int flash_size)427 int update_flash_size (int flash_size)
428 {
429 volatile struct mpc5xxx_mmap_ctl *mm =
430 (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
431 flash_info_t *dev;
432 int i;
433 int size = 0;
434 unsigned long base = 0x0;
435 u32 *cs_reg = (u32 *)&mm->cs0_start;
436
437 for (i = 0; i < 2; i++) {
438 dev = &flash_info[i];
439
440 if (dev->size) {
441 /* calculate new base addr for this chipselect */
442 base -= dev->size;
443 out_be32(cs_reg, START_REG(base));
444 cs_reg++;
445 out_be32(cs_reg, STOP_REG(base, dev->size));
446 cs_reg++;
447 /* recalculate the sectoraddr in the cfi driver */
448 size += flash_get_size(base, i);
449 }
450 }
451 flash_protect_default();
452 gd->bd->bi_flashstart = base;
453 return 0;
454 }
455 #endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
456
ft_board_setup(void * blob,bd_t * bd)457 int ft_board_setup(void *blob, bd_t *bd)
458 {
459 int phy_addr = CONFIG_PHY_ADDR;
460 char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
461
462 ft_cpu_setup(blob, bd);
463 /*
464 * There are 2 RTC nodes in the DTS, so remove
465 * the unneeded node here.
466 */
467 #if defined(CONFIG_DIGSY_REV5)
468 ft_delete_node(blob, "dallas,ds1339");
469 #else
470 ft_delete_node(blob, "mc,rv3029c2");
471 #endif
472 #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
473 #ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
474 /* Update reg property in all nor flash nodes too */
475 fdt_fixup_nor_flash_size(blob);
476 #endif
477 ft_adapt_flash_base(blob);
478 #endif
479 /* fix up the phy address */
480 do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
481
482 return 0;
483 }
484 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
485