1 /*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002, 2010
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
8 *
9 * SPDX-License-Identifier: GPL-2.0+
10 */
11
12 #include <common.h>
13 #include <netdev.h>
14 #include <asm/io.h>
15 #include <asm/arch/s3c24x0_cpu.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 #define FCLK_SPEED 1
20
21 #if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
22 #define M_MDIV 0xC3
23 #define M_PDIV 0x4
24 #define M_SDIV 0x1
25 #elif FCLK_SPEED==1 /* Fout = 202.8MHz */
26 #define M_MDIV 0xA1
27 #define M_PDIV 0x3
28 #define M_SDIV 0x1
29 #endif
30
31 #define USB_CLOCK 1
32
33 #if USB_CLOCK==0
34 #define U_M_MDIV 0xA1
35 #define U_M_PDIV 0x3
36 #define U_M_SDIV 0x1
37 #elif USB_CLOCK==1
38 #define U_M_MDIV 0x48
39 #define U_M_PDIV 0x3
40 #define U_M_SDIV 0x2
41 #endif
42
pll_delay(unsigned long loops)43 static inline void pll_delay(unsigned long loops)
44 {
45 __asm__ volatile ("1:\n"
46 "subs %0, %1, #1\n"
47 "bne 1b":"=r" (loops):"0" (loops));
48 }
49
50 /*
51 * Miscellaneous platform dependent initialisations
52 */
53
board_early_init_f(void)54 int board_early_init_f(void)
55 {
56 struct s3c24x0_clock_power * const clk_power =
57 s3c24x0_get_base_clock_power();
58 struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
59
60 /* to reduce PLL lock time, adjust the LOCKTIME register */
61 writel(0xFFFFFF, &clk_power->locktime);
62
63 /* configure MPLL */
64 writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV,
65 &clk_power->mpllcon);
66
67 /* some delay between MPLL and UPLL */
68 pll_delay(4000);
69
70 /* configure UPLL */
71 writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV,
72 &clk_power->upllcon);
73
74 /* some delay between MPLL and UPLL */
75 pll_delay(8000);
76
77 /* set up the I/O ports */
78 writel(0x007FFFFF, &gpio->gpacon);
79 writel(0x00044555, &gpio->gpbcon);
80 writel(0x000007FF, &gpio->gpbup);
81 writel(0xAAAAAAAA, &gpio->gpccon);
82 writel(0x0000FFFF, &gpio->gpcup);
83 writel(0xAAAAAAAA, &gpio->gpdcon);
84 writel(0x0000FFFF, &gpio->gpdup);
85 writel(0xAAAAAAAA, &gpio->gpecon);
86 writel(0x0000FFFF, &gpio->gpeup);
87 writel(0x000055AA, &gpio->gpfcon);
88 writel(0x000000FF, &gpio->gpfup);
89 writel(0xFF95FFBA, &gpio->gpgcon);
90 writel(0x0000FFFF, &gpio->gpgup);
91 writel(0x002AFAAA, &gpio->gphcon);
92 writel(0x000007FF, &gpio->gphup);
93
94 return 0;
95 }
96
board_init(void)97 int board_init(void)
98 {
99 /* arch number of SMDK2410-Board */
100 gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
101
102 /* adress of boot parameters */
103 gd->bd->bi_boot_params = 0x30000100;
104
105 icache_enable();
106 dcache_enable();
107
108 return 0;
109 }
110
dram_init(void)111 int dram_init(void)
112 {
113 /* dram_init must store complete ramsize in gd->ram_size */
114 gd->ram_size = PHYS_SDRAM_1_SIZE;
115 return 0;
116 }
117
118 #ifdef CONFIG_CMD_NET
board_eth_init(bd_t * bis)119 int board_eth_init(bd_t *bis)
120 {
121 int rc = 0;
122 #ifdef CONFIG_CS8900
123 rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
124 #endif
125 return rc;
126 }
127 #endif
128
129 /*
130 * Hardcoded flash setup:
131 * Flash 0 is a non-CFI AMD AM29LV800BB flash.
132 */
board_flash_get_legacy(ulong base,int banknum,flash_info_t * info)133 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
134 {
135 info->portwidth = FLASH_CFI_16BIT;
136 info->chipwidth = FLASH_CFI_BY16;
137 info->interface = FLASH_CFI_X16;
138 return 1;
139 }
140