1 /* 2 * U-boot - Configuration file for IBF-DSP561 board 3 */ 4 5 #ifndef __CONFIG_IBF_DSP561__H__ 6 #define __CONFIG_IBF_DSP561__H__ 7 8 #include <asm/config-pre.h> 9 10 11 /* 12 * Processor Settings 13 */ 14 #define CONFIG_BFIN_CPU bf561-0.5 15 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS 16 17 18 /* 19 * Clock Settings 20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV 21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV 22 */ 23 /* CONFIG_CLKIN_HZ is any value in Hz */ 24 #define CONFIG_CLKIN_HZ 25000000 25 /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ 26 /* 1 = CLKIN / 2 */ 27 #define CONFIG_CLKIN_HALF 0 28 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ 29 /* 1 = bypass PLL */ 30 #define CONFIG_PLL_BYPASS 0 31 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ 32 /* Values can range from 0-63 (where 0 means 64) */ 33 #define CONFIG_VCO_MULT 24 34 /* CCLK_DIV controls the core clock divider */ 35 /* Values can be 1, 2, 4, or 8 ONLY */ 36 #define CONFIG_CCLK_DIV 1 37 /* SCLK_DIV controls the system clock divider */ 38 /* Values can range from 1-15 */ 39 #define CONFIG_SCLK_DIV 5 40 41 42 /* 43 * Memory Settings 44 */ 45 #define CONFIG_MEM_ADD_WDTH 9 46 #define CONFIG_MEM_SIZE 64 47 48 #define CONFIG_EBIU_SDRRC_VAL 0x377 49 #define CONFIG_EBIU_SDGCTL_VAL 0x91998d 50 #define CONFIG_EBIU_SDBCTL_VAL 0x15 51 52 #define CONFIG_EBIU_AMGCTL_VAL 0x3F 53 #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 54 #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 55 56 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 57 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) 58 59 60 /* 61 * Network Settings 62 */ 63 #define ADI_CMDS_NETWORK 1 64 #define CONFIG_DRIVER_AX88180 1 65 #define AX88180_BASE 0x2c000000 66 #define CONFIG_HOSTNAME ibf-dsp561 67 68 69 /* 70 * Flash Settings 71 */ 72 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ 73 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ 74 #define CONFIG_SYS_FLASH_CFI_AMD_RESET 75 #define CONFIG_SYS_FLASH_BASE 0x20000000 76 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 77 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* max number of sectors on one chip */ 78 /* The BF561-EZKIT uses a top boot flash */ 79 #define CONFIG_ENV_IS_IN_FLASH 1 80 #define CONFIG_ENV_OFFSET 0x4000 81 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) 82 #define CONFIG_ENV_SIZE 0x2000 83 #define CONFIG_ENV_SECT_SIZE 0x12000 /* Total Size of Environment Sector */ 84 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) 85 #define ENV_IS_EMBEDDED 86 #else 87 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR 88 #endif 89 #ifdef ENV_IS_EMBEDDED 90 /* WARNING - the following is hand-optimized to fit within 91 * the sector before the environment sector. If it throws 92 * an error during compilation remove an object here to get 93 * it linked after the configuration sector. 94 */ 95 # define LDS_BOARD_TEXT \ 96 arch/blackfin/lib/built-in.o (.text*); \ 97 arch/blackfin/cpu/built-in.o (.text*); \ 98 . = DEFINED(env_offset) ? env_offset : .; \ 99 common/env_embedded.o (.text*); 100 #endif 101 102 103 /* 104 * I2C Settings 105 */ 106 #define CONFIG_SYS_I2C 107 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 108 #define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0 109 #define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1 110 111 /* 112 * Misc Settings 113 */ 114 #define CONFIG_UART_CONSOLE 0 115 116 117 /* 118 * Pull in common ADI header for remaining command/environment setup 119 */ 120 #include <configs/bfin_adi_common.h> 121 122 #endif 123