1 /* 2 * (C) Copyright 2004 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Kshitij Gupta <kshitij@ti.com> 6 * 7 * Configuration settings for the LogicPD i.MX31 Litekit board. 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 #include <asm/arch/imx-regs.h> 16 17 /* High Level Configuration Options */ 18 #define CONFIG_MX31 1 /* This is a mx31 */ 19 #define CONFIG_MX31_CLK32 32000 20 21 #define CONFIG_DISPLAY_CPUINFO 22 #define CONFIG_DISPLAY_BOARDINFO 23 24 #define CONFIG_SYS_TEXT_BASE 0xa0000000 25 26 #define CONFIG_MACH_TYPE MACH_TYPE_MX31LITE 27 28 /* Temporarily disabled */ 29 #if 0 30 #define CONFIG_OF_LIBFDT 1 31 #define CONFIG_FIT 1 32 #define CONFIG_FIT_VERBOSE 1 33 #endif 34 35 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 36 #define CONFIG_SETUP_MEMORY_TAGS 1 37 #define CONFIG_INITRD_TAG 1 38 39 /* 40 * Size of malloc() pool 41 */ 42 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) 43 44 /* 45 * Hardware drivers 46 */ 47 48 #define CONFIG_MXC_UART 49 #define CONFIG_MXC_UART_BASE UART1_BASE 50 #define CONFIG_MXC_GPIO 51 52 #define CONFIG_HARD_SPI 1 53 #define CONFIG_MXC_SPI 1 54 #define CONFIG_DEFAULT_SPI_BUS 1 55 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) 56 57 /* PMIC Controller */ 58 #define CONFIG_POWER 59 #define CONFIG_POWER_SPI 60 #define CONFIG_POWER_FSL 61 #define CONFIG_FSL_PMIC_BUS 1 62 #define CONFIG_FSL_PMIC_CS 0 63 #define CONFIG_FSL_PMIC_CLK 1000000 64 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) 65 #define CONFIG_FSL_PMIC_BITLEN 32 66 #define CONFIG_RTC_MC13XXX 67 68 /* allow to overwrite serial and ethaddr */ 69 #define CONFIG_ENV_OVERWRITE 70 #define CONFIG_CONS_INDEX 1 71 #define CONFIG_BAUDRATE 115200 72 73 /*********************************************************** 74 * Command definition 75 ***********************************************************/ 76 #define CONFIG_CMD_MII 77 #define CONFIG_CMD_PING 78 #define CONFIG_CMD_SPI 79 #define CONFIG_CMD_DATE 80 #define CONFIG_CMD_NAND 81 82 #define CONFIG_BOOTDELAY 3 83 84 #define CONFIG_NETMASK 255.255.255.0 85 #define CONFIG_IPADDR 192.168.23.168 86 #define CONFIG_SERVERIP 192.168.23.2 87 88 #define CONFIG_EXTRA_ENV_SETTINGS \ 89 "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \ 90 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ 91 "bootcmd=run bootcmd_net\0" \ 92 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; tftpboot 0x80000000 uImage-mx31; bootm\0" \ 93 "prg_uboot=tftpboot 0x80000000 u-boot-imx31_litekit.bin; protect off all; erase 0xa00d0000 0xa01effff; cp.b 0x80000000 0xa00d0000 $(filesize)\0" 94 95 96 #define CONFIG_SMC911X 1 97 #define CONFIG_SMC911X_BASE (CS4_BASE + 0x00020000) 98 #define CONFIG_SMC911X_32_BIT 1 99 100 /* 101 * Miscellaneous configurable options 102 */ 103 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 104 #define CONFIG_SYS_PROMPT "uboot> " 105 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 106 /* Print Buffer Size */ 107 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 108 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 109 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 110 111 #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ 112 #define CONFIG_SYS_MEMTEST_END 0x10000 113 114 #define CONFIG_SYS_LOAD_ADDR 0 /* default load address */ 115 116 #define CONFIG_CMDLINE_EDITING 1 117 118 /*----------------------------------------------------------------------- 119 * Physical Memory Map 120 */ 121 #define CONFIG_NR_DRAM_BANKS 1 122 #define PHYS_SDRAM_1 CSD0_BASE 123 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) 124 #define CONFIG_BOARD_EARLY_INIT_F 125 126 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 127 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 128 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 129 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 130 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET) 131 132 /*----------------------------------------------------------------------- 133 * FLASH and environment organization 134 */ 135 #define CONFIG_SYS_FLASH_BASE CS0_BASE 136 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 137 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ 138 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ 139 140 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x001f0000) 141 #define CONFIG_ENV_IS_IN_FLASH 1 142 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 143 #define CONFIG_ENV_SIZE (64 * 1024) 144 145 /*----------------------------------------------------------------------- 146 * CFI FLASH driver setup 147 */ 148 #define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ 149 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ 150 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ 151 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ 152 153 /* timeout values are in ticks */ 154 #define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ 155 #define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */ 156 157 /* 158 * JFFS2 partitions 159 */ 160 #undef CONFIG_CMD_MTDPARTS 161 #define CONFIG_JFFS2_DEV "nor0" 162 163 /* 164 * NAND flash 165 */ 166 #define CONFIG_NAND_MXC 167 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR 168 #define CONFIG_SYS_MAX_NAND_DEVICE 1 169 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR 170 #define CONFIG_MXC_NAND_HWECC 171 172 #endif /* __CONFIG_H */ 173