1 /*
2 * (C) Copyright 2009
3 * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
4 *
5 * (C) Copyright 2003-2005
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 /*
15 * High Level Configuration Options
16 * (easy to change)
17 */
18
19 #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
20 #define CONFIG_INKA4X0 1 /* INKA4x0 board */
21
22 /*
23 * Valid values for CONFIG_SYS_TEXT_BASE are:
24 * 0xFFE00000 boot low
25 * 0x00100000 boot from RAM (for testing only)
26 */
27 #ifndef CONFIG_SYS_TEXT_BASE
28 #define CONFIG_SYS_TEXT_BASE 0xFFE00000 /* Standard: boot low */
29 #endif
30 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds"
31
32 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
33
34 #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
35
36 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
37
38 /*
39 * Serial console configuration
40 */
41 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
42 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
43 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
44
45 /*
46 * PCI Mapping:
47 * 0x40000000 - 0x4fffffff - PCI Memory
48 * 0x50000000 - 0x50ffffff - PCI IO Space
49 */
50 #define CONFIG_PCI 1
51 #define CONFIG_PCI_PNP 1
52 #define CONFIG_PCI_SCAN_SHOW 1
53 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
54
55 #define CONFIG_PCI_MEM_BUS 0x40000000
56 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
57 #define CONFIG_PCI_MEM_SIZE 0x10000000
58
59 #define CONFIG_PCI_IO_BUS 0x50000000
60 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
61 #define CONFIG_PCI_IO_SIZE 0x01000000
62
63 #define CONFIG_SYS_XLB_PIPELINING 1
64
65 /* Partitions */
66 #define CONFIG_MAC_PARTITION
67 #define CONFIG_DOS_PARTITION
68 #define CONFIG_ISO_PARTITION
69
70
71 /*
72 * BOOTP options
73 */
74 #define CONFIG_BOOTP_BOOTFILESIZE
75 #define CONFIG_BOOTP_BOOTPATH
76 #define CONFIG_BOOTP_GATEWAY
77 #define CONFIG_BOOTP_HOSTNAME
78
79
80 /*
81 * Command line configuration.
82 */
83 #define CONFIG_CMD_DATE
84 #define CONFIG_CMD_DHCP
85 #define CONFIG_CMD_EXT2
86 #define CONFIG_CMD_FAT
87 #define CONFIG_CMD_IDE
88 #define CONFIG_CMD_PCI
89 #define CONFIG_CMD_PING
90 #define CONFIG_CMD_SNTP
91 #define CONFIG_CMD_USB
92
93 #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
94
95 #if (CONFIG_SYS_TEXT_BASE == 0xFFE00000) /* Boot low */
96 # define CONFIG_SYS_LOWBOOT 1
97 #endif
98
99 /*
100 * Autobooting
101 */
102 #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
103
104 #define CONFIG_PREBOOT "echo;" \
105 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
106 "echo"
107
108 #undef CONFIG_BOOTARGS
109
110 #define CONFIG_IPADDR 192.168.100.2
111 #define CONFIG_SERVERIP 192.168.100.1
112 #define CONFIG_NETMASK 255.255.255.0
113 #define HOSTNAME inka4x0
114 #define CONFIG_BOOTFILE "/tftpboot/inka4x0/uImage"
115 #define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx"
116
117 #define CONFIG_EXTRA_ENV_SETTINGS \
118 "netdev=eth0\0" \
119 "nfsargs=setenv bootargs root=/dev/nfs rw " \
120 "nfsroot=${serverip}:${rootpath}\0" \
121 "ramargs=setenv bootargs root=/dev/ram rw\0" \
122 "addip=setenv bootargs ${bootargs} " \
123 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
124 ":${hostname}:${netdev}:off panic=1\0" \
125 "addcons=setenv bootargs ${bootargs} " \
126 "console=ttyS0,${baudrate}\0" \
127 "flash_nfs=run nfsargs addip addcons;" \
128 "bootm ${kernel_addr}\0" \
129 "net_nfs=tftp 200000 ${bootfile};" \
130 "run nfsargs addip addcons;bootm\0" \
131 "enable_disp=mw.l 100000 04000000 1;" \
132 "cp.l 100000 f0000b20 1;" \
133 "cp.l 100000 f0000b28 1\0" \
134 "ideargs=setenv bootargs root=/dev/hda1 rw\0" \
135 "ide_boot=ext2load ide 0:1 200000 uImage;" \
136 "run ideargs addip addcons enable_disp;bootm\0" \
137 "brightness=255\0" \
138 ""
139
140 #define CONFIG_BOOTCOMMAND "run ide_boot"
141
142 /*
143 * IPB Bus clocking configuration.
144 */
145 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
146
147 /*
148 * Flash configuration
149 */
150 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
151 #define CONFIG_FLASH_CFI_DRIVER 1
152 #define CONFIG_SYS_FLASH_BASE 0xffe00000
153 #define CONFIG_SYS_FLASH_SIZE 0x00200000
154 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
155 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
156 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
157 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
158
159 /*
160 * Environment settings
161 */
162 #define CONFIG_ENV_IS_IN_FLASH 1
163 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
164 #define CONFIG_ENV_SIZE 0x2000
165 #define CONFIG_ENV_SECT_SIZE 0x2000
166 #define CONFIG_ENV_OVERWRITE 1
167 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
168
169 /*
170 * Memory map
171 */
172 #define CONFIG_SYS_MBAR 0xF0000000
173 #define CONFIG_SYS_SDRAM_BASE 0x00000000
174 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
175
176 /*
177 * SDRAM controller configuration
178 */
179 #undef CONFIG_SDR_MT48LC16M16A2
180 #undef CONFIG_DDR_MT46V16M16
181 #undef CONFIG_DDR_MT46V32M16
182 #undef CONFIG_DDR_HYB25D512160BF
183 #define CONFIG_DDR_K4H511638C
184
185 /* Use ON-Chip SRAM until RAM will be available */
186 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
187
188 /* preserve space for the post_word at end of on-chip SRAM */
189 #define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
190
191 #ifdef CONFIG_POST
192 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
193 #else
194 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
195 #endif
196
197 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
198 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
199
200 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
201 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
202 # define CONFIG_SYS_RAMBOOT 1
203 #endif
204
205 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
206 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
207 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
208
209 /*
210 * Ethernet configuration
211 */
212 #define CONFIG_MPC5xxx_FEC 1
213 #define CONFIG_MPC5xxx_FEC_MII100
214 /*
215 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
216 */
217 /* #define CONFIG_MPC5xxx_FEC_MII10 */
218 #define CONFIG_PHY_ADDR 0x00
219 #define CONFIG_MII
220
221 /*
222 * GPIO configuration
223 *
224 * use CS1 as gpio_wkup_6 output
225 * Bit 0 (mask: 0x80000000): 0
226 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
227 * 00 -> No Alternatives, I2C1 is used for onboard EEPROM
228 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
229 * EEPROM
230 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
231 * use PSC2 as UART: Bits 24-27 (mask: 0x00000070): 0100
232 * use PSC3 as UART: Bits 20-23 (mask: 0x00000700): 0100
233 * use PSC6 as UART: Bits 9-11 (mask: 0x00700000): 0101
234 */
235 #define CONFIG_SYS_GPS_PORT_CONFIG 0x01501444
236
237 /*
238 * RTC configuration
239 */
240 #define CONFIG_RTC_RTC4543 1 /* use external RTC */
241
242 /*
243 * Software (bit-bang) three wire serial configuration
244 *
245 * Note that we need the ifdefs because otherwise compilation of
246 * mkimage.c fails.
247 */
248 #define CONFIG_SOFT_TWS 1
249
250 #ifdef TWS_IMPLEMENTATION
251 #include <mpc5xxx.h>
252 #include <asm/io.h>
253
254 #define TWS_CE MPC5XXX_GPIO_WKUP_PSC1_4 /* GPIO_WKUP_0 */
255 #define TWS_WR MPC5XXX_GPIO_WKUP_PSC2_4 /* GPIO_WKUP_1 */
256 #define TWS_DATA MPC5XXX_GPIO_SINT_PSC3_4 /* GPIO_SINT_0 */
257 #define TWS_CLK MPC5XXX_GPIO_SINT_PSC3_5 /* GPIO_SINT_1 */
258
tws_ce(unsigned bit)259 static inline void tws_ce(unsigned bit)
260 {
261 struct mpc5xxx_wu_gpio *wu_gpio =
262 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
263 if (bit)
264 setbits_8(&wu_gpio->dvo, TWS_CE);
265 else
266 clrbits_8(&wu_gpio->dvo, TWS_CE);
267 }
268
tws_wr(unsigned bit)269 static inline void tws_wr(unsigned bit)
270 {
271 struct mpc5xxx_wu_gpio *wu_gpio =
272 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
273 if (bit)
274 setbits_8(&wu_gpio->dvo, TWS_WR);
275 else
276 clrbits_8(&wu_gpio->dvo, TWS_WR);
277 }
278
tws_clk(unsigned bit)279 static inline void tws_clk(unsigned bit)
280 {
281 struct mpc5xxx_gpio *gpio =
282 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
283 if (bit)
284 setbits_8(&gpio->sint_dvo, TWS_CLK);
285 else
286 clrbits_8(&gpio->sint_dvo, TWS_CLK);
287 }
288
tws_data(unsigned bit)289 static inline void tws_data(unsigned bit)
290 {
291 struct mpc5xxx_gpio *gpio =
292 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
293 if (bit)
294 setbits_8(&gpio->sint_dvo, TWS_DATA);
295 else
296 clrbits_8(&gpio->sint_dvo, TWS_DATA);
297 }
298
tws_data_read(void)299 static inline unsigned tws_data_read(void)
300 {
301 struct mpc5xxx_gpio *gpio =
302 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
303 return !!(in_8(&gpio->sint_ival) & TWS_DATA);
304 }
305
tws_data_config_output(unsigned output)306 static inline void tws_data_config_output(unsigned output)
307 {
308 struct mpc5xxx_gpio *gpio =
309 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
310 if (output)
311 setbits_8(&gpio->sint_ddr, TWS_DATA);
312 else
313 clrbits_8(&gpio->sint_ddr, TWS_DATA);
314 }
315 #endif /* TWS_IMPLEMENTATION */
316
317 /*
318 * Miscellaneous configurable options
319 */
320 #define CONFIG_SYS_LONGHELP /* undef to save memory */
321 #if defined(CONFIG_CMD_KGDB)
322 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
323 #else
324 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
325 #endif
326 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
327 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
328 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
329
330 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
331 #if defined(CONFIG_CMD_KGDB)
332 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
333 #endif
334
335 /* Enable an alternate, more extensive memory test */
336 #define CONFIG_SYS_ALT_MEMTEST
337
338 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
339 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
340
341 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
342
343 /*
344 * Enable loopw command.
345 */
346 #define CONFIG_LOOPW
347
348 /*
349 * Various low-level settings
350 */
351 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
352 #define CONFIG_SYS_HID0_FINAL HID0_ICE
353
354 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
355 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
356 #define CONFIG_SYS_BOOTCS_CFG 0x00087800 /* for pci_clk = 66 MHz */
357 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
358 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
359
360 /* 32Mbit SRAM @0x30000000 */
361 #define CONFIG_SYS_CS1_START 0x30000000
362 #define CONFIG_SYS_CS1_SIZE 0x00400000
363 #define CONFIG_SYS_CS1_CFG 0x31800 /* for pci_clk = 33 MHz */
364
365 /* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
366 #define CONFIG_SYS_CS2_START 0x80000000
367 #define CONFIG_SYS_CS2_SIZE 0x0001000
368 #define CONFIG_SYS_CS2_CFG 0x21800 /* for pci_clk = 33 MHz */
369
370 /* GPIO in @0x30400000 */
371 #define CONFIG_SYS_CS3_START 0x30400000
372 #define CONFIG_SYS_CS3_SIZE 0x00100000
373 #define CONFIG_SYS_CS3_CFG 0x31800 /* for pci_clk = 33 MHz */
374
375 #define CONFIG_SYS_CS_BURST 0x00000000
376 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
377
378 /*-----------------------------------------------------------------------
379 * USB stuff
380 *-----------------------------------------------------------------------
381 */
382 #define CONFIG_USB_OHCI
383 #define CONFIG_USB_CLOCK 0x00015555
384 #define CONFIG_USB_CONFIG 0x00001000
385 #define CONFIG_USB_STORAGE
386
387 /*-----------------------------------------------------------------------
388 * IDE/ATA stuff Supports IDE harddisk
389 *-----------------------------------------------------------------------
390 */
391
392 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
393
394 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
395 #undef CONFIG_IDE_LED /* LED for ide not supported */
396
397 #define CONFIG_IDE_PREINIT
398
399 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
400 #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
401
402 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
403 #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
404 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0060 /* Offset for data I/O */
405 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */
406 #define CONFIG_SYS_ATA_ALT_OFFSET 0x005C /* Offset for alternate registers */
407 #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
408
409 #define CONFIG_ATAPI 1
410
411 #define CONFIG_SYS_BRIGHTNESS 0xFF /* LCD Default Brightness (255 = off) */
412
413 #endif /* __CONFIG_H */
414