1 /* 2 * (C) Copyright 2007 3 * Stefan Roese, DENX Software Engineering, sr@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /************************************************************************ 9 * zeus.h - configuration for Zeus board 10 ***********************************************************************/ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /*----------------------------------------------------------------------- 15 * High Level Configuration Options 16 *----------------------------------------------------------------------*/ 17 #define CONFIG_ZEUS 1 /* Board is Zeus */ 18 #define CONFIG_405EP 1 /* Specifc 405EP support*/ 19 20 #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 21 22 #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ 23 24 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ 25 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ 26 27 #define PLLMR0_DEFAULT PLLMR0_333_111_55_111 28 #define PLLMR1_DEFAULT PLLMR1_333_111_55_111 29 30 #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ 31 32 #define CONFIG_OVERWRITE_ETHADDR_ONCE 1 33 34 #define CONFIG_PPC4xx_EMAC 35 #define CONFIG_MII 1 /* MII PHY management */ 36 #define CONFIG_PHY_ADDR 0x01 /* PHY address */ 37 #define CONFIG_HAS_ETH1 1 38 #define CONFIG_PHY1_ADDR 0x11 /* EMAC1 PHY address */ 39 #define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ 40 #define CONFIG_PHY_RESET 1 41 #define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ 42 43 /* 44 * BOOTP options 45 */ 46 #define CONFIG_BOOTP_BOOTFILESIZE 47 #define CONFIG_BOOTP_BOOTPATH 48 #define CONFIG_BOOTP_GATEWAY 49 #define CONFIG_BOOTP_HOSTNAME 50 51 /* 52 * Command line configuration. 53 */ 54 #define CONFIG_CMD_ASKENV 55 #define CONFIG_CMD_CACHE 56 #define CONFIG_CMD_DHCP 57 #define CONFIG_CMD_DIAG 58 #define CONFIG_CMD_EEPROM 59 #define CONFIG_CMD_ELF 60 #define CONFIG_CMD_I2C 61 #define CONFIG_CMD_IRQ 62 #define CONFIG_CMD_MII 63 #define CONFIG_CMD_PING 64 #define CONFIG_CMD_REGINFO 65 66 /* POST support */ 67 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ 68 CONFIG_SYS_POST_CPU | \ 69 CONFIG_SYS_POST_CACHE | \ 70 CONFIG_SYS_POST_UART | \ 71 CONFIG_SYS_POST_ETHER) 72 73 #define CONFIG_SYS_POST_ETHER_EXT_LOOPBACK /* eth POST using ext loopack connector */ 74 75 /* Define here the base-addresses of the UARTs to test in POST */ 76 #define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1 } 77 78 #define CONFIG_LOGBUFFER 79 #define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */ 80 81 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ 82 83 #undef CONFIG_WATCHDOG /* watchdog disabled */ 84 85 /*----------------------------------------------------------------------- 86 * SDRAM 87 *----------------------------------------------------------------------*/ 88 /* 89 * SDRAM configuration (please see cpu/ppc/sdram.[ch]) 90 */ 91 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ 92 #define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */ 93 94 /* SDRAM timings used in datasheet */ 95 #define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */ 96 #define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */ 97 #define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */ 98 #define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ 99 #define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */ 100 101 /*----------------------------------------------------------------------- 102 * Serial Port 103 *----------------------------------------------------------------------*/ 104 #define CONFIG_CONS_INDEX 1 105 #define CONFIG_SYS_NS16550 106 #define CONFIG_SYS_NS16550_SERIAL 107 #define CONFIG_SYS_NS16550_REG_SIZE 1 108 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 109 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ 110 #define CONFIG_SYS_BASE_BAUD 691200 111 #define CONFIG_BAUDRATE 115200 112 113 #define CONFIG_SYS_BAUDRATE_TABLE \ 114 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} 115 116 /*----------------------------------------------------------------------- 117 * Miscellaneous configurable options 118 *----------------------------------------------------------------------*/ 119 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 120 #if defined(CONFIG_CMD_KGDB) 121 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 122 #else 123 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 124 #endif 125 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 126 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 127 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 128 129 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 130 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 131 132 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 133 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ 134 135 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 136 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 137 138 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 139 #define CONFIG_LOOPW 1 /* enable loopw command */ 140 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ 141 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ 142 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ 143 144 /*----------------------------------------------------------------------- 145 * I2C 146 *----------------------------------------------------------------------*/ 147 #define CONFIG_SYS_I2C 148 #define CONFIG_SYS_I2C_PPC4XX 149 #define CONFIG_SYS_I2C_PPC4XX_CH0 150 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 151 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F 152 153 /* these are for the ST M24C02 2kbit serial i2c eeprom */ 154 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ 155 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 156 /* mask of address bits that overflow into the "EEPROM chip address" */ 157 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 158 159 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 8 byte write page size */ 160 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 161 162 /* 163 * The layout of the I2C EEPROM, used for bootstrap setup and for board- 164 * specific values, like ethaddr... that can be restored via the sw-reset 165 * button 166 */ 167 #define FACTORY_RESET_I2C_EEPROM 0x50 168 #define FACTORY_RESET_ENV_OFFS 0x80 169 #define FACTORY_RESET_ENV_SIZE 0x80 170 171 /*----------------------------------------------------------------------- 172 * Start addresses for the final memory configuration 173 * (Set up by the startup code) 174 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 175 */ 176 #define CONFIG_SYS_SDRAM_BASE 0x00000000 177 #define CONFIG_SYS_FLASH_BASE 0xFF000000 178 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ 179 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ 180 #define CONFIG_SYS_MONITOR_BASE (-CONFIG_SYS_MONITOR_LEN) 181 182 /* 183 * For booting Linux, the board info and command line data 184 * have to be in the first 8 MB of memory, since this is 185 * the maximum mapped by the Linux kernel during initialization. 186 */ 187 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 188 189 /*----------------------------------------------------------------------- 190 * FLASH organization 191 */ 192 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ 193 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ 194 195 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 196 197 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 198 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ 199 200 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 201 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 202 203 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ 204 #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */ 205 206 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 207 #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ 208 209 #ifdef CONFIG_ENV_IS_IN_FLASH 210 #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ 211 #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) 212 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ 213 214 /* Address and size of Redundant Environment Sector */ 215 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) 216 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 217 #endif 218 219 /*----------------------------------------------------------------------- 220 * Definitions for initial stack pointer and data area (in data cache) 221 */ 222 /* use on chip memory (OCM) for temperary stack until sdram is tested */ 223 #define CONFIG_SYS_TEMP_STACK_OCM 1 224 225 /* On Chip Memory location */ 226 #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 227 #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 228 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM */ 229 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ 230 231 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 232 /* reserve some memory for POST and BOOT limit info */ 233 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 16) 234 235 /* extra data in OCM */ 236 #define CONFIG_SYS_POST_MAGIC \ 237 (CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 8) 238 #define CONFIG_SYS_POST_VAL \ 239 (CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 12) 240 241 /*----------------------------------------------------------------------- 242 * External Bus Controller (EBC) Setup 243 */ 244 245 /* Memory Bank 0 (Flash 16M) initialization */ 246 #define CONFIG_SYS_EBC_PB0AP 0x05815600 247 #define CONFIG_SYS_EBC_PB0CR 0xFF09A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */ 248 249 /*----------------------------------------------------------------------- 250 * Definitions for GPIO setup (PPC405EP specific) 251 * 252 * GPIO0[0] - External Bus Controller BLAST output 253 * GPIO0[1-9] - Instruction trace outputs 254 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs 255 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs 256 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs 257 * GPIO0[24-27] - UART0 control signal inputs/outputs 258 * GPIO0[28-29] - UART1 data signal input/output 259 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs 260 */ 261 #define CONFIG_SYS_GPIO0_OSRL 0x15555550 /* Chip selects */ 262 #define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* UART_DTR-pin 27 alt out */ 263 #define CONFIG_SYS_GPIO0_ISR1L 0x10000041 /* Pin 2, 12 is input */ 264 #define CONFIG_SYS_GPIO0_ISR1H 0x15505440 /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */ 265 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 266 #define CONFIG_SYS_GPIO0_TSRH 0x00000000 267 #define CONFIG_SYS_GPIO0_TCR 0xBFF68317 /* 3-state OUT: 22/23/29; 12,2 is not 3-state */ 268 #define CONFIG_SYS_GPIO0_ODR 0x00000000 269 270 #define CONFIG_SYS_GPIO_SW_RESET 1 271 #define CONFIG_SYS_GPIO_ZEUS_PE 12 272 #define CONFIG_SYS_GPIO_LED_RED 22 273 #define CONFIG_SYS_GPIO_LED_GREEN 23 274 275 /* Time in milli-seconds */ 276 #define CONFIG_SYS_TIME_POST 5000 277 #define CONFIG_SYS_TIME_FACTORY_RESET 10000 278 279 #if defined(CONFIG_CMD_KGDB) 280 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 281 #endif 282 283 /* 284 * Pass open firmware flat tree 285 */ 286 #define CONFIG_OF_LIBFDT 287 #define CONFIG_OF_BOARD_SETUP 288 289 /* ENVIRONMENT VARS */ 290 291 #define CONFIG_PREBOOT "echo;echo Welcome to Bulletendpoints board v1.1;echo" 292 #define CONFIG_IPADDR 192.168.1.10 293 #define CONFIG_SERVERIP 192.168.1.100 294 #define CONFIG_GATEWAYIP 192.168.1.100 295 #if 0 296 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 297 #else 298 #define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ 299 #endif 300 301 #define CONFIG_EXTRA_ENV_SETTINGS \ 302 "logversion=2\0" \ 303 "hostname=zeus\0" \ 304 "netdev=eth0\0" \ 305 "ethact=ppc_4xx_eth0\0" \ 306 "netmask=255.255.255.0\0" \ 307 "ramdisk_size=50000\0" \ 308 "nfsargs=setenv bootargs root=/dev/nfs rw" \ 309 " nfsroot=${serverip}:${rootpath}\0" \ 310 "ramargs=setenv bootargs root=/dev/ram rw" \ 311 " ramdisk_size=${ramdisk_size}\0" \ 312 "addip=setenv bootargs ${bootargs} " \ 313 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 314 ":${hostname}:${netdev}:off panic=1\0" \ 315 "addtty=setenv bootargs ${bootargs} console=ttyS0," \ 316 "${baudrate}\0" \ 317 "net_nfs=tftp ${kernel_mem_addr} ${file_kernel};" \ 318 "run nfsargs addip addtty;bootm\0" \ 319 "net_ram=tftp ${kernel_mem_addr} ${file_kernel};" \ 320 "tftp ${ramdisk_mem_addr} ${file_fs};" \ 321 "run ramargs addip addtty;" \ 322 "bootm ${kernel_mem_addr} ${ramdisk_mem_addr}\0" \ 323 "rootpath=/target_fs/zeus\0" \ 324 "kernel_fl_addr=ff000000\0" \ 325 "kernel_mem_addr=200000\0" \ 326 "ramdisk_fl_addr=ff300000\0" \ 327 "ramdisk_mem_addr=4000000\0" \ 328 "uboot_fl_addr=fffc0000\0" \ 329 "uboot_mem_addr=100000\0" \ 330 "file_uboot=/zeus/u-boot.bin\0" \ 331 "tftp_uboot=tftp 100000 ${file_uboot}\0" \ 332 "update_uboot=protect off fffc0000 ffffffff;" \ 333 "era fffc0000 ffffffff;cp.b 100000 fffc0000 40000;" \ 334 "protect on fffc0000 ffffffff\0" \ 335 "upd_uboot=run tftp_uboot;run update_uboot\0" \ 336 "file_kernel=/zeus/uImage_ba\0" \ 337 "tftp_kernel=tftp 100000 ${file_kernel}\0" \ 338 "update_kernel=protect off ff000000 ff17ffff;" \ 339 "era ff000000 ff17ffff;cp.b 100000 ff000000 180000\0" \ 340 "upd_kernel=run tftp_kernel;run update_kernel\0" \ 341 "file_fs=/zeus/rootfs_ba.img\0" \ 342 "tftp_fs=tftp 100000 ${file_fs}\0" \ 343 "update_fs=protect off ff300000 ff87ffff;era ff300000 ff87ffff;"\ 344 "cp.b 100000 ff300000 580000\0" \ 345 "upd_fs=run tftp_fs;run update_fs\0" \ 346 "bootcmd=chkreset;run ramargs addip addtty addmisc;" \ 347 "bootm ${kernel_fl_addr} ${ramdisk_fl_addr}\0" \ 348 "" 349 350 #endif /* __CONFIG_H */ 351