1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
2 /*
3 * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
4 */
5
6 #ifndef _STM32PROG_H_
7 #define _STM32PROG_H_
8
9 /* - phase defines ------------------------------------------------*/
10 #define PHASE_FLASHLAYOUT 0x00
11 #define PHASE_FIRST_USER 0x10
12 #define PHASE_LAST_USER 0xF0
13 #define PHASE_CMD 0xF1
14 #define PHASE_OTP 0xF2
15 #define PHASE_PMIC 0xF4
16 #define PHASE_END 0xFE
17 #define PHASE_RESET 0xFF
18 #define PHASE_DO_RESET 0x1FF
19
20 #define DEFAULT_ADDRESS 0xFFFFFFFF
21
22 #define OTP_SIZE 1024
23 #define PMIC_SIZE 8
24
25 enum stm32prog_target {
26 STM32PROG_NONE,
27 STM32PROG_MMC,
28 STM32PROG_NAND,
29 STM32PROG_NOR,
30 STM32PROG_SPI_NAND,
31 STM32PROG_RAM
32 };
33
34 enum stm32prog_link_t {
35 LINK_SERIAL,
36 LINK_USB,
37 LINK_UNDEFINED,
38 };
39
40 enum stm32prog_header_t {
41 HEADER_NONE,
42 HEADER_STM32IMAGE,
43 HEADER_FIP,
44 };
45
46 struct image_header_s {
47 enum stm32prog_header_t type;
48 u32 image_checksum;
49 u32 image_length;
50 };
51
52 struct raw_header_s {
53 u32 magic_number;
54 u32 image_signature[64 / 4];
55 u32 image_checksum;
56 u32 header_version;
57 u32 image_length;
58 u32 image_entry_point;
59 u32 reserved1;
60 u32 load_address;
61 u32 reserved2;
62 u32 version_number;
63 u32 option_flags;
64 u32 ecdsa_algorithm;
65 u32 ecdsa_public_key[64 / 4];
66 u32 padding[83 / 4];
67 u32 binary_type;
68 };
69
70 #define BL_HEADER_SIZE sizeof(struct raw_header_s)
71
72 /* partition type in flashlayout file */
73 enum stm32prog_part_type {
74 PART_BINARY,
75 PART_SYSTEM,
76 PART_FILESYSTEM,
77 RAW_IMAGE
78 };
79
80 /* device information */
81 struct stm32prog_dev_t {
82 enum stm32prog_target target;
83 char dev_id;
84 u32 erase_size;
85 struct mmc *mmc;
86 struct mtd_info *mtd;
87 /* list of partition for this device / ordered in offset */
88 struct list_head part_list;
89 bool full_update;
90 };
91
92 /* partition information build from FlashLayout and device */
93 struct stm32prog_part_t {
94 /* FlashLayout information */
95 int option;
96 int id;
97 enum stm32prog_part_type part_type;
98 enum stm32prog_target target;
99 char dev_id;
100
101 /* partition name
102 * (16 char in gpt, + 1 for null terminated string
103 */
104 char name[16 + 1];
105 u64 addr;
106 u64 size;
107 enum stm32prog_part_type bin_nb; /* SSBL repeatition */
108
109 /* information on associated device */
110 struct stm32prog_dev_t *dev; /* pointer to device */
111 s16 part_id; /* partition id in device */
112 int alt_id; /* alt id in usb/dfu */
113
114 struct list_head list;
115 };
116
117 #define STM32PROG_MAX_DEV 5
118 struct stm32prog_data {
119 /* Layout information */
120 int dev_nb; /* device number*/
121 struct stm32prog_dev_t dev[STM32PROG_MAX_DEV]; /* array of device */
122 int part_nb; /* nb of partition */
123 struct stm32prog_part_t *part_array; /* array of partition */
124 bool tee_detected;
125 bool fsbl_nor_detected;
126
127 /* command internal information */
128 unsigned int phase;
129 u32 offset;
130 char error[255];
131 struct stm32prog_part_t *cur_part;
132 u32 *otp_part;
133 u8 pmic_part[PMIC_SIZE];
134
135 /* STM32 header information */
136 struct raw_header_s *header_data;
137 struct image_header_s header;
138
139 /* SERIAL information */
140 u32 cursor;
141 u32 packet_number;
142 u32 checksum;
143 u8 *buffer; /* size = USART_RAM_BUFFER_SIZE*/
144 int dfu_seq;
145 u8 read_phase;
146
147 /* bootm information */
148 u32 uimage;
149 u32 dtb;
150 };
151
152 extern struct stm32prog_data *stm32prog_data;
153
154 /* OTP access */
155 int stm32prog_otp_write(struct stm32prog_data *data, u32 offset,
156 u8 *buffer, long *size);
157 int stm32prog_otp_read(struct stm32prog_data *data, u32 offset,
158 u8 *buffer, long *size);
159 int stm32prog_otp_start(struct stm32prog_data *data);
160
161 /* PMIC access */
162 int stm32prog_pmic_write(struct stm32prog_data *data, u32 offset,
163 u8 *buffer, long *size);
164 int stm32prog_pmic_read(struct stm32prog_data *data, u32 offset,
165 u8 *buffer, long *size);
166 int stm32prog_pmic_start(struct stm32prog_data *data);
167
168 /* generic part*/
169 void stm32prog_header_check(struct raw_header_s *raw_header,
170 struct image_header_s *header);
171 int stm32prog_dfu_init(struct stm32prog_data *data);
172 void stm32prog_next_phase(struct stm32prog_data *data);
173 void stm32prog_do_reset(struct stm32prog_data *data);
174
175 char *stm32prog_get_error(struct stm32prog_data *data);
176
177 #define stm32prog_err(args...) {\
178 if (data->phase != PHASE_RESET) { \
179 sprintf(data->error, args); \
180 data->phase = PHASE_RESET; \
181 log_err("Error: %s\n", data->error); } \
182 }
183
184 /* Main function */
185 int stm32prog_init(struct stm32prog_data *data, ulong addr, ulong size);
186 void stm32prog_clean(struct stm32prog_data *data);
187
188 #ifdef CONFIG_CMD_STM32PROG_SERIAL
189 int stm32prog_serial_init(struct stm32prog_data *data, int link_dev);
190 bool stm32prog_serial_loop(struct stm32prog_data *data);
191 #else
stm32prog_serial_init(struct stm32prog_data * data,int link_dev)192 static inline int stm32prog_serial_init(struct stm32prog_data *data, int link_dev)
193 {
194 return -ENOSYS;
195 }
196
stm32prog_serial_loop(struct stm32prog_data * data)197 static inline bool stm32prog_serial_loop(struct stm32prog_data *data)
198 {
199 return false;
200 }
201 #endif
202
203 #ifdef CONFIG_CMD_STM32PROG_USB
204 bool stm32prog_usb_loop(struct stm32prog_data *data, int dev);
205 #else
stm32prog_usb_loop(struct stm32prog_data * data,int dev)206 static inline bool stm32prog_usb_loop(struct stm32prog_data *data, int dev)
207 {
208 return false;
209 }
210 #endif
211
212 #endif
213