1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Freescale MX28EVK IOMUX setup
4  *
5  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
6  * on behalf of DENX Software Engineering GmbH
7  */
8 
9 #include <common.h>
10 #include <config.h>
11 #include <asm/io.h>
12 #include <asm/arch/iomux-mx28.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/sys_proto.h>
15 
16 #define	MUX_CONFIG_SSP0	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
17 #define	MUX_CONFIG_GPMI	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
18 #define	MUX_CONFIG_ENET	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
19 #define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
20 #define	MUX_CONFIG_SSP2	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
21 #define	MUX_CONFIG_LCD	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
22 
23 const iomux_cfg_t iomux_setup[] = {
24 	/* DUART */
25 	MX28_PAD_PWM0__DUART_RX,
26 	MX28_PAD_PWM1__DUART_TX,
27 
28 	/* MMC0 */
29 	MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
30 	MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
31 	MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
32 	MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
33 	MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,
34 	MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,
35 	MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
36 	MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
37 	MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
38 	MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
39 		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
40 	MX28_PAD_SSP0_SCK__SSP0_SCK |
41 		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
42 	/* write protect */
43 	MX28_PAD_SSP1_SCK__GPIO_2_12,
44 	/* MMC0 slot power enable */
45 	MX28_PAD_PWM3__GPIO_3_28 |
46 		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
47 
48 #ifdef CONFIG_NAND_MXS
49 	/* GPMI NAND */
50 	MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
51 	MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
52 	MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
53 	MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
54 	MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
55 	MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
56 	MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
57 	MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
58 	MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
59 	MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
60 	MX28_PAD_GPMI_RDN__GPMI_RDN |
61 		(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
62 	MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
63 	MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
64 	MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
65 	MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
66 #endif
67 
68 	/* FEC0 */
69 	MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
70 	MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
71 	MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
72 	MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
73 	MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
74 	MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
75 	MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
76 	MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
77 	MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
78 	/* FEC0 Enable */
79 	MX28_PAD_SSP1_DATA3__GPIO_2_15 |
80 		(MXS_PAD_12MA | MXS_PAD_3V3),
81 	/* FEC0 Reset */
82 	MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
83 		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
84 
85 	/* FEC1 */
86 	MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET,
87 	MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET,
88 	MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET,
89 	MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
90 	MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET,
91 	MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
92 
93 	/* EMI */
94 	MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
95 	MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
96 	MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
97 	MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
98 	MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
99 	MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
100 	MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
101 	MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
102 	MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
103 	MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
104 	MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
105 	MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
106 	MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
107 	MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
108 	MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
109 	MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
110 	MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
111 	MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
112 	MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
113 	MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
114 	MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
115 	MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
116 	MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
117 	MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
118 	MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
119 
120 	MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
121 	MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
122 	MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
123 	MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
124 	MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
125 	MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
126 	MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
127 	MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
128 	MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
129 	MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
130 	MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
131 	MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
132 	MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
133 	MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
134 	MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
135 	MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
136 	MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
137 	MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
138 	MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
139 	MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
140 	MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
141 	MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
142 	MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
143 	MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
144 
145 	/* SPI2 (for SPI flash) */
146 	MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
147 	MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
148 	MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
149 	MX28_PAD_SSP2_SS0__SSP2_D3 |
150 		(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
151 	/* I2C */
152 	MX28_PAD_I2C0_SCL__I2C0_SCL,
153 	MX28_PAD_I2C0_SDA__I2C0_SDA,
154 
155 	/* LCD */
156 	MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
157 	MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
158 	MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
159 	MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
160 	MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
161 	MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
162 	MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
163 	MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
164 	MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
165 	MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
166 	MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
167 	MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
168 	MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
169 	MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
170 	MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
171 	MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
172 	MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
173 	MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
174 	MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD,
175 	MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD,
176 	MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD,
177 	MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
178 	MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
179 	MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
180 	MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD,
181 	MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD,
182 	MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD,
183 	MX28_PAD_LCD_CS__LCD_ENABLE | MUX_CONFIG_LCD,
184 	MX28_PAD_LCD_RESET__GPIO_3_30 | MUX_CONFIG_LCD, /* LCD power */
185 	MX28_PAD_PWM2__GPIO_3_18 | MUX_CONFIG_LCD, /* LCD contrast */
186 };
187 
188 #define HW_DRAM_CTL29	(0x74 >> 2)
189 #define CS_MAP		0xf
190 #define COLUMN_SIZE	0x2
191 #define ADDR_PINS	0x1
192 #define APREBIT		0xa
193 
194 #define HW_DRAM_CTL29_CONFIG	(CS_MAP << 24 | COLUMN_SIZE << 16 | \
195 					ADDR_PINS << 8 | APREBIT)
196 
mxs_adjust_memory_params(uint32_t * dram_vals)197 void mxs_adjust_memory_params(uint32_t *dram_vals)
198 {
199 	dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG;
200 }
201 
board_init_ll(const uint32_t arg,const uint32_t * resptr)202 void board_init_ll(const uint32_t arg, const uint32_t *resptr)
203 {
204 	mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
205 }
206