1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Board functions for Siemens CORVUS (AT91SAM9G45) based board
4 * (C) Copyright 2013 Siemens AG
5 *
6 * Based on:
7 * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
8 * (C) Copyright 2007-2008
9 * Stelian Pop <stelian@popies.net>
10 * Lead Tech Design <www.leadtechdesign.com>
11 */
12
13 #include <common.h>
14 #include <dm.h>
15 #include <init.h>
16 #include <log.h>
17 #include <asm/global_data.h>
18 #include <asm/io.h>
19 #include <asm/arch/at91sam9g45_matrix.h>
20 #include <asm/arch/at91sam9_smc.h>
21 #include <asm/arch/at91_common.h>
22 #include <asm/arch/at91_rstc.h>
23 #include <asm/arch/atmel_serial.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/gpio.h>
26 #include <asm/arch/clk.h>
27 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
28 #include <net.h>
29 #endif
30 #ifndef CONFIG_DM_ETH
31 #include <netdev.h>
32 #endif
33 #include <spi.h>
34
35 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
36 #include <asm/arch/atmel_usba_udc.h>
37 #endif
38
39 DECLARE_GLOBAL_DATA_PTR;
40
corvus_request_gpio(void)41 static void corvus_request_gpio(void)
42 {
43 gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
44 gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
45 gpio_request(AT91_PIN_PD7, "d0");
46 gpio_request(AT91_PIN_PD8, "d1");
47 gpio_request(AT91_PIN_PA12, "d2");
48 gpio_request(AT91_PIN_PA13, "d3");
49 gpio_request(AT91_PIN_PA15, "d4");
50 gpio_request(AT91_PIN_PB7, "recovery button");
51 gpio_request(AT91_PIN_PD1, "USB0");
52 gpio_request(AT91_PIN_PD3, "USB1");
53 gpio_request(AT91_PIN_PB18, "SPICS1");
54 gpio_request(AT91_PIN_PB3, "SPICS0");
55 gpio_request(CONFIG_RED_LED, "red led");
56 gpio_request(CONFIG_GREEN_LED, "green led");
57 }
58
corvus_nand_hw_init(void)59 static void corvus_nand_hw_init(void)
60 {
61 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
62 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
63 unsigned long csa;
64
65 /* Enable CS3 */
66 csa = readl(&matrix->ebicsa);
67 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
68 writel(csa, &matrix->ebicsa);
69
70 /* Configure SMC CS3 for NAND/SmartMedia */
71 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
72 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
73 &smc->cs[3].setup);
74 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
75 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
76 &smc->cs[3].pulse);
77 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
78 &smc->cs[3].cycle);
79 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
80 AT91_SMC_MODE_EXNW_DISABLE |
81 #ifdef CONFIG_SYS_NAND_DBW_16
82 AT91_SMC_MODE_DBW_16 |
83 #else /* CONFIG_SYS_NAND_DBW_8 */
84 AT91_SMC_MODE_DBW_8 |
85 #endif
86 AT91_SMC_MODE_TDF_CYCLE(3),
87 &smc->cs[3].mode);
88
89 at91_periph_clk_enable(ATMEL_ID_PIOC);
90 at91_periph_clk_enable(ATMEL_ID_PIOA);
91
92 /* Enable NandFlash */
93 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
94 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
95 }
96
97 #if defined(CONFIG_SPL_BUILD)
98 #include <spl.h>
99 #include <nand.h>
100
spl_board_init(void)101 void spl_board_init(void)
102 {
103 corvus_request_gpio();
104 /*
105 * For on the sam9m10g45ek board, the chip wm9711 stay in the test
106 * mode, so it need do some action to exit mode.
107 */
108 at91_set_gpio_output(AT91_PIN_PD7, 0);
109 at91_set_gpio_output(AT91_PIN_PD8, 0);
110 at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
111 at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
112 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
113 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
114 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
115
116 corvus_nand_hw_init();
117
118 /* Configure recovery button PINs */
119 at91_set_gpio_input(AT91_PIN_PB7, 1);
120
121 /* check if button is pressed */
122 if (at91_get_gpio_value(AT91_PIN_PB7) == 0) {
123 u32 boot_device;
124
125 debug("Recovery button pressed\n");
126 boot_device = spl_boot_device();
127 switch (boot_device) {
128 #ifdef CONFIG_SPL_NAND_SUPPORT
129 case BOOT_DEVICE_NAND:
130 nand_init();
131 spl_nand_erase_one(0, 0);
132 break;
133 #endif
134 }
135 }
136 }
137
138 #include <asm/arch/atmel_mpddrc.h>
ddr2_conf(struct atmel_mpddrc_config * ddr2)139 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
140 {
141 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
142
143 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
144 ATMEL_MPDDRC_CR_NR_ROW_14 |
145 ATMEL_MPDDRC_CR_DIC_DS |
146 ATMEL_MPDDRC_CR_DQMS_SHARED |
147 ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
148 ddr2->rtr = 0x24b;
149
150 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
151 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
152 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
153 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 75 ns */
154 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
155 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
156 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
157 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
158
159 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
160 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
161 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
162 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
163
164 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
165 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
166 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
167 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
168 }
169
mem_init(void)170 void mem_init(void)
171 {
172 struct atmel_mpddrc_config ddr2;
173
174 ddr2_conf(&ddr2);
175
176 at91_system_clk_enable(AT91_PMC_DDR);
177
178 /* DDRAM2 Controller initialize */
179 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
180 }
181 #endif
182
183 #ifdef CONFIG_CMD_USB
taurus_usb_hw_init(void)184 static void taurus_usb_hw_init(void)
185 {
186 at91_periph_clk_enable(ATMEL_ID_PIODE);
187
188 at91_set_gpio_output(AT91_PIN_PD1, 0);
189 at91_set_gpio_output(AT91_PIN_PD3, 0);
190 }
191 #endif
192
193 #ifdef CONFIG_MACB
corvus_macb_hw_init(void)194 static void corvus_macb_hw_init(void)
195 {
196 /* Enable clock */
197 at91_periph_clk_enable(ATMEL_ID_EMAC);
198
199 /*
200 * Disable pull-up on:
201 * RXDV (PA15) => PHY normal mode (not Test mode)
202 * ERX0 (PA12) => PHY ADDR0
203 * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
204 *
205 * PHY has internal pull-down
206 */
207 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
208 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0);
209 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0);
210
211 at91_phy_reset();
212
213 /* Re-enable pull-up */
214 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
215 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
216 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
217
218 /* And the pins. */
219 at91_macb_hw_init();
220 }
221 #endif
222
board_early_init_f(void)223 int board_early_init_f(void)
224 {
225 at91_seriald_hw_init();
226 corvus_request_gpio();
227 return 0;
228 }
229
230 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
231 /* from ./arch/arm/mach-at91/armv7/sama5d3_devices.c */
at91_udp_hw_init(void)232 void at91_udp_hw_init(void)
233 {
234 /* Enable UPLL clock */
235 at91_upll_clk_enable();
236
237 /* Enable UDPHS clock */
238 at91_periph_clk_enable(ATMEL_ID_UDPHS);
239 }
240 #endif
241
board_init(void)242 int board_init(void)
243 {
244 /* address of boot parameters */
245 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
246
247 /* we have to request the gpios again after relocation */
248 corvus_request_gpio();
249 #ifdef CONFIG_CMD_NAND
250 corvus_nand_hw_init();
251 #endif
252 #ifdef CONFIG_ATMEL_SPI
253 at91_spi0_hw_init(1 << 4);
254 #endif
255 #ifdef CONFIG_MACB
256 corvus_macb_hw_init();
257 #endif
258 #ifdef CONFIG_CMD_USB
259 taurus_usb_hw_init();
260 #endif
261 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
262 at91_udp_hw_init();
263 usba_udc_probe(&pdata);
264 #endif
265 return 0;
266 }
267
dram_init(void)268 int dram_init(void)
269 {
270 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
271 CONFIG_SYS_SDRAM_SIZE);
272 return 0;
273 }
274
275 #ifndef CONFIG_DM_ETH
board_eth_init(struct bd_info * bis)276 int board_eth_init(struct bd_info *bis)
277 {
278 int rc = 0;
279 #ifdef CONFIG_MACB
280 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
281 #endif
282 return rc;
283 }
284 #endif
285
286 /* SPI chip select control */
spi_cs_is_valid(unsigned int bus,unsigned int cs)287 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
288 {
289 return bus == 0 && cs < 2;
290 }
291
spi_cs_activate(struct spi_slave * slave)292 void spi_cs_activate(struct spi_slave *slave)
293 {
294 switch (slave->cs) {
295 case 1:
296 at91_set_gpio_output(AT91_PIN_PB18, 0);
297 break;
298 case 0:
299 default:
300 at91_set_gpio_output(AT91_PIN_PB3, 0);
301 break;
302 }
303 }
304
spi_cs_deactivate(struct spi_slave * slave)305 void spi_cs_deactivate(struct spi_slave *slave)
306 {
307 switch (slave->cs) {
308 case 1:
309 at91_set_gpio_output(AT91_PIN_PB18, 1);
310 break;
311 case 0:
312 default:
313 at91_set_gpio_output(AT91_PIN_PB3, 1);
314 break;
315 }
316 }
317
318 static struct atmel_serial_plat at91sam9260_serial_plat = {
319 .base_addr = ATMEL_BASE_DBGU,
320 };
321
322 U_BOOT_DRVINFO(at91sam9260_serial) = {
323 .name = "serial_atmel",
324 .plat = &at91sam9260_serial_plat,
325 };
326