1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2004-2011
4 * Texas Instruments, <www.ti.com>
5 *
6 * Author :
7 * Manikandan Pillai <mani.pillai@ti.com>
8 *
9 * Derived from Beagle Board and 3430 SDP code by
10 * Richard Woodruff <r-woodruff2@ti.com>
11 * Syed Mohammed Khasim <khasim@ti.com>
12 */
13 #include <common.h>
14 #include <dm.h>
15 #include <env.h>
16 #include <init.h>
17 #include <net.h>
18 #include <ns16550.h>
19 #include <serial.h>
20 #include <asm/global_data.h>
21 #include <asm/io.h>
22 #include <asm/arch/mem.h>
23 #include <asm/arch/mux.h>
24 #include <asm/arch/sys_proto.h>
25 #include <asm/arch/mmc_host_def.h>
26 #include <asm/gpio.h>
27 #include <twl4030.h>
28 #include <asm/mach-types.h>
29 #include <linux/delay.h>
30 #include <linux/mtd/rawnand.h>
31 #include "evm.h"
32
33 #define OMAP3EVM_GPIO_ETH_RST_GEN1 64
34 #define OMAP3EVM_GPIO_ETH_RST_GEN2 7
35
36 #define CONFIG_SMC911X_BASE 0x2C000000
37
38 DECLARE_GLOBAL_DATA_PTR;
39
40 static u32 omap3_evm_version;
41
get_omap3_evm_rev(void)42 u32 get_omap3_evm_rev(void)
43 {
44 return omap3_evm_version;
45 }
46
omap3_evm_get_revision(void)47 static void omap3_evm_get_revision(void)
48 {
49 #if defined(CONFIG_SMC911X)
50 /*
51 * Board revision can be ascertained only by identifying
52 * the Ethernet chipset.
53 */
54 unsigned int smsc_id;
55
56 /* Ethernet PHY ID is stored at ID_REV register */
57 smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000;
58 printf("Read back SMSC id 0x%x\n", smsc_id);
59
60 switch (smsc_id) {
61 /* SMSC9115 chipset */
62 case 0x01150000:
63 omap3_evm_version = OMAP3EVM_BOARD_GEN_1;
64 break;
65 /* SMSC 9220 chipset */
66 case 0x92200000:
67 default:
68 omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
69 }
70 #else /* !CONFIG_SMC911X */
71 #if defined(CONFIG_STATIC_BOARD_REV)
72 /* Look for static defintion of the board revision */
73 omap3_evm_version = CONFIG_STATIC_BOARD_REV;
74 #else
75 /* Fallback to the default above */
76 omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
77 #endif /* CONFIG_STATIC_BOARD_REV */
78 #endif /* CONFIG_SMC911X */
79 }
80
81 #if defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)
82 /* MUSB port on OMAP3EVM Rev >= E requires extvbus programming. */
omap3_evm_need_extvbus(void)83 u8 omap3_evm_need_extvbus(void)
84 {
85 u8 retval = 0;
86
87 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
88 retval = 1;
89
90 return retval;
91 }
92 #endif /* CONFIG_USB_MUSB_{GADGET,HOST} */
93
94 /*
95 * Routine: board_init
96 * Description: Early hardware init.
97 */
board_init(void)98 int board_init(void)
99 {
100 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
101 /* board id for Linux */
102 gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
103 /* boot param addr */
104 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
105
106 return 0;
107 }
108
109 #if defined(CONFIG_SPL_OS_BOOT)
spl_start_uboot(void)110 int spl_start_uboot(void)
111 {
112 /* break into full u-boot on 'c' */
113 if (serial_tstc() && serial_getc() == 'c')
114 return 1;
115
116 return 0;
117 }
118 #endif /* CONFIG_SPL_OS_BOOT */
119
120 #if defined(CONFIG_SPL_BUILD)
121 /*
122 * Routine: get_board_mem_timings
123 * Description: If we use SPL then there is no x-loader nor config header
124 * so we have to setup the DDR timings ourself on the first bank. This
125 * provides the timing values back to the function that configures
126 * the memory.
127 */
get_board_mem_timings(struct board_sdrc_timings * timings)128 void get_board_mem_timings(struct board_sdrc_timings *timings)
129 {
130 int pop_mfr, pop_id;
131
132 /*
133 * We need to identify what PoP memory is on the board so that
134 * we know what timings to use. To map the ID values please see
135 * nand_ids.c
136 */
137 identify_nand_chip(&pop_mfr, &pop_id);
138
139 if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) {
140 /* 256MB DDR */
141 timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
142 timings->ctrla = HYNIX_V_ACTIMA_200;
143 timings->ctrlb = HYNIX_V_ACTIMB_200;
144 } else {
145 /* 128MB DDR */
146 timings->mcfg = MICRON_V_MCFG_165(128 << 20);
147 timings->ctrla = MICRON_V_ACTIMA_165;
148 timings->ctrlb = MICRON_V_ACTIMB_165;
149 }
150 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
151 timings->mr = MICRON_V_MR_165;
152 }
153 #endif /* CONFIG_SPL_BUILD */
154
155 /*
156 * Routine: misc_init_r
157 * Description: Init ethernet (done here so udelay works)
158 */
misc_init_r(void)159 int misc_init_r(void)
160 {
161 twl4030_power_init();
162
163 #if defined(CONFIG_SMC911X)
164 setup_net_chip();
165 #endif
166 omap3_evm_get_revision();
167
168 #if defined(CONFIG_SMC911X)
169 reset_net_chip();
170 #endif
171 omap_die_id_display();
172
173 #if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET) && \
174 !defined(CONFIG_SMC911X)
175 omap_die_id_usbethaddr();
176 #endif
177 return 0;
178 }
179
180 /*
181 * Routine: set_muxconf_regs
182 * Description: Setting up the configuration Mux registers specific to the
183 * hardware. Many pins need to be moved from protect to primary
184 * mode.
185 */
set_muxconf_regs(void)186 void set_muxconf_regs(void)
187 {
188 MUX_EVM();
189 }
190
191 #if defined(CONFIG_SMC911X)
192 /*
193 * Routine: setup_net_chip
194 * Description: Setting up the configuration GPMC registers specific to the
195 * Ethernet hardware.
196 */
setup_net_chip(void)197 static void setup_net_chip(void)
198 {
199 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
200
201 /* Configure GPMC registers */
202 writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
203 writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
204 writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
205 writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
206 writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
207 writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
208 writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
209
210 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
211 writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
212 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
213 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
214 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
215 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
216 &ctrl_base->gpmc_nadv_ale);
217 }
218
219 /**
220 * Reset the ethernet chip.
221 */
reset_net_chip(void)222 static void reset_net_chip(void)
223 {
224 int ret;
225 int rst_gpio;
226
227 if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1) {
228 rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN1;
229 } else {
230 rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN2;
231 }
232
233 ret = gpio_request(rst_gpio, "");
234 if (ret < 0) {
235 printf("Unable to get GPIO %d\n", rst_gpio);
236 return ;
237 }
238
239 /* Configure as output */
240 gpio_direction_output(rst_gpio, 0);
241
242 /* Send a pulse on the GPIO pin */
243 gpio_set_value(rst_gpio, 1);
244 udelay(1);
245 gpio_set_value(rst_gpio, 0);
246 udelay(1);
247 gpio_set_value(rst_gpio, 1);
248 }
249 #endif /* CONFIG_SMC911X */
250
251 #if defined(CONFIG_MMC)
board_mmc_power_init(void)252 void board_mmc_power_init(void)
253 {
254 twl4030_power_mmc_init(0);
255 }
256 #endif /* CONFIG_MMC */
257