1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2015-2016 Freescale Semiconductor, Inc.
4  * Copyright 2017 NXP
5  */
6 
7 #ifndef _EMAC_H_
8 #define _EMAC_H_
9 
10 #include <linux/bitops.h>
11 #define EMAC_IEVENT_REG		0x004
12 #define EMAC_IMASK_REG		0x008
13 #define EMAC_R_DES_ACTIVE_REG	0x010
14 #define EMAC_X_DES_ACTIVE_REG	0x014
15 #define EMAC_ECNTRL_REG		0x024
16 #define EMAC_MII_DATA_REG	0x040
17 #define EMAC_MII_CTRL_REG	0x044
18 #define EMAC_MIB_CTRL_STS_REG	0x064
19 #define EMAC_RCNTRL_REG		0x084
20 #define EMAC_TCNTRL_REG		0x0C4
21 #define EMAC_PHY_ADDR_LOW	0x0E4
22 #define EMAC_PHY_ADDR_HIGH	0x0E8
23 #define EMAC_TFWR_STR_FWD	0x144
24 #define EMAC_RX_SECTIOM_FULL	0x190
25 #define EMAC_TX_SECTION_EMPTY	0x1A0
26 #define EMAC_TRUNC_FL		0x1B0
27 
28 /* GEMAC definitions and settings */
29 #define EMAC_PORT_0			0
30 #define EMAC_PORT_1			1
31 
32 /* GEMAC Bit definitions */
33 #define EMAC_IEVENT_HBERR                BIT(31)
34 #define EMAC_IEVENT_BABR                 BIT(30)
35 #define EMAC_IEVENT_BABT                 BIT(29)
36 #define EMAC_IEVENT_GRA                  BIT(28)
37 #define EMAC_IEVENT_TXF                  BIT(27)
38 #define EMAC_IEVENT_TXB                  BIT(26)
39 #define EMAC_IEVENT_RXF                  BIT(25)
40 #define EMAC_IEVENT_RXB                  BIT(24)
41 #define EMAC_IEVENT_MII                  BIT(23)
42 #define EMAC_IEVENT_EBERR                BIT(22)
43 #define EMAC_IEVENT_LC                   BIT(21)
44 #define EMAC_IEVENT_RL                   BIT(20)
45 #define EMAC_IEVENT_UN                   BIT(19)
46 
47 #define EMAC_IMASK_HBERR                 BIT(31)
48 #define EMAC_IMASK_BABR                  BIT(30)
49 #define EMAC_IMASKT_BABT                 BIT(29)
50 #define EMAC_IMASK_GRA                   BIT(28)
51 #define EMAC_IMASKT_TXF                  BIT(27)
52 #define EMAC_IMASK_TXB                   BIT(26)
53 #define EMAC_IMASKT_RXF                  BIT(25)
54 #define EMAC_IMASK_RXB                   BIT(24)
55 #define EMAC_IMASK_MII                   BIT(23)
56 #define EMAC_IMASK_EBERR                 BIT(22)
57 #define EMAC_IMASK_LC                    BIT(21)
58 #define EMAC_IMASKT_RL                   BIT(20)
59 #define EMAC_IMASK_UN                    BIT(19)
60 
61 #define EMAC_RCNTRL_MAX_FL_SHIFT         16
62 #define EMAC_RCNTRL_LOOP                 BIT(0)
63 #define EMAC_RCNTRL_DRT                  BIT(1)
64 #define EMAC_RCNTRL_MII_MODE             BIT(2)
65 #define EMAC_RCNTRL_PROM                 BIT(3)
66 #define EMAC_RCNTRL_BC_REJ               BIT(4)
67 #define EMAC_RCNTRL_FCE                  BIT(5)
68 #define EMAC_RCNTRL_RGMII                BIT(6)
69 #define EMAC_RCNTRL_SGMII                BIT(7)
70 #define EMAC_RCNTRL_RMII                 BIT(8)
71 #define EMAC_RCNTRL_RMII_10T             BIT(9)
72 #define EMAC_RCNTRL_CRC_FWD		 BIT(10)
73 
74 #define EMAC_TCNTRL_GTS                  BIT(0)
75 #define EMAC_TCNTRL_HBC                  BIT(1)
76 #define EMAC_TCNTRL_FDEN                 BIT(2)
77 #define EMAC_TCNTRL_TFC_PAUSE            BIT(3)
78 #define EMAC_TCNTRL_RFC_PAUSE            BIT(4)
79 
80 #define EMAC_ECNTRL_RESET                BIT(0)      /* reset the EMAC */
81 #define EMAC_ECNTRL_ETHER_EN             BIT(1)      /* enable the EMAC */
82 #define EMAC_ECNTRL_SPEED                BIT(5)
83 #define EMAC_ECNTRL_DBSWAP               BIT(8)
84 
85 #define EMAC_X_WMRK_STRFWD               BIT(8)
86 
87 #define EMAC_X_DES_ACTIVE_TDAR           BIT(24)
88 #define EMAC_R_DES_ACTIVE_RDAR           BIT(24)
89 
90 #define EMAC_TFWR			(0x4)
91 #define EMAC_RX_SECTION_FULL_32		(0x5)
92 #define EMAC_TRUNC_FL_16K		(0x3FFF)
93 #define EMAC_TX_SECTION_EMPTY_30	(0x30)
94 #define EMAC_MIBC_NO_CLR_NO_DIS		(0x0)
95 
96 /*
97  * The possible operating speeds of the MAC, currently supporting 10, 100 and
98  * 1000Mb modes.
99  */
100 enum mac_speed {PFE_MAC_SPEED_10M, PFE_MAC_SPEED_100M, PFE_MAC_SPEED_1000M,
101 		PFE_MAC_SPEED_1000M_PCS};
102 
103 /* MII-related definitios */
104 #define EMAC_MII_DATA_ST         0x40000000      /* Start of frame delimiter */
105 #define EMAC_MII_DATA_OP_RD      0x20000000      /* Perform a read operation */
106 #define EMAC_MII_DATA_OP_CL45_RD 0x30000000      /* Perform a read operation */
107 #define EMAC_MII_DATA_OP_WR      0x10000000      /* Perform a write operation */
108 #define EMAC_MII_DATA_OP_CL45_WR 0x10000000      /* Perform a write operation */
109 #define EMAC_MII_DATA_PA_MSK     0x0f800000      /* PHY Address field mask */
110 #define EMAC_MII_DATA_RA_MSK     0x007c0000      /* PHY Register field mask */
111 #define EMAC_MII_DATA_TA         0x00020000      /* Turnaround */
112 #define EMAC_MII_DATA_DATAMSK    0x0000ffff      /* PHY data field */
113 
114 #define EMAC_MII_DATA_RA_SHIFT   18      /* MII Register address bits */
115 #define EMAC_MII_DATA_RA_MASK	 0x1F      /* MII Register address mask */
116 #define EMAC_MII_DATA_PA_SHIFT   23      /* MII PHY address bits */
117 #define EMAC_MII_DATA_PA_MASK    0x1F      /* MII PHY address mask */
118 
119 #define EMAC_MII_DATA_RA(v) ((v & EMAC_MII_DATA_RA_MASK) <<\
120 				EMAC_MII_DATA_RA_SHIFT)
121 #define EMAC_MII_DATA_PA(v) ((v & EMAC_MII_DATA_RA_MASK) <<\
122 				EMAC_MII_DATA_PA_SHIFT)
123 #define EMAC_MII_DATA(v)    (v & 0xffff)
124 
125 #define EMAC_MII_SPEED_SHIFT	1
126 #define EMAC_HOLDTIME_SHIFT	8
127 #define EMAC_HOLDTIME_MASK	0x7
128 #define EMAC_HOLDTIME(v)    ((v & EMAC_HOLDTIME_MASK) << EMAC_HOLDTIME_SHIFT)
129 
130 /* Internal PHY Registers - SGMII */
131 #define PHY_SGMII_CR_PHY_RESET      0x8000
132 #define PHY_SGMII_CR_RESET_AN       0x0200
133 #define PHY_SGMII_CR_DEF_VAL        0x1140
134 #define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
135 #define PHY_SGMII_IF_MODE_AN        0x0002
136 #define PHY_SGMII_IF_MODE_SGMII     0x0001
137 #define PHY_SGMII_IF_MODE_SGMII_GBT 0x0008
138 #define PHY_SGMII_ENABLE_AN         0x1000
139 
140 #endif /* _EMAC_H_ */
141