1 /** @file 2 Intel CPUID leaf definitions. 3 4 Provides defines for CPUID leaf indexes. Data structures are provided for 5 registers returned by a CPUID leaf that contain one or more bit fields. 6 If a register returned is a single 32-bit value, then a data structure is 7 not provided for that register. 8 9 Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR> 10 SPDX-License-Identifier: BSD-2-Clause-Patent 11 12 @par Specification Reference: 13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A, 14 November 2018, CPUID instruction. 15 16 **/ 17 18 #ifndef __INTEL_CPUID_H__ 19 #define __INTEL_CPUID_H__ 20 21 /** 22 CPUID Signature Information 23 24 @param EAX CPUID_SIGNATURE (0x00) 25 26 @retval EAX Returns the highest value the CPUID instruction recognizes for 27 returning basic processor information. The value is returned is 28 processor specific. 29 @retval EBX First 4 characters of a vendor identification string. 30 @retval ECX Last 4 characters of a vendor identification string. 31 @retval EDX Middle 4 characters of a vendor identification string. 32 33 <b>Example usage</b> 34 @code 35 UINT32 Eax; 36 UINT32 Ebx; 37 UINT32 Ecx; 38 UINT32 Edx; 39 40 AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx); 41 @endcode 42 **/ 43 #define CPUID_SIGNATURE 0x00 44 45 /// 46 /// @{ CPUID signature values returned by Intel processors 47 /// 48 #define CPUID_SIGNATURE_GENUINE_INTEL_EBX SIGNATURE_32 ('G', 'e', 'n', 'u') 49 #define CPUID_SIGNATURE_GENUINE_INTEL_EDX SIGNATURE_32 ('i', 'n', 'e', 'I') 50 #define CPUID_SIGNATURE_GENUINE_INTEL_ECX SIGNATURE_32 ('n', 't', 'e', 'l') 51 /// 52 /// @} 53 /// 54 55 56 /** 57 CPUID Version Information 58 59 @param EAX CPUID_VERSION_INFO (0x01) 60 61 @retval EAX Returns Model, Family, Stepping Information described by the 62 type CPUID_VERSION_INFO_EAX. 63 @retval EBX Returns Brand, Cache Line Size, and Initial APIC ID described by 64 the type CPUID_VERSION_INFO_EBX. 65 @retval ECX CPU Feature Information described by the type 66 CPUID_VERSION_INFO_ECX. 67 @retval EDX CPU Feature Information described by the type 68 CPUID_VERSION_INFO_EDX. 69 70 <b>Example usage</b> 71 @code 72 CPUID_VERSION_INFO_EAX Eax; 73 CPUID_VERSION_INFO_EBX Ebx; 74 CPUID_VERSION_INFO_ECX Ecx; 75 CPUID_VERSION_INFO_EDX Edx; 76 77 AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32); 78 @endcode 79 **/ 80 #define CPUID_VERSION_INFO 0x01 81 82 /** 83 CPUID Version Information returned in EAX for CPUID leaf 84 #CPUID_VERSION_INFO. 85 **/ 86 typedef union { 87 /// 88 /// Individual bit fields 89 /// 90 struct { 91 UINT32 SteppingId:4; ///< [Bits 3:0] Stepping ID 92 UINT32 Model:4; ///< [Bits 7:4] Model 93 UINT32 FamilyId:4; ///< [Bits 11:8] Family 94 UINT32 ProcessorType:2; ///< [Bits 13:12] Processor Type 95 UINT32 Reserved1:2; ///< [Bits 15:14] Reserved 96 UINT32 ExtendedModelId:4; ///< [Bits 19:16] Extended Model ID 97 UINT32 ExtendedFamilyId:8; ///< [Bits 27:20] Extended Family ID 98 UINT32 Reserved2:4; ///< Reserved 99 } Bits; 100 /// 101 /// All bit fields as a 32-bit value 102 /// 103 UINT32 Uint32; 104 } CPUID_VERSION_INFO_EAX; 105 106 /// 107 /// @{ Define value for bit field CPUID_VERSION_INFO_EAX.ProcessorType 108 /// 109 #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_ORIGINAL_OEM_PROCESSOR 0x00 110 #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_INTEL_OVERDRIVE_PROCESSOR 0x01 111 #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_DUAL_PROCESSOR 0x02 112 /// 113 /// @} 114 /// 115 116 /** 117 CPUID Version Information returned in EBX for CPUID leaf 118 #CPUID_VERSION_INFO. 119 **/ 120 typedef union { 121 /// 122 /// Individual bit fields 123 /// 124 struct { 125 /// 126 /// [Bits 7:0] Provides an entry into a brand string table that contains 127 /// brand strings for IA-32 processors. 128 /// 129 UINT32 BrandIndex:8; 130 /// 131 /// [Bits 15:8] Indicates the size of the cache line flushed by the CLFLUSH 132 /// and CLFLUSHOPT instructions in 8-byte increments. This field was 133 /// introduced in the Pentium 4 processor. 134 /// 135 UINT32 CacheLineSize:8; 136 /// 137 /// [Bits 23:16] Maximum number of addressable IDs for logical processors 138 /// in this physical package. 139 /// 140 /// @note 141 /// The nearest power-of-2 integer that is not smaller than EBX[23:16] is 142 /// the number of unique initial APICIDs reserved for addressing different 143 /// logical processors in a physical package. This field is only valid if 144 /// CPUID.1.EDX.HTT[bit 28]= 1. 145 /// 146 UINT32 MaximumAddressableIdsForLogicalProcessors:8; 147 /// 148 /// [Bits 31:24] The 8-bit ID that is assigned to the local APIC on the 149 /// processor during power up. This field was introduced in the Pentium 4 150 /// processor. 151 /// 152 UINT32 InitialLocalApicId:8; 153 } Bits; 154 /// 155 /// All bit fields as a 32-bit value 156 /// 157 UINT32 Uint32; 158 } CPUID_VERSION_INFO_EBX; 159 160 /** 161 CPUID Version Information returned in ECX for CPUID leaf 162 #CPUID_VERSION_INFO. 163 **/ 164 typedef union { 165 /// 166 /// Individual bit fields 167 /// 168 struct { 169 /// 170 /// [Bit 0] Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the 171 /// processor supports this technology 172 /// 173 UINT32 SSE3:1; 174 /// 175 /// [Bit 1] A value of 1 indicates the processor supports the PCLMULQDQ 176 /// instruction. Carryless Multiplication 177 /// 178 UINT32 PCLMULQDQ:1; 179 /// 180 /// [Bit 2] 64-bit DS Area. A value of 1 indicates the processor supports 181 /// DS area using 64-bit layout. 182 /// 183 UINT32 DTES64:1; 184 /// 185 /// [Bit 3] MONITOR/MWAIT. A value of 1 indicates the processor supports 186 /// this feature. 187 /// 188 UINT32 MONITOR:1; 189 /// 190 /// [Bit 4] CPL Qualified Debug Store. A value of 1 indicates the processor 191 /// supports the extensions to the Debug Store feature to allow for branch 192 /// message storage qualified by CPL 193 /// 194 UINT32 DS_CPL:1; 195 /// 196 /// [Bit 5] Virtual Machine Extensions. A value of 1 indicates that the 197 /// processor supports this technology. 198 /// 199 UINT32 VMX:1; 200 /// 201 /// [Bit 6] Safer Mode Extensions. A value of 1 indicates that the processor 202 /// supports this technology 203 /// 204 UINT32 SMX:1; 205 /// 206 /// [Bit 7] Enhanced Intel SpeedStep(R) technology. A value of 1 indicates 207 /// that the processor supports this technology 208 /// 209 UINT32 EIST:1; 210 /// 211 /// [Bit 8] Thermal Monitor 2. A value of 1 indicates whether the processor 212 /// supports this technology 213 /// 214 UINT32 TM2:1; 215 /// 216 /// [Bit 9] A value of 1 indicates the presence of the Supplemental Streaming 217 /// SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction 218 /// extensions are not present in the processor. 219 /// 220 UINT32 SSSE3:1; 221 /// 222 /// [Bit 10] L1 Context ID. A value of 1 indicates the L1 data cache mode 223 /// can be set to either adaptive mode or shared mode. A value of 0 indicates 224 /// this feature is not supported. See definition of the IA32_MISC_ENABLE MSR 225 /// Bit 24 (L1 Data Cache Context Mode) for details 226 /// 227 UINT32 CNXT_ID:1; 228 /// 229 /// [Bit 11] A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE 230 /// MSR for silicon debug 231 /// 232 UINT32 SDBG:1; 233 /// 234 /// [Bit 12] A value of 1 indicates the processor supports FMA (Fused Multiple 235 /// Add) extensions using YMM state. 236 /// 237 UINT32 FMA:1; 238 /// 239 /// [Bit 13] CMPXCHG16B Available. A value of 1 indicates that the feature 240 /// is available. 241 /// 242 UINT32 CMPXCHG16B:1; 243 /// 244 /// [Bit 14] xTPR Update Control. A value of 1 indicates that the processor 245 /// supports changing IA32_MISC_ENABLE[Bit 23]. 246 /// 247 UINT32 xTPR_Update_Control:1; 248 /// 249 /// [Bit 15] Perfmon and Debug Capability: A value of 1 indicates the 250 /// processor supports the performance and debug feature indication MSR 251 /// IA32_PERF_CAPABILITIES. 252 /// 253 UINT32 PDCM:1; 254 UINT32 Reserved:1; 255 /// 256 /// [Bit 17] Process-context identifiers. A value of 1 indicates that the 257 /// processor supports PCIDs and that software may set CR4.PCIDE to 1. 258 /// 259 UINT32 PCID:1; 260 /// 261 /// [Bit 18] A value of 1 indicates the processor supports the ability to 262 /// prefetch data from a memory mapped device. Direct Cache Access. 263 /// 264 UINT32 DCA:1; 265 /// 266 /// [Bit 19] A value of 1 indicates that the processor supports SSE4.1. 267 /// 268 UINT32 SSE4_1:1; 269 /// 270 /// [Bit 20] A value of 1 indicates that the processor supports SSE4.2. 271 /// 272 UINT32 SSE4_2:1; 273 /// 274 /// [Bit 21] A value of 1 indicates that the processor supports x2APIC 275 /// feature. 276 /// 277 UINT32 x2APIC:1; 278 /// 279 /// [Bit 22] A value of 1 indicates that the processor supports MOVBE 280 /// instruction. 281 /// 282 UINT32 MOVBE:1; 283 /// 284 /// [Bit 23] A value of 1 indicates that the processor supports the POPCNT 285 /// instruction. 286 /// 287 UINT32 POPCNT:1; 288 /// 289 /// [Bit 24] A value of 1 indicates that the processor's local APIC timer 290 /// supports one-shot operation using a TSC deadline value. 291 /// 292 UINT32 TSC_Deadline:1; 293 /// 294 /// [Bit 25] A value of 1 indicates that the processor supports the AESNI 295 /// instruction extensions. 296 /// 297 UINT32 AESNI:1; 298 /// 299 /// [Bit 26] A value of 1 indicates that the processor supports the 300 /// XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV 301 /// instructions, and XCR0. 302 /// 303 UINT32 XSAVE:1; 304 /// 305 /// [Bit 27] A value of 1 indicates that the OS has set CR4.OSXSAVE[Bit 18] 306 /// to enable XSETBV/XGETBV instructions to access XCR0 and to support 307 /// processor extended state management using XSAVE/XRSTOR. 308 /// 309 UINT32 OSXSAVE:1; 310 /// 311 /// [Bit 28] A value of 1 indicates the processor supports the AVX instruction 312 /// extensions. 313 /// 314 UINT32 AVX:1; 315 /// 316 /// [Bit 29] A value of 1 indicates that processor supports 16-bit 317 /// floating-point conversion instructions. 318 /// 319 UINT32 F16C:1; 320 /// 321 /// [Bit 30] A value of 1 indicates that processor supports RDRAND instruction. 322 /// 323 UINT32 RDRAND:1; 324 /// 325 /// [Bit 31] Always returns 0. 326 /// 327 UINT32 NotUsed:1; 328 } Bits; 329 /// 330 /// All bit fields as a 32-bit value 331 /// 332 UINT32 Uint32; 333 } CPUID_VERSION_INFO_ECX; 334 335 /** 336 CPUID Version Information returned in EDX for CPUID leaf 337 #CPUID_VERSION_INFO. 338 **/ 339 typedef union { 340 /// 341 /// Individual bit fields 342 /// 343 struct { 344 /// 345 /// [Bit 0] Floating Point Unit On-Chip. The processor contains an x87 FPU. 346 /// 347 UINT32 FPU:1; 348 /// 349 /// [Bit 1] Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements, 350 /// including CR4.VME for controlling the feature, CR4.PVI for protected 351 /// mode virtual interrupts, software interrupt indirection, expansion of 352 /// the TSS with the software indirection bitmap, and EFLAGS.VIF and 353 /// EFLAGS.VIP flags. 354 /// 355 UINT32 VME:1; 356 /// 357 /// [Bit 2] Debugging Extensions. Support for I/O breakpoints, including 358 /// CR4.DE for controlling the feature, and optional trapping of accesses to 359 /// DR4 and DR5. 360 /// 361 UINT32 DE:1; 362 /// 363 /// [Bit 3] Page Size Extension. Large pages of size 4 MByte are supported, 364 /// including CR4.PSE for controlling the feature, the defined dirty bit in 365 /// PDE (Page Directory Entries), optional reserved bit trapping in CR3, 366 /// PDEs, and PTEs. 367 /// 368 UINT32 PSE:1; 369 /// 370 /// [Bit 4] Time Stamp Counter. The RDTSC instruction is supported, 371 /// including CR4.TSD for controlling privilege. 372 /// 373 UINT32 TSC:1; 374 /// 375 /// [Bit 5] Model Specific Registers RDMSR and WRMSR Instructions. The 376 /// RDMSR and WRMSR instructions are supported. Some of the MSRs are 377 /// implementation dependent. 378 /// 379 UINT32 MSR:1; 380 /// 381 /// [Bit 6] Physical Address Extension. Physical addresses greater than 32 382 /// bits are supported: extended page table entry formats, an extra level in 383 /// the page translation tables is defined, 2-MByte pages are supported 384 /// instead of 4 Mbyte pages if PAE bit is 1. 385 /// 386 UINT32 PAE:1; 387 /// 388 /// [Bit 7] Machine Check Exception. Exception 18 is defined for Machine 389 /// Checks, including CR4.MCE for controlling the feature. This feature does 390 /// not define the model-specific implementations of machine-check error 391 /// logging, reporting, and processor shutdowns. Machine Check exception 392 /// handlers may have to depend on processor version to do model specific 393 /// processing of the exception, or test for the presence of the Machine 394 /// Check feature. 395 /// 396 UINT32 MCE:1; 397 /// 398 /// [Bit 8] CMPXCHG8B Instruction. The compare-and-exchange 8 bytes(64 bits) 399 /// instruction is supported (implicitly locked and atomic). 400 /// 401 UINT32 CX8:1; 402 /// 403 /// [Bit 9] APIC On-Chip. The processor contains an Advanced Programmable 404 /// Interrupt Controller (APIC), responding to memory mapped commands in the 405 /// physical address range FFFE0000H to FFFE0FFFH (by default - some 406 /// processors permit the APIC to be relocated). 407 /// 408 UINT32 APIC:1; 409 UINT32 Reserved1:1; 410 /// 411 /// [Bit 11] SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT 412 /// and associated MSRs are supported. 413 /// 414 UINT32 SEP:1; 415 /// 416 /// [Bit 12] Memory Type Range Registers. MTRRs are supported. The MTRRcap 417 /// MSR contains feature bits that describe what memory types are supported, 418 /// how many variable MTRRs are supported, and whether fixed MTRRs are 419 /// supported. 420 /// 421 UINT32 MTRR:1; 422 /// 423 /// [Bit 13] Page Global Bit. The global bit is supported in paging-structure 424 /// entries that map a page, indicating TLB entries that are common to 425 /// different processes and need not be flushed. The CR4.PGE bit controls 426 /// this feature. 427 /// 428 UINT32 PGE:1; 429 /// 430 /// [Bit 14] Machine Check Architecture. A value of 1 indicates the Machine 431 /// Check Architecture of reporting machine errors is supported. The MCG_CAP 432 /// MSR contains feature bits describing how many banks of error reporting 433 /// MSRs are supported. 434 /// 435 UINT32 MCA:1; 436 /// 437 /// [Bit 15] Conditional Move Instructions. The conditional move instruction 438 /// CMOV is supported. In addition, if x87 FPU is present as indicated by the 439 /// CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported. 440 /// 441 UINT32 CMOV:1; 442 /// 443 /// [Bit 16] Page Attribute Table. Page Attribute Table is supported. This 444 /// feature augments the Memory Type Range Registers (MTRRs), allowing an 445 /// operating system to specify attributes of memory accessed through a 446 /// linear address on a 4KB granularity. 447 /// 448 UINT32 PAT:1; 449 /// 450 /// [Bit 17] 36-Bit Page Size Extension. 4-MByte pages addressing physical 451 /// memory beyond 4 GBytes are supported with 32-bit paging. This feature 452 /// indicates that upper bits of the physical address of a 4-MByte page are 453 /// encoded in bits 20:13 of the page-directory entry. Such physical 454 /// addresses are limited by MAXPHYADDR and may be up to 40 bits in size. 455 /// 456 UINT32 PSE_36:1; 457 /// 458 /// [Bit 18] Processor Serial Number. The processor supports the 96-bit 459 /// processor identification number feature and the feature is enabled. 460 /// 461 UINT32 PSN:1; 462 /// 463 /// [Bit 19] CLFLUSH Instruction. CLFLUSH Instruction is supported. 464 /// 465 UINT32 CLFSH:1; 466 UINT32 Reserved2:1; 467 /// 468 /// [Bit 21] Debug Store. The processor supports the ability to write debug 469 /// information into a memory resident buffer. This feature is used by the 470 /// branch trace store (BTS) and precise event-based sampling (PEBS) 471 /// facilities. 472 /// 473 UINT32 DS:1; 474 /// 475 /// [Bit 22] Thermal Monitor and Software Controlled Clock Facilities. The 476 /// processor implements internal MSRs that allow processor temperature to 477 /// be monitored and processor performance to be modulated in predefined 478 /// duty cycles under software control. 479 /// 480 UINT32 ACPI:1; 481 /// 482 /// [Bit 23] Intel MMX Technology. The processor supports the Intel MMX 483 /// technology. 484 /// 485 UINT32 MMX:1; 486 /// 487 /// [Bit 24] FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR 488 /// instructions are supported for fast save and restore of the floating 489 /// point context. Presence of this bit also indicates that CR4.OSFXSR is 490 /// available for an operating system to indicate that it supports the 491 /// FXSAVE and FXRSTOR instructions. 492 /// 493 UINT32 FXSR:1; 494 /// 495 /// [Bit 25] SSE. The processor supports the SSE extensions. 496 /// 497 UINT32 SSE:1; 498 /// 499 /// [Bit 26] SSE2. The processor supports the SSE2 extensions. 500 /// 501 UINT32 SSE2:1; 502 /// 503 /// [Bit 27] Self Snoop. The processor supports the management of 504 /// conflicting memory types by performing a snoop of its own cache 505 /// structure for transactions issued to the bus. 506 /// 507 UINT32 SS:1; 508 /// 509 /// [Bit 28] Max APIC IDs reserved field is Valid. A value of 0 for HTT 510 /// indicates there is only a single logical processor in the package and 511 /// software should assume only a single APIC ID is reserved. A value of 1 512 /// for HTT indicates the value in CPUID.1.EBX[23:16] (the Maximum number of 513 /// addressable IDs for logical processors in this package) is valid for the 514 /// package. 515 /// 516 UINT32 HTT:1; 517 /// 518 /// [Bit 29] Thermal Monitor. The processor implements the thermal monitor 519 /// automatic thermal control circuitry (TCC). 520 /// 521 UINT32 TM:1; 522 UINT32 Reserved3:1; 523 /// 524 /// [Bit 31] Pending Break Enable. The processor supports the use of the 525 /// FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is 526 /// asserted) to signal the processor that an interrupt is pending and that 527 /// the processor should return to normal operation to handle the interrupt. 528 /// Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability. 529 /// 530 UINT32 PBE:1; 531 } Bits; 532 /// 533 /// All bit fields as a 32-bit value 534 /// 535 UINT32 Uint32; 536 } CPUID_VERSION_INFO_EDX; 537 538 539 /** 540 CPUID Cache and TLB Information 541 542 @param EAX CPUID_CACHE_INFO (0x02) 543 544 @retval EAX Cache and TLB Information described by the type 545 CPUID_CACHE_INFO_CACHE_TLB. 546 CPUID_CACHE_INFO_CACHE_TLB.CacheDescriptor[0] always returns 547 0x01 and must be ignored. Only valid if 548 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear. 549 @retval EBX Cache and TLB Information described by the type 550 CPUID_CACHE_INFO_CACHE_TLB. Only valid if 551 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear. 552 @retval ECX Cache and TLB Information described by the type 553 CPUID_CACHE_INFO_CACHE_TLB. Only valid if 554 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear. 555 @retval EDX Cache and TLB Information described by the type 556 CPUID_CACHE_INFO_CACHE_TLB. Only valid if 557 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear. 558 559 <b>Example usage</b> 560 @code 561 CPUID_CACHE_INFO_CACHE_TLB Eax; 562 CPUID_CACHE_INFO_CACHE_TLB Ebx; 563 CPUID_CACHE_INFO_CACHE_TLB Ecx; 564 CPUID_CACHE_INFO_CACHE_TLB Edx; 565 566 AsmCpuid (CPUID_CACHE_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32); 567 @endcode 568 569 <b>Cache Descriptor values</b> 570 <table> 571 <tr><th>Value </th><th> Type </th><th> Description </th></tr> 572 <tr><td> 0x00 </td><td> General </td><td> Null descriptor, this byte contains no information</td></tr> 573 <tr><td> 0x01 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries</td></tr> 574 <tr><td> 0x02 </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, fully associative, 2 entries</td></tr> 575 <tr><td> 0x03 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 64 entries</td></tr> 576 <tr><td> 0x04 </td><td> TLB </td><td> Data TLB: 4 MByte pages, 4-way set associative, 8 entries</td></tr> 577 <tr><td> 0x05 </td><td> TLB </td><td> Data TLB1: 4 MByte pages, 4-way set associative, 32 entries</td></tr> 578 <tr><td> 0x06 </td><td> Cache </td><td> 1st-level instruction cache: 8 KBytes, 4-way set associative, 579 32 byte line size</td></tr> 580 <tr><td> 0x08 </td><td> Cache </td><td> 1st-level instruction cache: 16 KBytes, 4-way set associative, 581 32 byte line size</td></tr> 582 <tr><td> 0x09 </td><td> Cache </td><td> 1st-level instruction cache: 32KBytes, 4-way set associative, 583 64 byte line size</td></tr> 584 <tr><td> 0x0A </td><td> Cache </td><td> 1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size</td></tr> 585 <tr><td> 0x0B </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries</td></tr> 586 <tr><td> 0x0C </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size</td></tr> 587 <tr><td> 0x0D </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size</td></tr> 588 <tr><td> 0x0E </td><td> Cache </td><td> 1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size</td></tr> 589 <tr><td> 0x1D </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size</td></tr> 590 <tr><td> 0x21 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size</td></tr> 591 <tr><td> 0x22 </td><td> Cache </td><td> 3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 592 2 lines per sector</td></tr> 593 <tr><td> 0x23 </td><td> Cache </td><td> 3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 594 2 lines per sector</td></tr> 595 <tr><td> 0x24 </td><td> Cache </td><td> 2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size</td></tr> 596 <tr><td> 0x25 </td><td> Cache </td><td> 3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 597 2 lines per sector</td></tr> 598 <tr><td> 0x29 </td><td> Cache </td><td> 3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 599 2 lines per sector</td></tr> 600 <tr><td> 0x2C </td><td> Cache </td><td> 1st-level data cache: 32 KBytes, 8-way set associative, 601 64 byte line size</td></tr> 602 <tr><td> 0x30 </td><td> Cache </td><td> 1st-level instruction cache: 32 KBytes, 8-way set associative, 603 64 byte line size</td></tr> 604 <tr><td> 0x40 </td><td> Cache </td><td> No 2nd-level cache or, if processor contains a valid 2nd-level cache, 605 no 3rd-level cache</td></tr> 606 <tr><td> 0x41 </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size</td></tr> 607 <tr><td> 0x42 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size</td></tr> 608 <tr><td> 0x43 </td><td> Cache </td><td> 2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size</td></tr> 609 <tr><td> 0x44 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size</td></tr> 610 <tr><td> 0x45 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size</td></tr> 611 <tr><td> 0x46 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size</td></tr> 612 <tr><td> 0x47 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size</td></tr> 613 <tr><td> 0x48 </td><td> Cache </td><td> 2nd-level cache: 3MByte, 12-way set associative, 64 byte line size</td></tr> 614 <tr><td> 0x49 </td><td> Cache </td><td> 3rd-level cache: 4MB, 16-way set associative, 64-byte line size 615 (Intel Xeon processor MP, Family 0FH, Model 06H)<BR> 616 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr> 617 <tr><td> 0x4A </td><td> Cache </td><td> 3rd-level cache: 6MByte, 12-way set associative, 64 byte line size</td></tr> 618 <tr><td> 0x4B </td><td> Cache </td><td> 3rd-level cache: 8MByte, 16-way set associative, 64 byte line size</td></tr> 619 <tr><td> 0x4C </td><td> Cache </td><td> 3rd-level cache: 12MByte, 12-way set associative, 64 byte line size</td></tr> 620 <tr><td> 0x4D </td><td> Cache </td><td> 3rd-level cache: 16MByte, 16-way set associative, 64 byte line size</td></tr> 621 <tr><td> 0x4E </td><td> Cache </td><td> 2nd-level cache: 6MByte, 24-way set associative, 64 byte line size</td></tr> 622 <tr><td> 0x4F </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 32 entries</td></tr> 623 <tr><td> 0x50 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries</td></tr> 624 <tr><td> 0x51 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries</td></tr> 625 <tr><td> 0x52 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries</td></tr> 626 <tr><td> 0x55 </td><td> TLB </td><td> Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries</td></tr> 627 <tr><td> 0x56 </td><td> TLB </td><td> Data TLB0: 4 MByte pages, 4-way set associative, 16 entries</td></tr> 628 <tr><td> 0x57 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, 4-way associative, 16 entries</td></tr> 629 <tr><td> 0x59 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, fully associative, 16 entries</td></tr> 630 <tr><td> 0x5A </td><td> TLB </td><td> Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries</td></tr> 631 <tr><td> 0x5B </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 64 entries</td></tr> 632 <tr><td> 0x5C </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,128 entries</td></tr> 633 <tr><td> 0x5D </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,256 entries</td></tr> 634 <tr><td> 0x60 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size</td></tr> 635 <tr><td> 0x61 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, fully associative, 48 entries</td></tr> 636 <tr><td> 0x63 </td><td> TLB </td><td> Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 637 32 entries and a separate array with 1 GByte pages, 4-way set associative, 638 4 entries</td></tr> 639 <tr><td> 0x64 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 512 entries</td></tr> 640 <tr><td> 0x66 </td><td> Cache </td><td> 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size</td></tr> 641 <tr><td> 0x67 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size</td></tr> 642 <tr><td> 0x68 </td><td> Cache </td><td> 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size</td></tr> 643 <tr><td> 0x6A </td><td> Cache </td><td> uTLB: 4 KByte pages, 8-way set associative, 64 entries</td></tr> 644 <tr><td> 0x6B </td><td> Cache </td><td> DTLB: 4 KByte pages, 8-way set associative, 256 entries</td></tr> 645 <tr><td> 0x6C </td><td> Cache </td><td> DTLB: 2M/4M pages, 8-way set associative, 128 entries</td></tr> 646 <tr><td> 0x6D </td><td> Cache </td><td> DTLB: 1 GByte pages, fully associative, 16 entries</td></tr> 647 <tr><td> 0x70 </td><td> Cache </td><td> Trace cache: 12 K-uop, 8-way set associative</td></tr> 648 <tr><td> 0x71 </td><td> Cache </td><td> Trace cache: 16 K-uop, 8-way set associative</td></tr> 649 <tr><td> 0x72 </td><td> Cache </td><td> Trace cache: 32 K-uop, 8-way set associative</td></tr> 650 <tr><td> 0x76 </td><td> TLB </td><td> Instruction TLB: 2M/4M pages, fully associative, 8 entries</td></tr> 651 <tr><td> 0x78 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 64byte line size</td></tr> 652 <tr><td> 0x79 </td><td> Cache </td><td> 2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 653 2 lines per sector</td></tr> 654 <tr><td> 0x7A </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 655 2 lines per sector</td></tr> 656 <tr><td> 0x7B </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 657 2 lines per sector</td></tr> 658 <tr><td> 0x7C </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 659 2 lines per sector</td></tr> 660 <tr><td> 0x7D </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 64byte line size</td></tr> 661 <tr><td> 0x7F </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size</td></tr> 662 <tr><td> 0x80 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size</td></tr> 663 <tr><td> 0x82 </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size</td></tr> 664 <tr><td> 0x83 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size</td></tr> 665 <tr><td> 0x84 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size</td></tr> 666 <tr><td> 0x85 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size</td></tr> 667 <tr><td> 0x86 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr> 668 <tr><td> 0x87 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr> 669 <tr><td> 0xA0 </td><td> DTLB </td><td> DTLB: 4k pages, fully associative, 32 entries</td></tr> 670 <tr><td> 0xB0 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr> 671 <tr><td> 0xB1 </td><td> TLB </td><td> Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries</td></tr> 672 <tr><td> 0xB2 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 4-way set associative, 64 entries</td></tr> 673 <tr><td> 0xB3 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr> 674 <tr><td> 0xB4 </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 256 entries</td></tr> 675 <tr><td> 0xB5 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative, 64 entries</td></tr> 676 <tr><td> 0xB6 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative, 677 128 entries</td></tr> 678 <tr><td> 0xBA </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 64 entries</td></tr> 679 <tr><td> 0xC0 </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries</td></tr> 680 <tr><td> 0xC1 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 681 1024 entries</td></tr> 682 <tr><td> 0xC2 </td><td> DTLB </td><td> DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries</td></tr> 683 <tr><td> 0xC3 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 684 1536 entries. Also 1GBbyte pages, 4-way, 16 entries.</td></tr> 685 <tr><td> 0xC4 </td><td> DTLB </td><td> DTLB: 2M/4M Byte pages, 4-way associative, 32 entries</td></tr> 686 <tr><td> 0xCA </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries</td></tr> 687 <tr><td> 0xD0 </td><td> Cache </td><td> 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr> 688 <tr><td> 0xD1 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size</td></tr> 689 <tr><td> 0xD2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size</td></tr> 690 <tr><td> 0xD6 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr> 691 <tr><td> 0xD7 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size</td></tr> 692 <tr><td> 0xD8 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size</td></tr> 693 <tr><td> 0xDC </td><td> Cache </td><td> 3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size</td></tr> 694 <tr><td> 0xDD </td><td> Cache </td><td> 3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size</td></tr> 695 <tr><td> 0xDE </td><td> Cache </td><td> 3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size</td></tr> 696 <tr><td> 0xE2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size</td></tr> 697 <tr><td> 0xE3 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr> 698 <tr><td> 0xE4 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size</td></tr> 699 <tr><td> 0xEA </td><td> Cache </td><td> 3rd-level cache: 12MByte, 24-way set associative, 64 byte line size</td></tr> 700 <tr><td> 0xEB </td><td> Cache </td><td> 3rd-level cache: 18MByte, 24-way set associative, 64 byte line size</td></tr> 701 <tr><td> 0xEC </td><td> Cache </td><td> 3rd-level cache: 24MByte, 24-way set associative, 64 byte line size</td></tr> 702 <tr><td> 0xF0 </td><td> Prefetch</td><td> 64-Byte prefetching</td></tr> 703 <tr><td> 0xF1 </td><td> Prefetch</td><td> 128-Byte prefetching</td></tr> 704 <tr><td> 0xFE </td><td> General </td><td> CPUID leaf 2 does not report TLB descriptor information; use CPUID 705 leaf 18H to query TLB and other address translation parameters.</td></tr> 706 <tr><td> 0xFF </td><td> General </td><td> CPUID leaf 2 does not report cache descriptor information, 707 use CPUID leaf 4 to query cache parameters</td></tr> 708 </table> 709 **/ 710 #define CPUID_CACHE_INFO 0x02 711 712 /** 713 CPUID Cache and TLB Information returned in EAX, EBX, ECX, and EDX for CPUID 714 leaf #CPUID_CACHE_INFO. 715 **/ 716 typedef union { 717 /// 718 /// Individual bit fields 719 /// 720 struct { 721 UINT32 Reserved:31; 722 /// 723 /// [Bit 31] If 0, then the cache descriptor bytes in the register are valid. 724 /// if 1, then none of the cache descriptor bytes in the register are valid. 725 /// 726 UINT32 NotValid:1; 727 } Bits; 728 /// 729 /// Array of Cache and TLB descriptor bytes 730 /// 731 UINT8 CacheDescriptor[4]; 732 /// 733 /// All bit fields as a 32-bit value 734 /// 735 UINT32 Uint32; 736 } CPUID_CACHE_INFO_CACHE_TLB; 737 738 739 /** 740 CPUID Processor Serial Number 741 742 Processor serial number (PSN) is not supported in the Pentium 4 processor 743 or later. On all models, use the PSN flag (returned using CPUID) to check 744 for PSN support before accessing the feature. 745 746 @param EAX CPUID_SERIAL_NUMBER (0x03) 747 748 @retval EAX Reserved. 749 @retval EBX Reserved. 750 @retval ECX Bits 31:0 of 96 bit processor serial number. (Available in 751 Pentium III processor only; otherwise, the value in this 752 register is reserved.) 753 @retval EDX Bits 63:32 of 96 bit processor serial number. (Available in 754 Pentium III processor only; otherwise, the value in this 755 register is reserved.) 756 757 <b>Example usage</b> 758 @code 759 UINT32 Ecx; 760 UINT32 Edx; 761 762 AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx); 763 @endcode 764 **/ 765 #define CPUID_SERIAL_NUMBER 0x03 766 767 768 /** 769 CPUID Cache Parameters 770 771 @param EAX CPUID_CACHE_PARAMS (0x04) 772 @param ECX Cache Level. Valid values start at 0. Software can enumerate 773 the deterministic cache parameters for each level of the cache 774 hierarchy starting with an index value of 0, until the 775 parameters report the value associated with the CacheType 776 field in CPUID_CACHE_PARAMS_EAX is 0. 777 778 @retval EAX Returns cache type information described by the type 779 CPUID_CACHE_PARAMS_EAX. 780 @retval EBX Returns cache line and associativity information described by 781 the type CPUID_CACHE_PARAMS_EBX. 782 @retval ECX Returns the number of sets in the cache. 783 @retval EDX Returns cache WINVD/INVD behavior described by the type 784 CPUID_CACHE_PARAMS_EDX. 785 786 <b>Example usage</b> 787 @code 788 UINT32 CacheLevel; 789 CPUID_CACHE_PARAMS_EAX Eax; 790 CPUID_CACHE_PARAMS_EBX Ebx; 791 UINT32 Ecx; 792 CPUID_CACHE_PARAMS_EDX Edx; 793 794 CacheLevel = 0; 795 do { 796 AsmCpuidEx ( 797 CPUID_CACHE_PARAMS, CacheLevel, 798 &Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32 799 ); 800 CacheLevel++; 801 } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL); 802 @endcode 803 **/ 804 #define CPUID_CACHE_PARAMS 0x04 805 806 /** 807 CPUID Cache Parameters Information returned in EAX for CPUID leaf 808 #CPUID_CACHE_PARAMS. 809 **/ 810 typedef union { 811 /// 812 /// Individual bit fields 813 /// 814 struct { 815 /// 816 /// [Bits 4:0] Cache type field. If #CPUID_CACHE_PARAMS_CACHE_TYPE_NULL, 817 /// then there is no information for the requested cache level. 818 /// 819 UINT32 CacheType:5; 820 /// 821 /// [Bits 7:5] Cache level (Starts at 1). 822 /// 823 UINT32 CacheLevel:3; 824 /// 825 /// [Bit 8] Self Initializing cache level (does not need SW initialization). 826 /// 827 UINT32 SelfInitializingCache:1; 828 /// 829 /// [Bit 9] Fully Associative cache. 830 /// 831 UINT32 FullyAssociativeCache:1; 832 /// 833 /// [Bits 13:10] Reserved. 834 /// 835 UINT32 Reserved:4; 836 /// 837 /// [Bits 25:14] Maximum number of addressable IDs for logical processors 838 /// sharing this cache. 839 /// 840 /// Add one to the return value to get the result. 841 /// The nearest power-of-2 integer that is not smaller than (1 + EAX[25:14]) 842 /// is the number of unique initial APIC IDs reserved for addressing 843 /// different logical processors sharing this cache. 844 /// 845 UINT32 MaximumAddressableIdsForLogicalProcessors:12; 846 /// 847 /// [Bits 31:26] Maximum number of addressable IDs for processor cores in 848 /// the physical package. 849 /// 850 /// The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26]) 851 /// is the number of unique Core_IDs reserved for addressing different 852 /// processor cores in a physical package. Core ID is a subset of bits of 853 /// the initial APIC ID. 854 /// The returned value is constant for valid initial values in ECX. Valid 855 /// ECX values start from 0. 856 /// 857 UINT32 MaximumAddressableIdsForProcessorCores:6; 858 } Bits; 859 /// 860 /// All bit fields as a 32-bit value 861 /// 862 UINT32 Uint32; 863 } CPUID_CACHE_PARAMS_EAX; 864 865 /// 866 /// @{ Define value for bit field CPUID_CACHE_PARAMS_EAX.CacheType 867 /// 868 #define CPUID_CACHE_PARAMS_CACHE_TYPE_NULL 0x00 869 #define CPUID_CACHE_PARAMS_CACHE_TYPE_DATA 0x01 870 #define CPUID_CACHE_PARAMS_CACHE_TYPE_INSTRUCTION 0x02 871 #define CPUID_CACHE_PARAMS_CACHE_TYPE_UNIFIED 0x03 872 /// 873 /// @} 874 /// 875 876 /** 877 CPUID Cache Parameters Information returned in EBX for CPUID leaf 878 #CPUID_CACHE_PARAMS. 879 **/ 880 typedef union { 881 /// 882 /// Individual bit fields 883 /// 884 struct { 885 /// 886 /// [Bits 11:0] System Coherency Line Size. Add one to the return value to 887 /// get the result. 888 /// 889 UINT32 LineSize:12; 890 /// 891 /// [Bits 21:12] Physical Line Partitions. Add one to the return value to 892 /// get the result. 893 /// 894 UINT32 LinePartitions:10; 895 /// 896 /// [Bits 31:22] Ways of associativity. Add one to the return value to get 897 /// the result. 898 /// 899 UINT32 Ways:10; 900 } Bits; 901 /// 902 /// All bit fields as a 32-bit value 903 /// 904 UINT32 Uint32; 905 } CPUID_CACHE_PARAMS_EBX; 906 907 /** 908 CPUID Cache Parameters Information returned in EDX for CPUID leaf 909 #CPUID_CACHE_PARAMS. 910 **/ 911 typedef union { 912 /// 913 /// Individual bit fields 914 /// 915 struct { 916 /// 917 /// [Bit 0] Write-Back Invalidate/Invalidate. 918 /// 0 = WBINVD/INVD from threads sharing this cache acts upon lower level 919 /// caches for threads sharing this cache. 920 /// 1 = WBINVD/INVD is not guaranteed to act upon lower level caches of 921 /// non-originating threads sharing this cache. 922 /// 923 UINT32 Invalidate:1; 924 /// 925 /// [Bit 1] Cache Inclusiveness. 926 /// 0 = Cache is not inclusive of lower cache levels. 927 /// 1 = Cache is inclusive of lower cache levels. 928 /// 929 UINT32 CacheInclusiveness:1; 930 /// 931 /// [Bit 2] Complex Cache Indexing. 932 /// 0 = Direct mapped cache. 933 /// 1 = A complex function is used to index the cache, potentially using all 934 /// address bits. 935 /// 936 UINT32 ComplexCacheIndexing:1; 937 UINT32 Reserved:29; 938 } Bits; 939 /// 940 /// All bit fields as a 32-bit value 941 /// 942 UINT32 Uint32; 943 } CPUID_CACHE_PARAMS_EDX; 944 945 946 /** 947 CPUID MONITOR/MWAIT Information 948 949 @param EAX CPUID_MONITOR_MWAIT (0x05) 950 951 @retval EAX Smallest monitor-line size in bytes described by the type 952 CPUID_MONITOR_MWAIT_EAX. 953 @retval EBX Largest monitor-line size in bytes described by the type 954 CPUID_MONITOR_MWAIT_EBX. 955 @retval ECX Enumeration of Monitor-Mwait extensions support described by 956 the type CPUID_MONITOR_MWAIT_ECX. 957 @retval EDX Sub C-states supported described by the type 958 CPUID_MONITOR_MWAIT_EDX. 959 960 <b>Example usage</b> 961 @code 962 CPUID_MONITOR_MWAIT_EAX Eax; 963 CPUID_MONITOR_MWAIT_EBX Ebx; 964 CPUID_MONITOR_MWAIT_ECX Ecx; 965 CPUID_MONITOR_MWAIT_EDX Edx; 966 967 AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32); 968 @endcode 969 **/ 970 #define CPUID_MONITOR_MWAIT 0x05 971 972 /** 973 CPUID MONITOR/MWAIT Information returned in EAX for CPUID leaf 974 #CPUID_MONITOR_MWAIT. 975 **/ 976 typedef union { 977 /// 978 /// Individual bit fields 979 /// 980 struct { 981 /// 982 /// [Bits 15:0] Smallest monitor-line size in bytes (default is processor's 983 /// monitor granularity). 984 /// 985 UINT32 SmallestMonitorLineSize:16; 986 UINT32 Reserved:16; 987 } Bits; 988 /// 989 /// All bit fields as a 32-bit value 990 /// 991 UINT32 Uint32; 992 } CPUID_MONITOR_MWAIT_EAX; 993 994 /** 995 CPUID MONITOR/MWAIT Information returned in EBX for CPUID leaf 996 #CPUID_MONITOR_MWAIT. 997 **/ 998 typedef union { 999 /// 1000 /// Individual bit fields 1001 /// 1002 struct { 1003 /// 1004 /// [Bits 15:0] Largest monitor-line size in bytes (default is processor's 1005 /// monitor granularity). 1006 /// 1007 UINT32 LargestMonitorLineSize:16; 1008 UINT32 Reserved:16; 1009 } Bits; 1010 /// 1011 /// All bit fields as a 32-bit value 1012 /// 1013 UINT32 Uint32; 1014 } CPUID_MONITOR_MWAIT_EBX; 1015 1016 /** 1017 CPUID MONITOR/MWAIT Information returned in ECX for CPUID leaf 1018 #CPUID_MONITOR_MWAIT. 1019 **/ 1020 typedef union { 1021 /// 1022 /// Individual bit fields 1023 /// 1024 struct { 1025 /// 1026 /// [Bit 0] If 0, then only EAX and EBX are valid. If 1, then EAX, EBX, ECX, 1027 /// and EDX are valid. 1028 /// 1029 UINT32 ExtensionsSupported:1; 1030 /// 1031 /// [Bit 1] Supports treating interrupts as break-event for MWAIT, even when 1032 /// interrupts disabled. 1033 /// 1034 UINT32 InterruptAsBreak:1; 1035 UINT32 Reserved:30; 1036 } Bits; 1037 /// 1038 /// All bit fields as a 32-bit value 1039 /// 1040 UINT32 Uint32; 1041 } CPUID_MONITOR_MWAIT_ECX; 1042 1043 /** 1044 CPUID MONITOR/MWAIT Information returned in EDX for CPUID leaf 1045 #CPUID_MONITOR_MWAIT. 1046 1047 @note 1048 The definition of C0 through C7 states for MWAIT extension are 1049 processor-specific C-states, not ACPI C-states. 1050 **/ 1051 typedef union { 1052 /// 1053 /// Individual bit fields 1054 /// 1055 struct { 1056 /// 1057 /// [Bits 3:0] Number of C0 sub C-states supported using MWAIT. 1058 /// 1059 UINT32 C0States:4; 1060 /// 1061 /// [Bits 7:4] Number of C1 sub C-states supported using MWAIT. 1062 /// 1063 UINT32 C1States:4; 1064 /// 1065 /// [Bits 11:8] Number of C2 sub C-states supported using MWAIT. 1066 /// 1067 UINT32 C2States:4; 1068 /// 1069 /// [Bits 15:12] Number of C3 sub C-states supported using MWAIT. 1070 /// 1071 UINT32 C3States:4; 1072 /// 1073 /// [Bits 19:16] Number of C4 sub C-states supported using MWAIT. 1074 /// 1075 UINT32 C4States:4; 1076 /// 1077 /// [Bits 23:20] Number of C5 sub C-states supported using MWAIT. 1078 /// 1079 UINT32 C5States:4; 1080 /// 1081 /// [Bits 27:24] Number of C6 sub C-states supported using MWAIT. 1082 /// 1083 UINT32 C6States:4; 1084 /// 1085 /// [Bits 31:28] Number of C7 sub C-states supported using MWAIT. 1086 /// 1087 UINT32 C7States:4; 1088 } Bits; 1089 /// 1090 /// All bit fields as a 32-bit value 1091 /// 1092 UINT32 Uint32; 1093 } CPUID_MONITOR_MWAIT_EDX; 1094 1095 1096 /** 1097 CPUID Thermal and Power Management 1098 1099 @param EAX CPUID_THERMAL_POWER_MANAGEMENT (0x06) 1100 1101 @retval EAX Thermal and power management features described by the type 1102 CPUID_THERMAL_POWER_MANAGEMENT_EAX. 1103 @retval EBX Number of Interrupt Thresholds in Digital Thermal Sensor 1104 described by the type CPUID_THERMAL_POWER_MANAGEMENT_EBX. 1105 @retval ECX Performance features described by the type 1106 CPUID_THERMAL_POWER_MANAGEMENT_ECX. 1107 @retval EDX Reserved. 1108 1109 <b>Example usage</b> 1110 @code 1111 CPUID_THERMAL_POWER_MANAGEMENT_EAX Eax; 1112 CPUID_THERMAL_POWER_MANAGEMENT_EBX Ebx; 1113 CPUID_THERMAL_POWER_MANAGEMENT_ECX Ecx; 1114 1115 AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL); 1116 @endcode 1117 **/ 1118 #define CPUID_THERMAL_POWER_MANAGEMENT 0x06 1119 1120 /** 1121 CPUID Thermal and Power Management Information returned in EAX for CPUID leaf 1122 #CPUID_THERMAL_POWER_MANAGEMENT. 1123 **/ 1124 typedef union { 1125 /// 1126 /// Individual bit fields 1127 /// 1128 struct { 1129 /// 1130 /// [Bit 0] Digital temperature sensor is supported if set. 1131 /// 1132 UINT32 DigitalTemperatureSensor:1; 1133 /// 1134 /// [Bit 1] Intel Turbo Boost Technology Available (see IA32_MISC_ENABLE[38]). 1135 /// 1136 UINT32 TurboBoostTechnology:1; 1137 /// 1138 /// [Bit 2] APIC-Timer-always-running feature is supported if set. 1139 /// 1140 UINT32 ARAT:1; 1141 UINT32 Reserved1:1; 1142 /// 1143 /// [Bit 4] Power limit notification controls are supported if set. 1144 /// 1145 UINT32 PLN:1; 1146 /// 1147 /// [Bit 5] Clock modulation duty cycle extension is supported if set. 1148 /// 1149 UINT32 ECMD:1; 1150 /// 1151 /// [Bit 6] Package thermal management is supported if set. 1152 /// 1153 UINT32 PTM:1; 1154 /// 1155 /// [Bit 7] HWP base registers (IA32_PM_ENABLE[Bit 0], IA32_HWP_CAPABILITIES, 1156 /// IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set. 1157 /// 1158 UINT32 HWP:1; 1159 /// 1160 /// [Bit 8] IA32_HWP_INTERRUPT MSR is supported if set. 1161 /// 1162 UINT32 HWP_Notification:1; 1163 /// 1164 /// [Bit 9] IA32_HWP_REQUEST[Bits 41:32] is supported if set. 1165 /// 1166 UINT32 HWP_Activity_Window:1; 1167 /// 1168 /// [Bit 10] IA32_HWP_REQUEST[Bits 31:24] is supported if set. 1169 /// 1170 UINT32 HWP_Energy_Performance_Preference:1; 1171 /// 1172 /// [Bit 11] IA32_HWP_REQUEST_PKG MSR is supported if set. 1173 /// 1174 UINT32 HWP_Package_Level_Request:1; 1175 UINT32 Reserved2:1; 1176 /// 1177 /// [Bit 13] HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1, 1178 /// IA32_THREAD_STALL MSRs are supported if set. 1179 /// 1180 UINT32 HDC:1; 1181 /// 1182 /// [Bit 14] Intel Turbo Boost Max Technology 3.0 available. 1183 /// 1184 UINT32 TurboBoostMaxTechnology30:1; 1185 /// 1186 /// [Bit 15] HWP Capabilities. 1187 /// Highest Performance change is supported if set. 1188 /// 1189 UINT32 HWPCapabilities:1; 1190 /// 1191 /// [Bit 16] HWP PECI override is supported if set. 1192 /// 1193 UINT32 HWPPECIOverride:1; 1194 /// 1195 /// [Bit 17] Flexible HWP is supported if set. 1196 /// 1197 UINT32 FlexibleHWP:1; 1198 /// 1199 /// [Bit 18] Fast access mode for the IA32_HWP_REQUEST MSR is supported if set. 1200 /// 1201 UINT32 FastAccessMode:1; 1202 UINT32 Reserved4:1; 1203 /// 1204 /// [Bit 20] Ignoring Idle Logical Processor HWP request is supported if set. 1205 /// 1206 UINT32 IgnoringIdleLogicalProcessorHWPRequest:1; 1207 UINT32 Reserved5:11; 1208 } Bits; 1209 /// 1210 /// All bit fields as a 32-bit value 1211 /// 1212 UINT32 Uint32; 1213 } CPUID_THERMAL_POWER_MANAGEMENT_EAX; 1214 1215 /** 1216 CPUID Thermal and Power Management Information returned in EBX for CPUID leaf 1217 #CPUID_THERMAL_POWER_MANAGEMENT. 1218 **/ 1219 typedef union { 1220 /// 1221 /// Individual bit fields 1222 /// 1223 struct { 1224 /// 1225 /// {Bits 3:0] Number of Interrupt Thresholds in Digital Thermal Sensor. 1226 /// 1227 UINT32 InterruptThresholds:4; 1228 UINT32 Reserved:28; 1229 } Bits; 1230 /// 1231 /// All bit fields as a 32-bit value 1232 /// 1233 UINT32 Uint32; 1234 } CPUID_THERMAL_POWER_MANAGEMENT_EBX; 1235 1236 /** 1237 CPUID Thermal and Power Management Information returned in ECX for CPUID leaf 1238 #CPUID_THERMAL_POWER_MANAGEMENT. 1239 **/ 1240 typedef union { 1241 /// 1242 /// Individual bit fields 1243 /// 1244 struct { 1245 /// 1246 /// [Bit 0] Hardware Coordination Feedback Capability (Presence of IA32_MPERF 1247 /// and IA32_APERF). The capability to provide a measure of delivered 1248 /// processor performance (since last reset of the counters), as a percentage 1249 /// of the expected processor performance when running at the TSC frequency. 1250 /// 1251 UINT32 HardwareCoordinationFeedback:1; 1252 UINT32 Reserved1:2; 1253 /// 1254 /// [Bit 3] If this bit is set, then the processor supports performance-energy 1255 /// bias preference and the architectural MSR called IA32_ENERGY_PERF_BIAS 1256 /// (1B0H). 1257 /// 1258 UINT32 PerformanceEnergyBias:1; 1259 UINT32 Reserved2:28; 1260 } Bits; 1261 /// 1262 /// All bit fields as a 32-bit value 1263 /// 1264 UINT32 Uint32; 1265 } CPUID_THERMAL_POWER_MANAGEMENT_ECX; 1266 1267 1268 /** 1269 CPUID Structured Extended Feature Flags Enumeration 1270 1271 @param EAX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07) 1272 @param ECX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO (0x00). 1273 1274 @note 1275 If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf 1276 index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX. 1277 1278 @retval EAX The maximum input value for ECX to retrieve sub-leaf information. 1279 @retval EBX Structured Extended Feature Flags described by the type 1280 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX. 1281 @retval EBX Structured Extended Feature Flags described by the type 1282 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX. 1283 @retval EDX Reserved. 1284 1285 <b>Example usage</b> 1286 @code 1287 UINT32 Eax; 1288 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx; 1289 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx; 1290 UINT32 SubLeaf; 1291 1292 AsmCpuidEx ( 1293 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 1294 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, 1295 &Eax, NULL, NULL, NULL 1296 ); 1297 for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) { 1298 AsmCpuidEx ( 1299 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 1300 SubLeaf, 1301 NULL, &Ebx.Uint32, &Ecx.Uint32, NULL 1302 ); 1303 } 1304 @endcode 1305 **/ 1306 #define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07 1307 1308 /// 1309 /// CPUID Structured Extended Feature Flags Enumeration sub-leaf 1310 /// 1311 #define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO 0x00 1312 1313 /** 1314 CPUID Structured Extended Feature Flags Enumeration in EBX for CPUID leaf 1315 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf 1316 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO. 1317 **/ 1318 typedef union { 1319 /// 1320 /// Individual bit fields 1321 /// 1322 struct { 1323 /// 1324 /// [Bit 0] Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1. 1325 /// 1326 UINT32 FSGSBASE:1; 1327 /// 1328 /// [Bit 1] IA32_TSC_ADJUST MSR is supported if 1. 1329 /// 1330 UINT32 IA32_TSC_ADJUST:1; 1331 /// 1332 /// [Bit 2] Intel SGX is supported if 1. See section 37.7 "DISCOVERING SUPPORT 1333 /// FOR INTEL(R) SGX AND ENABLING ENCLAVE INSTRUCTIONS". 1334 /// 1335 UINT32 SGX:1; 1336 /// 1337 /// [Bit 3] If 1 indicates the processor supports the first group of advanced 1338 /// bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT) 1339 /// 1340 UINT32 BMI1:1; 1341 /// 1342 /// [Bit 4] Hardware Lock Elision 1343 /// 1344 UINT32 HLE:1; 1345 /// 1346 /// [Bit 5] If 1 indicates the processor supports AVX2 instruction extensions. 1347 /// 1348 UINT32 AVX2:1; 1349 /// 1350 /// [Bit 6] x87 FPU Data Pointer updated only on x87 exceptions if 1. 1351 /// 1352 UINT32 FDP_EXCPTN_ONLY:1; 1353 /// 1354 /// [Bit 7] Supports Supervisor-Mode Execution Prevention if 1. 1355 /// 1356 UINT32 SMEP:1; 1357 /// 1358 /// [Bit 8] If 1 indicates the processor supports the second group of 1359 /// advanced bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX, 1360 /// SARX, SHLX, SHRX) 1361 /// 1362 UINT32 BMI2:1; 1363 /// 1364 /// [Bit 9] Supports Enhanced REP MOVSB/STOSB if 1. 1365 /// 1366 UINT32 EnhancedRepMovsbStosb:1; 1367 /// 1368 /// [Bit 10] If 1, supports INVPCID instruction for system software that 1369 /// manages process-context identifiers. 1370 /// 1371 UINT32 INVPCID:1; 1372 /// 1373 /// [Bit 11] Restricted Transactional Memory 1374 /// 1375 UINT32 RTM:1; 1376 /// 1377 /// [Bit 12] Supports Intel(R) Resource Director Technology (Intel(R) RDT) 1378 /// Monitoring capability if 1. 1379 /// 1380 UINT32 RDT_M:1; 1381 /// 1382 /// [Bit 13] Deprecates FPU CS and FPU DS values if 1. 1383 /// 1384 UINT32 DeprecateFpuCsDs:1; 1385 /// 1386 /// [Bit 14] Supports Intel(R) Memory Protection Extensions if 1. 1387 /// 1388 UINT32 MPX:1; 1389 /// 1390 /// [Bit 15] Supports Intel(R) Resource Director Technology (Intel(R) RDT) 1391 /// Allocation capability if 1. 1392 /// 1393 UINT32 RDT_A:1; 1394 /// 1395 /// [Bit 16] AVX512F. 1396 /// 1397 UINT32 AVX512F:1; 1398 /// 1399 /// [Bit 17] AVX512DQ. 1400 /// 1401 UINT32 AVX512DQ:1; 1402 /// 1403 /// [Bit 18] If 1 indicates the processor supports the RDSEED instruction. 1404 /// 1405 UINT32 RDSEED:1; 1406 /// 1407 /// [Bit 19] If 1 indicates the processor supports the ADCX and ADOX 1408 /// instructions. 1409 /// 1410 UINT32 ADX:1; 1411 /// 1412 /// [Bit 20] Supports Supervisor-Mode Access Prevention (and the CLAC/STAC 1413 /// instructions) if 1. 1414 /// 1415 UINT32 SMAP:1; 1416 /// 1417 /// [Bit 21] AVX512_IFMA. 1418 /// 1419 UINT32 AVX512_IFMA:1; 1420 UINT32 Reserved6:1; 1421 /// 1422 /// [Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction. 1423 /// 1424 UINT32 CLFLUSHOPT:1; 1425 /// 1426 /// [Bit 24] If 1 indicates the processor supports the CLWB instruction. 1427 /// 1428 UINT32 CLWB:1; 1429 /// 1430 /// [Bit 25] If 1 indicates the processor supports the Intel Processor Trace 1431 /// extensions. 1432 /// 1433 UINT32 IntelProcessorTrace:1; 1434 /// 1435 /// [Bit 26] AVX512PF. (Intel Xeon Phi only.). 1436 /// 1437 UINT32 AVX512PF:1; 1438 /// 1439 /// [Bit 27] AVX512ER. (Intel Xeon Phi only.). 1440 /// 1441 UINT32 AVX512ER:1; 1442 /// 1443 /// [Bit 28] AVX512CD. 1444 /// 1445 UINT32 AVX512CD:1; 1446 /// 1447 /// [Bit 29] Supports Intel(R) Secure Hash Algorithm Extensions (Intel(R) 1448 /// SHA Extensions) if 1. 1449 /// 1450 UINT32 SHA:1; 1451 /// 1452 /// [Bit 30] AVX512BW. 1453 /// 1454 UINT32 AVX512BW:1; 1455 /// 1456 /// [Bit 31] AVX512VL. 1457 /// 1458 UINT32 AVX512VL:1; 1459 } Bits; 1460 /// 1461 /// All bit fields as a 32-bit value 1462 /// 1463 UINT32 Uint32; 1464 } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX; 1465 1466 /** 1467 CPUID Structured Extended Feature Flags Enumeration in ECX for CPUID leaf 1468 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf 1469 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO. 1470 **/ 1471 typedef union { 1472 /// 1473 /// Individual bit fields 1474 /// 1475 struct { 1476 /// 1477 /// [Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction. 1478 /// (Intel Xeon Phi only.) 1479 /// 1480 UINT32 PREFETCHWT1:1; 1481 /// 1482 /// [Bit 1] AVX512_VBMI. 1483 /// 1484 UINT32 AVX512_VBMI:1; 1485 /// 1486 /// [Bit 2] Supports user-mode instruction prevention if 1. 1487 /// 1488 UINT32 UMIP:1; 1489 /// 1490 /// [Bit 3] Supports protection keys for user-mode pages if 1. 1491 /// 1492 UINT32 PKU:1; 1493 /// 1494 /// [Bit 4] If 1, OS has set CR4.PKE to enable protection keys (and the 1495 /// RDPKRU/WRPKRU instructions). 1496 /// 1497 UINT32 OSPKE:1; 1498 UINT32 Reserved5:9; 1499 /// 1500 /// [Bits 14] AVX512_VPOPCNTDQ. (Intel Xeon Phi only.). 1501 /// 1502 UINT32 AVX512_VPOPCNTDQ:1; 1503 UINT32 Reserved7:1; 1504 /// 1505 /// [Bits 16] Supports 5-level paging if 1. 1506 /// 1507 UINT32 FiveLevelPage:1; 1508 /// 1509 /// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions 1510 /// in 64-bit mode. 1511 /// 1512 UINT32 MAWAU:5; 1513 /// 1514 /// [Bit 22] RDPID and IA32_TSC_AUX are available if 1. 1515 /// 1516 UINT32 RDPID:1; 1517 UINT32 Reserved3:7; 1518 /// 1519 /// [Bit 30] Supports SGX Launch Configuration if 1. 1520 /// 1521 UINT32 SGX_LC:1; 1522 UINT32 Reserved4:1; 1523 } Bits; 1524 /// 1525 /// All bit fields as a 32-bit value 1526 /// 1527 UINT32 Uint32; 1528 } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX; 1529 1530 /** 1531 CPUID Structured Extended Feature Flags Enumeration in EDX for CPUID leaf 1532 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf 1533 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO. 1534 **/ 1535 typedef union { 1536 /// 1537 /// Individual bit fields 1538 /// 1539 struct { 1540 /// 1541 /// [Bit 1:0] Reserved. 1542 /// 1543 UINT32 Reserved1:2; 1544 /// 1545 /// [Bit 2] AVX512_4VNNIW. (Intel Xeon Phi only.) 1546 /// 1547 UINT32 AVX512_4VNNIW:1; 1548 /// 1549 /// [Bit 3] AVX512_4FMAPS. (Intel Xeon Phi only.) 1550 /// 1551 UINT32 AVX512_4FMAPS:1; 1552 /// 1553 /// [Bit 25:4] Reserved. 1554 /// 1555 UINT32 Reserved2:22; 1556 /// 1557 /// [Bit 26] Enumerates support for indirect branch restricted speculation 1558 /// (IBRS) and the indirect branch pre-dictor barrier (IBPB). Processors 1559 /// that set this bit support the IA32_SPEC_CTRL MSR and the IA32_PRED_CMD 1560 /// MSR. They allow software to set IA32_SPEC_CTRL[0] (IBRS) and 1561 /// IA32_PRED_CMD[0] (IBPB). 1562 /// 1563 UINT32 EnumeratesSupportForIBRSAndIBPB:1; 1564 /// 1565 /// [Bit 27] Enumerates support for single thread indirect branch 1566 /// predictors (STIBP). Processors that set this bit support the 1567 /// IA32_SPEC_CTRL MSR. They allow software to set IA32_SPEC_CTRL[1] 1568 /// (STIBP). 1569 /// 1570 UINT32 EnumeratesSupportForSTIBP:1; 1571 /// 1572 /// [Bit 28] Enumerates support for L1D_FLUSH. Processors that set this bit 1573 /// support the IA32_FLUSH_CMD MSR. They allow software to set 1574 /// IA32_FLUSH_CMD[0] (L1D_FLUSH). 1575 /// 1576 UINT32 EnumeratesSupportForL1D_FLUSH:1; 1577 /// 1578 /// [Bit 29] Enumerates support for the IA32_ARCH_CAPABILITIES MSR. 1579 /// 1580 UINT32 EnumeratesSupportForCapability:1; 1581 /// 1582 /// [Bit 30] Reserved. 1583 /// 1584 UINT32 Reserved3:1; 1585 /// 1586 /// [Bit 31] Enumerates support for Speculative Store Bypass Disable (SSBD). 1587 /// Processors that set this bit sup-port the IA32_SPEC_CTRL MSR. They allow 1588 /// software to set IA32_SPEC_CTRL[2] (SSBD). 1589 /// 1590 UINT32 EnumeratesSupportForSSBD:1; 1591 } Bits; 1592 /// 1593 /// All bit fields as a 32-bit value 1594 /// 1595 UINT32 Uint32; 1596 } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX; 1597 1598 /** 1599 CPUID Direct Cache Access Information 1600 1601 @param EAX CPUID_DIRECT_CACHE_ACCESS_INFO (0x09) 1602 1603 @retval EAX Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1F8H). 1604 @retval EBX Reserved. 1605 @retval ECX Reserved. 1606 @retval EDX Reserved. 1607 1608 <b>Example usage</b> 1609 @code 1610 UINT32 Eax; 1611 1612 AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL); 1613 @endcode 1614 **/ 1615 #define CPUID_DIRECT_CACHE_ACCESS_INFO 0x09 1616 1617 1618 /** 1619 CPUID Architectural Performance Monitoring 1620 1621 @param EAX CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING (0x0A) 1622 1623 @retval EAX Architectural Performance Monitoring information described by 1624 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX. 1625 @retval EBX Architectural Performance Monitoring information described by 1626 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX. 1627 @retval ECX Reserved. 1628 @retval EDX Architectural Performance Monitoring information described by 1629 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX. 1630 1631 <b>Example usage</b> 1632 @code 1633 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX Eax; 1634 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX Ebx; 1635 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX Edx; 1636 1637 AsmCpuid (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING, &Eax.Uint32, &Ebx.Uint32, NULL, &Edx.Uint32); 1638 @endcode 1639 **/ 1640 #define CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING 0x0A 1641 1642 /** 1643 CPUID Architectural Performance Monitoring EAX for CPUID leaf 1644 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING. 1645 **/ 1646 typedef union { 1647 /// 1648 /// Individual bit fields 1649 /// 1650 struct { 1651 /// 1652 /// [Bit 7:0] Version ID of architectural performance monitoring. 1653 /// 1654 UINT32 ArchPerfMonVerID:8; 1655 /// 1656 /// [Bits 15:8] Number of general-purpose performance monitoring counter 1657 /// per logical processor. 1658 /// 1659 /// IA32_PERFEVTSELx MSRs start at address 186H and occupy a contiguous 1660 /// block of MSR address space. Each performance event select register is 1661 /// paired with a corresponding performance counter in the 0C1H address 1662 /// block. 1663 /// 1664 UINT32 PerformanceMonitorCounters:8; 1665 /// 1666 /// [Bits 23:16] Bit width of general-purpose, performance monitoring counter. 1667 /// 1668 /// The bit width of an IA32_PMCx MSR. This the number of valid bits for 1669 /// read operation. On write operations, the lower-order 32 bits of the MSR 1670 /// may be written with any value, and the high-order bits are sign-extended 1671 /// from the value of bit 31. 1672 /// 1673 UINT32 PerformanceMonitorCounterWidth:8; 1674 /// 1675 /// [Bits 31:24] Length of EBX bit vector to enumerate architectural 1676 /// performance monitoring events. 1677 /// 1678 UINT32 EbxBitVectorLength:8; 1679 } Bits; 1680 /// 1681 /// All bit fields as a 32-bit value 1682 /// 1683 UINT32 Uint32; 1684 } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX; 1685 1686 /** 1687 CPUID Architectural Performance Monitoring EBX for CPUID leaf 1688 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING. 1689 **/ 1690 typedef union { 1691 /// 1692 /// Individual bit fields 1693 /// 1694 struct { 1695 /// 1696 /// [Bit 0] Core cycle event not available if 1. 1697 /// 1698 UINT32 UnhaltedCoreCycles:1; 1699 /// 1700 /// [Bit 1] Instruction retired event not available if 1. 1701 /// 1702 UINT32 InstructionsRetired:1; 1703 /// 1704 /// [Bit 2] Reference cycles event not available if 1. 1705 /// 1706 UINT32 UnhaltedReferenceCycles:1; 1707 /// 1708 /// [Bit 3] Last-level cache reference event not available if 1. 1709 /// 1710 UINT32 LastLevelCacheReferences:1; 1711 /// 1712 /// [Bit 4] Last-level cache misses event not available if 1. 1713 /// 1714 UINT32 LastLevelCacheMisses:1; 1715 /// 1716 /// [Bit 5] Branch instruction retired event not available if 1. 1717 /// 1718 UINT32 BranchInstructionsRetired:1; 1719 /// 1720 /// [Bit 6] Branch mispredict retired event not available if 1. 1721 /// 1722 UINT32 AllBranchMispredictRetired:1; 1723 UINT32 Reserved:25; 1724 } Bits; 1725 /// 1726 /// All bit fields as a 32-bit value 1727 /// 1728 UINT32 Uint32; 1729 } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX; 1730 1731 /** 1732 CPUID Architectural Performance Monitoring EDX for CPUID leaf 1733 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING. 1734 **/ 1735 typedef union { 1736 /// 1737 /// Individual bit fields 1738 /// 1739 struct { 1740 /// 1741 /// [Bits 4:0] Number of fixed-function performance counters 1742 /// (if Version ID > 1). 1743 /// 1744 UINT32 FixedFunctionPerformanceCounters:5; 1745 /// 1746 /// [Bits 12:5] Bit width of fixed-function performance counters 1747 /// (if Version ID > 1). 1748 /// 1749 UINT32 FixedFunctionPerformanceCounterWidth:8; 1750 UINT32 Reserved1:2; 1751 /// 1752 /// [Bits 15] AnyThread deprecation. 1753 /// 1754 UINT32 AnyThreadDeprecation:1; 1755 UINT32 Reserved2:16; 1756 } Bits; 1757 /// 1758 /// All bit fields as a 32-bit value 1759 /// 1760 UINT32 Uint32; 1761 } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX; 1762 1763 1764 /** 1765 CPUID Extended Topology Information 1766 1767 @note 1768 CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first 1769 checking for the existence of Leaf 1FH before using leaf 0BH. 1770 Most of Leaf 0BH output depends on the initial value in ECX. The EDX output 1771 of leaf 0BH is always valid and does not vary with input value in ECX. Output 1772 value in ECX[7:0] always equals input value in ECX[7:0]. 1773 Sub-leaf index 0 enumerates SMT level. Each subsequent higher sub-leaf index 1774 enumerates a higher-level topological entity in hierarchical order. 1775 For sub-leaves that return an invalid level-type of 0 in ECX[15:8]; EAX and 1776 EBX will return 0. 1777 If an input value n in ECX returns the invalid level-type of 0 in ECX[15:8], 1778 other input values with ECX > n also return 0 in ECX[15:8]. 1779 1780 @param EAX CPUID_EXTENDED_TOPOLOGY (0x0B) 1781 @param ECX Level number 1782 1783 @retval EAX Extended topology information described by the type 1784 CPUID_EXTENDED_TOPOLOGY_EAX. 1785 @retval EBX Extended topology information described by the type 1786 CPUID_EXTENDED_TOPOLOGY_EBX. 1787 @retval ECX Extended topology information described by the type 1788 CPUID_EXTENDED_TOPOLOGY_ECX. 1789 @retval EDX x2APIC ID the current logical processor. 1790 1791 <b>Example usage</b> 1792 @code 1793 CPUID_EXTENDED_TOPOLOGY_EAX Eax; 1794 CPUID_EXTENDED_TOPOLOGY_EBX Ebx; 1795 CPUID_EXTENDED_TOPOLOGY_ECX Ecx; 1796 UINT32 Edx; 1797 UINT32 LevelNumber; 1798 1799 LevelNumber = 0; 1800 do { 1801 AsmCpuidEx ( 1802 CPUID_EXTENDED_TOPOLOGY, LevelNumber, 1803 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx 1804 ); 1805 LevelNumber++; 1806 } while (Eax.Bits.ApicIdShift != 0); 1807 @endcode 1808 **/ 1809 #define CPUID_EXTENDED_TOPOLOGY 0x0B 1810 1811 /** 1812 CPUID Extended Topology Information EAX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY. 1813 **/ 1814 typedef union { 1815 /// 1816 /// Individual bit fields 1817 /// 1818 struct { 1819 /// 1820 /// [Bits 4:0] Number of bits to shift right on x2APIC ID to get a unique 1821 /// topology ID of the next level type. All logical processors with the 1822 /// same next level ID share current level. 1823 /// 1824 /// @note 1825 /// Software should use this field (EAX[4:0]) to enumerate processor 1826 /// topology of the system. 1827 /// 1828 UINT32 ApicIdShift:5; 1829 UINT32 Reserved:27; 1830 } Bits; 1831 /// 1832 /// All bit fields as a 32-bit value 1833 /// 1834 UINT32 Uint32; 1835 } CPUID_EXTENDED_TOPOLOGY_EAX; 1836 1837 /** 1838 CPUID Extended Topology Information EBX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY. 1839 **/ 1840 typedef union { 1841 /// 1842 /// Individual bit fields 1843 /// 1844 struct { 1845 /// 1846 /// [Bits 15:0] Number of logical processors at this level type. The number 1847 /// reflects configuration as shipped by Intel. 1848 /// 1849 /// @note 1850 /// Software must not use EBX[15:0] to enumerate processor topology of the 1851 /// system. This value in this field (EBX[15:0]) is only intended for 1852 /// display/diagnostic purposes. The actual number of logical processors 1853 /// available to BIOS/OS/Applications may be different from the value of 1854 /// EBX[15:0], depending on software and platform hardware configurations. 1855 /// 1856 UINT32 LogicalProcessors:16; 1857 UINT32 Reserved:16; 1858 } Bits; 1859 /// 1860 /// All bit fields as a 32-bit value 1861 /// 1862 UINT32 Uint32; 1863 } CPUID_EXTENDED_TOPOLOGY_EBX; 1864 1865 /** 1866 CPUID Extended Topology Information ECX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY. 1867 **/ 1868 typedef union { 1869 /// 1870 /// Individual bit fields 1871 /// 1872 struct { 1873 /// 1874 /// [Bits 7:0] Level number. Same value in ECX input. 1875 /// 1876 UINT32 LevelNumber:8; 1877 /// 1878 /// [Bits 15:8] Level type. 1879 /// 1880 /// @note 1881 /// The value of the "level type" field is not related to level numbers in 1882 /// any way, higher "level type" values do not mean higher levels. 1883 /// 1884 UINT32 LevelType:8; 1885 UINT32 Reserved:16; 1886 } Bits; 1887 /// 1888 /// All bit fields as a 32-bit value 1889 /// 1890 UINT32 Uint32; 1891 } CPUID_EXTENDED_TOPOLOGY_ECX; 1892 1893 /// 1894 /// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType 1895 /// 1896 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x00 1897 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x01 1898 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x02 1899 /// 1900 /// @} 1901 /// 1902 1903 1904 /** 1905 CPUID Extended State Information 1906 1907 @param EAX CPUID_EXTENDED_STATE (0x0D) 1908 @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00). 1909 CPUID_EXTENDED_STATE_SUB_LEAF (0x01). 1910 CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02). 1911 Sub leafs 2..n based on supported bits in XCR0 or IA32_XSS_MSR. 1912 **/ 1913 #define CPUID_EXTENDED_STATE 0x0D 1914 1915 /** 1916 CPUID Extended State Information Main Leaf 1917 1918 @param EAX CPUID_EXTENDED_STATE (0x0D) 1919 @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00) 1920 1921 @retval EAX Reports the supported bits of the lower 32 bits of XCR0. XCR0[n] 1922 can be set to 1 only if EAX[n] is 1. The format of the extended 1923 state main leaf is described by the type 1924 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX. 1925 @retval EBX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save 1926 area) required by enabled features in XCR0. May be different than 1927 ECX if some features at the end of the XSAVE save area are not 1928 enabled. 1929 @retval ECX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save 1930 area) of the XSAVE/XRSTOR save area required by all supported 1931 features in the processor, i.e., all the valid bit fields in XCR0. 1932 @retval EDX Reports the supported bits of the upper 32 bits of XCR0. 1933 XCR0[n+32] can be set to 1 only if EDX[n] is 1. 1934 1935 <b>Example usage</b> 1936 @code 1937 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax; 1938 UINT32 Ebx; 1939 UINT32 Ecx; 1940 UINT32 Edx; 1941 1942 AsmCpuidEx ( 1943 CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF, 1944 &Eax.Uint32, &Ebx, &Ecx, &Edx 1945 ); 1946 @endcode 1947 **/ 1948 #define CPUID_EXTENDED_STATE_MAIN_LEAF 0x00 1949 1950 /** 1951 CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE, 1952 sub-leaf #CPUID_EXTENDED_STATE_MAIN_LEAF. 1953 **/ 1954 typedef union { 1955 /// 1956 /// Individual bit fields 1957 /// 1958 struct { 1959 /// 1960 /// [Bit 0] x87 state. 1961 /// 1962 UINT32 x87:1; 1963 /// 1964 /// [Bit 1] SSE state. 1965 /// 1966 UINT32 SSE:1; 1967 /// 1968 /// [Bit 2] AVX state. 1969 /// 1970 UINT32 AVX:1; 1971 /// 1972 /// [Bits 4:3] MPX state. 1973 /// 1974 UINT32 MPX:2; 1975 /// 1976 /// [Bits 7:5] AVX-512 state. 1977 /// 1978 UINT32 AVX_512:3; 1979 /// 1980 /// [Bit 8] Used for IA32_XSS. 1981 /// 1982 UINT32 IA32_XSS:1; 1983 /// 1984 /// [Bit 9] PKRU state. 1985 /// 1986 UINT32 PKRU:1; 1987 UINT32 Reserved1:3; 1988 /// 1989 /// [Bit 13] Used for IA32_XSS, part 2. 1990 /// 1991 UINT32 IA32_XSS_2:1; 1992 UINT32 Reserved2:18; 1993 } Bits; 1994 /// 1995 /// All bit fields as a 32-bit value 1996 /// 1997 UINT32 Uint32; 1998 } CPUID_EXTENDED_STATE_MAIN_LEAF_EAX; 1999 2000 /** 2001 CPUID Extended State Information Sub Leaf 2002 2003 @param EAX CPUID_EXTENDED_STATE (0x0D) 2004 @param ECX CPUID_EXTENDED_STATE_SUB_LEAF (0x01) 2005 2006 @retval EAX The format of the extended state sub-leaf is described by the 2007 type CPUID_EXTENDED_STATE_SUB_LEAF_EAX. 2008 @retval EBX The size in bytes of the XSAVE area containing all states 2009 enabled by XCRO | IA32_XSS. 2010 @retval ECX The format of the extended state sub-leaf is described by the 2011 type CPUID_EXTENDED_STATE_SUB_LEAF_ECX. 2012 @retval EDX Reports the supported bits of the upper 32 bits of the 2013 IA32_XSS MSR. IA32_XSS[n+32] can be set to 1 only if EDX[n] is 1. 2014 2015 <b>Example usage</b> 2016 @code 2017 CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax; 2018 UINT32 Ebx; 2019 CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx; 2020 UINT32 Edx; 2021 2022 AsmCpuidEx ( 2023 CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF, 2024 &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx 2025 ); 2026 @endcode 2027 **/ 2028 #define CPUID_EXTENDED_STATE_SUB_LEAF 0x01 2029 2030 /** 2031 CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE, 2032 sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF. 2033 **/ 2034 typedef union { 2035 /// 2036 /// Individual bit fields 2037 /// 2038 struct { 2039 /// 2040 /// [Bit 0] XSAVEOPT is available. 2041 /// 2042 UINT32 XSAVEOPT:1; 2043 /// 2044 /// [Bit 1] Supports XSAVEC and the compacted form of XRSTOR if set. 2045 /// 2046 UINT32 XSAVEC:1; 2047 /// 2048 /// [Bit 2] Supports XGETBV with ECX = 1 if set. 2049 /// 2050 UINT32 XGETBV:1; 2051 /// 2052 /// [Bit 3] Supports XSAVES/XRSTORS and IA32_XSS if set. 2053 /// 2054 UINT32 XSAVES:1; 2055 UINT32 Reserved:28; 2056 } Bits; 2057 /// 2058 /// All bit fields as a 32-bit value 2059 /// 2060 UINT32 Uint32; 2061 } CPUID_EXTENDED_STATE_SUB_LEAF_EAX; 2062 2063 /** 2064 CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE, 2065 sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF. 2066 **/ 2067 typedef union { 2068 /// 2069 /// Individual bit fields 2070 /// 2071 struct { 2072 /// 2073 /// [Bits 7:0] Used for XCR0. 2074 /// 2075 UINT32 XCR0:1; 2076 /// 2077 /// [Bit 8] PT STate. 2078 /// 2079 UINT32 PT:1; 2080 /// 2081 /// [Bit 9] Used for XCR0. 2082 /// 2083 UINT32 XCR0_1:1; 2084 UINT32 Reserved1:3; 2085 /// 2086 /// [Bit 13] HWP state. 2087 /// 2088 UINT32 HWPState:1; 2089 UINT32 Reserved8:18; 2090 } Bits; 2091 /// 2092 /// All bit fields as a 32-bit value 2093 /// 2094 UINT32 Uint32; 2095 } CPUID_EXTENDED_STATE_SUB_LEAF_ECX; 2096 2097 /** 2098 CPUID Extended State Information Size and Offset Sub Leaf 2099 2100 @note 2101 Leaf 0DH output depends on the initial value in ECX. 2102 Each sub-leaf index (starting at position 2) is supported if it corresponds to 2103 a supported bit in either the XCR0 register or the IA32_XSS MSR. 2104 If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf 2105 n (0 <= n <= 31) is invalid if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1 2106 returns 0 in ECX[n]. Sub-leaf n (32 <= n <= 63) is invalid if sub-leaf 0 2107 returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32]. 2108 2109 @param EAX CPUID_EXTENDED_STATE (0x0D) 2110 @param ECX CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02). Sub leafs 2..n based 2111 on supported bits in XCR0 or IA32_XSS_MSR. 2112 2113 @retval EAX The size in bytes (from the offset specified in EBX) of the save 2114 area for an extended state feature associated with a valid 2115 sub-leaf index, n. 2116 @retval EBX The offset in bytes of this extended state component's save area 2117 from the beginning of the XSAVE/XRSTOR area. This field reports 2118 0 if the sub-leaf index, n, does not map to a valid bit in the 2119 XCR0 register. 2120 @retval ECX The format of the extended state components's save area as 2121 described by the type CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX. 2122 This field reports 0 if the sub-leaf index, n, is invalid. 2123 @retval EDX This field reports 0 if the sub-leaf index, n, is invalid; 2124 otherwise it is reserved. 2125 2126 <b>Example usage</b> 2127 @code 2128 UINT32 Eax; 2129 UINT32 Ebx; 2130 CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX Ecx; 2131 UINT32 Edx; 2132 UINTN SubLeaf; 2133 2134 for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) { 2135 AsmCpuidEx ( 2136 CPUID_EXTENDED_STATE, SubLeaf, 2137 &Eax, &Ebx, &Ecx.Uint32, &Edx 2138 ); 2139 } 2140 @endcode 2141 **/ 2142 #define CPUID_EXTENDED_STATE_SIZE_OFFSET 0x02 2143 2144 /** 2145 CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE, 2146 sub-leaf #CPUID_EXTENDED_STATE_SIZE_OFFSET. 2147 **/ 2148 typedef union { 2149 /// 2150 /// Individual bit fields 2151 /// 2152 struct { 2153 /// 2154 /// [Bit 0] Is set if the bit n (corresponding to the sub-leaf index) is 2155 /// supported in the IA32_XSS MSR; it is clear if bit n is instead supported 2156 /// in XCR0. 2157 /// 2158 UINT32 XSS:1; 2159 /// 2160 /// [Bit 1] is set if, when the compacted format of an XSAVE area is used, 2161 /// this extended state component located on the next 64-byte boundary 2162 /// following the preceding state component (otherwise, it is located 2163 /// immediately following the preceding state component). 2164 /// 2165 UINT32 Compacted:1; 2166 UINT32 Reserved:30; 2167 } Bits; 2168 /// 2169 /// All bit fields as a 32-bit value 2170 /// 2171 UINT32 Uint32; 2172 } CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX; 2173 2174 2175 /** 2176 CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information 2177 2178 @param EAX CPUID_INTEL_RDT_MONITORING (0x0F) 2179 @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00). 2180 CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01). 2181 2182 **/ 2183 #define CPUID_INTEL_RDT_MONITORING 0x0F 2184 2185 /** 2186 CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information 2187 Enumeration Sub-leaf 2188 2189 @param EAX CPUID_INTEL_RDT_MONITORING (0x0F) 2190 @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00) 2191 2192 @retval EAX Reserved. 2193 @retval EBX Maximum range (zero-based) of RMID within this physical 2194 processor of all types. 2195 @retval ECX Reserved. 2196 @retval EDX L3 Cache Intel RDT Monitoring Information Enumeration described by 2197 the type CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX. 2198 2199 <b>Example usage</b> 2200 @code 2201 UINT32 Ebx; 2202 CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx; 2203 2204 AsmCpuidEx ( 2205 CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF, 2206 NULL, &Ebx, NULL, &Edx.Uint32 2207 ); 2208 @endcode 2209 **/ 2210 #define CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF 0x00 2211 2212 /** 2213 CPUID Intel RDT Monitoring Information EDX for CPUID leaf 2214 #CPUID_INTEL_RDT_MONITORING, sub-leaf 2215 #CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF. 2216 **/ 2217 typedef union { 2218 /// 2219 /// Individual bit fields 2220 /// 2221 struct { 2222 UINT32 Reserved1:1; 2223 /// 2224 /// [Bit 1] Supports L3 Cache Intel RDT Monitoring if 1. 2225 /// 2226 UINT32 L3CacheRDT_M:1; 2227 UINT32 Reserved2:30; 2228 } Bits; 2229 /// 2230 /// All bit fields as a 32-bit value 2231 /// 2232 UINT32 Uint32; 2233 } CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX; 2234 2235 /** 2236 CPUID L3 Cache Intel RDT Monitoring Capability Enumeration Sub-leaf 2237 2238 @param EAX CPUID_INTEL_RDT_MONITORING (0x0F) 2239 @param ECX CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01) 2240 2241 @retval EAX Reserved. 2242 @retval EBX Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes). 2243 @retval ECX Maximum range (zero-based) of RMID of this resource type. 2244 @retval EDX L3 Cache Intel RDT Monitoring Capability information described by the 2245 type CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX. 2246 2247 <b>Example usage</b> 2248 @code 2249 UINT32 Ebx; 2250 UINT32 Ecx; 2251 CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx; 2252 2253 AsmCpuidEx ( 2254 CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF, 2255 NULL, &Ebx, &Ecx, &Edx.Uint32 2256 ); 2257 @endcode 2258 **/ 2259 #define CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF 0x01 2260 2261 /** 2262 CPUID L3 Cache Intel RDT Monitoring Capability Information EDX for CPUID leaf 2263 #CPUID_INTEL_RDT_MONITORING, sub-leaf 2264 #CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF. 2265 **/ 2266 typedef union { 2267 /// 2268 /// Individual bit fields 2269 /// 2270 struct { 2271 /// 2272 /// [Bit 0] Supports L3 occupancy monitoring if 1. 2273 /// 2274 UINT32 L3CacheOccupancyMonitoring:1; 2275 /// 2276 /// [Bit 1] Supports L3 Total Bandwidth monitoring if 1. 2277 /// 2278 UINT32 L3CacheTotalBandwidthMonitoring:1; 2279 /// 2280 /// [Bit 2] Supports L3 Local Bandwidth monitoring if 1. 2281 /// 2282 UINT32 L3CacheLocalBandwidthMonitoring:1; 2283 UINT32 Reserved:29; 2284 } Bits; 2285 /// 2286 /// All bit fields as a 32-bit value 2287 /// 2288 UINT32 Uint32; 2289 } CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX; 2290 2291 2292 /** 2293 CPUID Intel Resource Director Technology (Intel RDT) Allocation Information 2294 2295 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10). 2296 @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00). 2297 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01). 2298 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02). 2299 **/ 2300 #define CPUID_INTEL_RDT_ALLOCATION 0x10 2301 2302 /** 2303 Intel Resource Director Technology (Intel RDT) Allocation Enumeration Sub-leaf 2304 2305 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10) 2306 @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00). 2307 2308 @retval EAX Reserved. 2309 @retval EBX L3 and L2 Cache Allocation Technology information described by 2310 the type CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX. 2311 @retval ECX Reserved. 2312 @retval EDX Reserved. 2313 2314 <b>Example usage</b> 2315 @code 2316 CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX Ebx; 2317 2318 AsmCpuidEx ( 2319 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF, 2320 NULL, &Ebx.Uint32, NULL, NULL 2321 ); 2322 @endcode 2323 **/ 2324 #define CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF 0x00 2325 2326 /** 2327 CPUID L3 and L2 Cache Allocation Support Information EBX for CPUID leaf 2328 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf 2329 #CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF. 2330 **/ 2331 typedef union { 2332 /// 2333 /// Individual bit fields 2334 /// 2335 struct { 2336 UINT32 Reserved1:1; 2337 /// 2338 /// [Bit 1] Supports L3 Cache Allocation Technology if 1. 2339 /// 2340 UINT32 L3CacheAllocation:1; 2341 /// 2342 /// [Bit 2] Supports L2 Cache Allocation Technology if 1. 2343 /// 2344 UINT32 L2CacheAllocation:1; 2345 /// 2346 /// [Bit 3] Supports Memory Bandwidth Allocation if 1. 2347 /// 2348 UINT32 MemoryBandwidth:1; 2349 UINT32 Reserved3:28; 2350 } Bits; 2351 /// 2352 /// All bit fields as a 32-bit value 2353 /// 2354 UINT32 Uint32; 2355 } CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX; 2356 2357 2358 /** 2359 L3 Cache Allocation Technology Enumeration Sub-leaf 2360 2361 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10) 2362 @param ECX CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01) 2363 2364 @retval EAX RESID L3 Cache Allocation Technology information described by 2365 the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX. 2366 @retval EBX Bit-granular map of isolation/contention of allocation units. 2367 @retval ECX RESID L3 Cache Allocation Technology information described by 2368 the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX. 2369 @retval EDX RESID L3 Cache Allocation Technology information described by 2370 the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX. 2371 2372 <b>Example usage</b> 2373 @code 2374 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX Eax; 2375 UINT32 Ebx; 2376 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX Ecx; 2377 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx; 2378 2379 AsmCpuidEx ( 2380 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF, 2381 &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32 2382 ); 2383 @endcode 2384 **/ 2385 #define CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF 0x01 2386 2387 /** 2388 CPUID L3 Cache Allocation Technology Information EAX for CPUID leaf 2389 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf 2390 #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF. 2391 **/ 2392 typedef union { 2393 /// 2394 /// Individual bit fields 2395 /// 2396 struct { 2397 /// 2398 /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID 2399 /// using minus-one notation. 2400 /// 2401 UINT32 CapacityLength:5; 2402 UINT32 Reserved:27; 2403 } Bits; 2404 /// 2405 /// All bit fields as a 32-bit value 2406 /// 2407 UINT32 Uint32; 2408 } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX; 2409 2410 /** 2411 CPUID L3 Cache Allocation Technology Information ECX for CPUID leaf 2412 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf 2413 #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF. 2414 **/ 2415 typedef union { 2416 /// 2417 /// Individual bit fields 2418 /// 2419 struct { 2420 UINT32 Reserved3:2; 2421 /// 2422 /// [Bit 2] Code and Data Prioritization Technology supported if 1. 2423 /// 2424 UINT32 CodeDataPrioritization:1; 2425 UINT32 Reserved2:29; 2426 } Bits; 2427 /// 2428 /// All bit fields as a 32-bit value 2429 /// 2430 UINT32 Uint32; 2431 } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX; 2432 2433 /** 2434 CPUID L3 Cache Allocation Technology Information EDX for CPUID leaf 2435 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf 2436 #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF. 2437 **/ 2438 typedef union { 2439 /// 2440 /// Individual bit fields 2441 /// 2442 struct { 2443 /// 2444 /// [Bits 15:0] Highest COS number supported for this ResID. 2445 /// 2446 UINT32 HighestCosNumber:16; 2447 UINT32 Reserved:16; 2448 } Bits; 2449 /// 2450 /// All bit fields as a 32-bit value 2451 /// 2452 UINT32 Uint32; 2453 } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX; 2454 2455 /** 2456 L2 Cache Allocation Technology Enumeration Sub-leaf 2457 2458 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10) 2459 @param ECX CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02) 2460 2461 @retval EAX RESID L2 Cache Allocation Technology information described by 2462 the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX. 2463 @retval EBX Bit-granular map of isolation/contention of allocation units. 2464 @retval ECX Reserved. 2465 @retval EDX RESID L2 Cache Allocation Technology information described by 2466 the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX. 2467 2468 <b>Example usage</b> 2469 @code 2470 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX Eax; 2471 UINT32 Ebx; 2472 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx; 2473 2474 AsmCpuidEx ( 2475 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF, 2476 &Eax.Uint32, &Ebx, NULL, &Edx.Uint32 2477 ); 2478 @endcode 2479 **/ 2480 #define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF 0x02 2481 2482 /** 2483 CPUID L2 Cache Allocation Technology Information EAX for CPUID leaf 2484 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf 2485 #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF. 2486 **/ 2487 typedef union { 2488 /// 2489 /// Individual bit fields 2490 /// 2491 struct { 2492 /// 2493 /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID 2494 /// using minus-one notation. 2495 /// 2496 UINT32 CapacityLength:5; 2497 UINT32 Reserved:27; 2498 } Bits; 2499 /// 2500 /// All bit fields as a 32-bit value 2501 /// 2502 UINT32 Uint32; 2503 } CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX; 2504 2505 /** 2506 CPUID L2 Cache Allocation Technology Information EDX for CPUID leaf 2507 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf 2508 #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF. 2509 **/ 2510 typedef union { 2511 /// 2512 /// Individual bit fields 2513 /// 2514 struct { 2515 /// 2516 /// [Bits 15:0] Highest COS number supported for this ResID. 2517 /// 2518 UINT32 HighestCosNumber:16; 2519 UINT32 Reserved:16; 2520 } Bits; 2521 /// 2522 /// All bit fields as a 32-bit value 2523 /// 2524 UINT32 Uint32; 2525 } CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX; 2526 2527 /** 2528 Memory Bandwidth Allocation Enumeration Sub-leaf 2529 2530 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10) 2531 @param ECX CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF (0x03) 2532 2533 @retval EAX RESID memory bandwidth Allocation Technology information 2534 described by the type 2535 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX. 2536 @retval EBX Reserved. 2537 @retval ECX RESID memory bandwidth Allocation Technology information 2538 described by the type 2539 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX. 2540 @retval EDX RESID memory bandwidth Allocation Technology information 2541 described by the type 2542 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX. 2543 2544 <b>Example usage</b> 2545 @code 2546 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX Eax; 2547 UINT32 Ebx; 2548 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX Ecx; 2549 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX Edx; 2550 2551 2552 AsmCpuidEx ( 2553 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF, 2554 &Eax.Uint32, &Ebx, NULL, &Edx.Uint32 2555 ); 2556 @endcode 2557 **/ 2558 #define CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF 0x03 2559 2560 /** 2561 CPUID memory bandwidth Allocation Technology Information EAX for CPUID leaf 2562 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf 2563 #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF. 2564 **/ 2565 typedef union { 2566 /// 2567 /// Individual bit fields 2568 /// 2569 struct { 2570 /// 2571 /// [Bits 11:0] Reports the maximum MBA throttling value supported for 2572 /// the corresponding ResID using minus-one notation. 2573 /// 2574 UINT32 MaximumMBAThrottling:12; 2575 UINT32 Reserved:20; 2576 } Bits; 2577 /// 2578 /// All bit fields as a 32-bit value 2579 /// 2580 UINT32 Uint32; 2581 } CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX; 2582 2583 /** 2584 CPUID memory bandwidth Allocation Technology Information ECX for CPUID leaf 2585 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf 2586 #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF. 2587 **/ 2588 typedef union { 2589 /// 2590 /// Individual bit fields 2591 /// 2592 struct { 2593 /// 2594 /// [Bits 1:0] Reserved. 2595 /// 2596 UINT32 Reserved1:2; 2597 /// 2598 /// [Bits 3] Reports whether the response of the delay values is linear. 2599 /// 2600 UINT32 Liner:1; 2601 UINT32 Reserved2:29; 2602 } Bits; 2603 /// 2604 /// All bit fields as a 32-bit value 2605 /// 2606 UINT32 Uint32; 2607 } CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX; 2608 2609 /** 2610 CPUID memory bandwidth Allocation Technology Information EDX for CPUID leaf 2611 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf 2612 #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF. 2613 **/ 2614 typedef union { 2615 /// 2616 /// Individual bit fields 2617 /// 2618 struct { 2619 /// 2620 /// [Bits 15:0] Highest COS number supported for this ResID. 2621 /// 2622 UINT32 HighestCosNumber:16; 2623 UINT32 Reserved:16; 2624 } Bits; 2625 /// 2626 /// All bit fields as a 32-bit value 2627 /// 2628 UINT32 Uint32; 2629 } CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX; 2630 2631 /** 2632 Intel SGX resource capability and configuration. 2633 See Section 37.7.2 "Intel(R) SGX Resource Enumeration Leaves". 2634 2635 If CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor also supports querying 2636 CPUID with EAX=12H on Intel SGX resource capability and configuration. 2637 2638 @param EAX CPUID_INTEL_SGX (0x12) 2639 @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00). 2640 CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01). 2641 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02). 2642 Sub leafs 2..n based on the sub-leaf-type encoding (returned in EAX[3:0]) 2643 until the sub-leaf type is invalid. 2644 2645 **/ 2646 #define CPUID_INTEL_SGX 0x12 2647 2648 /** 2649 Sub-Leaf 0 Enumeration of Intel SGX Capabilities. 2650 Enumerates Intel SGX capability, including enclave instruction opcode support. 2651 2652 @param EAX CPUID_INTEL_SGX (0x12) 2653 @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00) 2654 2655 @retval EAX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is 2656 described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX. 2657 @retval EBX MISCSELECT: Reports the bit vector of supported extended features 2658 that can be written to the MISC region of the SSA. 2659 @retval ECX Reserved. 2660 @retval EDX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is 2661 described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX. 2662 2663 <b>Example usage</b> 2664 @code 2665 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX Eax; 2666 UINT32 Ebx; 2667 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx; 2668 2669 AsmCpuidEx ( 2670 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF, 2671 &Eax.Uint32, &Ebx, NULL, &Edx.Uint32 2672 ); 2673 @endcode 2674 **/ 2675 #define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF 0x00 2676 2677 /** 2678 Sub-Leaf 0 Enumeration of Intel SGX Capabilities EAX for CPUID leaf #CPUID_INTEL_SGX, 2679 sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF. 2680 **/ 2681 typedef union { 2682 /// 2683 /// Individual bit fields 2684 /// 2685 struct { 2686 /// 2687 /// [Bit 0] If 1, indicates leaf functions of SGX1 instruction are supported. 2688 /// 2689 UINT32 SGX1:1; 2690 /// 2691 /// [Bit 1] If 1, indicates leaf functions of SGX2 instruction are supported. 2692 /// 2693 UINT32 SGX2:1; 2694 UINT32 Reserved1:3; 2695 /// 2696 /// [Bit 5] If 1, indicates Intel SGX supports ENCLV instruction leaves 2697 /// EINCVIRTCHILD, EDECVIRTCHILD, and ESETCONTEXT. 2698 /// 2699 UINT32 ENCLV:1; 2700 /// 2701 /// [Bit 6] If 1, indicates Intel SGX supports ENCLS instruction leaves ETRACKC, 2702 /// ERDINFO, ELDBC, and ELDUC. 2703 /// 2704 UINT32 ENCLS:1; 2705 UINT32 Reserved2:25; 2706 } Bits; 2707 /// 2708 /// All bit fields as a 32-bit value 2709 /// 2710 UINT32 Uint32; 2711 } CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX; 2712 2713 /** 2714 Sub-Leaf 0 Enumeration of Intel SGX Capabilities EDX for CPUID leaf #CPUID_INTEL_SGX, 2715 sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF. 2716 **/ 2717 typedef union { 2718 /// 2719 /// Individual bit fields 2720 /// 2721 struct { 2722 /// 2723 /// [Bit 7:0] The maximum supported enclave size is 2^(EDX[7:0]) bytes 2724 /// when not in 64-bit mode. 2725 /// 2726 UINT32 MaxEnclaveSize_Not64:8; 2727 /// 2728 /// [Bit 15:8] The maximum supported enclave size is 2^(EDX[15:8]) bytes 2729 /// when operating in 64-bit mode. 2730 /// 2731 UINT32 MaxEnclaveSize_64:8; 2732 UINT32 Reserved:16; 2733 } Bits; 2734 /// 2735 /// All bit fields as a 32-bit value 2736 /// 2737 UINT32 Uint32; 2738 } CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX; 2739 2740 2741 /** 2742 Sub-Leaf 1 Enumeration of Intel SGX Capabilities. 2743 Enumerates Intel SGX capability of processor state configuration and enclave 2744 configuration in the SECS structure. 2745 2746 @param EAX CPUID_INTEL_SGX (0x12) 2747 @param ECX CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01) 2748 2749 @retval EAX Report the valid bits of SECS.ATTRIBUTES[31:0] that software can 2750 set with ECREATE. SECS.ATTRIBUTES[n] can be set to 1 using ECREATE 2751 only if EAX[n] is 1, where n < 32. 2752 @retval EBX Report the valid bits of SECS.ATTRIBUTES[63:32] that software can 2753 set with ECREATE. SECS.ATTRIBUTES[n+32] can be set to 1 using ECREATE 2754 only if EBX[n] is 1, where n < 32. 2755 @retval ECX Report the valid bits of SECS.ATTRIBUTES[95:64] that software can 2756 set with ECREATE. SECS.ATTRIBUTES[n+64] can be set to 1 using ECREATE 2757 only if ECX[n] is 1, where n < 32. 2758 @retval EDX Report the valid bits of SECS.ATTRIBUTES[127:96] that software can 2759 set with ECREATE. SECS.ATTRIBUTES[n+96] can be set to 1 using ECREATE 2760 only if EDX[n] is 1, where n < 32. 2761 2762 <b>Example usage</b> 2763 @code 2764 UINT32 Eax; 2765 UINT32 Ebx; 2766 UINT32 Ecx; 2767 UINT32 Edx; 2768 2769 AsmCpuidEx ( 2770 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF, 2771 &Eax, &Ebx, &Ecx, &Edx 2772 ); 2773 @endcode 2774 **/ 2775 #define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF 0x01 2776 2777 2778 /** 2779 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources. 2780 Enumerates available EPC resources. 2781 2782 @param EAX CPUID_INTEL_SGX (0x12) 2783 @param ECX CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02) 2784 2785 @retval EAX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX 2786 Resources is described by the type 2787 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX. 2788 @retval EBX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX 2789 Resources is described by the type 2790 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX. 2791 @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX 2792 Resources is described by the type 2793 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX. 2794 @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX 2795 Resources is described by the type 2796 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX. 2797 2798 <b>Example usage</b> 2799 @code 2800 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX Eax; 2801 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX Ebx; 2802 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX Ecx; 2803 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX Edx; 2804 2805 AsmCpuidEx ( 2806 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF, 2807 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 2808 ); 2809 @endcode 2810 **/ 2811 #define CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF 0x02 2812 2813 /** 2814 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EAX for CPUID 2815 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF. 2816 **/ 2817 typedef union { 2818 /// 2819 /// Individual bit fields 2820 /// 2821 struct { 2822 /// 2823 /// [Bit 3:0] Sub-leaf-type encoding. 2824 /// 0000b: This sub-leaf is invalid, EBX:EAX and EDX:ECX report 0. 2825 /// 0001b: This sub-leaf provides information on the Enclave Page Cache (EPC) 2826 /// in EBX:EAX and EDX:ECX. 2827 /// All other encoding are reserved. 2828 /// 2829 UINT32 SubLeafType:4; 2830 UINT32 Reserved:8; 2831 /// 2832 /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the physical address of 2833 /// the base of the EPC section. 2834 /// 2835 UINT32 LowAddressOfEpcSection:20; 2836 } Bits; 2837 /// 2838 /// All bit fields as a 32-bit value 2839 /// 2840 UINT32 Uint32; 2841 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX; 2842 2843 /** 2844 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EBX for CPUID 2845 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF. 2846 **/ 2847 typedef union { 2848 /// 2849 /// Individual bit fields 2850 /// 2851 struct { 2852 /// 2853 /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the physical address of 2854 /// the base of the EPC section. 2855 /// 2856 UINT32 HighAddressOfEpcSection:20; 2857 UINT32 Reserved:12; 2858 } Bits; 2859 /// 2860 /// All bit fields as a 32-bit value 2861 /// 2862 UINT32 Uint32; 2863 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX; 2864 2865 /** 2866 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources ECX for CPUID 2867 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF. 2868 **/ 2869 typedef union { 2870 /// 2871 /// Individual bit fields 2872 /// 2873 struct { 2874 /// 2875 /// [Bit 3:0] The EPC section encoding. 2876 /// 0000b: Not valid. 2877 /// 0001b: The EPC section is confidentiality, integrity and replay protected. 2878 /// All other encoding are reserved. 2879 /// 2880 UINT32 EpcSection:4; 2881 UINT32 Reserved:8; 2882 /// 2883 /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the size of the 2884 /// corresponding EPC section within the Processor Reserved Memory. 2885 /// 2886 UINT32 LowSizeOfEpcSection:20; 2887 } Bits; 2888 /// 2889 /// All bit fields as a 32-bit value 2890 /// 2891 UINT32 Uint32; 2892 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX; 2893 2894 /** 2895 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EDX for CPUID 2896 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF. 2897 **/ 2898 typedef union { 2899 /// 2900 /// Individual bit fields 2901 /// 2902 struct { 2903 /// 2904 /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the size of the 2905 /// corresponding EPC section within the Processor Reserved Memory. 2906 /// 2907 UINT32 HighSizeOfEpcSection:20; 2908 UINT32 Reserved:12; 2909 } Bits; 2910 /// 2911 /// All bit fields as a 32-bit value 2912 /// 2913 UINT32 Uint32; 2914 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX; 2915 2916 2917 /** 2918 CPUID Intel Processor Trace Information 2919 2920 @param EAX CPUID_INTEL_PROCESSOR_TRACE (0x14) 2921 @param ECX CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF (0x00). 2922 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01). 2923 2924 **/ 2925 #define CPUID_INTEL_PROCESSOR_TRACE 0x14 2926 2927 /** 2928 CPUID Intel Processor Trace Information Main Leaf 2929 2930 @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14) 2931 @param ECX CPUID_INTEL_PROCEDSSOR_TRACE_MAIN_LEAF (0x00) 2932 2933 @retval EAX Reports the maximum sub-leaf supported in leaf 14H. 2934 @retval EBX Returns Intel processor trace information described by the 2935 type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX. 2936 @retval ECX Returns Intel processor trace information described by the 2937 type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX. 2938 @retval EDX Reserved. 2939 2940 <b>Example usage</b> 2941 @code 2942 UINT32 Eax; 2943 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Ebx; 2944 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx; 2945 2946 AsmCpuidEx ( 2947 CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, 2948 &Eax, &Ebx.Uint32, &Ecx.Uint32, NULL 2949 ); 2950 @endcode 2951 **/ 2952 #define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF 0x00 2953 2954 /** 2955 CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE, 2956 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF. 2957 **/ 2958 typedef union { 2959 /// 2960 /// Individual bit fields 2961 /// 2962 struct { 2963 /// 2964 /// [Bit 0] If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1, 2965 /// and that IA32_RTIT_CR3_MATCH MSR can be accessed. 2966 /// 2967 UINT32 Cr3Filter:1; 2968 /// 2969 /// [Bit 1] If 1, indicates support of Configurable PSB and Cycle-Accurate 2970 /// Mode. 2971 /// 2972 UINT32 ConfigurablePsb:1; 2973 /// 2974 /// [Bit 2] If 1, indicates support of IP Filtering, TraceStop filtering, 2975 /// and preservation of Intel PT MSRs across warm reset. 2976 /// 2977 UINT32 IpTraceStopFiltering:1; 2978 /// 2979 /// [Bit 3] If 1, indicates support of MTC timing packet and suppression of 2980 /// COFI-based packets. 2981 /// 2982 UINT32 Mtc:1; 2983 /// 2984 /// [Bit 4] If 1, indicates support of PTWRITE. Writes can set 2985 /// IA32_RTIT_CTL[12] (PTWEn) and IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE 2986 /// can generate packets. 2987 /// 2988 UINT32 PTWrite:1; 2989 /// 2990 /// [Bit 5] If 1, indicates support of Power Event Trace. Writes can set 2991 /// IA32_RTIT_CTL[4] (PwrEvtEn), enabling Power Event Trace packet 2992 /// generation. 2993 /// 2994 UINT32 PowerEventTrace:1; 2995 UINT32 Reserved:26; 2996 } Bits; 2997 /// 2998 /// All bit fields as a 32-bit value 2999 /// 3000 UINT32 Uint32; 3001 } CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX; 3002 3003 /** 3004 CPUID Intel Processor Trace ECX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE, 3005 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF. 3006 **/ 3007 typedef union { 3008 /// 3009 /// Individual bit fields 3010 /// 3011 struct { 3012 /// 3013 /// [Bit 0] If 1, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence 3014 /// utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and 3015 /// IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed. 3016 /// 3017 UINT32 RTIT:1; 3018 /// 3019 /// [Bit 1] If 1, ToPA tables can hold any number of output entries, up to 3020 /// the maximum allowed by the MaskOrTableOffset field of 3021 /// IA32_RTIT_OUTPUT_MASK_PTRS. 3022 /// 3023 UINT32 ToPA:1; 3024 /// 3025 /// [Bit 2] If 1, indicates support of Single-Range Output scheme. 3026 /// 3027 UINT32 SingleRangeOutput:1; 3028 /// 3029 /// [Bit 3] If 1, indicates support of output to Trace Transport subsystem. 3030 /// 3031 UINT32 TraceTransportSubsystem:1; 3032 UINT32 Reserved:27; 3033 /// 3034 /// [Bit 31] If 1, generated packets which contain IP payloads have LIP 3035 /// values, which include the CS base component. 3036 /// 3037 UINT32 LIP:1; 3038 } Bits; 3039 /// 3040 /// All bit fields as a 32-bit value 3041 /// 3042 UINT32 Uint32; 3043 } CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX; 3044 3045 3046 /** 3047 CPUID Intel Processor Trace Information Sub-leaf 3048 3049 @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14) 3050 @param ECX CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01) 3051 3052 @retval EAX Returns Intel processor trace information described by the 3053 type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX. 3054 @retval EBX Returns Intel processor trace information described by the 3055 type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX. 3056 @retval ECX Reserved. 3057 @retval EDX Reserved. 3058 3059 <b>Example usage</b> 3060 @code 3061 UINT32 MaximumSubLeaf; 3062 UINT32 SubLeaf; 3063 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX Eax; 3064 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX Ebx; 3065 3066 AsmCpuidEx ( 3067 CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, 3068 &MaximumSubLeaf, NULL, NULL, NULL 3069 ); 3070 3071 for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) { 3072 AsmCpuidEx ( 3073 CPUID_INTEL_PROCESSOR_TRACE, SubLeaf, 3074 &Eax.Uint32, &Ebx.Uint32, NULL, NULL 3075 ); 3076 } 3077 @endcode 3078 **/ 3079 #define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF 0x01 3080 3081 /** 3082 CPUID Intel Processor Trace EAX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE, 3083 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF. 3084 **/ 3085 typedef union { 3086 /// 3087 /// Individual bit fields 3088 /// 3089 struct { 3090 /// 3091 /// [Bits 2:0] Number of configurable Address Ranges for filtering. 3092 /// 3093 UINT32 ConfigurableAddressRanges:3; 3094 UINT32 Reserved:13; 3095 /// 3096 /// [Bits 31:16] Bitmap of supported MTC period encodings 3097 /// 3098 UINT32 MtcPeriodEncodings:16; 3099 3100 } Bits; 3101 /// 3102 /// All bit fields as a 32-bit value 3103 /// 3104 UINT32 Uint32; 3105 } CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX; 3106 3107 /** 3108 CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE, 3109 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF. 3110 **/ 3111 typedef union { 3112 /// 3113 /// Individual bit fields 3114 /// 3115 struct { 3116 /// 3117 /// [Bits 15:0] Bitmap of supported Cycle Threshold value encodings. 3118 /// 3119 UINT32 CycleThresholdEncodings:16; 3120 /// 3121 /// [Bits 31:16] Bitmap of supported Configurable PSB frequency encodings. 3122 /// 3123 UINT32 PsbFrequencyEncodings:16; 3124 3125 } Bits; 3126 /// 3127 /// All bit fields as a 32-bit value 3128 /// 3129 UINT32 Uint32; 3130 } CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX; 3131 3132 3133 /** 3134 CPUID Time Stamp Counter and Nominal Core Crystal Clock Information 3135 3136 @note 3137 If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated. 3138 EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core 3139 crystal clock frequency. 3140 If ECX is 0, the nominal core crystal clock frequency is not enumerated. 3141 "TSC frequency" = "core crystal clock frequency" * EBX/EAX. 3142 The core crystal clock may differ from the reference clock, bus clock, or core 3143 clock frequencies. 3144 3145 @param EAX CPUID_TIME_STAMP_COUNTER (0x15) 3146 3147 @retval EAX An unsigned integer which is the denominator of the 3148 TSC/"core crystal clock" ratio 3149 @retval EBX An unsigned integer which is the numerator of the 3150 TSC/"core crystal clock" ratio. 3151 @retval ECX An unsigned integer which is the nominal frequency 3152 of the core crystal clock in Hz. 3153 @retval EDX Reserved. 3154 3155 <b>Example usage</b> 3156 @code 3157 UINT32 Eax; 3158 UINT32 Ebx; 3159 UINT32 Ecx; 3160 3161 AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL); 3162 @endcode 3163 **/ 3164 #define CPUID_TIME_STAMP_COUNTER 0x15 3165 3166 3167 /** 3168 CPUID Processor Frequency Information 3169 3170 @note 3171 Data is returned from this interface in accordance with the processor's 3172 specification and does not reflect actual values. Suitable use of this data 3173 includes the display of processor information in like manner to the processor 3174 brand string and for determining the appropriate range to use when displaying 3175 processor information e.g. frequency history graphs. The returned information 3176 should not be used for any other purpose as the returned information does not 3177 accurately correlate to information / counters returned by other processor 3178 interfaces. While a processor may support the Processor Frequency Information 3179 leaf, fields that return a value of zero are not supported. 3180 3181 @param EAX CPUID_TIME_STAMP_COUNTER (0x16) 3182 3183 @retval EAX Returns processor base frequency information described by the 3184 type CPUID_PROCESSOR_FREQUENCY_EAX. 3185 @retval EBX Returns maximum frequency information described by the type 3186 CPUID_PROCESSOR_FREQUENCY_EBX. 3187 @retval ECX Returns bus frequency information described by the type 3188 CPUID_PROCESSOR_FREQUENCY_ECX. 3189 @retval EDX Reserved. 3190 3191 <b>Example usage</b> 3192 @code 3193 CPUID_PROCESSOR_FREQUENCY_EAX Eax; 3194 CPUID_PROCESSOR_FREQUENCY_EBX Ebx; 3195 CPUID_PROCESSOR_FREQUENCY_ECX Ecx; 3196 3197 AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL); 3198 @endcode 3199 **/ 3200 #define CPUID_PROCESSOR_FREQUENCY 0x16 3201 3202 /** 3203 CPUID Processor Frequency Information EAX for CPUID leaf 3204 #CPUID_PROCESSOR_FREQUENCY. 3205 **/ 3206 typedef union { 3207 /// 3208 /// Individual bit fields 3209 /// 3210 struct { 3211 /// 3212 /// [Bits 15:0] Processor Base Frequency (in MHz). 3213 /// 3214 UINT32 ProcessorBaseFrequency:16; 3215 UINT32 Reserved:16; 3216 } Bits; 3217 /// 3218 /// All bit fields as a 32-bit value 3219 /// 3220 UINT32 Uint32; 3221 } CPUID_PROCESSOR_FREQUENCY_EAX; 3222 3223 /** 3224 CPUID Processor Frequency Information EBX for CPUID leaf 3225 #CPUID_PROCESSOR_FREQUENCY. 3226 **/ 3227 typedef union { 3228 /// 3229 /// Individual bit fields 3230 /// 3231 struct { 3232 /// 3233 /// [Bits 15:0] Maximum Frequency (in MHz). 3234 /// 3235 UINT32 MaximumFrequency:16; 3236 UINT32 Reserved:16; 3237 } Bits; 3238 /// 3239 /// All bit fields as a 32-bit value 3240 /// 3241 UINT32 Uint32; 3242 } CPUID_PROCESSOR_FREQUENCY_EBX; 3243 3244 /** 3245 CPUID Processor Frequency Information ECX for CPUID leaf 3246 #CPUID_PROCESSOR_FREQUENCY. 3247 **/ 3248 typedef union { 3249 /// 3250 /// Individual bit fields 3251 /// 3252 struct { 3253 /// 3254 /// [Bits 15:0] Bus (Reference) Frequency (in MHz). 3255 /// 3256 UINT32 BusFrequency:16; 3257 UINT32 Reserved:16; 3258 } Bits; 3259 /// 3260 /// All bit fields as a 32-bit value 3261 /// 3262 UINT32 Uint32; 3263 } CPUID_PROCESSOR_FREQUENCY_ECX; 3264 3265 3266 /** 3267 CPUID SoC Vendor Information 3268 3269 @param EAX CPUID_SOC_VENDOR (0x17) 3270 @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00) 3271 CPUID_SOC_VENDOR_BRAND_STRING1 (0x01) 3272 CPUID_SOC_VENDOR_BRAND_STRING1 (0x02) 3273 CPUID_SOC_VENDOR_BRAND_STRING1 (0x03) 3274 3275 @note 3276 Leaf 17H output depends on the initial value in ECX. SOC Vendor Brand String 3277 is a UTF-8 encoded string padded with trailing bytes of 00H. The complete SOC 3278 Vendor Brand String is constructed by concatenating in ascending order of 3279 EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3. 3280 3281 **/ 3282 #define CPUID_SOC_VENDOR 0x17 3283 3284 /** 3285 CPUID SoC Vendor Information 3286 3287 @param EAX CPUID_SOC_VENDOR (0x17) 3288 @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00) 3289 3290 @retval EAX MaxSOCID_Index. Reports the maximum input value of supported 3291 sub-leaf in leaf 17H. 3292 @retval EBX Returns SoC Vendor information described by the type 3293 CPUID_SOC_VENDOR_MAIN_LEAF_EBX. 3294 @retval ECX Project ID. A unique number an SOC vendor assigns to its SOC 3295 projects. 3296 @retval EDX Stepping ID. A unique number within an SOC project that an SOC 3297 vendor assigns. 3298 3299 <b>Example usage</b> 3300 @code 3301 UINT32 Eax; 3302 CPUID_SOC_VENDOR_MAIN_LEAF_EBX Ebx; 3303 UINT32 Ecx; 3304 UINT32 Edx; 3305 3306 AsmCpuidEx ( 3307 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF, 3308 &Eax, &Ebx.Uint32, &Ecx, &Edx 3309 ); 3310 @endcode 3311 **/ 3312 #define CPUID_SOC_VENDOR_MAIN_LEAF 0x00 3313 3314 /** 3315 CPUID SoC Vendor Information EBX for CPUID leaf #CPUID_SOC_VENDOR sub-leaf 3316 #CPUID_SOC_VENDOR_MAIN_LEAF. 3317 **/ 3318 typedef union { 3319 /// 3320 /// Individual bit fields 3321 /// 3322 struct { 3323 /// 3324 /// [Bits 15:0] SOC Vendor ID. 3325 /// 3326 UINT32 SocVendorId:16; 3327 /// 3328 /// [Bit 16] If 1, the SOC Vendor ID field is assigned via an industry 3329 /// standard enumeration scheme. Otherwise, the SOC Vendor ID field is 3330 /// assigned by Intel. 3331 /// 3332 UINT32 IsVendorScheme:1; 3333 UINT32 Reserved:15; 3334 } Bits; 3335 /// 3336 /// All bit fields as a 32-bit value 3337 /// 3338 UINT32 Uint32; 3339 } CPUID_SOC_VENDOR_MAIN_LEAF_EBX; 3340 3341 /** 3342 CPUID SoC Vendor Information 3343 3344 @param EAX CPUID_SOC_VENDOR (0x17) 3345 @param ECX CPUID_SOC_VENDOR_BRAND_STRING1 (0x01) 3346 3347 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type 3348 CPUID_SOC_VENDOR_BRAND_STRING_DATA. 3349 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type 3350 CPUID_SOC_VENDOR_BRAND_STRING_DATA. 3351 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type 3352 CPUID_SOC_VENDOR_BRAND_STRING_DATA. 3353 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type 3354 CPUID_SOC_VENDOR_BRAND_STRING_DATA. 3355 3356 <b>Example usage</b> 3357 @code 3358 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax; 3359 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx; 3360 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx; 3361 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx; 3362 3363 AsmCpuidEx ( 3364 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1, 3365 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 3366 ); 3367 @endcode 3368 **/ 3369 #define CPUID_SOC_VENDOR_BRAND_STRING1 0x01 3370 3371 /** 3372 CPUID SoC Vendor Brand String for CPUID leafs #CPUID_SOC_VENDOR_BRAND_STRING1, 3373 #CPUID_SOC_VENDOR_BRAND_STRING2, and #CPUID_SOC_VENDOR_BRAND_STRING3. 3374 **/ 3375 typedef union { 3376 /// 3377 /// 4 UTF-8 characters of Soc Vendor Brand String 3378 /// 3379 CHAR8 BrandString[4]; 3380 /// 3381 /// All fields as a 32-bit value 3382 /// 3383 UINT32 Uint32; 3384 } CPUID_SOC_VENDOR_BRAND_STRING_DATA; 3385 3386 /** 3387 CPUID SoC Vendor Information 3388 3389 @param EAX CPUID_SOC_VENDOR (0x17) 3390 @param ECX CPUID_SOC_VENDOR_BRAND_STRING2 (0x02) 3391 3392 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type 3393 CPUID_SOC_VENDOR_BRAND_STRING_DATA. 3394 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type 3395 CPUID_SOC_VENDOR_BRAND_STRING_DATA. 3396 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type 3397 CPUID_SOC_VENDOR_BRAND_STRING_DATA. 3398 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type 3399 CPUID_SOC_VENDOR_BRAND_STRING_DATA. 3400 3401 <b>Example usage</b> 3402 @code 3403 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax; 3404 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx; 3405 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx; 3406 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx; 3407 3408 AsmCpuidEx ( 3409 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2, 3410 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 3411 ); 3412 @endcode 3413 **/ 3414 #define CPUID_SOC_VENDOR_BRAND_STRING2 0x02 3415 3416 /** 3417 CPUID SoC Vendor Information 3418 3419 @param EAX CPUID_SOC_VENDOR (0x17) 3420 @param ECX CPUID_SOC_VENDOR_BRAND_STRING3 (0x03) 3421 3422 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type 3423 CPUID_SOC_VENDOR_BRAND_STRING_DATA. 3424 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type 3425 CPUID_SOC_VENDOR_BRAND_STRING_DATA. 3426 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type 3427 CPUID_SOC_VENDOR_BRAND_STRING_DATA. 3428 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type 3429 CPUID_SOC_VENDOR_BRAND_STRING_DATA. 3430 3431 <b>Example usage</b> 3432 @code 3433 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax; 3434 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx; 3435 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx; 3436 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx; 3437 3438 AsmCpuidEx ( 3439 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3, 3440 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 3441 ); 3442 @endcode 3443 **/ 3444 #define CPUID_SOC_VENDOR_BRAND_STRING3 0x03 3445 3446 /** 3447 CPUID Deterministic Address Translation Parameters 3448 3449 @note 3450 Each sub-leaf enumerates a different address translation structure. 3451 If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf 3452 index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX. A 3453 sub-leaf index is also invalid if EDX[4:0] returns 0. 3454 Valid sub-leaves do not need to be contiguous or in any particular order. A 3455 valid sub-leaf may be in a higher input ECX value than an invalid sub-leaf or 3456 than a valid sub-leaf of a higher or lower-level structure. 3457 * Some unified TLBs will allow a single TLB entry to satisfy data read/write 3458 and instruction fetches. Others will require separate entries (e.g., one 3459 loaded on data read/write and another loaded on an instruction fetch). 3460 Please see the Intel 64 and IA-32 Architectures Optimization Reference Manual 3461 for details of a particular product. 3462 ** Add one to the return value to get the result. 3463 3464 @param EAX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (0x18) 3465 @param ECX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF (0x00) 3466 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_SUB_LEAF (0x*) 3467 3468 **/ 3469 #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS 0x18 3470 3471 /** 3472 CPUID Deterministic Address Translation Parameters 3473 3474 @param EAX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (0x18) 3475 @param ECX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF (0x00) 3476 3477 @retval EAX Reports the maximum input value of supported sub-leaf in leaf 18H. 3478 @retval EBX Returns Deterministic Address Translation Parameters described by 3479 the type CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX. 3480 @retval ECX Number of Sets. 3481 @retval EDX Returns Deterministic Address Translation Parameters described by 3482 the type CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX. 3483 3484 <b>Example usage</b> 3485 @code 3486 UINT32 Eax; 3487 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX Ebx; 3488 UINT32 Ecx; 3489 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX Edx; 3490 3491 AsmCpuidEx ( 3492 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS, 3493 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF, 3494 &Eax, &Ebx.Uint32, &Ecx, &Edx.Uint32 3495 ); 3496 @endcode 3497 **/ 3498 #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF 0x00 3499 3500 /** 3501 CPUID Deterministic Address Translation Parameters EBX for CPUID leafs. 3502 **/ 3503 typedef union { 3504 /// 3505 /// Individual bit fields 3506 /// 3507 struct { 3508 /// 3509 /// [Bits 0] 4K page size entries supported by this structure. 3510 /// 3511 UINT32 Page4K:1; 3512 /// 3513 /// [Bits 1] 2MB page size entries supported by this structure. 3514 /// 3515 UINT32 Page2M:1; 3516 /// 3517 /// [Bits 2] 4MB page size entries supported by this structure. 3518 /// 3519 UINT32 Page4M:1; 3520 /// 3521 /// [Bits 3] 1 GB page size entries supported by this structure. 3522 /// 3523 UINT32 Page1G:1; 3524 /// 3525 /// [Bits 7:4] Reserved. 3526 /// 3527 UINT32 Reserved1:4; 3528 /// 3529 /// [Bits 10:8] Partitioning (0: Soft partitioning between the logical 3530 /// processors sharing this structure) 3531 /// 3532 UINT32 Partitioning:3; 3533 /// 3534 /// [Bits 15:11] Reserved. 3535 /// 3536 UINT32 Reserved2:5; 3537 /// 3538 /// [Bits 31:16] W = Ways of associativity. 3539 /// 3540 UINT32 Way:16; 3541 } Bits; 3542 /// 3543 /// All bit fields as a 32-bit value 3544 /// 3545 UINT32 Uint32; 3546 } CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX; 3547 3548 /** 3549 CPUID Deterministic Address Translation Parameters EDX for CPUID leafs. 3550 **/ 3551 typedef union { 3552 /// 3553 /// Individual bit fields 3554 /// 3555 struct { 3556 /// 3557 /// [Bits 4:0] Translation cache type field. 3558 /// 3559 UINT32 TranslationCacheType:5; 3560 /// 3561 /// [Bits 7:5] Translation cache level (starts at 1). 3562 /// 3563 UINT32 TranslationCacheLevel:3; 3564 /// 3565 /// [Bits 8] Fully associative structure. 3566 /// 3567 UINT32 FullyAssociative:1; 3568 /// 3569 /// [Bits 13:9] Reserved. 3570 /// 3571 UINT32 Reserved1:5; 3572 /// 3573 /// [Bits 25:14] Maximum number of addressable IDs for logical 3574 /// processors sharing this translation cache. 3575 /// 3576 UINT32 MaximumNum:12; 3577 /// 3578 /// [Bits 31:26] Reserved. 3579 /// 3580 UINT32 Reserved2:6; 3581 } Bits; 3582 /// 3583 /// All bit fields as a 32-bit value 3584 /// 3585 UINT32 Uint32; 3586 } CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX; 3587 3588 /// 3589 /// @{ Define value for CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX.TranslationCacheType 3590 /// 3591 #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_INVALID 0x00 3592 #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_DATA_TLB 0x01 3593 #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_INSTRUCTION_TLB 0x02 3594 #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_UNIFIED_TLB 0x03 3595 /// 3596 /// @} 3597 /// 3598 3599 3600 /** 3601 CPUID V2 Extended Topology Enumeration Leaf 3602 3603 @note 3604 CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first checking 3605 for the existence of Leaf 1FH and using this if available. 3606 Most of Leaf 1FH output depends on the initial value in ECX. The EDX output of leaf 3607 1FH is always valid and does not vary with input value in ECX. Output value in ECX[7:0] 3608 always equals input value in ECX[7:0]. Sub-leaf index 0 enumerates SMT level. Each 3609 subsequent higher sub-leaf index enumerates a higher-level topological entity in 3610 hierarchical order. For sub-leaves that return an invalid level-type of 0 in ECX[15:8]; 3611 EAX and EBX will return 0. If an input value n in ECX returns the invalid level-type of 3612 0 in ECX[15:8], other input values with ECX > n also return 0 in ECX[15:8]. 3613 3614 Software should use this field (EAX[4:0]) to enumerate processor topology of the system. 3615 Software must not use EBX[15:0] to enumerate processor topology of the system. This value 3616 in this field (EBX[15:0]) is only intended for display/diagnostic purposes. The actual 3617 number of logical processors available to BIOS/OS/Applications may be different from the 3618 value of EBX[15:0], depending on software and platform hardware configurations. 3619 3620 @param EAX CPUID_V2_EXTENDED_TOPOLOGY (0x1F) 3621 @param ECX Level number 3622 3623 **/ 3624 #define CPUID_V2_EXTENDED_TOPOLOGY 0x1F 3625 3626 /// 3627 /// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType 3628 /// The value of the "level type" field is not related to level numbers in 3629 /// any way, higher "level type" values do not mean higher levels. 3630 /// 3631 #define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE 0x03 3632 #define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE 0x04 3633 #define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE 0x05 3634 /// 3635 /// @} 3636 /// 3637 3638 /** 3639 CPUID Extended Function 3640 3641 @param EAX CPUID_EXTENDED_FUNCTION (0x80000000) 3642 3643 @retval EAX Maximum Input Value for Extended Function CPUID Information. 3644 @retval EBX Reserved. 3645 @retval ECX Reserved. 3646 @retval EDX Reserved. 3647 3648 <b>Example usage</b> 3649 @code 3650 UINT32 Eax; 3651 3652 AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL); 3653 @endcode 3654 **/ 3655 #define CPUID_EXTENDED_FUNCTION 0x80000000 3656 3657 3658 /** 3659 CPUID Extended Processor Signature and Feature Bits 3660 3661 @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001) 3662 3663 @retval EAX CPUID_EXTENDED_CPU_SIG. 3664 @retval EBX Reserved. 3665 @retval ECX Extended Processor Signature and Feature Bits information 3666 described by the type CPUID_EXTENDED_CPU_SIG_ECX. 3667 @retval EDX Extended Processor Signature and Feature Bits information 3668 described by the type CPUID_EXTENDED_CPU_SIG_EDX. 3669 3670 <b>Example usage</b> 3671 @code 3672 UINT32 Eax; 3673 CPUID_EXTENDED_CPU_SIG_ECX Ecx; 3674 CPUID_EXTENDED_CPU_SIG_EDX Edx; 3675 3676 AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32); 3677 @endcode 3678 **/ 3679 #define CPUID_EXTENDED_CPU_SIG 0x80000001 3680 3681 /** 3682 CPUID Extended Processor Signature and Feature Bits ECX for CPUID leaf 3683 #CPUID_EXTENDED_CPU_SIG. 3684 **/ 3685 typedef union { 3686 /// 3687 /// Individual bit fields 3688 /// 3689 struct { 3690 /// 3691 /// [Bit 0] LAHF/SAHF available in 64-bit mode. 3692 /// 3693 UINT32 LAHF_SAHF:1; 3694 UINT32 Reserved1:4; 3695 /// 3696 /// [Bit 5] LZCNT. 3697 /// 3698 UINT32 LZCNT:1; 3699 UINT32 Reserved2:2; 3700 /// 3701 /// [Bit 8] PREFETCHW. 3702 /// 3703 UINT32 PREFETCHW:1; 3704 UINT32 Reserved3:23; 3705 } Bits; 3706 /// 3707 /// All bit fields as a 32-bit value 3708 /// 3709 UINT32 Uint32; 3710 } CPUID_EXTENDED_CPU_SIG_ECX; 3711 3712 /** 3713 CPUID Extended Processor Signature and Feature Bits EDX for CPUID leaf 3714 #CPUID_EXTENDED_CPU_SIG. 3715 **/ 3716 typedef union { 3717 /// 3718 /// Individual bit fields 3719 /// 3720 struct { 3721 UINT32 Reserved1:11; 3722 /// 3723 /// [Bit 11] SYSCALL/SYSRET available in 64-bit mode. 3724 /// 3725 UINT32 SYSCALL_SYSRET:1; 3726 UINT32 Reserved2:8; 3727 /// 3728 /// [Bit 20] Execute Disable Bit available. 3729 /// 3730 UINT32 NX:1; 3731 UINT32 Reserved3:5; 3732 /// 3733 /// [Bit 26] 1-GByte pages are available if 1. 3734 /// 3735 UINT32 Page1GB:1; 3736 /// 3737 /// [Bit 27] RDTSCP and IA32_TSC_AUX are available if 1. 3738 /// 3739 UINT32 RDTSCP:1; 3740 UINT32 Reserved4:1; 3741 /// 3742 /// [Bit 29] Intel(R) 64 Architecture available if 1. 3743 /// 3744 UINT32 LM:1; 3745 UINT32 Reserved5:2; 3746 } Bits; 3747 /// 3748 /// All bit fields as a 32-bit value 3749 /// 3750 UINT32 Uint32; 3751 } CPUID_EXTENDED_CPU_SIG_EDX; 3752 3753 3754 /** 3755 CPUID Processor Brand String 3756 3757 @param EAX CPUID_BRAND_STRING1 (0x80000002) 3758 3759 @retval EAX Processor Brand String in type CPUID_BRAND_STRING_DATA. 3760 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. 3761 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. 3762 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. 3763 3764 <b>Example usage</b> 3765 @code 3766 CPUID_BRAND_STRING_DATA Eax; 3767 CPUID_BRAND_STRING_DATA Ebx; 3768 CPUID_BRAND_STRING_DATA Ecx; 3769 CPUID_BRAND_STRING_DATA Edx; 3770 3771 AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32); 3772 @endcode 3773 **/ 3774 #define CPUID_BRAND_STRING1 0x80000002 3775 3776 /** 3777 CPUID Processor Brand String for CPUID leafs #CPUID_BRAND_STRING1, 3778 #CPUID_BRAND_STRING2, and #CPUID_BRAND_STRING3. 3779 **/ 3780 typedef union { 3781 /// 3782 /// 4 ASCII characters of Processor Brand String 3783 /// 3784 CHAR8 BrandString[4]; 3785 /// 3786 /// All fields as a 32-bit value 3787 /// 3788 UINT32 Uint32; 3789 } CPUID_BRAND_STRING_DATA; 3790 3791 /** 3792 CPUID Processor Brand String 3793 3794 @param EAX CPUID_BRAND_STRING2 (0x80000003) 3795 3796 @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. 3797 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. 3798 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. 3799 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. 3800 3801 <b>Example usage</b> 3802 @code 3803 CPUID_BRAND_STRING_DATA Eax; 3804 CPUID_BRAND_STRING_DATA Ebx; 3805 CPUID_BRAND_STRING_DATA Ecx; 3806 CPUID_BRAND_STRING_DATA Edx; 3807 3808 AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32); 3809 @endcode 3810 **/ 3811 #define CPUID_BRAND_STRING2 0x80000003 3812 3813 /** 3814 CPUID Processor Brand String 3815 3816 @param EAX CPUID_BRAND_STRING3 (0x80000004) 3817 3818 @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. 3819 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. 3820 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. 3821 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. 3822 3823 <b>Example usage</b> 3824 @code 3825 CPUID_BRAND_STRING_DATA Eax; 3826 CPUID_BRAND_STRING_DATA Ebx; 3827 CPUID_BRAND_STRING_DATA Ecx; 3828 CPUID_BRAND_STRING_DATA Edx; 3829 3830 AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32); 3831 @endcode 3832 **/ 3833 #define CPUID_BRAND_STRING3 0x80000004 3834 3835 3836 /** 3837 CPUID Extended Cache information 3838 3839 @param EAX CPUID_EXTENDED_CACHE_INFO (0x80000006) 3840 3841 @retval EAX Reserved. 3842 @retval EBX Reserved. 3843 @retval ECX Extended cache information described by the type 3844 CPUID_EXTENDED_CACHE_INFO_ECX. 3845 @retval EDX Reserved. 3846 3847 <b>Example usage</b> 3848 @code 3849 CPUID_EXTENDED_CACHE_INFO_ECX Ecx; 3850 3851 AsmCpuid (CPUID_EXTENDED_CACHE_INFO, NULL, NULL, &Ecx.Uint32, NULL); 3852 @endcode 3853 **/ 3854 #define CPUID_EXTENDED_CACHE_INFO 0x80000006 3855 3856 /** 3857 CPUID Extended Cache information ECX for CPUID leaf #CPUID_EXTENDED_CACHE_INFO. 3858 **/ 3859 typedef union { 3860 /// 3861 /// Individual bit fields 3862 /// 3863 struct { 3864 /// 3865 /// [Bits 7:0] Cache line size in bytes. 3866 /// 3867 UINT32 CacheLineSize:8; 3868 UINT32 Reserved:4; 3869 /// 3870 /// [Bits 15:12] L2 Associativity field. Supported values are in the range 3871 /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED to 3872 /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL 3873 /// 3874 UINT32 L2Associativity:4; 3875 /// 3876 /// [Bits 31:16] Cache size in 1K units. 3877 /// 3878 UINT32 CacheSize:16; 3879 } Bits; 3880 /// 3881 /// All bit fields as a 32-bit value 3882 /// 3883 UINT32 Uint32; 3884 } CPUID_EXTENDED_CACHE_INFO_ECX; 3885 3886 /// 3887 /// @{ Define value for bit field CPUID_EXTENDED_CACHE_INFO_ECX.L2Associativity 3888 /// 3889 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED 0x00 3890 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DIRECT_MAPPED 0x01 3891 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_2_WAY 0x02 3892 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_4_WAY 0x04 3893 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_8_WAY 0x06 3894 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_16_WAY 0x08 3895 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_32_WAY 0x0A 3896 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_48_WAY 0x0B 3897 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_64_WAY 0x0C 3898 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_96_WAY 0x0D 3899 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_128_WAY 0x0E 3900 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL 0x0F 3901 /// 3902 /// @} 3903 /// 3904 3905 /** 3906 CPUID Extended Time Stamp Counter information 3907 3908 @param EAX CPUID_EXTENDED_TIME_STAMP_COUNTER (0x80000007) 3909 3910 @retval EAX Reserved. 3911 @retval EBX Reserved. 3912 @retval ECX Reserved. 3913 @retval EDX Extended time stamp counter (TSC) information described by the 3914 type CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX. 3915 3916 <b>Example usage</b> 3917 @code 3918 CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX Edx; 3919 3920 AsmCpuid (CPUID_EXTENDED_TIME_STAMP_COUNTER, NULL, NULL, NULL, &Edx.Uint32); 3921 @endcode 3922 **/ 3923 #define CPUID_EXTENDED_TIME_STAMP_COUNTER 0x80000007 3924 3925 /** 3926 CPUID Extended Time Stamp Counter information EDX for CPUID leaf 3927 #CPUID_EXTENDED_TIME_STAMP_COUNTER. 3928 **/ 3929 typedef union { 3930 /// 3931 /// Individual bit fields 3932 /// 3933 struct { 3934 UINT32 Reserved1:8; 3935 /// 3936 /// [Bit 8] Invariant TSC available if 1. 3937 /// 3938 UINT32 InvariantTsc:1; 3939 UINT32 Reserved2:23; 3940 } Bits; 3941 /// 3942 /// All bit fields as a 32-bit value 3943 /// 3944 UINT32 Uint32; 3945 } CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX; 3946 3947 3948 /** 3949 CPUID Linear Physical Address Size 3950 3951 @param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008) 3952 3953 @retval EAX Linear/Physical Address Size described by the type 3954 CPUID_VIR_PHY_ADDRESS_SIZE_EAX. 3955 @retval EBX Reserved. 3956 @retval ECX Reserved. 3957 @retval EDX Reserved. 3958 3959 <b>Example usage</b> 3960 @code 3961 CPUID_VIR_PHY_ADDRESS_SIZE_EAX Eax; 3962 3963 AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Eax.Uint32, NULL, NULL, NULL); 3964 @endcode 3965 **/ 3966 #define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008 3967 3968 /** 3969 CPUID Linear Physical Address Size EAX for CPUID leaf 3970 #CPUID_VIR_PHY_ADDRESS_SIZE. 3971 **/ 3972 typedef union { 3973 /// 3974 /// Individual bit fields 3975 /// 3976 struct { 3977 /// 3978 /// [Bits 7:0] Number of physical address bits. 3979 /// 3980 /// @note 3981 /// If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address 3982 /// number supported should come from this field. 3983 /// 3984 UINT32 PhysicalAddressBits:8; 3985 /// 3986 /// [Bits 15:8] Number of linear address bits. 3987 /// 3988 UINT32 LinearAddressBits:8; 3989 UINT32 Reserved:16; 3990 } Bits; 3991 /// 3992 /// All bit fields as a 32-bit value 3993 /// 3994 UINT32 Uint32; 3995 } CPUID_VIR_PHY_ADDRESS_SIZE_EAX; 3996 3997 #endif 3998