1 #pragma once
2 
3 #define IA32_APIC_BASE_MSR 		0x1B
4 
5 #define APIC_REGISTER_SPACE 		4096
6 #define APIC_REGISTER_ALIGNED_SIZE 	4
7 
8 #define PAGE_OFFSET(addr) 		((unsigned long)(addr) & (getpagesize() - 1))
9 
10 enum apic_register_offset
11 {
12 	APIC_ID		= 0x2,
13 	APIC_VER 	= 0x3,
14 	APIC_TPR 	= 0x8,
15 	APIC_APR 	= 0x9,
16 	APIC_PPR 	= 0xA,
17 	APIC_EOI 	= 0xB,
18 	APIC_RRD 	= 0xC,
19 	APIC_LDR 	= 0xD,
20 	APIC_DFR 	= 0xE,
21 	APIC_SIVR 	= 0xF,
22 	APIC_ISR	= 0x10,
23 	APIC_TMR	= 0x18,
24 	APIC_IRR 	= 0x20,
25 	APIC_ESR	= 0x28,
26 	APIC_LVT 	= 0x2F,
27 	APIC_ICR0 	= 0x30,
28 	APIC_ICR1 	= 0x31,
29 	APIC_LVTT 	= 0x32,
30 	APIC_LVTTS 	= 0x33,
31 	APIC_LVTPC 	= 0x34,
32 	APIC_LVT0 	= 0x35,
33 	APIC_LVT1 	= 0x36,
34 	APIC_LVTER 	= 0x37,
35 	APIC_TICR 	= 0x38,
36 	APIC_TCCR 	= 0x39,
37 	APIC_TDCR 	= 0x3E,
38 };
39