1# Author: Andreas Herrmann <andreas.herrmann3@amd.com>
2#
3# Copyright (C) 2009 Advanced Micro Devices, Inc.
4
5# This source file contains information based on:
6# - "41526 Rev 3.00 - July 07, 2008, AMD Family 11h Processor BKDG"
7
8# See scripts/createheader.py for the general format of this register
9# definitions.
10
11{LSMCAaddr=0x0000;load-store MCA address
12    ADDR:48
13    :16
14} # alias of MC3_ADDR
15
16{LSMCAstatus=0x0001;load-store MCA status
17    ErrorCode:16
18    :29
19    UECC:1
20    CECC:1
21    :10
22    PCC:1
23    ADDRV:1
24    MISCV:1
25    EN:1
26    UC:1
27    OVER:1
28    VAL:1
29} # alias of MC3_STATUS
30
31{TSC=0x0010;time-stamp counter
32    TSC:64
33}
34
35{APIC_BASE=0x001b;APIC base address
36    :8
37    BSC:1
38    :2
39    ApicEn:1
40    ApicBar:36
41    :16
42}
43
44{EBL_CR_POWERON=0x002a;cluster ID
45    :16
46    ClusterID:2
47    :46
48}
49
50{PATCH_LEVEL=0x008b;microcode patch level
51    PATCH_LEVEL:32
52    :32
53}
54
55{MTRRcap=0x00fe;MTRR capabilities
56    MtrrCapVCnt:8
57    MtrrCapFix:1
58    :1
59    MtrrCapWc:1
60    :53
61}
62
63{SYSENTER_CS=0x0174;SYSENTER/SYSEXIT code segment selector
64    SYSENTER_CS:16
65    :48
66}
67
68{SYSENTER_ESP=0x0175;SYSENTER/SYSEXIT stack pointer
69    SYSENTER_ESP:32
70    :32
71}
72
73{SYSENTER_EIP=0x0176;SYSENTER/SYSEXIT instruction pointer
74    SYSENTER_EIP:32
75    :32
76}
77
78{MCG_CAP=0x0179;global MC capabilities
79    Count:8
80    MCG_CTL_P:1
81    :55
82}
83
84{MCG_STAT=0x017a;global MC status
85    RIPV:1
86    EIPV:1
87    MCIP:1
88    :61
89}
90
91{MCG_CTL=0x017b;global MC control
92    DCE:1
93    ICE:1
94    BUE:1
95    LSE:1
96    NBE:1
97    FRE:1
98    :58
99}
100
101{DBG_CTL_MSR=0x01d9;debug control
102    LBR:1
103    BTF:1
104    PB0:1
105    PB1:1
106    PB2:1
107    PB3:1
108    :58
109}
110
111{BR_FROM=0x01db;last branch from IP
112    LastBranchFromIP:64
113}
114
115{BR_TO=0x01dc;last branch to IP
116    LastBranchToIP:64
117}
118
119{LastExceptionFromIP=0x01dd;last exception from IP
120    LastIntFromIP:64
121}
122
123{LastExceptionToIP=0x01de;last exception to IP
124    LastIntToIP:64
125}
126
127{MTRRphysBase0=0x0200;base of variable-size MTRR (0)
128    MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
129    :4
130    PhyBase:36
131    :16
132}
133
134{MTRRphysMask0=0x0201;mask of variable-size MTRR (0)
135    :11
136    Valid:1
137    PhysMask:36
138    :16
139}
140
141{MTRRphysBase1=0x0202;base of variable-size MTRR (1)
142    MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
143    :4
144    PhyBase:36
145    :16
146}
147
148{MTRRphysMask1=0x0203;mask of variable-size MTRR (1)
149    :11
150    Valid:1
151    PhysMask:36
152    :16
153}
154
155{MTRRphysBase2=0x0204;base of variable-size MTRR (2)
156    MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
157    :4
158    PhyBase:36
159    :16
160}
161
162{MTRRphysMask2=0x0205;mask of variable-size MTRR (2)
163    :11
164    Valid:1
165    PhysMask:36
166    :16
167}
168
169{MTRRphysBase3=0x0206;base of variable-size MTRR (3)
170    MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
171    :4
172    PhyBase:36
173    :16
174}
175
176{MTRRphysMask3=0x0207;mask of variable-size MTRR (3)
177    :11
178    Valid:1
179    PhysMask:36
180    :16
181}
182
183{MTRRphysBase4=0x0208;base of variable-size MTRR (4)
184    MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
185    :4
186    PhyBase:36
187    :16
188}
189
190{MTRRphysMask4=0x0209;mask of variable-size MTRR (4)
191    :11
192    Valid:1
193    PhysMask:36
194    :16
195}
196
197{MTRRphysBase5=0x020a;base of variable-size MTRR (5)
198    MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
199    :4
200    PhyBase:36
201    :16
202}
203
204{MTRRphysMask5=0x020b;mask of variable-size MTRR (5)
205    :11
206    Valid:1
207    PhysMask:36
208    :16
209}
210
211{MTRRphysBase6=0x020c;base of variable-size MTRR (6)
212    MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
213    :4
214    PhyBase:36
215    :16
216}
217
218{MTRRphysMask6=0x020d;mask of variable-size MTRR (6)
219    :11
220    Valid:1
221    PhysMask:36
222    :16
223}
224
225{MTRRphysBase7=0x020e;base of variable-size MTRR (7)
226    MemType:8;0=UC;1=WC;4=WT;5=WP;6=WB
227    :4
228    PhyBase:36
229    :16
230}
231
232{MTRRphysMask7=0x020f;mask of variable-size MTRR (7)
233    :11
234    Valid:1
235    PhysMask:36
236    :16
237}
238
239{MTRRfix64K_00000=0x0250;fixed range MTRR
240    0xxxxType:8
241    1xxxxType:8
242    2xxxxType:8
243    3xxxxType:8
244    4xxxxType:8
245    5xxxxType:8
246    6xxxxType:8
247    7xxxxType:8
248}
249
250{MTRRfix16K_80000=0x0258;fixed range MTRR
251    80xxxType:8
252    84xxxType:8
253    88xxxType:8
254    8CxxxType:8
255    90xxxType:8
256    94xxxType:8
257    98xxxType:8
258    9CxxxType:8
259}
260
261{MTRRfix16K_A0000=0x0259;fixed range MTRR
262    A0xxxType:8
263    A4xxxType:8
264    A8xxxType:8
265    ACxxxType:8
266    B0xxxType:8
267    B4xxxType:8
268    B8xxxType:8
269    BCxxxType:8
270}
271
272{MTRRfix4K_C0000=0x0268;fixed range MTRR
273    C0xxxType:8
274    C1xxxType:8
275    C2xxxType:8
276    C3xxxType:8
277    C4xxxType:8
278    C5xxxType:8
279    C6xxxType:8
280    C7xxxType:8
281}
282
283{MTRRfix4K_C8000=0x0269;fixed range MTRR
284    C8xxxType:8
285    C9xxxType:8
286    CAxxxType:8
287    CBxxxType:8
288    CCxxxType:8
289    CDxxxType:8
290    CExxxType:8
291    CFxxxType:8
292}
293
294{MTRRfix4K_D0000=0x026a;fixed range MTRR
295    D0xxxType:8
296    D1xxxType:8
297    D2xxxType:8
298    D3xxxType:8
299    D4xxxType:8
300    D5xxxType:8
301    D6xxxType:8
302    D7xxxType:8
303}
304
305{MTRRfix4K_D8000=0x026b;fixed range MTRR
306    D8xxxType:8
307    D9xxxType:8
308    DAxxxType:8
309    DBxxxType:8
310    DCxxxType:8
311    DDxxxType:8
312    DExxxType:8
313    DFxxxType:8
314}
315
316{MTRRfix4K_E0000=0x026c;fixed range MTRR
317    E0xxxType:8
318    E1xxxType:8
319    E2xxxType:8
320    E3xxxType:8
321    E4xxxType:8
322    E5xxxType:8
323    E6xxxType:8
324    E7xxxType:8
325}
326
327{MTRRfix4K_E8000=0x026d;fixed range MTRR
328    E8xxxType:8
329    E9xxxType:8
330    EAxxxType:8
331    EBxxxType:8
332    ECxxxType:8
333    EDxxxType:8
334    EExxxType:8
335    EFxxxType:8
336}
337
338{MTRRfix4K_F0000=0x026e;fixed range MTRR
339    F0xxxType:8
340    F1xxxType:8
341    F2xxxType:8
342    F3xxxType:8
343    F4xxxType:8
344    F5xxxType:8
345    F6xxxType:8
346    F7xxxType:8
347}
348
349{MTRRfix4K_F8000=0x026f;fixed range MTRR
350    F8xxxType:8
351    F9xxxType:8
352    FAxxxType:8
353    FBxxxType:8
354    FCxxxType:8
355    FDxxxType:8
356    FExxxType:8
357    FFxxxType:8
358}
359
360{PAT=0x0277;page attribute table
361    PA0MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
362    :5
363    PA1MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
364    :5
365    PA2MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
366    :5
367    PA3MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
368    :5
369    PA4MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
370    :5
371    PA5MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
372    :5
373    PA6MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
374    :5
375    PA7MemType:3;0=UC;1=WC;4=WT;5=WP;6=WB;7=UC-
376    :5
377}
378
379{MTRRdefType=0x02ff;MTRR default memory type
380    MemType:8
381    :2
382    MtrrDefTypeFixEn:1
383    MtrrDefTypeEn:1
384    :52
385}
386
387{MC0_CTL=0x0400;data cache MC control
388    ECCI:1
389    ECCM:1
390    DECC:1
391    DMTP:1
392    DSTP:1
393    L1TP:1
394    L2TP:1
395    :57
396}
397
398{MC0_STATUS=0x0401;data cache MC status
399    ErrorCode:16
400    ErrorCodeExt:4
401    :20
402    Scrub:1
403    :4
404    UECC:1
405    CECC:1
406    Syndrome:8
407    :2
408    PCC:1
409    AddrV:1
410    MiscV:1
411    En:1
412    UC:1
413    OVER:1
414    VAL:1
415}
416
417{MC0_ADDR=0x0402;data cache MC address
418    ADDR:48
419    :16
420}
421
422{MC0_MISC=0x0403;data cache MC miscellaneous
423    :64
424}
425
426{MC1_CTL=0x0404;instruction cache MC control
427    ECCI:1
428    ECCM:1
429    IDP:1
430    IMTP:1
431    ISTP:1
432    L1TP:1
433    L2TP:1
434    :2
435    RDDE:1
436    :54
437}
438
439{MC1_STATUS=0x0405;instruction cache MC status
440    ErrorCode:16
441    ErrorCodeExt:4
442    :25
443    UECC:1
444    CECC:1
445    :10
446    PCC:1
447    AddrV:1
448    MiscV:1
449    En:1
450    UC:1
451    OVER:1
452    VAL:1
453}
454
455{MC1_ADDR=0x0406;instruction cache MC address
456    ADDR:48
457    :16
458}
459
460{MC1_MISC=0x0407;instruction cache MC miscellaneous
461    :64
462}
463
464{MC2_CTL=0x0408;bus unit MC control
465    S_RDE_HP:1
466    S_RDE_TLB:1
467    S_RDE_ALL:1
468    S_ECC1_TLB:1
469    S_ECC1_HP:1
470    S_ECCM_TLB:1
471    S_ECCM_HP:1
472    L2T_PAR_ICDC:1
473    L2T_PAR_TLB:1
474    L2_PAR_SNP:1
475    L2_PAR_CPB:1
476    L2_PAR_SCR:1
477    L2D_ECC1_TLB:1
478    L2D_ECC1_SNP:1
479    L2D_ECC1_CPB:1
480    L2D_ECCM_TLB:1
481    L2D_ECCM_SNP:1
482    L2D_ECCM_CPB:1
483    L2T_ECC1_SCR:1
484    L2T_ECCM_SCR:1
485    :44
486}
487
488{MC2_STATUS=0x0409;bus unit MC status
489    ErrorCode:16
490    ErrorCodeExt:4
491    :25
492    UECC:1
493    CECC:1
494    :10
495    PCC:1
496    AddrV:1
497    MiscV:1
498    En:1
499    UC:1
500    OVER:1
501    VAL:1
502}
503
504{MC2_ADDR=0x040a;bus unit MC address register
505    ADDR:48
506    :16
507}
508
509{MC2_MISC=0x040b;bus unit MC miscellaneous
510    :64
511}
512
513{MC3_CTL=0x040c;load store unit MC control
514    S_RDE_L:1
515    S_RDE_S:1
516    :62
517}
518
519{MC3_STATUS=0x040d;load store unit MC status
520    ErrorCode:16
521    :29
522    UECC:1
523    CECC:1
524    :10
525    PCC:1
526    ADDRV:1
527    MISCV:1
528    EN:1
529    UC:1
530    OVER:1
531    VAL:1
532}
533
534{MC3_ADDR=0x040e;load store unit MC address
535    ADDR:48
536    :16
537}
538
539{MC3_MISC=0x040f;load store unit MC miscellaneous
540    :64
541}
542
543{MC4_CTL=0x0410;northbridge MC control
544    :2
545    CrcErr0En:1
546    :2
547    SyncPkt0En:1
548    :2
549    MstrAbrtEn:1
550    TgtAbrtEn:1
551    :1
552    AtomicRMWEn:1
553    WDTRptEn:1
554    DevErrEn:1
555    :2
556    HtProtEn:1
557    HtDataEn:1
558    :1
559    RtryHt0En:1
560    :5
561    McaUsPwDatErrEn:1
562    :1
563    TblWlkDatErrEn:1
564    :36
565}
566
567{MC4_STATUS=0x0411;northbridge MC status
568    ErrorCode:16
569    ErrorCodeExt:5
570    :11
571    ErrCpu0:1
572    ErrCpu1:1
573    :2
574    LDTLink:1
575    :4
576    SubLink:1
577    :15
578    PCC:1
579    AddrV:1
580    :1
581    En:1
582    UC:1
583    Over:1
584    Val:1
585}
586
587{MC4_ADDR=0x0412;northbridge MC address
588    NBaddr:64
589}
590
591# 0x0413 reserved (was MC4_MISC0)
592
593{EFER=0xc0000080;extended feature enable
594    SYSCALL:1
595    :7
596    LME:1
597    :1
598    LMA:1
599    NXE:1
600    SVME:1
601    LMSLE:1
602    FFXSE:1
603    :49
604}
605
606{STAR=0xc0000081;SYSCALL target address
607    Target:32
608    SysCallSel:16
609    SysRetSel:16
610}
611
612{STAR64=0xc0000082;long mode SYSCALL target address
613    LSTAR:64
614}
615
616{STARCOMPAT=0xc0000083;compat mode SYSCALL target address
617    CSTAR:64
618}
619
620{SYSCALL_FLAG_MASK=0xc0000084;SYSCALL flag mask
621    MASK:32
622    :32
623}
624
625{FS_BASE=0xc0000100;FS base
626    FS_BASE:64
627}
628
629{GS_BASE=0xc0000101;GS base
630    GS_BASE:64
631}
632
633{KernelGSbase=0xc0000102;kernel GS base
634    KernelGSBase:64
635}
636
637{TSC_AUX=0xc0000103;auxiliary time stamp counter data
638    TscAux:32
639    :32
640}
641
642{PERF_CTL0=0xc0010000;performance event select (0)
643    EventSelect:8
644    UnitMask:8
645    User:1
646    OS:1
647    Edge:1
648    PC:1
649    Int:1
650    :1
651    En:1
652    Inv:1
653    CntMask:8
654    EventSelect:4
655    :28
656}
657
658{PERF_CTL1=0xc0010001;performance event select (1)
659    EventSelect:8
660    UnitMask:8
661    User:1
662    OS:1
663    Edge:1
664    PC:1
665    Int:1
666    :1
667    En:1
668    Inv:1
669    CntMask:8
670    EventSelect:4
671    :28
672}
673
674{PERF_CTL2=0xc0010002;performance event select (2)
675    EventSelect:8
676    UnitMask:8
677    User:1
678    OS:1
679    Edge:1
680    PC:1
681    Int:1
682    :1
683    En:1
684    Inv:1
685    CntMask:8
686    EventSelect:4
687    :28
688}
689
690{PERF_CTL3=0xc0010003;performance event select (3)
691    EventSelect:8
692    UnitMask:8
693    User:1
694    OS:1
695    Edge:1
696    :1
697    Int:1
698    :1
699    En:1
700    Inv:1
701    CntMask:8
702    EventSelect:4
703    :28
704}
705
706{PERF_CTR0=0xc0010004;performance event counter (0)
707    CTR:48
708    :16
709}
710
711{PERF_CTR1=0xc0010005;performance event counter (1)
712    CTR:48
713    :16
714}
715
716{PERF_CTR2=0xc0010006;performance event counter (2)
717    CTR:48
718    :16
719}
720
721{PERF_CTR3=0xc0010007;performance event counter (3)
722    CTR:48
723    :16
724}
725
726{SYS_CFG=0xc0010010;system configuration
727    SysAckLimit:5
728    SysVicLimit:3
729    :1
730    SetDirtyEnS:1
731    SetDirtyEnO:1
732    :5
733    ChxToDirtyDis:1
734    SysUcLockEn:1
735    MtrrFixDramEn:1
736    MtrrFixDramModeEn:1
737    MtrrVarDramEn:1
738    MtrrTom2En:1
739    Tom2ForceMemTypeWB:1
740    :41
741}
742
743{HWCR=0xc0010015;hardware configuration
744    SmmLock:1
745    SlowFence:1
746    :1
747    TlbCacheDis:1
748    INVD_WBINVD:1
749    :1
750    FFDIS:1
751    DisLock:1
752    IgnneEm:1
753    :4
754    SmiSpCycDis:1
755    RsmSpCycDis:1
756    SseDis:1
757    :1
758    Wrap32Dis:1
759    McStatusWrEn:1
760    :1
761    IoCfgGpFault:1
762    :2
763    ForceUsRdWrSzPrb:1
764    TscFreqSel:1
765    :39
766}
767
768{IORR_BASE0=0xc0010016;base of variable I/O range (0)
769    :3
770    WrMem:1
771    RdMem:1
772    :7
773    PhyBase:36
774    :16
775}
776
777{IORR_MASK0=0xc0010017;mask of variable I/O range (0)
778    :11
779    Valid:1
780    PhyMask:36
781    :16
782}
783
784{IORR_BASE1=0xc0010018;base of variable I/O range (1)
785    :3
786    WrMem:1
787    RdMem:1
788    :7
789    PhyBase:36
790    :16
791}
792
793{IORR_MASK1=0xc0010019;mask of variable I/O range (1)
794    :11
795    Valid:1
796    PhyMask:36
797    :16
798}
799
800{TOP_MEM=0xc001001a;top of memory address
801    :23
802    TOM:17
803    :24
804}
805
806{TOM2=0xc001001d;second top of memory address
807    :23
808    TOM2:17
809    :24
810}
811
812{NB_CFG=0xc001001f;northbridge configuration
813    :42
814    EnaPStateSpyCyc:1
815    :2
816    DisUsSysMgtReqToNcHt:1
817    EnableCf8ExtCfg:1
818    :3
819    DisOrderRdRsp:1
820    :7
821    EnConvertToNonIsoc:1
822    :5
823}
824
825{ProcessorNameString0=0xc0010030;processor name string (0)
826    CpuNameString:64
827}
828
829{ProcessorNameString1=0xc0010031;processor name string (1)
830    CpuNameString:64
831}
832
833{ProcessorNameString2=0xc0010032;processor name string (2)
834    CpuNameString:64
835}
836
837{ProcessorNameString3=0xc0010033;processor name string (3)
838    CpuNameString:64
839}
840
841{ProcessorNameString4=0xc0010034;processor name string (4)
842    CpuNameString:64
843}
844
845{ProcessorNameString5=0xc0010035;processor name string (5)
846    CpuNameString:64
847}
848
849{MC0_CTL_MASK=0xc0010044;data cache MC control mask
850    ECCI:1
851    ECCM:1
852    DECC:1
853    DMTP:1
854    DSTP:1
855    L1TP:1
856    L2TP:1
857    :57
858}
859
860{MC1_CTL_MASK=0xc0010045;instruction cache MC control mask
861    ECCI:1
862    ECCM:1
863    IDP:1
864    IMTP:1
865    ISTP:1
866    L1TP:1
867    L2TP:1
868    :2
869    RDDE:1
870    :54
871}
872
873{MC2_CTL_MASK=0xc0010046;bus unit MC control mask
874    S_RDE_HP:1
875    S_RDE_TLB:1
876    S_RDE_ALL:1
877    S_ECC1_TLB:1
878    S_ECC1_HP:1
879    S_ECCM_TLB:1
880    S_ECCM_HP:1
881    L2T_PAR_ICDC:1
882    L2T_PAR_TLB:1
883    L2_PAR_SNP:1
884    L2_PAR_CPB:1
885    L2_PAR_SCR:1
886    L2D_ECC1_TLB:1
887    L2D_ECC1_SNP:1
888    L2D_ECC1_CPB:1
889    L2D_ECCM_TLB:1
890    L2D_ECCM_SNP:1
891    L2D_ECCM_CPB:1
892    L2T_ECC1_SCR:1
893    L2T_ECCM_SCR:1
894    :44
895}
896
897{MC3_CTL_MASK=0xc0010047;load store unit MC control mask
898    S_RDE_L:1
899    S_RDE_S:1
900    :62
901}
902
903{MC4_CTL_MASK=0xc0010048;northbridge MC control mask
904    :2
905    CrcErr0En:1
906    :2
907    SyncPkt0En:1
908    :2
909    MstrAbrtEn:1
910    TgtAbrtEn:1
911    :1
912    AtomicRMWEn:1
913    WDTRptEn:1
914    DevErrEn:1
915    :2
916    HtProtEn:1
917    HtDataEn:1
918    :1
919    RtryHt0En:1
920    :5
921    McaUsPwDatErrEn:1
922    :1
923    TblWlkDatErrEn:1
924    :36
925}
926
927{SMI_ON_IO_TRAP_0=0xc0010050;IO trap address (0)
928    SmiAddr:32
929    SmiMask:24
930    :5
931    ConfigSmi:1
932    SmiOnWrEn:1
933    SmiOnRdEn:1
934}
935
936{SMI_ON_IO_TRAP_1=0xc0010051;IO trap address (1)
937    SmiAddr:32
938    SmiMask:24
939    :5
940    ConfigSmi:1
941    SmiOnWrEn:1
942    SmiOnRdEn:1
943}
944
945{SMI_ON_IO_TRAP_2=0xc0010052;IO trap address (2)
946    SmiAddr:32
947    SmiMask:24
948    :5
949    ConfigSmi:1
950    SmiOnWrEn:1
951    SmiOnRdEn:1
952}
953
954{SMI_ON_IO_TRAP_3=0xc0010053;IO trap address (3)
955    SmiAddr:32
956    SmiMask:24
957    :5
958    ConfigSmi:1
959    SmiOnWrEn:1
960    SmiOnRdEn:1
961}
962
963{SMI_ON_IO_TRAP_CTL_STS=0xc0010054;IO trap control
964    :1
965    SmiEn_0:1
966    :1
967    SmiEn_1:1
968    :1
969    SmiEn_2:1
970    :1
971    SmiEn_3:1
972    :7
973    IoTrapEn:1
974    :48
975}
976
977{IntPendingMessage=0xc0010055;interrupt pending and CMP-halt
978    IOMsgAddr:16
979    IOMsgData:8
980    IntrPndMsgDis:1
981    IntrPndMsg:1
982    IORd:1
983    SmiOnCmpHalt:1
984    C1eOnCmpHalt:1
985    :35
986}
987
988{SmiTriggerIoCycle=0xc0010056;SMI trigger IO cycle
989    IoPortAddress:16
990    IoData:8
991    :1
992    IoCycleEn:1
993    IoRd:1
994    :37
995}
996
997{MmioConfigBase=0xc0010058;MMIO configuration base address
998    Enable:1
999    :1
1000    BusRange:4;0=1;1=2;2;4;3=8;4=16;5=32;6=64;7=128;8=256
1001    :14
1002    MmiocCfgBaseAddr:20
1003    :24
1004}
1005
1006{BISTresults=0xc0010060;BIST results register
1007    ICFT:1
1008    ICST:1
1009    ICTLB2:1
1010    BTA:1
1011    BSA:1
1012    ICD:1
1013    PDA:1
1014    BH:1
1015    ICTLB1:1
1016    ICLRU:1
1017    BSR:1
1018    DCD:1
1019    DCECC:1
1020    DCTLB1:1
1021    DCT:1
1022    DCTLB2:1
1023    DCLRU:1
1024    FPCR:1
1025    FPRR:1
1026    FPRQ:1
1027    :2
1028    ROBD:1
1029    L2D:1
1030    L2T:1
1031    WDB:1
1032    VDB:1
1033    L2LRU:1
1034    FF:1
1035    PDC:1
1036    :1
1037    MC:1
1038    :32
1039}
1040
1041{PstateCurrentLimit=0xc0010061;P-state current limit
1042    CurPstateLimit:3
1043    :1
1044    PstateMaxVal:3
1045    :57
1046}
1047
1048{PstateControl=0xc0010062;P-state control
1049    PstateCmd:3
1050    :61
1051}
1052
1053{PstateStatus=0xc0010063;P-state status
1054    CurPstate:3
1055    :61
1056}
1057
1058{Pstate0=0xc0010064;P-state 0
1059    CpuFid:6
1060    CpuDid:3
1061    CpuVid:7
1062    :16
1063    IddValue:8
1064    IddDiv:2
1065    :21
1066    PstateEn:1
1067}
1068
1069{Pstate1=0xc0010065;P-state 1
1070    CpuFid:6
1071    CpuDid:3
1072    CpuVid:7
1073    :16
1074    IddValue:8
1075    IddDiv:2
1076    :21
1077    PstateEn:1
1078}
1079
1080{Pstate2=0xc0010066;P-state 2
1081    CpuFid:6
1082    CpuDid:3
1083    CpuVid:7
1084    :16
1085    IddValue:8
1086    IddDiv:2
1087    :21
1088    PstateEn:1
1089}
1090
1091{Pstate3=0xc0010067;P-state 3
1092    CpuFid:6
1093    CpuDid:3
1094    CpuVid:7
1095    :16
1096    IddValue:8
1097    IddDiv:2
1098    :21
1099    PstateEn:1
1100}
1101
1102{Pstate4=0xc0010068;P-state 4
1103    CpuFid:6
1104    CpuDid:3
1105    CpuVid:7
1106    :16
1107    IddValue:8
1108    IddDiv:2
1109    :21
1110    PstateEn:1
1111}
1112
1113{Pstate5=0xc0010069;P-state 5
1114    CpuFid:6
1115    CpuDid:3
1116    CpuVid:7
1117    :16
1118    IddValue:8
1119    IddDiv:2
1120    :21
1121    PstateEn:1
1122}
1123
1124{Pstate6=0xc001006a;P-state 6
1125    CpuFid:6
1126    CpuDid:3
1127    CpuVid:7
1128    :16
1129    IddValue:8
1130    IddDiv:2
1131    :21
1132    PstateEn:1
1133}
1134
1135{Pstate7=0xc001006b;P-state 7
1136    CpuFid:6
1137    CpuDid:3
1138    CpuVid:7
1139    :16
1140    IddValue:8
1141    IddDiv:2
1142    :21
1143    PstateEn:1
1144}
1145
1146{COFVIDcontrol=0xc0010070;COFVID control
1147    CpuFid:6
1148    CpuDid:3
1149    CpuVid:7
1150    PstateId:3
1151    :45
1152}
1153
1154{COFVIDstatus=0xc0010071;COFVID status
1155    CurCpuFid:6
1156    CurCpuDid:3
1157    CurCpuVid:7
1158    CurPstate:3
1159    :6
1160    CurNbVid:7
1161    StartupPstate:3
1162    MaxVid:7
1163    MinVid:7
1164    MainPllOpFreqIdMax:6
1165    :1
1166    CurPstateLimit:3
1167    :5
1168}
1169
1170{SMM_BASE=0xc0010111;SMM base address
1171    SMM_BASE:32
1172    :32
1173}
1174
1175{SMMAddr=0xc0010112;SMM TSeg base address
1176    :17
1177    TSegBase:23
1178    :24
1179}
1180
1181{SMMMask=0xc0010113;SMM Tseg mask
1182    AValid:1
1183    TValid:1
1184    AClose:1
1185    TClose:1
1186    AMTypeIoWc:1
1187    TMTypeIoWc:1
1188    :2
1189    AMTypeDram:3
1190    :1
1191    TMTypeDram:3
1192    :2
1193    TSegMask:23
1194    :24
1195}
1196
1197{VM_CR=0xc0010114;virtual machine control
1198    dpd:1
1199    r_init:1
1200    dis_a20m:1
1201    Lock:1
1202    Svme_Disable:1
1203    :59
1204}
1205
1206{IGNNE=0xc0010115;IGNNE
1207    IGNNE:1
1208    :63
1209}
1210
1211# 0xc0010116 SMM_CTL, write-only
1212
1213{VM_HSAVE_PA=0xc0010117;virtual machine host save physical address
1214    VM_HSAVE_PA:64
1215}
1216
1217# 0xc0010118 SVM Lock key, write-only
1218
1219{OSVW_ID_Length=0xc0010140;OS visible work-around ID length
1220    OSVW_ID_Length:16
1221    :48
1222}
1223
1224{OsvwStatus=0xc0010141;OS visible work-around status
1225    OsvwStatusBits:64
1226}
1227
1228{DC_CFG=0xc0011022;data cache configuration register
1229    :8
1230    DIS_CLR_WBTOL2_SMC_HIT:1
1231    :4
1232    DIS_HW_PF:1
1233    :1
1234    DIS_PF_HW_FOR_SW:1
1235    :48
1236}
1237
1238{BU_CFG=0xc0011023;bus unit configuration register
1239    :48
1240    WbEnhWsbDis:1
1241    :15
1242}
1243
1244### Local Variables: ###
1245### mode:shell-script ###
1246### End: ###
1247