1 /*
2 * Copyright 2013 The Native Client Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can
4 * be found in the LICENSE file.
5 */
6
7 // DO NOT EDIT: GENERATED CODE
8
9 #include "native_client/src/trusted/validator_arm/gen/arm32_decode_baselines.h"
10 #include "native_client/src/trusted/validator_arm/inst_classes_inline.h"
11
12 namespace nacl_arm_dec {
13
14 // ADC_immediate_cccc0010101snnnnddddiiiiiiiiiiii_case_0:
15 //
16 // {NZCV: 16,
17 // None: 32,
18 // Rd: Rd(15:12),
19 // Rn: Rn(19:16),
20 // S: S(20),
21 // cond: cond(31:28),
22 // defs: {Rd, NZCV
23 // if setflags
24 // else None},
25 // fields: [cond(31:28), S(20), Rn(19:16), Rd(15:12), imm12(11:0)],
26 // imm12: imm12(11:0),
27 // imm32: ARMExpandImm(imm12),
28 // pattern: cccc0010101snnnnddddiiiiiiiiiiii,
29 // rule: ADC_immediate,
30 // safety: [(Rd(15:12)=1111 &&
31 // S(20)=1) => DECODER_ERROR,
32 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS],
33 // setflags: S(20)=1,
34 // uses: {Rn}}
35 RegisterList ADC_immediate_cccc0010101snnnnddddiiiiiiiiiiii_case_0::
defs(Instruction inst) const36 defs(Instruction inst) const {
37 UNREFERENCED_PARAMETER(inst); // To silence compiler.
38 // defs: '{inst(15:12), 16
39 // if inst(20)=1
40 // else 32}'
41 return RegisterList().
42 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
43 Add(Register(((inst.Bits() & 0x00100000) ==
44 0x00100000
45 ? 16
46 : 32)));
47 }
48
49 SafetyLevel ADC_immediate_cccc0010101snnnnddddiiiiiiiiiiii_case_0::
safety(Instruction inst) const50 safety(Instruction inst) const {
51 UNREFERENCED_PARAMETER(inst); // To silence compiler.
52
53 // (inst(15:12)=1111 &&
54 // inst(20)=1) => DECODER_ERROR
55 if ((((inst.Bits() & 0x0000F000) ==
56 0x0000F000) &&
57 ((inst.Bits() & 0x00100000) ==
58 0x00100000)))
59 return DECODER_ERROR;
60
61 // inst(15:12)=1111 => FORBIDDEN_OPERANDS
62 if ((inst.Bits() & 0x0000F000) ==
63 0x0000F000)
64 return FORBIDDEN_OPERANDS;
65
66 return MAY_BE_SAFE;
67 }
68
69
70 RegisterList ADC_immediate_cccc0010101snnnnddddiiiiiiiiiiii_case_0::
uses(Instruction inst) const71 uses(Instruction inst) const {
72 UNREFERENCED_PARAMETER(inst); // To silence compiler.
73 // uses: '{inst(19:16)}'
74 return RegisterList().
75 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
76 }
77
78 // ADC_register_cccc0000101snnnnddddiiiiitt0mmmm_case_0:
79 //
80 // {NZCV: 16,
81 // None: 32,
82 // Rd: Rd(15:12),
83 // Rm: Rm(3:0),
84 // Rn: Rn(19:16),
85 // S: S(20),
86 // cond: cond(31:28),
87 // defs: {Rd, NZCV
88 // if S
89 // else None},
90 // fields: [cond(31:28),
91 // S(20),
92 // Rn(19:16),
93 // Rd(15:12),
94 // imm5(11:7),
95 // type(6:5),
96 // Rm(3:0)],
97 // imm5: imm5(11:7),
98 // pattern: cccc0000101snnnnddddiiiiitt0mmmm,
99 // rule: ADC_register,
100 // safety: [(Rd(15:12)=1111 &&
101 // S(20)=1) => DECODER_ERROR,
102 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS],
103 // shift: DecodeImmShift(type, imm5),
104 // type: type(6:5),
105 // uses: {Rn, Rm}}
106 RegisterList ADC_register_cccc0000101snnnnddddiiiiitt0mmmm_case_0::
defs(Instruction inst) const107 defs(Instruction inst) const {
108 UNREFERENCED_PARAMETER(inst); // To silence compiler.
109 // defs: '{inst(15:12), 16
110 // if inst(20)
111 // else 32}'
112 return RegisterList().
113 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
114 Add(Register(((((inst.Bits() & 0x00100000) >> 20) != 0)
115 ? 16
116 : 32)));
117 }
118
119 SafetyLevel ADC_register_cccc0000101snnnnddddiiiiitt0mmmm_case_0::
safety(Instruction inst) const120 safety(Instruction inst) const {
121 UNREFERENCED_PARAMETER(inst); // To silence compiler.
122
123 // (inst(15:12)=1111 &&
124 // inst(20)=1) => DECODER_ERROR
125 if ((((inst.Bits() & 0x0000F000) ==
126 0x0000F000) &&
127 ((inst.Bits() & 0x00100000) ==
128 0x00100000)))
129 return DECODER_ERROR;
130
131 // inst(15:12)=1111 => FORBIDDEN_OPERANDS
132 if ((inst.Bits() & 0x0000F000) ==
133 0x0000F000)
134 return FORBIDDEN_OPERANDS;
135
136 return MAY_BE_SAFE;
137 }
138
139
140 RegisterList ADC_register_cccc0000101snnnnddddiiiiitt0mmmm_case_0::
uses(Instruction inst) const141 uses(Instruction inst) const {
142 UNREFERENCED_PARAMETER(inst); // To silence compiler.
143 // uses: '{inst(19:16), inst(3:0)}'
144 return RegisterList().
145 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
146 Add(Register((inst.Bits() & 0x0000000F)));
147 }
148
149 // ADC_register_shifted_register_cccc0000101snnnnddddssss0tt1mmmm_case_0:
150 //
151 // {NZCV: 16,
152 // None: 32,
153 // Pc: 15,
154 // Rd: Rd(15:12),
155 // Rm: Rm(3:0),
156 // Rn: Rn(19:16),
157 // Rs: Rs(11:8),
158 // S: S(20),
159 // cond: cond(31:28),
160 // defs: {Rd, NZCV
161 // if setflags
162 // else None},
163 // fields: [cond(31:28),
164 // S(20),
165 // Rn(19:16),
166 // Rd(15:12),
167 // Rs(11:8),
168 // type(6:5),
169 // Rm(3:0)],
170 // pattern: cccc0000101snnnnddddssss0tt1mmmm,
171 // rule: ADC_register_shifted_register,
172 // safety: [Pc in {Rn, Rd, Rm, Rs} => UNPREDICTABLE],
173 // setflags: S(20)=1,
174 // shift_t: DecodeRegShift(type),
175 // type: type(6:5),
176 // uses: {Rn, Rm, Rs}}
177 RegisterList ADC_register_shifted_register_cccc0000101snnnnddddssss0tt1mmmm_case_0::
defs(Instruction inst) const178 defs(Instruction inst) const {
179 UNREFERENCED_PARAMETER(inst); // To silence compiler.
180 // defs: '{inst(15:12), 16
181 // if inst(20)=1
182 // else 32}'
183 return RegisterList().
184 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
185 Add(Register(((inst.Bits() & 0x00100000) ==
186 0x00100000
187 ? 16
188 : 32)));
189 }
190
191 SafetyLevel ADC_register_shifted_register_cccc0000101snnnnddddssss0tt1mmmm_case_0::
safety(Instruction inst) const192 safety(Instruction inst) const {
193 UNREFERENCED_PARAMETER(inst); // To silence compiler.
194
195 // 15 ==
196 // inst(19:16) ||
197 // 15 ==
198 // inst(15:12) ||
199 // 15 ==
200 // inst(3:0) ||
201 // 15 ==
202 // inst(11:8) => UNPREDICTABLE
203 if ((((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
204 (((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
205 (((15) == ((inst.Bits() & 0x0000000F)))) ||
206 (((15) == (((inst.Bits() & 0x00000F00) >> 8)))))
207 return UNPREDICTABLE;
208
209 return MAY_BE_SAFE;
210 }
211
212
213 RegisterList ADC_register_shifted_register_cccc0000101snnnnddddssss0tt1mmmm_case_0::
uses(Instruction inst) const214 uses(Instruction inst) const {
215 UNREFERENCED_PARAMETER(inst); // To silence compiler.
216 // uses: '{inst(19:16), inst(3:0), inst(11:8)}'
217 return RegisterList().
218 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
219 Add(Register((inst.Bits() & 0x0000000F))).
220 Add(Register(((inst.Bits() & 0x00000F00) >> 8)));
221 }
222
223 // ADD_immediate_cccc0010100snnnnddddiiiiiiiiiiii_case_0:
224 //
225 // {NZCV: 16,
226 // None: 32,
227 // Rd: Rd(15:12),
228 // Rn: Rn(19:16),
229 // S: S(20),
230 // cond: cond(31:28),
231 // defs: {Rd, NZCV
232 // if setflags
233 // else None},
234 // fields: [cond(31:28), S(20), Rn(19:16), Rd(15:12), imm12(11:0)],
235 // imm12: imm12(11:0),
236 // imm32: ARMExpandImm(imm12),
237 // pattern: cccc0010100snnnnddddiiiiiiiiiiii,
238 // rule: ADD_immediate,
239 // safety: [(Rd(15:12)=1111 &&
240 // S(20)=1) => DECODER_ERROR,
241 // (Rn(19:16)=1111 &&
242 // S(20)=0) => DECODER_ERROR,
243 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS],
244 // setflags: S(20)=1,
245 // uses: {Rn}}
246 RegisterList ADD_immediate_cccc0010100snnnnddddiiiiiiiiiiii_case_0::
defs(Instruction inst) const247 defs(Instruction inst) const {
248 UNREFERENCED_PARAMETER(inst); // To silence compiler.
249 // defs: '{inst(15:12), 16
250 // if inst(20)=1
251 // else 32}'
252 return RegisterList().
253 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
254 Add(Register(((inst.Bits() & 0x00100000) ==
255 0x00100000
256 ? 16
257 : 32)));
258 }
259
260 SafetyLevel ADD_immediate_cccc0010100snnnnddddiiiiiiiiiiii_case_0::
safety(Instruction inst) const261 safety(Instruction inst) const {
262 UNREFERENCED_PARAMETER(inst); // To silence compiler.
263
264 // (inst(15:12)=1111 &&
265 // inst(20)=1) => DECODER_ERROR
266 if ((((inst.Bits() & 0x0000F000) ==
267 0x0000F000) &&
268 ((inst.Bits() & 0x00100000) ==
269 0x00100000)))
270 return DECODER_ERROR;
271
272 // (inst(19:16)=1111 &&
273 // inst(20)=0) => DECODER_ERROR
274 if ((((inst.Bits() & 0x000F0000) ==
275 0x000F0000) &&
276 ((inst.Bits() & 0x00100000) ==
277 0x00000000)))
278 return DECODER_ERROR;
279
280 // inst(15:12)=1111 => FORBIDDEN_OPERANDS
281 if ((inst.Bits() & 0x0000F000) ==
282 0x0000F000)
283 return FORBIDDEN_OPERANDS;
284
285 return MAY_BE_SAFE;
286 }
287
288
289 RegisterList ADD_immediate_cccc0010100snnnnddddiiiiiiiiiiii_case_0::
uses(Instruction inst) const290 uses(Instruction inst) const {
291 UNREFERENCED_PARAMETER(inst); // To silence compiler.
292 // uses: '{inst(19:16)}'
293 return RegisterList().
294 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
295 }
296
297 // ADD_register_cccc0000100snnnnddddiiiiitt0mmmm_case_0:
298 //
299 // {NZCV: 16,
300 // None: 32,
301 // Rd: Rd(15:12),
302 // Rm: Rm(3:0),
303 // Rn: Rn(19:16),
304 // S: S(20),
305 // cond: cond(31:28),
306 // defs: {Rd, NZCV
307 // if S
308 // else None},
309 // fields: [cond(31:28),
310 // S(20),
311 // Rn(19:16),
312 // Rd(15:12),
313 // imm5(11:7),
314 // type(6:5),
315 // Rm(3:0)],
316 // imm5: imm5(11:7),
317 // pattern: cccc0000100snnnnddddiiiiitt0mmmm,
318 // rule: ADD_register,
319 // safety: [(Rd(15:12)=1111 &&
320 // S(20)=1) => DECODER_ERROR,
321 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS],
322 // shift: DecodeImmShift(type, imm5),
323 // type: type(6:5),
324 // uses: {Rn, Rm}}
325 RegisterList ADD_register_cccc0000100snnnnddddiiiiitt0mmmm_case_0::
defs(Instruction inst) const326 defs(Instruction inst) const {
327 UNREFERENCED_PARAMETER(inst); // To silence compiler.
328 // defs: '{inst(15:12), 16
329 // if inst(20)
330 // else 32}'
331 return RegisterList().
332 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
333 Add(Register(((((inst.Bits() & 0x00100000) >> 20) != 0)
334 ? 16
335 : 32)));
336 }
337
338 SafetyLevel ADD_register_cccc0000100snnnnddddiiiiitt0mmmm_case_0::
safety(Instruction inst) const339 safety(Instruction inst) const {
340 UNREFERENCED_PARAMETER(inst); // To silence compiler.
341
342 // (inst(15:12)=1111 &&
343 // inst(20)=1) => DECODER_ERROR
344 if ((((inst.Bits() & 0x0000F000) ==
345 0x0000F000) &&
346 ((inst.Bits() & 0x00100000) ==
347 0x00100000)))
348 return DECODER_ERROR;
349
350 // inst(15:12)=1111 => FORBIDDEN_OPERANDS
351 if ((inst.Bits() & 0x0000F000) ==
352 0x0000F000)
353 return FORBIDDEN_OPERANDS;
354
355 return MAY_BE_SAFE;
356 }
357
358
359 RegisterList ADD_register_cccc0000100snnnnddddiiiiitt0mmmm_case_0::
uses(Instruction inst) const360 uses(Instruction inst) const {
361 UNREFERENCED_PARAMETER(inst); // To silence compiler.
362 // uses: '{inst(19:16), inst(3:0)}'
363 return RegisterList().
364 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
365 Add(Register((inst.Bits() & 0x0000000F)));
366 }
367
368 // ADD_register_shifted_register_cccc0000100snnnnddddssss0tt1mmmm_case_0:
369 //
370 // {NZCV: 16,
371 // None: 32,
372 // Pc: 15,
373 // Rd: Rd(15:12),
374 // Rm: Rm(3:0),
375 // Rn: Rn(19:16),
376 // Rs: Rs(11:8),
377 // S: S(20),
378 // cond: cond(31:28),
379 // defs: {Rd, NZCV
380 // if setflags
381 // else None},
382 // fields: [cond(31:28),
383 // S(20),
384 // Rn(19:16),
385 // Rd(15:12),
386 // Rs(11:8),
387 // type(6:5),
388 // Rm(3:0)],
389 // pattern: cccc0000100snnnnddddssss0tt1mmmm,
390 // rule: ADD_register_shifted_register,
391 // safety: [Pc in {Rn, Rd, Rm, Rs} => UNPREDICTABLE],
392 // setflags: S(20)=1,
393 // shift_t: DecodeRegShift(type),
394 // type: type(6:5),
395 // uses: {Rn, Rm, Rs}}
396 RegisterList ADD_register_shifted_register_cccc0000100snnnnddddssss0tt1mmmm_case_0::
defs(Instruction inst) const397 defs(Instruction inst) const {
398 UNREFERENCED_PARAMETER(inst); // To silence compiler.
399 // defs: '{inst(15:12), 16
400 // if inst(20)=1
401 // else 32}'
402 return RegisterList().
403 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
404 Add(Register(((inst.Bits() & 0x00100000) ==
405 0x00100000
406 ? 16
407 : 32)));
408 }
409
410 SafetyLevel ADD_register_shifted_register_cccc0000100snnnnddddssss0tt1mmmm_case_0::
safety(Instruction inst) const411 safety(Instruction inst) const {
412 UNREFERENCED_PARAMETER(inst); // To silence compiler.
413
414 // 15 ==
415 // inst(19:16) ||
416 // 15 ==
417 // inst(15:12) ||
418 // 15 ==
419 // inst(3:0) ||
420 // 15 ==
421 // inst(11:8) => UNPREDICTABLE
422 if ((((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
423 (((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
424 (((15) == ((inst.Bits() & 0x0000000F)))) ||
425 (((15) == (((inst.Bits() & 0x00000F00) >> 8)))))
426 return UNPREDICTABLE;
427
428 return MAY_BE_SAFE;
429 }
430
431
432 RegisterList ADD_register_shifted_register_cccc0000100snnnnddddssss0tt1mmmm_case_0::
uses(Instruction inst) const433 uses(Instruction inst) const {
434 UNREFERENCED_PARAMETER(inst); // To silence compiler.
435 // uses: '{inst(19:16), inst(3:0), inst(11:8)}'
436 return RegisterList().
437 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
438 Add(Register((inst.Bits() & 0x0000000F))).
439 Add(Register(((inst.Bits() & 0x00000F00) >> 8)));
440 }
441
442 // ADR_A1_cccc001010001111ddddiiiiiiiiiiii_case_0:
443 //
444 // {Pc: 15,
445 // Rd: Rd(15:12),
446 // cond: cond(31:28),
447 // defs: {Rd},
448 // fields: [cond(31:28), Rd(15:12), imm12(11:0)],
449 // imm12: imm12(11:0),
450 // imm32: ARMExpandImm(imm12),
451 // pattern: cccc001010001111ddddiiiiiiiiiiii,
452 // rule: ADR_A1,
453 // safety: [Rd(15:12)=1111 => FORBIDDEN_OPERANDS],
454 // uses: {Pc}}
455 RegisterList ADR_A1_cccc001010001111ddddiiiiiiiiiiii_case_0::
defs(Instruction inst) const456 defs(Instruction inst) const {
457 UNREFERENCED_PARAMETER(inst); // To silence compiler.
458 // defs: '{inst(15:12)}'
459 return RegisterList().
460 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
461 }
462
463 SafetyLevel ADR_A1_cccc001010001111ddddiiiiiiiiiiii_case_0::
safety(Instruction inst) const464 safety(Instruction inst) const {
465 UNREFERENCED_PARAMETER(inst); // To silence compiler.
466
467 // inst(15:12)=1111 => FORBIDDEN_OPERANDS
468 if ((inst.Bits() & 0x0000F000) ==
469 0x0000F000)
470 return FORBIDDEN_OPERANDS;
471
472 return MAY_BE_SAFE;
473 }
474
475
476 RegisterList ADR_A1_cccc001010001111ddddiiiiiiiiiiii_case_0::
uses(Instruction inst) const477 uses(Instruction inst) const {
478 UNREFERENCED_PARAMETER(inst); // To silence compiler.
479 // uses: '{15}'
480 return RegisterList().
481 Add(Register(15));
482 }
483
484 // ADR_A2_cccc001001001111ddddiiiiiiiiiiii_case_0:
485 //
486 // {Pc: 15,
487 // Rd: Rd(15:12),
488 // cond: cond(31:28),
489 // defs: {Rd},
490 // fields: [cond(31:28), Rd(15:12), imm12(11:0)],
491 // imm12: imm12(11:0),
492 // imm32: ARMExpandImm(imm12),
493 // pattern: cccc001001001111ddddiiiiiiiiiiii,
494 // rule: ADR_A2,
495 // safety: [Rd(15:12)=1111 => FORBIDDEN_OPERANDS],
496 // uses: {Pc}}
497 RegisterList ADR_A2_cccc001001001111ddddiiiiiiiiiiii_case_0::
defs(Instruction inst) const498 defs(Instruction inst) const {
499 UNREFERENCED_PARAMETER(inst); // To silence compiler.
500 // defs: '{inst(15:12)}'
501 return RegisterList().
502 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
503 }
504
505 SafetyLevel ADR_A2_cccc001001001111ddddiiiiiiiiiiii_case_0::
safety(Instruction inst) const506 safety(Instruction inst) const {
507 UNREFERENCED_PARAMETER(inst); // To silence compiler.
508
509 // inst(15:12)=1111 => FORBIDDEN_OPERANDS
510 if ((inst.Bits() & 0x0000F000) ==
511 0x0000F000)
512 return FORBIDDEN_OPERANDS;
513
514 return MAY_BE_SAFE;
515 }
516
517
518 RegisterList ADR_A2_cccc001001001111ddddiiiiiiiiiiii_case_0::
uses(Instruction inst) const519 uses(Instruction inst) const {
520 UNREFERENCED_PARAMETER(inst); // To silence compiler.
521 // uses: '{15}'
522 return RegisterList().
523 Add(Register(15));
524 }
525
526 // AND_immediate_cccc0010000snnnnddddiiiiiiiiiiii_case_0:
527 //
528 // {NZCV: 16,
529 // None: 32,
530 // Rd: Rd(15:12),
531 // Rn: Rn(19:16),
532 // S: S(20),
533 // cond: cond(31:28),
534 // defs: {Rd, NZCV
535 // if setflags
536 // else None},
537 // fields: [cond(31:28), S(20), Rn(19:16), Rd(15:12), imm12(11:0)],
538 // imm12: imm12(11:0),
539 // imm32: ARMExpandImm(imm12),
540 // pattern: cccc0010000snnnnddddiiiiiiiiiiii,
541 // rule: AND_immediate,
542 // safety: [(Rd(15:12)=1111 &&
543 // S(20)=1) => DECODER_ERROR,
544 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS],
545 // setflags: S(20)=1,
546 // uses: {Rn}}
547 RegisterList AND_immediate_cccc0010000snnnnddddiiiiiiiiiiii_case_0::
defs(Instruction inst) const548 defs(Instruction inst) const {
549 UNREFERENCED_PARAMETER(inst); // To silence compiler.
550 // defs: '{inst(15:12), 16
551 // if inst(20)=1
552 // else 32}'
553 return RegisterList().
554 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
555 Add(Register(((inst.Bits() & 0x00100000) ==
556 0x00100000
557 ? 16
558 : 32)));
559 }
560
561 SafetyLevel AND_immediate_cccc0010000snnnnddddiiiiiiiiiiii_case_0::
safety(Instruction inst) const562 safety(Instruction inst) const {
563 UNREFERENCED_PARAMETER(inst); // To silence compiler.
564
565 // (inst(15:12)=1111 &&
566 // inst(20)=1) => DECODER_ERROR
567 if ((((inst.Bits() & 0x0000F000) ==
568 0x0000F000) &&
569 ((inst.Bits() & 0x00100000) ==
570 0x00100000)))
571 return DECODER_ERROR;
572
573 // inst(15:12)=1111 => FORBIDDEN_OPERANDS
574 if ((inst.Bits() & 0x0000F000) ==
575 0x0000F000)
576 return FORBIDDEN_OPERANDS;
577
578 return MAY_BE_SAFE;
579 }
580
581
582 RegisterList AND_immediate_cccc0010000snnnnddddiiiiiiiiiiii_case_0::
uses(Instruction inst) const583 uses(Instruction inst) const {
584 UNREFERENCED_PARAMETER(inst); // To silence compiler.
585 // uses: '{inst(19:16)}'
586 return RegisterList().
587 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
588 }
589
590 // AND_register_cccc0000000snnnnddddiiiiitt0mmmm_case_0:
591 //
592 // {NZCV: 16,
593 // None: 32,
594 // Rd: Rd(15:12),
595 // Rm: Rm(3:0),
596 // Rn: Rn(19:16),
597 // S: S(20),
598 // cond: cond(31:28),
599 // defs: {Rd, NZCV
600 // if S
601 // else None},
602 // fields: [cond(31:28),
603 // S(20),
604 // Rn(19:16),
605 // Rd(15:12),
606 // imm5(11:7),
607 // type(6:5),
608 // Rm(3:0)],
609 // imm5: imm5(11:7),
610 // pattern: cccc0000000snnnnddddiiiiitt0mmmm,
611 // rule: AND_register,
612 // safety: [(Rd(15:12)=1111 &&
613 // S(20)=1) => DECODER_ERROR,
614 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS],
615 // shift: DecodeImmShift(type, imm5),
616 // type: type(6:5),
617 // uses: {Rn, Rm}}
618 RegisterList AND_register_cccc0000000snnnnddddiiiiitt0mmmm_case_0::
defs(Instruction inst) const619 defs(Instruction inst) const {
620 UNREFERENCED_PARAMETER(inst); // To silence compiler.
621 // defs: '{inst(15:12), 16
622 // if inst(20)
623 // else 32}'
624 return RegisterList().
625 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
626 Add(Register(((((inst.Bits() & 0x00100000) >> 20) != 0)
627 ? 16
628 : 32)));
629 }
630
631 SafetyLevel AND_register_cccc0000000snnnnddddiiiiitt0mmmm_case_0::
safety(Instruction inst) const632 safety(Instruction inst) const {
633 UNREFERENCED_PARAMETER(inst); // To silence compiler.
634
635 // (inst(15:12)=1111 &&
636 // inst(20)=1) => DECODER_ERROR
637 if ((((inst.Bits() & 0x0000F000) ==
638 0x0000F000) &&
639 ((inst.Bits() & 0x00100000) ==
640 0x00100000)))
641 return DECODER_ERROR;
642
643 // inst(15:12)=1111 => FORBIDDEN_OPERANDS
644 if ((inst.Bits() & 0x0000F000) ==
645 0x0000F000)
646 return FORBIDDEN_OPERANDS;
647
648 return MAY_BE_SAFE;
649 }
650
651
652 RegisterList AND_register_cccc0000000snnnnddddiiiiitt0mmmm_case_0::
uses(Instruction inst) const653 uses(Instruction inst) const {
654 UNREFERENCED_PARAMETER(inst); // To silence compiler.
655 // uses: '{inst(19:16), inst(3:0)}'
656 return RegisterList().
657 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
658 Add(Register((inst.Bits() & 0x0000000F)));
659 }
660
661 // AND_register_shifted_register_cccc0000000snnnnddddssss0tt1mmmm_case_0:
662 //
663 // {NZCV: 16,
664 // None: 32,
665 // Pc: 15,
666 // Rd: Rd(15:12),
667 // Rm: Rm(3:0),
668 // Rn: Rn(19:16),
669 // Rs: Rs(11:8),
670 // S: S(20),
671 // cond: cond(31:28),
672 // defs: {Rd, NZCV
673 // if setflags
674 // else None},
675 // fields: [cond(31:28),
676 // S(20),
677 // Rn(19:16),
678 // Rd(15:12),
679 // Rs(11:8),
680 // type(6:5),
681 // Rm(3:0)],
682 // pattern: cccc0000000snnnnddddssss0tt1mmmm,
683 // rule: AND_register_shifted_register,
684 // safety: [Pc in {Rn, Rd, Rm, Rs} => UNPREDICTABLE],
685 // setflags: S(20)=1,
686 // shift_t: DecodeRegShift(type),
687 // type: type(6:5),
688 // uses: {Rn, Rm, Rs}}
689 RegisterList AND_register_shifted_register_cccc0000000snnnnddddssss0tt1mmmm_case_0::
defs(Instruction inst) const690 defs(Instruction inst) const {
691 UNREFERENCED_PARAMETER(inst); // To silence compiler.
692 // defs: '{inst(15:12), 16
693 // if inst(20)=1
694 // else 32}'
695 return RegisterList().
696 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
697 Add(Register(((inst.Bits() & 0x00100000) ==
698 0x00100000
699 ? 16
700 : 32)));
701 }
702
703 SafetyLevel AND_register_shifted_register_cccc0000000snnnnddddssss0tt1mmmm_case_0::
safety(Instruction inst) const704 safety(Instruction inst) const {
705 UNREFERENCED_PARAMETER(inst); // To silence compiler.
706
707 // 15 ==
708 // inst(19:16) ||
709 // 15 ==
710 // inst(15:12) ||
711 // 15 ==
712 // inst(3:0) ||
713 // 15 ==
714 // inst(11:8) => UNPREDICTABLE
715 if ((((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
716 (((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
717 (((15) == ((inst.Bits() & 0x0000000F)))) ||
718 (((15) == (((inst.Bits() & 0x00000F00) >> 8)))))
719 return UNPREDICTABLE;
720
721 return MAY_BE_SAFE;
722 }
723
724
725 RegisterList AND_register_shifted_register_cccc0000000snnnnddddssss0tt1mmmm_case_0::
uses(Instruction inst) const726 uses(Instruction inst) const {
727 UNREFERENCED_PARAMETER(inst); // To silence compiler.
728 // uses: '{inst(19:16), inst(3:0), inst(11:8)}'
729 return RegisterList().
730 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
731 Add(Register((inst.Bits() & 0x0000000F))).
732 Add(Register(((inst.Bits() & 0x00000F00) >> 8)));
733 }
734
735 // ASR_immediate_cccc0001101s0000ddddiiiii100mmmm_case_0:
736 //
737 // {NZCV: 16,
738 // None: 32,
739 // Rd: Rd(15:12),
740 // Rm: Rm(3:0),
741 // S: S(20),
742 // cond: cond(31:28),
743 // defs: {Rd, NZCV
744 // if S
745 // else None},
746 // fields: [cond(31:28),
747 // S(20),
748 // Rd(15:12),
749 // imm5(11:7),
750 // type(6:5),
751 // Rm(3:0)],
752 // imm5: imm5(11:7),
753 // pattern: cccc0001101s0000ddddiiiii100mmmm,
754 // rule: ASR_immediate,
755 // safety: [(Rd(15:12)=1111 &&
756 // S(20)=1) => DECODER_ERROR,
757 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS],
758 // shift: DecodeImmShift(type, imm5),
759 // type: type(6:5),
760 // uses: {Rm}}
761 RegisterList ASR_immediate_cccc0001101s0000ddddiiiii100mmmm_case_0::
defs(Instruction inst) const762 defs(Instruction inst) const {
763 UNREFERENCED_PARAMETER(inst); // To silence compiler.
764 // defs: '{inst(15:12), 16
765 // if inst(20)
766 // else 32}'
767 return RegisterList().
768 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
769 Add(Register(((((inst.Bits() & 0x00100000) >> 20) != 0)
770 ? 16
771 : 32)));
772 }
773
774 SafetyLevel ASR_immediate_cccc0001101s0000ddddiiiii100mmmm_case_0::
safety(Instruction inst) const775 safety(Instruction inst) const {
776 UNREFERENCED_PARAMETER(inst); // To silence compiler.
777
778 // (inst(15:12)=1111 &&
779 // inst(20)=1) => DECODER_ERROR
780 if ((((inst.Bits() & 0x0000F000) ==
781 0x0000F000) &&
782 ((inst.Bits() & 0x00100000) ==
783 0x00100000)))
784 return DECODER_ERROR;
785
786 // inst(15:12)=1111 => FORBIDDEN_OPERANDS
787 if ((inst.Bits() & 0x0000F000) ==
788 0x0000F000)
789 return FORBIDDEN_OPERANDS;
790
791 return MAY_BE_SAFE;
792 }
793
794
795 RegisterList ASR_immediate_cccc0001101s0000ddddiiiii100mmmm_case_0::
uses(Instruction inst) const796 uses(Instruction inst) const {
797 UNREFERENCED_PARAMETER(inst); // To silence compiler.
798 // uses: '{inst(3:0)}'
799 return RegisterList().
800 Add(Register((inst.Bits() & 0x0000000F)));
801 }
802
803 // ASR_register_cccc0001101s0000ddddmmmm0101nnnn_case_0:
804 //
805 // {NZCV: 16,
806 // None: 32,
807 // Pc: 15,
808 // Rd: Rd(15:12),
809 // Rm: Rm(11:8),
810 // Rn: Rn(3:0),
811 // S: S(20),
812 // cond: cond(31:28),
813 // defs: {Rd, NZCV
814 // if setflags
815 // else None},
816 // fields: [cond(31:28), S(20), Rd(15:12), Rm(11:8), Rn(3:0)],
817 // pattern: cccc0001101s0000ddddmmmm0101nnnn,
818 // rule: ASR_register,
819 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE],
820 // setflags: S(20)=1,
821 // uses: {Rn, Rm}}
822 RegisterList ASR_register_cccc0001101s0000ddddmmmm0101nnnn_case_0::
defs(Instruction inst) const823 defs(Instruction inst) const {
824 UNREFERENCED_PARAMETER(inst); // To silence compiler.
825 // defs: '{inst(15:12), 16
826 // if inst(20)=1
827 // else 32}'
828 return RegisterList().
829 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
830 Add(Register(((inst.Bits() & 0x00100000) ==
831 0x00100000
832 ? 16
833 : 32)));
834 }
835
836 SafetyLevel ASR_register_cccc0001101s0000ddddmmmm0101nnnn_case_0::
safety(Instruction inst) const837 safety(Instruction inst) const {
838 UNREFERENCED_PARAMETER(inst); // To silence compiler.
839
840 // 15 ==
841 // inst(15:12) ||
842 // 15 ==
843 // inst(3:0) ||
844 // 15 ==
845 // inst(11:8) => UNPREDICTABLE
846 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
847 (((15) == ((inst.Bits() & 0x0000000F)))) ||
848 (((15) == (((inst.Bits() & 0x00000F00) >> 8)))))
849 return UNPREDICTABLE;
850
851 return MAY_BE_SAFE;
852 }
853
854
855 RegisterList ASR_register_cccc0001101s0000ddddmmmm0101nnnn_case_0::
uses(Instruction inst) const856 uses(Instruction inst) const {
857 UNREFERENCED_PARAMETER(inst); // To silence compiler.
858 // uses: '{inst(3:0), inst(11:8)}'
859 return RegisterList().
860 Add(Register((inst.Bits() & 0x0000000F))).
861 Add(Register(((inst.Bits() & 0x00000F00) >> 8)));
862 }
863
864 // BFC_cccc0111110mmmmmddddlllll0011111_case_0:
865 //
866 // {Pc: 15,
867 // Rd: Rd(15:12),
868 // arch: v6T2,
869 // cond: cond(31:28),
870 // defs: {Rd},
871 // fields: [cond(31:28), msb(20:16), Rd(15:12), lsb(11:7)],
872 // lsb: lsb(11:7),
873 // msb: msb(20:16),
874 // pattern: cccc0111110mmmmmddddlllll0011111,
875 // rule: BFC,
876 // safety: [Rd ==
877 // Pc => UNPREDICTABLE,
878 // msb <
879 // lsb => UNPREDICTABLE],
880 // uses: {Rd}}
881 RegisterList BFC_cccc0111110mmmmmddddlllll0011111_case_0::
defs(Instruction inst) const882 defs(Instruction inst) const {
883 UNREFERENCED_PARAMETER(inst); // To silence compiler.
884 // defs: '{inst(15:12)}'
885 return RegisterList().
886 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
887 }
888
889 SafetyLevel BFC_cccc0111110mmmmmddddlllll0011111_case_0::
safety(Instruction inst) const890 safety(Instruction inst) const {
891 UNREFERENCED_PARAMETER(inst); // To silence compiler.
892
893 // 15 ==
894 // inst(15:12) => UNPREDICTABLE
895 if (((((inst.Bits() & 0x0000F000) >> 12)) == (15)))
896 return UNPREDICTABLE;
897
898 // inst(20:16) <
899 // inst(11:7) => UNPREDICTABLE
900 if (((((inst.Bits() & 0x001F0000) >> 16)) < (((inst.Bits() & 0x00000F80) >> 7))))
901 return UNPREDICTABLE;
902
903 return MAY_BE_SAFE;
904 }
905
906
907 RegisterList BFC_cccc0111110mmmmmddddlllll0011111_case_0::
uses(Instruction inst) const908 uses(Instruction inst) const {
909 UNREFERENCED_PARAMETER(inst); // To silence compiler.
910 // uses: '{inst(15:12)}'
911 return RegisterList().
912 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
913 }
914
915 // BFI_cccc0111110mmmmmddddlllll001nnnn_case_0:
916 //
917 // {Pc: 15,
918 // Rd: Rd(15:12),
919 // Rn: Rn(3:0),
920 // arch: v6T2,
921 // cond: cond(31:28),
922 // defs: {Rd},
923 // fields: [cond(31:28), msb(20:16), Rd(15:12), lsb(11:7), Rn(3:0)],
924 // lsb: lsb(11:7),
925 // msb: msb(20:16),
926 // pattern: cccc0111110mmmmmddddlllll001nnnn,
927 // rule: BFI,
928 // safety: [Rn ==
929 // Pc => DECODER_ERROR,
930 // Rd ==
931 // Pc => UNPREDICTABLE,
932 // msb <
933 // lsb => UNPREDICTABLE],
934 // uses: {Rn, Rd}}
935 RegisterList BFI_cccc0111110mmmmmddddlllll001nnnn_case_0::
defs(Instruction inst) const936 defs(Instruction inst) const {
937 UNREFERENCED_PARAMETER(inst); // To silence compiler.
938 // defs: '{inst(15:12)}'
939 return RegisterList().
940 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
941 }
942
943 SafetyLevel BFI_cccc0111110mmmmmddddlllll001nnnn_case_0::
safety(Instruction inst) const944 safety(Instruction inst) const {
945 UNREFERENCED_PARAMETER(inst); // To silence compiler.
946
947 // 15 ==
948 // inst(3:0) => DECODER_ERROR
949 if ((((inst.Bits() & 0x0000000F)) == (15)))
950 return DECODER_ERROR;
951
952 // 15 ==
953 // inst(15:12) => UNPREDICTABLE
954 if (((((inst.Bits() & 0x0000F000) >> 12)) == (15)))
955 return UNPREDICTABLE;
956
957 // inst(20:16) <
958 // inst(11:7) => UNPREDICTABLE
959 if (((((inst.Bits() & 0x001F0000) >> 16)) < (((inst.Bits() & 0x00000F80) >> 7))))
960 return UNPREDICTABLE;
961
962 return MAY_BE_SAFE;
963 }
964
965
966 RegisterList BFI_cccc0111110mmmmmddddlllll001nnnn_case_0::
uses(Instruction inst) const967 uses(Instruction inst) const {
968 UNREFERENCED_PARAMETER(inst); // To silence compiler.
969 // uses: '{inst(3:0), inst(15:12)}'
970 return RegisterList().
971 Add(Register((inst.Bits() & 0x0000000F))).
972 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
973 }
974
975 // BIC_immediate_cccc0011110snnnnddddiiiiiiiiiiii_case_0:
976 //
977 // {NZCV: 16,
978 // None: 32,
979 // Rd: Rd(15:12),
980 // Rn: Rn(19:16),
981 // S: S(20),
982 // clears_bits: (imm32 &&
983 // clears_mask()) ==
984 // clears_mask(),
985 // cond: cond(31:28),
986 // defs: {Rd, NZCV
987 // if setflags
988 // else None},
989 // fields: [cond(31:28), S(20), Rn(19:16), Rd(15:12), imm12(11:0)],
990 // imm12: imm12(11:0),
991 // imm32: ARMExpandImm(imm12),
992 // pattern: cccc0011110snnnnddddiiiiiiiiiiii,
993 // rule: BIC_immediate,
994 // safety: [(Rd(15:12)=1111 &&
995 // S(20)=1) => DECODER_ERROR,
996 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS],
997 // setflags: S(20)=1,
998 // uses: {Rn}}
999 bool BIC_immediate_cccc0011110snnnnddddiiiiiiiiiiii_case_0::
clears_bits(Instruction inst,uint32_t clears_mask) const1000 clears_bits(Instruction inst, uint32_t clears_mask) const {
1001 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1002 // clears_bits: '(ARMExpandImm(inst(11:0)) &&
1003 // clears_mask()) ==
1004 // clears_mask()'
1005 return ((((nacl_arm_dec::ARMExpandImm((inst.Bits() & 0x00000FFF)) & clears_mask))) == (clears_mask));
1006 }
1007
1008 RegisterList BIC_immediate_cccc0011110snnnnddddiiiiiiiiiiii_case_0::
defs(Instruction inst) const1009 defs(Instruction inst) const {
1010 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1011 // defs: '{inst(15:12), 16
1012 // if inst(20)=1
1013 // else 32}'
1014 return RegisterList().
1015 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
1016 Add(Register(((inst.Bits() & 0x00100000) ==
1017 0x00100000
1018 ? 16
1019 : 32)));
1020 }
1021
1022 SafetyLevel BIC_immediate_cccc0011110snnnnddddiiiiiiiiiiii_case_0::
safety(Instruction inst) const1023 safety(Instruction inst) const {
1024 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1025
1026 // (inst(15:12)=1111 &&
1027 // inst(20)=1) => DECODER_ERROR
1028 if ((((inst.Bits() & 0x0000F000) ==
1029 0x0000F000) &&
1030 ((inst.Bits() & 0x00100000) ==
1031 0x00100000)))
1032 return DECODER_ERROR;
1033
1034 // inst(15:12)=1111 => FORBIDDEN_OPERANDS
1035 if ((inst.Bits() & 0x0000F000) ==
1036 0x0000F000)
1037 return FORBIDDEN_OPERANDS;
1038
1039 return MAY_BE_SAFE;
1040 }
1041
1042
1043 RegisterList BIC_immediate_cccc0011110snnnnddddiiiiiiiiiiii_case_0::
uses(Instruction inst) const1044 uses(Instruction inst) const {
1045 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1046 // uses: '{inst(19:16)}'
1047 return RegisterList().
1048 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
1049 }
1050
1051 // BIC_register_cccc0001110snnnnddddiiiiitt0mmmm_case_0:
1052 //
1053 // {NZCV: 16,
1054 // None: 32,
1055 // Rd: Rd(15:12),
1056 // Rm: Rm(3:0),
1057 // Rn: Rn(19:16),
1058 // S: S(20),
1059 // cond: cond(31:28),
1060 // defs: {Rd, NZCV
1061 // if S
1062 // else None},
1063 // fields: [cond(31:28),
1064 // S(20),
1065 // Rn(19:16),
1066 // Rd(15:12),
1067 // imm5(11:7),
1068 // type(6:5),
1069 // Rm(3:0)],
1070 // imm5: imm5(11:7),
1071 // pattern: cccc0001110snnnnddddiiiiitt0mmmm,
1072 // rule: BIC_register,
1073 // safety: [(Rd(15:12)=1111 &&
1074 // S(20)=1) => DECODER_ERROR,
1075 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS],
1076 // shift: DecodeImmShift(type, imm5),
1077 // type: type(6:5),
1078 // uses: {Rn, Rm}}
1079 RegisterList BIC_register_cccc0001110snnnnddddiiiiitt0mmmm_case_0::
defs(Instruction inst) const1080 defs(Instruction inst) const {
1081 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1082 // defs: '{inst(15:12), 16
1083 // if inst(20)
1084 // else 32}'
1085 return RegisterList().
1086 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
1087 Add(Register(((((inst.Bits() & 0x00100000) >> 20) != 0)
1088 ? 16
1089 : 32)));
1090 }
1091
1092 SafetyLevel BIC_register_cccc0001110snnnnddddiiiiitt0mmmm_case_0::
safety(Instruction inst) const1093 safety(Instruction inst) const {
1094 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1095
1096 // (inst(15:12)=1111 &&
1097 // inst(20)=1) => DECODER_ERROR
1098 if ((((inst.Bits() & 0x0000F000) ==
1099 0x0000F000) &&
1100 ((inst.Bits() & 0x00100000) ==
1101 0x00100000)))
1102 return DECODER_ERROR;
1103
1104 // inst(15:12)=1111 => FORBIDDEN_OPERANDS
1105 if ((inst.Bits() & 0x0000F000) ==
1106 0x0000F000)
1107 return FORBIDDEN_OPERANDS;
1108
1109 return MAY_BE_SAFE;
1110 }
1111
1112
1113 RegisterList BIC_register_cccc0001110snnnnddddiiiiitt0mmmm_case_0::
uses(Instruction inst) const1114 uses(Instruction inst) const {
1115 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1116 // uses: '{inst(19:16), inst(3:0)}'
1117 return RegisterList().
1118 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
1119 Add(Register((inst.Bits() & 0x0000000F)));
1120 }
1121
1122 // BIC_register_shifted_register_cccc0001110snnnnddddssss0tt1mmmm_case_0:
1123 //
1124 // {NZCV: 16,
1125 // None: 32,
1126 // Pc: 15,
1127 // Rd: Rd(15:12),
1128 // Rm: Rm(3:0),
1129 // Rn: Rn(19:16),
1130 // Rs: Rs(11:8),
1131 // S: S(20),
1132 // cond: cond(31:28),
1133 // defs: {Rd, NZCV
1134 // if setflags
1135 // else None},
1136 // fields: [cond(31:28),
1137 // S(20),
1138 // Rn(19:16),
1139 // Rd(15:12),
1140 // Rs(11:8),
1141 // type(6:5),
1142 // Rm(3:0)],
1143 // pattern: cccc0001110snnnnddddssss0tt1mmmm,
1144 // rule: BIC_register_shifted_register,
1145 // safety: [Pc in {Rn, Rd, Rm, Rs} => UNPREDICTABLE],
1146 // setflags: S(20)=1,
1147 // shift_t: DecodeRegShift(type),
1148 // type: type(6:5),
1149 // uses: {Rn, Rm, Rs}}
1150 RegisterList BIC_register_shifted_register_cccc0001110snnnnddddssss0tt1mmmm_case_0::
defs(Instruction inst) const1151 defs(Instruction inst) const {
1152 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1153 // defs: '{inst(15:12), 16
1154 // if inst(20)=1
1155 // else 32}'
1156 return RegisterList().
1157 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
1158 Add(Register(((inst.Bits() & 0x00100000) ==
1159 0x00100000
1160 ? 16
1161 : 32)));
1162 }
1163
1164 SafetyLevel BIC_register_shifted_register_cccc0001110snnnnddddssss0tt1mmmm_case_0::
safety(Instruction inst) const1165 safety(Instruction inst) const {
1166 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1167
1168 // 15 ==
1169 // inst(19:16) ||
1170 // 15 ==
1171 // inst(15:12) ||
1172 // 15 ==
1173 // inst(3:0) ||
1174 // 15 ==
1175 // inst(11:8) => UNPREDICTABLE
1176 if ((((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
1177 (((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
1178 (((15) == ((inst.Bits() & 0x0000000F)))) ||
1179 (((15) == (((inst.Bits() & 0x00000F00) >> 8)))))
1180 return UNPREDICTABLE;
1181
1182 return MAY_BE_SAFE;
1183 }
1184
1185
1186 RegisterList BIC_register_shifted_register_cccc0001110snnnnddddssss0tt1mmmm_case_0::
uses(Instruction inst) const1187 uses(Instruction inst) const {
1188 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1189 // uses: '{inst(19:16), inst(3:0), inst(11:8)}'
1190 return RegisterList().
1191 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
1192 Add(Register((inst.Bits() & 0x0000000F))).
1193 Add(Register(((inst.Bits() & 0x00000F00) >> 8)));
1194 }
1195
1196 // BKPT_cccc00010010iiiiiiiiiiii0111iiii_case_0:
1197 //
1198 // {arch: v5T,
1199 // cond: cond(31:28),
1200 // defs: {},
1201 // fields: [cond(31:28), imm12(19:8), imm4(3:0)],
1202 // imm12: imm12(19:8),
1203 // imm32: ZeroExtend(imm12:imm4, 32),
1204 // imm4: imm4(3:0),
1205 // inst: inst,
1206 // is_literal_pool_head: inst ==
1207 // LiteralPoolHeadConstant(),
1208 // pattern: cccc00010010iiiiiiiiiiii0111iiii,
1209 // rule: BKPT,
1210 // safety: [cond(31:28)=~1110 => UNPREDICTABLE,
1211 // not IsBreakPointAndConstantPoolHead(inst) => FORBIDDEN_OPERANDS],
1212 // uses: {},
1213 // violations: [implied by 'is_literal_pool_head']}
1214 RegisterList BKPT_cccc00010010iiiiiiiiiiii0111iiii_case_0::
defs(Instruction inst) const1215 defs(Instruction inst) const {
1216 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1217 // defs: '{}'
1218 return RegisterList();
1219 }
1220
1221 bool BKPT_cccc00010010iiiiiiiiiiii0111iiii_case_0::
is_literal_pool_head(Instruction inst) const1222 is_literal_pool_head(Instruction inst) const {
1223 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1224 // is_literal_pool_head: 'LiteralPoolHeadConstant() ==
1225 // inst'
1226 return ((inst.Bits()) == (nacl_arm_dec::LiteralPoolHeadConstant()));
1227 }
1228
1229 SafetyLevel BKPT_cccc00010010iiiiiiiiiiii0111iiii_case_0::
safety(Instruction inst) const1230 safety(Instruction inst) const {
1231 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1232
1233 // inst(31:28)=~1110 => UNPREDICTABLE
1234 if ((inst.Bits() & 0xF0000000) !=
1235 0xE0000000)
1236 return UNPREDICTABLE;
1237
1238 // not IsBreakPointAndConstantPoolHead(inst) => FORBIDDEN_OPERANDS
1239 if (!(nacl_arm_dec::IsBreakPointAndConstantPoolHead(inst.Bits())))
1240 return FORBIDDEN_OPERANDS;
1241
1242 return MAY_BE_SAFE;
1243 }
1244
1245
1246 RegisterList BKPT_cccc00010010iiiiiiiiiiii0111iiii_case_0::
uses(Instruction inst) const1247 uses(Instruction inst) const {
1248 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1249 // uses: '{}'
1250 return RegisterList();
1251 }
1252
1253 ViolationSet BKPT_cccc00010010iiiiiiiiiiii0111iiii_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const1254 get_violations(const nacl_arm_val::DecodedInstruction& first,
1255 const nacl_arm_val::DecodedInstruction& second,
1256 const nacl_arm_val::SfiValidator& sfi,
1257 nacl_arm_val::AddressSet* branches,
1258 nacl_arm_val::AddressSet* critical,
1259 uint32_t* next_inst_addr) const {
1260 ViolationSet violations = ClassDecoder::get_violations(
1261 first, second, sfi, branches, critical, next_inst_addr);
1262
1263 // If a pool head, mark address appropriately and then skip over
1264 // the constant bundle.
1265 validate_literal_pool_head(second, sfi, critical, next_inst_addr);
1266
1267 return violations;
1268 }
1269
1270
1271 // BLX_immediate_1111101hiiiiiiiiiiiiiiiiiiiiiiii_case_0:
1272 //
1273 // {arch: v5,
1274 // defs: {},
1275 // pattern: 1111101hiiiiiiiiiiiiiiiiiiiiiiii,
1276 // rule: BLX_immediate,
1277 // safety: [true => FORBIDDEN],
1278 // true: true,
1279 // uses: {}}
1280 RegisterList BLX_immediate_1111101hiiiiiiiiiiiiiiiiiiiiiiii_case_0::
defs(Instruction inst) const1281 defs(Instruction inst) const {
1282 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1283 // defs: '{}'
1284 return RegisterList();
1285 }
1286
1287 SafetyLevel BLX_immediate_1111101hiiiiiiiiiiiiiiiiiiiiiiii_case_0::
safety(Instruction inst) const1288 safety(Instruction inst) const {
1289 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1290
1291 // true => FORBIDDEN
1292 if (true)
1293 return FORBIDDEN;
1294
1295 return MAY_BE_SAFE;
1296 }
1297
1298
1299 RegisterList BLX_immediate_1111101hiiiiiiiiiiiiiiiiiiiiiiii_case_0::
uses(Instruction inst) const1300 uses(Instruction inst) const {
1301 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1302 // uses: '{}'
1303 return RegisterList();
1304 }
1305
1306 // BLX_register_cccc000100101111111111110011mmmm_case_0:
1307 //
1308 // {Lr: 14,
1309 // Pc: 15,
1310 // Rm: Rm(3:0),
1311 // arch: v5T,
1312 // cond: cond(31:28),
1313 // defs: {Pc, Lr},
1314 // fields: [cond(31:28), Rm(3:0)],
1315 // pattern: cccc000100101111111111110011mmmm,
1316 // rule: BLX_register,
1317 // safety: [Rm(3:0)=1111 => FORBIDDEN_OPERANDS],
1318 // target: Rm,
1319 // uses: {Rm},
1320 // violations: [implied by 'target']}
1321 RegisterList BLX_register_cccc000100101111111111110011mmmm_case_0::
defs(Instruction inst) const1322 defs(Instruction inst) const {
1323 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1324 // defs: '{15, 14}'
1325 return RegisterList().
1326 Add(Register(15)).
1327 Add(Register(14));
1328 }
1329
1330 SafetyLevel BLX_register_cccc000100101111111111110011mmmm_case_0::
safety(Instruction inst) const1331 safety(Instruction inst) const {
1332 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1333
1334 // inst(3:0)=1111 => FORBIDDEN_OPERANDS
1335 if ((inst.Bits() & 0x0000000F) ==
1336 0x0000000F)
1337 return FORBIDDEN_OPERANDS;
1338
1339 return MAY_BE_SAFE;
1340 }
1341
1342
1343 Register BLX_register_cccc000100101111111111110011mmmm_case_0::
branch_target_register(Instruction inst) const1344 branch_target_register(Instruction inst) const {
1345 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1346 // target: 'inst(3:0)'
1347 return Register((inst.Bits() & 0x0000000F));
1348 }
1349
1350 RegisterList BLX_register_cccc000100101111111111110011mmmm_case_0::
uses(Instruction inst) const1351 uses(Instruction inst) const {
1352 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1353 // uses: '{inst(3:0)}'
1354 return RegisterList().
1355 Add(Register((inst.Bits() & 0x0000000F)));
1356 }
1357
1358 ViolationSet BLX_register_cccc000100101111111111110011mmmm_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const1359 get_violations(const nacl_arm_val::DecodedInstruction& first,
1360 const nacl_arm_val::DecodedInstruction& second,
1361 const nacl_arm_val::SfiValidator& sfi,
1362 nacl_arm_val::AddressSet* branches,
1363 nacl_arm_val::AddressSet* critical,
1364 uint32_t* next_inst_addr) const {
1365 ViolationSet violations = ClassDecoder::get_violations(
1366 first, second, sfi, branches, critical, next_inst_addr);
1367
1368 // Indirect branches (through a target register) need to be masked,
1369 // and if they represent a call, they need to be end-of-bundle aligned.
1370 violations = ViolationUnion(
1371 violations, get_branch_mask_violations(first, second, sfi, critical));
1372 violations = ViolationUnion(
1373 violations, get_call_position_violations(second, sfi));
1374
1375 return violations;
1376 }
1377
1378
1379 // BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_0:
1380 //
1381 // {Cond: Cond(31:28),
1382 // Lr: 14,
1383 // Pc: 15,
1384 // defs: {Pc, Lr},
1385 // fields: [Cond(31:28), imm24(23:0)],
1386 // imm24: imm24(23:0),
1387 // imm32: SignExtend(imm24:'00'(1:0), 32),
1388 // pattern: cccc1011iiiiiiiiiiiiiiiiiiiiiiii,
1389 // relative: true,
1390 // relative_offset: imm32 + 8,
1391 // rule: BL_BLX_immediate,
1392 // safety: [true => MAY_BE_SAFE],
1393 // true: true,
1394 // uses: {Pc},
1395 // violations: [implied by 'relative']}
1396 RegisterList BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_0::
defs(Instruction inst) const1397 defs(Instruction inst) const {
1398 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1399 // defs: '{15, 14}'
1400 return RegisterList().
1401 Add(Register(15)).
1402 Add(Register(14));
1403 }
1404
1405 bool BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_0::
is_relative_branch(Instruction inst) const1406 is_relative_branch(Instruction inst) const {
1407 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1408 // relative: 'true'
1409 return true;
1410 }
1411
1412 int32_t BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_0::
branch_target_offset(Instruction inst) const1413 branch_target_offset(Instruction inst) const {
1414 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1415 // relative_offset: "SignExtend(inst(23:0):'00'(1:0), 32) + 8"
1416 return (((((((inst.Bits() & 0x00FFFFFF)) << 2) | (0 & 0x00000003))) & 0x02000000)
1417 ? ((((((inst.Bits() & 0x00FFFFFF)) << 2) | (0 & 0x00000003))) | 0xFC000000)
1418 : ((((inst.Bits() & 0x00FFFFFF)) << 2) | (0 & 0x00000003))) + 8;
1419 }
1420
1421 SafetyLevel BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_0::
safety(Instruction inst) const1422 safety(Instruction inst) const {
1423 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1424
1425 // true => MAY_BE_SAFE
1426 if (true)
1427 return MAY_BE_SAFE;
1428
1429 return MAY_BE_SAFE;
1430 }
1431
1432
1433 RegisterList BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_0::
uses(Instruction inst) const1434 uses(Instruction inst) const {
1435 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1436 // uses: '{15}'
1437 return RegisterList().
1438 Add(Register(15));
1439 }
1440
1441 ViolationSet BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const1442 get_violations(const nacl_arm_val::DecodedInstruction& first,
1443 const nacl_arm_val::DecodedInstruction& second,
1444 const nacl_arm_val::SfiValidator& sfi,
1445 nacl_arm_val::AddressSet* branches,
1446 nacl_arm_val::AddressSet* critical,
1447 uint32_t* next_inst_addr) const {
1448 ViolationSet violations = ClassDecoder::get_violations(
1449 first, second, sfi, branches, critical, next_inst_addr);
1450
1451 // Direct (relative) branches can represent a call. If so, they need
1452 // to be end-of-bundle aligned.
1453 violations = ViolationUnion(
1454 violations, get_call_position_violations(second, sfi));
1455
1456 return violations;
1457 }
1458
1459
1460 // BXJ_cccc000100101111111111110010mmmm_case_0:
1461 //
1462 // {arch: v5TEJ,
1463 // defs: {},
1464 // pattern: cccc000100101111111111110010mmmm,
1465 // rule: BXJ,
1466 // safety: [true => FORBIDDEN],
1467 // true: true,
1468 // uses: {}}
1469 RegisterList BXJ_cccc000100101111111111110010mmmm_case_0::
defs(Instruction inst) const1470 defs(Instruction inst) const {
1471 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1472 // defs: '{}'
1473 return RegisterList();
1474 }
1475
1476 SafetyLevel BXJ_cccc000100101111111111110010mmmm_case_0::
safety(Instruction inst) const1477 safety(Instruction inst) const {
1478 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1479
1480 // true => FORBIDDEN
1481 if (true)
1482 return FORBIDDEN;
1483
1484 return MAY_BE_SAFE;
1485 }
1486
1487
1488 RegisterList BXJ_cccc000100101111111111110010mmmm_case_0::
uses(Instruction inst) const1489 uses(Instruction inst) const {
1490 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1491 // uses: '{}'
1492 return RegisterList();
1493 }
1494
1495 // B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_0:
1496 //
1497 // {Cond: Cond(31:28),
1498 // Pc: 15,
1499 // defs: {Pc},
1500 // fields: [Cond(31:28), imm24(23:0)],
1501 // imm24: imm24(23:0),
1502 // imm32: SignExtend(imm24:'00'(1:0), 32),
1503 // pattern: cccc1010iiiiiiiiiiiiiiiiiiiiiiii,
1504 // relative: true,
1505 // relative_offset: imm32 + 8,
1506 // rule: B,
1507 // safety: [true => MAY_BE_SAFE],
1508 // true: true,
1509 // uses: {Pc},
1510 // violations: [implied by 'relative']}
1511 RegisterList B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_0::
defs(Instruction inst) const1512 defs(Instruction inst) const {
1513 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1514 // defs: '{15}'
1515 return RegisterList().
1516 Add(Register(15));
1517 }
1518
1519 bool B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_0::
is_relative_branch(Instruction inst) const1520 is_relative_branch(Instruction inst) const {
1521 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1522 // relative: 'true'
1523 return true;
1524 }
1525
1526 int32_t B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_0::
branch_target_offset(Instruction inst) const1527 branch_target_offset(Instruction inst) const {
1528 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1529 // relative_offset: "SignExtend(inst(23:0):'00'(1:0), 32) + 8"
1530 return (((((((inst.Bits() & 0x00FFFFFF)) << 2) | (0 & 0x00000003))) & 0x02000000)
1531 ? ((((((inst.Bits() & 0x00FFFFFF)) << 2) | (0 & 0x00000003))) | 0xFC000000)
1532 : ((((inst.Bits() & 0x00FFFFFF)) << 2) | (0 & 0x00000003))) + 8;
1533 }
1534
1535 SafetyLevel B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_0::
safety(Instruction inst) const1536 safety(Instruction inst) const {
1537 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1538
1539 // true => MAY_BE_SAFE
1540 if (true)
1541 return MAY_BE_SAFE;
1542
1543 return MAY_BE_SAFE;
1544 }
1545
1546
1547 RegisterList B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_0::
uses(Instruction inst) const1548 uses(Instruction inst) const {
1549 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1550 // uses: '{15}'
1551 return RegisterList().
1552 Add(Register(15));
1553 }
1554
1555 ViolationSet B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const1556 get_violations(const nacl_arm_val::DecodedInstruction& first,
1557 const nacl_arm_val::DecodedInstruction& second,
1558 const nacl_arm_val::SfiValidator& sfi,
1559 nacl_arm_val::AddressSet* branches,
1560 nacl_arm_val::AddressSet* critical,
1561 uint32_t* next_inst_addr) const {
1562 ViolationSet violations = ClassDecoder::get_violations(
1563 first, second, sfi, branches, critical, next_inst_addr);
1564
1565 // Direct (relative) branches can represent a call. If so, they need
1566 // to be end-of-bundle aligned.
1567 violations = ViolationUnion(
1568 violations, get_call_position_violations(second, sfi));
1569
1570 return violations;
1571 }
1572
1573
1574 // Bx_cccc000100101111111111110001mmmm_case_0:
1575 //
1576 // {Pc: 15,
1577 // Rm: Rm(3:0),
1578 // arch: v4T,
1579 // cond: cond(31:28),
1580 // defs: {Pc},
1581 // fields: [cond(31:28), Rm(3:0)],
1582 // pattern: cccc000100101111111111110001mmmm,
1583 // rule: Bx,
1584 // safety: [Rm(3:0)=1111 => FORBIDDEN_OPERANDS],
1585 // target: Rm,
1586 // uses: {Rm},
1587 // violations: [implied by 'target']}
1588 RegisterList Bx_cccc000100101111111111110001mmmm_case_0::
defs(Instruction inst) const1589 defs(Instruction inst) const {
1590 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1591 // defs: '{15}'
1592 return RegisterList().
1593 Add(Register(15));
1594 }
1595
1596 SafetyLevel Bx_cccc000100101111111111110001mmmm_case_0::
safety(Instruction inst) const1597 safety(Instruction inst) const {
1598 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1599
1600 // inst(3:0)=1111 => FORBIDDEN_OPERANDS
1601 if ((inst.Bits() & 0x0000000F) ==
1602 0x0000000F)
1603 return FORBIDDEN_OPERANDS;
1604
1605 return MAY_BE_SAFE;
1606 }
1607
1608
1609 Register Bx_cccc000100101111111111110001mmmm_case_0::
branch_target_register(Instruction inst) const1610 branch_target_register(Instruction inst) const {
1611 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1612 // target: 'inst(3:0)'
1613 return Register((inst.Bits() & 0x0000000F));
1614 }
1615
1616 RegisterList Bx_cccc000100101111111111110001mmmm_case_0::
uses(Instruction inst) const1617 uses(Instruction inst) const {
1618 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1619 // uses: '{inst(3:0)}'
1620 return RegisterList().
1621 Add(Register((inst.Bits() & 0x0000000F)));
1622 }
1623
1624 ViolationSet Bx_cccc000100101111111111110001mmmm_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const1625 get_violations(const nacl_arm_val::DecodedInstruction& first,
1626 const nacl_arm_val::DecodedInstruction& second,
1627 const nacl_arm_val::SfiValidator& sfi,
1628 nacl_arm_val::AddressSet* branches,
1629 nacl_arm_val::AddressSet* critical,
1630 uint32_t* next_inst_addr) const {
1631 ViolationSet violations = ClassDecoder::get_violations(
1632 first, second, sfi, branches, critical, next_inst_addr);
1633
1634 // Indirect branches (through a target register) need to be masked,
1635 // and if they represent a call, they need to be end-of-bundle aligned.
1636 violations = ViolationUnion(
1637 violations, get_branch_mask_violations(first, second, sfi, critical));
1638 violations = ViolationUnion(
1639 violations, get_call_position_violations(second, sfi));
1640
1641 return violations;
1642 }
1643
1644
1645 // CDP2_11111110iiiiiiiiiiiiiiiiiii0iiii_case_0:
1646 //
1647 // {arch: v5,
1648 // defs: {},
1649 // pattern: 11111110iiiiiiiiiiiiiiiiiii0iiii,
1650 // rule: CDP2,
1651 // safety: [true => FORBIDDEN],
1652 // true: true,
1653 // uses: {}}
1654 RegisterList CDP2_11111110iiiiiiiiiiiiiiiiiii0iiii_case_0::
defs(Instruction inst) const1655 defs(Instruction inst) const {
1656 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1657 // defs: '{}'
1658 return RegisterList();
1659 }
1660
1661 SafetyLevel CDP2_11111110iiiiiiiiiiiiiiiiiii0iiii_case_0::
safety(Instruction inst) const1662 safety(Instruction inst) const {
1663 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1664
1665 // true => FORBIDDEN
1666 if (true)
1667 return FORBIDDEN;
1668
1669 return MAY_BE_SAFE;
1670 }
1671
1672
1673 RegisterList CDP2_11111110iiiiiiiiiiiiiiiiiii0iiii_case_0::
uses(Instruction inst) const1674 uses(Instruction inst) const {
1675 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1676 // uses: '{}'
1677 return RegisterList();
1678 }
1679
1680 // CDP_cccc1110oooonnnnddddccccooo0mmmm_case_0:
1681 //
1682 // {defs: {},
1683 // pattern: cccc1110oooonnnnddddccccooo0mmmm,
1684 // rule: CDP,
1685 // safety: [true => FORBIDDEN],
1686 // true: true,
1687 // uses: {}}
1688 RegisterList CDP_cccc1110oooonnnnddddccccooo0mmmm_case_0::
defs(Instruction inst) const1689 defs(Instruction inst) const {
1690 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1691 // defs: '{}'
1692 return RegisterList();
1693 }
1694
1695 SafetyLevel CDP_cccc1110oooonnnnddddccccooo0mmmm_case_0::
safety(Instruction inst) const1696 safety(Instruction inst) const {
1697 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1698
1699 // true => FORBIDDEN
1700 if (true)
1701 return FORBIDDEN;
1702
1703 return MAY_BE_SAFE;
1704 }
1705
1706
1707 RegisterList CDP_cccc1110oooonnnnddddccccooo0mmmm_case_0::
uses(Instruction inst) const1708 uses(Instruction inst) const {
1709 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1710 // uses: '{}'
1711 return RegisterList();
1712 }
1713
1714 // CLREX_11110101011111111111000000011111_case_0:
1715 //
1716 // {arch: V6K,
1717 // defs: {},
1718 // pattern: 11110101011111111111000000011111,
1719 // rule: CLREX,
1720 // safety: [true => FORBIDDEN],
1721 // true: true,
1722 // uses: {}}
1723 RegisterList CLREX_11110101011111111111000000011111_case_0::
defs(Instruction inst) const1724 defs(Instruction inst) const {
1725 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1726 // defs: '{}'
1727 return RegisterList();
1728 }
1729
1730 SafetyLevel CLREX_11110101011111111111000000011111_case_0::
safety(Instruction inst) const1731 safety(Instruction inst) const {
1732 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1733
1734 // true => FORBIDDEN
1735 if (true)
1736 return FORBIDDEN;
1737
1738 return MAY_BE_SAFE;
1739 }
1740
1741
1742 RegisterList CLREX_11110101011111111111000000011111_case_0::
uses(Instruction inst) const1743 uses(Instruction inst) const {
1744 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1745 // uses: '{}'
1746 return RegisterList();
1747 }
1748
1749 // CLZ_cccc000101101111dddd11110001mmmm_case_0:
1750 //
1751 // {Pc: 15,
1752 // Rd: Rd(15:12),
1753 // Rm: Rm(3:0),
1754 // arch: v5T,
1755 // cond: cond(31:28),
1756 // defs: {Rd},
1757 // fields: [cond(31:28), Rd(15:12), Rm(3:0)],
1758 // pattern: cccc000101101111dddd11110001mmmm,
1759 // rule: CLZ,
1760 // safety: [Pc in {Rd, Rm} => UNPREDICTABLE],
1761 // uses: {Rm}}
1762 RegisterList CLZ_cccc000101101111dddd11110001mmmm_case_0::
defs(Instruction inst) const1763 defs(Instruction inst) const {
1764 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1765 // defs: '{inst(15:12)}'
1766 return RegisterList().
1767 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
1768 }
1769
1770 SafetyLevel CLZ_cccc000101101111dddd11110001mmmm_case_0::
safety(Instruction inst) const1771 safety(Instruction inst) const {
1772 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1773
1774 // 15 ==
1775 // inst(15:12) ||
1776 // 15 ==
1777 // inst(3:0) => UNPREDICTABLE
1778 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
1779 (((15) == ((inst.Bits() & 0x0000000F)))))
1780 return UNPREDICTABLE;
1781
1782 return MAY_BE_SAFE;
1783 }
1784
1785
1786 RegisterList CLZ_cccc000101101111dddd11110001mmmm_case_0::
uses(Instruction inst) const1787 uses(Instruction inst) const {
1788 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1789 // uses: '{inst(3:0)}'
1790 return RegisterList().
1791 Add(Register((inst.Bits() & 0x0000000F)));
1792 }
1793
1794 // CMN_immediate_cccc00110111nnnn0000iiiiiiiiiiii_case_0:
1795 //
1796 // {NZCV: 16,
1797 // Rn: Rn(19:16),
1798 // cond: cond(31:28),
1799 // defs: {NZCV},
1800 // fields: [cond(31:28), Rn(19:16), imm12(11:0)],
1801 // imm12: imm12(11:0),
1802 // imm32: ARMExpandImm_C(imm12),
1803 // pattern: cccc00110111nnnn0000iiiiiiiiiiii,
1804 // rule: CMN_immediate,
1805 // uses: {Rn}}
1806 RegisterList CMN_immediate_cccc00110111nnnn0000iiiiiiiiiiii_case_0::
defs(Instruction inst) const1807 defs(Instruction inst) const {
1808 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1809 // defs: '{16}'
1810 return RegisterList().
1811 Add(Register(16));
1812 }
1813
1814 SafetyLevel CMN_immediate_cccc00110111nnnn0000iiiiiiiiiiii_case_0::
safety(Instruction inst) const1815 safety(Instruction inst) const {
1816 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1817
1818 return MAY_BE_SAFE;
1819 }
1820
1821
1822 RegisterList CMN_immediate_cccc00110111nnnn0000iiiiiiiiiiii_case_0::
uses(Instruction inst) const1823 uses(Instruction inst) const {
1824 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1825 // uses: '{inst(19:16)}'
1826 return RegisterList().
1827 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
1828 }
1829
1830 // CMN_register_cccc00010111nnnn0000iiiiitt0mmmm_case_0:
1831 //
1832 // {NZCV: 16,
1833 // None: 32,
1834 // Rm: Rm(3:0),
1835 // Rn: Rn(19:16),
1836 // S: S(20),
1837 // cond: cond(31:28),
1838 // defs: {NZCV
1839 // if S
1840 // else None},
1841 // fields: [cond(31:28),
1842 // S(20),
1843 // Rn(19:16),
1844 // imm5(11:7),
1845 // type(6:5),
1846 // Rm(3:0)],
1847 // imm5: imm5(11:7),
1848 // pattern: cccc00010111nnnn0000iiiiitt0mmmm,
1849 // rule: CMN_register,
1850 // shift: DecodeImmShift(type, imm5),
1851 // type: type(6:5),
1852 // uses: {Rn, Rm}}
1853 RegisterList CMN_register_cccc00010111nnnn0000iiiiitt0mmmm_case_0::
defs(Instruction inst) const1854 defs(Instruction inst) const {
1855 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1856 // defs: '{16
1857 // if inst(20)
1858 // else 32}'
1859 return RegisterList().
1860 Add(Register(((((inst.Bits() & 0x00100000) >> 20) != 0)
1861 ? 16
1862 : 32)));
1863 }
1864
1865 SafetyLevel CMN_register_cccc00010111nnnn0000iiiiitt0mmmm_case_0::
safety(Instruction inst) const1866 safety(Instruction inst) const {
1867 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1868
1869 return MAY_BE_SAFE;
1870 }
1871
1872
1873 RegisterList CMN_register_cccc00010111nnnn0000iiiiitt0mmmm_case_0::
uses(Instruction inst) const1874 uses(Instruction inst) const {
1875 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1876 // uses: '{inst(19:16), inst(3:0)}'
1877 return RegisterList().
1878 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
1879 Add(Register((inst.Bits() & 0x0000000F)));
1880 }
1881
1882 // CMN_register_shifted_register_cccc00010111nnnn0000ssss0tt1mmmm_case_0:
1883 //
1884 // {NZCV: 16,
1885 // Pc: 15,
1886 // Rm: Rm(3:0),
1887 // Rn: Rn(19:16),
1888 // Rs: Rs(11:8),
1889 // cond: cond(31:28),
1890 // defs: {NZCV},
1891 // fields: [cond(31:28), Rn(19:16), Rs(11:8), type(6:5), Rm(3:0)],
1892 // pattern: cccc00010111nnnn0000ssss0tt1mmmm,
1893 // rule: CMN_register_shifted_register,
1894 // safety: [Pc in {Rn, Rm, Rs} => UNPREDICTABLE],
1895 // shift_t: DecodeRegShift(type),
1896 // type: type(6:5),
1897 // uses: {Rn, Rm, Rs}}
1898 RegisterList CMN_register_shifted_register_cccc00010111nnnn0000ssss0tt1mmmm_case_0::
defs(Instruction inst) const1899 defs(Instruction inst) const {
1900 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1901 // defs: '{16}'
1902 return RegisterList().
1903 Add(Register(16));
1904 }
1905
1906 SafetyLevel CMN_register_shifted_register_cccc00010111nnnn0000ssss0tt1mmmm_case_0::
safety(Instruction inst) const1907 safety(Instruction inst) const {
1908 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1909
1910 // 15 ==
1911 // inst(19:16) ||
1912 // 15 ==
1913 // inst(3:0) ||
1914 // 15 ==
1915 // inst(11:8) => UNPREDICTABLE
1916 if ((((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
1917 (((15) == ((inst.Bits() & 0x0000000F)))) ||
1918 (((15) == (((inst.Bits() & 0x00000F00) >> 8)))))
1919 return UNPREDICTABLE;
1920
1921 return MAY_BE_SAFE;
1922 }
1923
1924
1925 RegisterList CMN_register_shifted_register_cccc00010111nnnn0000ssss0tt1mmmm_case_0::
uses(Instruction inst) const1926 uses(Instruction inst) const {
1927 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1928 // uses: '{inst(19:16), inst(3:0), inst(11:8)}'
1929 return RegisterList().
1930 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
1931 Add(Register((inst.Bits() & 0x0000000F))).
1932 Add(Register(((inst.Bits() & 0x00000F00) >> 8)));
1933 }
1934
1935 // CMP_immediate_cccc00110101nnnn0000iiiiiiiiiiii_case_0:
1936 //
1937 // {NZCV: 16,
1938 // Rn: Rn(19:16),
1939 // cond: cond(31:28),
1940 // defs: {NZCV},
1941 // fields: [cond(31:28), Rn(19:16), imm12(11:0)],
1942 // imm12: imm12(11:0),
1943 // imm32: ARMExpandImm_C(imm12),
1944 // pattern: cccc00110101nnnn0000iiiiiiiiiiii,
1945 // rule: CMP_immediate,
1946 // uses: {Rn}}
1947 RegisterList CMP_immediate_cccc00110101nnnn0000iiiiiiiiiiii_case_0::
defs(Instruction inst) const1948 defs(Instruction inst) const {
1949 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1950 // defs: '{16}'
1951 return RegisterList().
1952 Add(Register(16));
1953 }
1954
1955 SafetyLevel CMP_immediate_cccc00110101nnnn0000iiiiiiiiiiii_case_0::
safety(Instruction inst) const1956 safety(Instruction inst) const {
1957 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1958
1959 return MAY_BE_SAFE;
1960 }
1961
1962
1963 RegisterList CMP_immediate_cccc00110101nnnn0000iiiiiiiiiiii_case_0::
uses(Instruction inst) const1964 uses(Instruction inst) const {
1965 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1966 // uses: '{inst(19:16)}'
1967 return RegisterList().
1968 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
1969 }
1970
1971 // CMP_register_cccc00010101nnnn0000iiiiitt0mmmm_case_0:
1972 //
1973 // {NZCV: 16,
1974 // None: 32,
1975 // Rm: Rm(3:0),
1976 // Rn: Rn(19:16),
1977 // S: S(20),
1978 // cond: cond(31:28),
1979 // defs: {NZCV
1980 // if S
1981 // else None},
1982 // fields: [cond(31:28),
1983 // S(20),
1984 // Rn(19:16),
1985 // imm5(11:7),
1986 // type(6:5),
1987 // Rm(3:0)],
1988 // imm5: imm5(11:7),
1989 // pattern: cccc00010101nnnn0000iiiiitt0mmmm,
1990 // rule: CMP_register,
1991 // shift: DecodeImmShift(type, imm5),
1992 // type: type(6:5),
1993 // uses: {Rn, Rm}}
1994 RegisterList CMP_register_cccc00010101nnnn0000iiiiitt0mmmm_case_0::
defs(Instruction inst) const1995 defs(Instruction inst) const {
1996 UNREFERENCED_PARAMETER(inst); // To silence compiler.
1997 // defs: '{16
1998 // if inst(20)
1999 // else 32}'
2000 return RegisterList().
2001 Add(Register(((((inst.Bits() & 0x00100000) >> 20) != 0)
2002 ? 16
2003 : 32)));
2004 }
2005
2006 SafetyLevel CMP_register_cccc00010101nnnn0000iiiiitt0mmmm_case_0::
safety(Instruction inst) const2007 safety(Instruction inst) const {
2008 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2009
2010 return MAY_BE_SAFE;
2011 }
2012
2013
2014 RegisterList CMP_register_cccc00010101nnnn0000iiiiitt0mmmm_case_0::
uses(Instruction inst) const2015 uses(Instruction inst) const {
2016 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2017 // uses: '{inst(19:16), inst(3:0)}'
2018 return RegisterList().
2019 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
2020 Add(Register((inst.Bits() & 0x0000000F)));
2021 }
2022
2023 // CMP_register_shifted_register_cccc00010101nnnn0000ssss0tt1mmmm_case_0:
2024 //
2025 // {NZCV: 16,
2026 // Pc: 15,
2027 // Rm: Rm(3:0),
2028 // Rn: Rn(19:16),
2029 // Rs: Rs(11:8),
2030 // cond: cond(31:28),
2031 // defs: {NZCV},
2032 // fields: [cond(31:28), Rn(19:16), Rs(11:8), type(6:5), Rm(3:0)],
2033 // pattern: cccc00010101nnnn0000ssss0tt1mmmm,
2034 // rule: CMP_register_shifted_register,
2035 // safety: [Pc in {Rn, Rm, Rs} => UNPREDICTABLE],
2036 // shift_t: DecodeRegShift(type),
2037 // type: type(6:5),
2038 // uses: {Rn, Rm, Rs}}
2039 RegisterList CMP_register_shifted_register_cccc00010101nnnn0000ssss0tt1mmmm_case_0::
defs(Instruction inst) const2040 defs(Instruction inst) const {
2041 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2042 // defs: '{16}'
2043 return RegisterList().
2044 Add(Register(16));
2045 }
2046
2047 SafetyLevel CMP_register_shifted_register_cccc00010101nnnn0000ssss0tt1mmmm_case_0::
safety(Instruction inst) const2048 safety(Instruction inst) const {
2049 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2050
2051 // 15 ==
2052 // inst(19:16) ||
2053 // 15 ==
2054 // inst(3:0) ||
2055 // 15 ==
2056 // inst(11:8) => UNPREDICTABLE
2057 if ((((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
2058 (((15) == ((inst.Bits() & 0x0000000F)))) ||
2059 (((15) == (((inst.Bits() & 0x00000F00) >> 8)))))
2060 return UNPREDICTABLE;
2061
2062 return MAY_BE_SAFE;
2063 }
2064
2065
2066 RegisterList CMP_register_shifted_register_cccc00010101nnnn0000ssss0tt1mmmm_case_0::
uses(Instruction inst) const2067 uses(Instruction inst) const {
2068 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2069 // uses: '{inst(19:16), inst(3:0), inst(11:8)}'
2070 return RegisterList().
2071 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
2072 Add(Register((inst.Bits() & 0x0000000F))).
2073 Add(Register(((inst.Bits() & 0x00000F00) >> 8)));
2074 }
2075
2076 // CPS_111100010000iii00000000iii0iiiii_case_0:
2077 //
2078 // {arch: v6,
2079 // defs: {},
2080 // pattern: 111100010000iii00000000iii0iiiii,
2081 // rule: CPS,
2082 // safety: [true => FORBIDDEN],
2083 // true: true,
2084 // uses: {}}
2085 RegisterList CPS_111100010000iii00000000iii0iiiii_case_0::
defs(Instruction inst) const2086 defs(Instruction inst) const {
2087 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2088 // defs: '{}'
2089 return RegisterList();
2090 }
2091
2092 SafetyLevel CPS_111100010000iii00000000iii0iiiii_case_0::
safety(Instruction inst) const2093 safety(Instruction inst) const {
2094 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2095
2096 // true => FORBIDDEN
2097 if (true)
2098 return FORBIDDEN;
2099
2100 return MAY_BE_SAFE;
2101 }
2102
2103
2104 RegisterList CPS_111100010000iii00000000iii0iiiii_case_0::
uses(Instruction inst) const2105 uses(Instruction inst) const {
2106 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2107 // uses: '{}'
2108 return RegisterList();
2109 }
2110
2111 // CVT_between_half_precision_and_single_precision_111100111d11ss10dddd011p00m0mmmm_case_0:
2112 //
2113 // {D: D(22),
2114 // M: M(5),
2115 // Vd: Vd(15:12),
2116 // Vm: Vm(3:0),
2117 // arch: ASIMDhp,
2118 // d: D:Vd,
2119 // defs: {},
2120 // elements: 4,
2121 // esize: 16,
2122 // fields: [D(22), size(19:18), Vd(15:12), op(8), M(5), Vm(3:0)],
2123 // half_to_single: op(8)=1,
2124 // m: M:Vm,
2125 // op: op(8),
2126 // pattern: 111100111d11ss10dddd011p00m0mmmm,
2127 // rule: CVT_between_half_precision_and_single_precision,
2128 // safety: [size(19:18)=~01 => UNDEFINED,
2129 // half_to_single &&
2130 // Vd(0)=1 => UNDEFINED,
2131 // not half_to_single &&
2132 // Vm(0)=1 => UNDEFINED],
2133 // size: size(19:18),
2134 // uses: {}}
2135 RegisterList CVT_between_half_precision_and_single_precision_111100111d11ss10dddd011p00m0mmmm_case_0::
defs(Instruction inst) const2136 defs(Instruction inst) const {
2137 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2138 // defs: '{}'
2139 return RegisterList();
2140 }
2141
2142 SafetyLevel CVT_between_half_precision_and_single_precision_111100111d11ss10dddd011p00m0mmmm_case_0::
safety(Instruction inst) const2143 safety(Instruction inst) const {
2144 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2145
2146 // inst(19:18)=~01 => UNDEFINED
2147 if ((inst.Bits() & 0x000C0000) !=
2148 0x00040000)
2149 return UNDEFINED;
2150
2151 // inst(8)=1 &&
2152 // inst(15:12)(0)=1 => UNDEFINED
2153 if (((inst.Bits() & 0x00000100) ==
2154 0x00000100) &&
2155 ((((inst.Bits() & 0x0000F000) >> 12) & 0x00000001) ==
2156 0x00000001))
2157 return UNDEFINED;
2158
2159 // not inst(8)=1 &&
2160 // inst(3:0)(0)=1 => UNDEFINED
2161 if ((!((inst.Bits() & 0x00000100) ==
2162 0x00000100)) &&
2163 (((inst.Bits() & 0x0000000F) & 0x00000001) ==
2164 0x00000001))
2165 return UNDEFINED;
2166
2167 return MAY_BE_SAFE;
2168 }
2169
2170
2171 RegisterList CVT_between_half_precision_and_single_precision_111100111d11ss10dddd011p00m0mmmm_case_0::
uses(Instruction inst) const2172 uses(Instruction inst) const {
2173 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2174 // uses: '{}'
2175 return RegisterList();
2176 }
2177
2178 // DBG_cccc001100100000111100001111iiii_case_0:
2179 //
2180 // {arch: v7,
2181 // defs: {},
2182 // pattern: cccc001100100000111100001111iiii,
2183 // rule: DBG,
2184 // safety: [true => FORBIDDEN],
2185 // true: true,
2186 // uses: {}}
2187 RegisterList DBG_cccc001100100000111100001111iiii_case_0::
defs(Instruction inst) const2188 defs(Instruction inst) const {
2189 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2190 // defs: '{}'
2191 return RegisterList();
2192 }
2193
2194 SafetyLevel DBG_cccc001100100000111100001111iiii_case_0::
safety(Instruction inst) const2195 safety(Instruction inst) const {
2196 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2197
2198 // true => FORBIDDEN
2199 if (true)
2200 return FORBIDDEN;
2201
2202 return MAY_BE_SAFE;
2203 }
2204
2205
2206 RegisterList DBG_cccc001100100000111100001111iiii_case_0::
uses(Instruction inst) const2207 uses(Instruction inst) const {
2208 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2209 // uses: '{}'
2210 return RegisterList();
2211 }
2212
2213 // DMB_1111010101111111111100000101xxxx_case_0:
2214 //
2215 // {arch: v7,
2216 // defs: {},
2217 // fields: [option(3:0)],
2218 // option: option(3:0),
2219 // pattern: 1111010101111111111100000101xxxx,
2220 // rule: DMB,
2221 // safety: [not option in {'1111'(3:0), '1110'(3:0), '1011'(3:0), '1010'(3:0), '0111'(3:0), '0110'(3:0), '0011'(3:0), '0010'(3:0)} => FORBIDDEN_OPERANDS],
2222 // uses: {}}
2223 RegisterList DMB_1111010101111111111100000101xxxx_case_0::
defs(Instruction inst) const2224 defs(Instruction inst) const {
2225 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2226 // defs: '{}'
2227 return RegisterList();
2228 }
2229
2230 SafetyLevel DMB_1111010101111111111100000101xxxx_case_0::
safety(Instruction inst) const2231 safety(Instruction inst) const {
2232 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2233
2234 // not '1111'(3:0) ==
2235 // inst(3:0) ||
2236 // '1110'(3:0) ==
2237 // inst(3:0) ||
2238 // '1011'(3:0) ==
2239 // inst(3:0) ||
2240 // '1010'(3:0) ==
2241 // inst(3:0) ||
2242 // '0111'(3:0) ==
2243 // inst(3:0) ||
2244 // '0110'(3:0) ==
2245 // inst(3:0) ||
2246 // '0011'(3:0) ==
2247 // inst(3:0) ||
2248 // '0010'(3:0) ==
2249 // inst(3:0) => FORBIDDEN_OPERANDS
2250 if (!(((((inst.Bits() & 0x0000000F)) == ((15 & 0x0000000F)))) ||
2251 ((((inst.Bits() & 0x0000000F)) == ((14 & 0x0000000F)))) ||
2252 ((((inst.Bits() & 0x0000000F)) == ((11 & 0x0000000F)))) ||
2253 ((((inst.Bits() & 0x0000000F)) == ((10 & 0x0000000F)))) ||
2254 ((((inst.Bits() & 0x0000000F)) == ((7 & 0x0000000F)))) ||
2255 ((((inst.Bits() & 0x0000000F)) == ((6 & 0x0000000F)))) ||
2256 ((((inst.Bits() & 0x0000000F)) == ((3 & 0x0000000F)))) ||
2257 ((((inst.Bits() & 0x0000000F)) == ((2 & 0x0000000F))))))
2258 return FORBIDDEN_OPERANDS;
2259
2260 return MAY_BE_SAFE;
2261 }
2262
2263
2264 RegisterList DMB_1111010101111111111100000101xxxx_case_0::
uses(Instruction inst) const2265 uses(Instruction inst) const {
2266 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2267 // uses: '{}'
2268 return RegisterList();
2269 }
2270
2271 // DSB_1111010101111111111100000100xxxx_case_0:
2272 //
2273 // {arch: v6T2,
2274 // defs: {},
2275 // fields: [option(3:0)],
2276 // option: option(3:0),
2277 // pattern: 1111010101111111111100000100xxxx,
2278 // rule: DSB,
2279 // safety: [not option in {'1111'(3:0), '1110'(3:0), '1011'(3:0), '1010'(3:0), '0111'(3:0), '0110'(3:0), '0011'(3:0), '0010'(3:0)} => FORBIDDEN_OPERANDS],
2280 // uses: {}}
2281 RegisterList DSB_1111010101111111111100000100xxxx_case_0::
defs(Instruction inst) const2282 defs(Instruction inst) const {
2283 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2284 // defs: '{}'
2285 return RegisterList();
2286 }
2287
2288 SafetyLevel DSB_1111010101111111111100000100xxxx_case_0::
safety(Instruction inst) const2289 safety(Instruction inst) const {
2290 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2291
2292 // not '1111'(3:0) ==
2293 // inst(3:0) ||
2294 // '1110'(3:0) ==
2295 // inst(3:0) ||
2296 // '1011'(3:0) ==
2297 // inst(3:0) ||
2298 // '1010'(3:0) ==
2299 // inst(3:0) ||
2300 // '0111'(3:0) ==
2301 // inst(3:0) ||
2302 // '0110'(3:0) ==
2303 // inst(3:0) ||
2304 // '0011'(3:0) ==
2305 // inst(3:0) ||
2306 // '0010'(3:0) ==
2307 // inst(3:0) => FORBIDDEN_OPERANDS
2308 if (!(((((inst.Bits() & 0x0000000F)) == ((15 & 0x0000000F)))) ||
2309 ((((inst.Bits() & 0x0000000F)) == ((14 & 0x0000000F)))) ||
2310 ((((inst.Bits() & 0x0000000F)) == ((11 & 0x0000000F)))) ||
2311 ((((inst.Bits() & 0x0000000F)) == ((10 & 0x0000000F)))) ||
2312 ((((inst.Bits() & 0x0000000F)) == ((7 & 0x0000000F)))) ||
2313 ((((inst.Bits() & 0x0000000F)) == ((6 & 0x0000000F)))) ||
2314 ((((inst.Bits() & 0x0000000F)) == ((3 & 0x0000000F)))) ||
2315 ((((inst.Bits() & 0x0000000F)) == ((2 & 0x0000000F))))))
2316 return FORBIDDEN_OPERANDS;
2317
2318 return MAY_BE_SAFE;
2319 }
2320
2321
2322 RegisterList DSB_1111010101111111111100000100xxxx_case_0::
uses(Instruction inst) const2323 uses(Instruction inst) const {
2324 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2325 // uses: '{}'
2326 return RegisterList();
2327 }
2328
2329 // EOR_immediate_cccc0010001snnnnddddiiiiiiiiiiii_case_0:
2330 //
2331 // {NZCV: 16,
2332 // None: 32,
2333 // Rd: Rd(15:12),
2334 // Rn: Rn(19:16),
2335 // S: S(20),
2336 // cond: cond(31:28),
2337 // defs: {Rd, NZCV
2338 // if setflags
2339 // else None},
2340 // fields: [cond(31:28), S(20), Rn(19:16), Rd(15:12), imm12(11:0)],
2341 // imm12: imm12(11:0),
2342 // imm32: ARMExpandImm(imm12),
2343 // pattern: cccc0010001snnnnddddiiiiiiiiiiii,
2344 // rule: EOR_immediate,
2345 // safety: [(Rd(15:12)=1111 &&
2346 // S(20)=1) => DECODER_ERROR,
2347 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS],
2348 // setflags: S(20)=1,
2349 // uses: {Rn}}
2350 RegisterList EOR_immediate_cccc0010001snnnnddddiiiiiiiiiiii_case_0::
defs(Instruction inst) const2351 defs(Instruction inst) const {
2352 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2353 // defs: '{inst(15:12), 16
2354 // if inst(20)=1
2355 // else 32}'
2356 return RegisterList().
2357 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
2358 Add(Register(((inst.Bits() & 0x00100000) ==
2359 0x00100000
2360 ? 16
2361 : 32)));
2362 }
2363
2364 SafetyLevel EOR_immediate_cccc0010001snnnnddddiiiiiiiiiiii_case_0::
safety(Instruction inst) const2365 safety(Instruction inst) const {
2366 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2367
2368 // (inst(15:12)=1111 &&
2369 // inst(20)=1) => DECODER_ERROR
2370 if ((((inst.Bits() & 0x0000F000) ==
2371 0x0000F000) &&
2372 ((inst.Bits() & 0x00100000) ==
2373 0x00100000)))
2374 return DECODER_ERROR;
2375
2376 // inst(15:12)=1111 => FORBIDDEN_OPERANDS
2377 if ((inst.Bits() & 0x0000F000) ==
2378 0x0000F000)
2379 return FORBIDDEN_OPERANDS;
2380
2381 return MAY_BE_SAFE;
2382 }
2383
2384
2385 RegisterList EOR_immediate_cccc0010001snnnnddddiiiiiiiiiiii_case_0::
uses(Instruction inst) const2386 uses(Instruction inst) const {
2387 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2388 // uses: '{inst(19:16)}'
2389 return RegisterList().
2390 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
2391 }
2392
2393 // EOR_register_cccc0000001snnnnddddiiiiitt0mmmm_case_0:
2394 //
2395 // {NZCV: 16,
2396 // None: 32,
2397 // Rd: Rd(15:12),
2398 // Rm: Rm(3:0),
2399 // Rn: Rn(19:16),
2400 // S: S(20),
2401 // cond: cond(31:28),
2402 // defs: {Rd, NZCV
2403 // if S
2404 // else None},
2405 // fields: [cond(31:28),
2406 // S(20),
2407 // Rn(19:16),
2408 // Rd(15:12),
2409 // imm5(11:7),
2410 // type(6:5),
2411 // Rm(3:0)],
2412 // imm5: imm5(11:7),
2413 // pattern: cccc0000001snnnnddddiiiiitt0mmmm,
2414 // rule: EOR_register,
2415 // safety: [(Rd(15:12)=1111 &&
2416 // S(20)=1) => DECODER_ERROR,
2417 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS],
2418 // shift: DecodeImmShift(type, imm5),
2419 // type: type(6:5),
2420 // uses: {Rn, Rm}}
2421 RegisterList EOR_register_cccc0000001snnnnddddiiiiitt0mmmm_case_0::
defs(Instruction inst) const2422 defs(Instruction inst) const {
2423 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2424 // defs: '{inst(15:12), 16
2425 // if inst(20)
2426 // else 32}'
2427 return RegisterList().
2428 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
2429 Add(Register(((((inst.Bits() & 0x00100000) >> 20) != 0)
2430 ? 16
2431 : 32)));
2432 }
2433
2434 SafetyLevel EOR_register_cccc0000001snnnnddddiiiiitt0mmmm_case_0::
safety(Instruction inst) const2435 safety(Instruction inst) const {
2436 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2437
2438 // (inst(15:12)=1111 &&
2439 // inst(20)=1) => DECODER_ERROR
2440 if ((((inst.Bits() & 0x0000F000) ==
2441 0x0000F000) &&
2442 ((inst.Bits() & 0x00100000) ==
2443 0x00100000)))
2444 return DECODER_ERROR;
2445
2446 // inst(15:12)=1111 => FORBIDDEN_OPERANDS
2447 if ((inst.Bits() & 0x0000F000) ==
2448 0x0000F000)
2449 return FORBIDDEN_OPERANDS;
2450
2451 return MAY_BE_SAFE;
2452 }
2453
2454
2455 RegisterList EOR_register_cccc0000001snnnnddddiiiiitt0mmmm_case_0::
uses(Instruction inst) const2456 uses(Instruction inst) const {
2457 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2458 // uses: '{inst(19:16), inst(3:0)}'
2459 return RegisterList().
2460 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
2461 Add(Register((inst.Bits() & 0x0000000F)));
2462 }
2463
2464 // EOR_register_shifted_register_cccc0000001snnnnddddssss0tt1mmmm_case_0:
2465 //
2466 // {NZCV: 16,
2467 // None: 32,
2468 // Pc: 15,
2469 // Rd: Rd(15:12),
2470 // Rm: Rm(3:0),
2471 // Rn: Rn(19:16),
2472 // Rs: Rs(11:8),
2473 // S: S(20),
2474 // cond: cond(31:28),
2475 // defs: {Rd, NZCV
2476 // if setflags
2477 // else None},
2478 // fields: [cond(31:28),
2479 // S(20),
2480 // Rn(19:16),
2481 // Rd(15:12),
2482 // Rs(11:8),
2483 // type(6:5),
2484 // Rm(3:0)],
2485 // pattern: cccc0000001snnnnddddssss0tt1mmmm,
2486 // rule: EOR_register_shifted_register,
2487 // safety: [Pc in {Rn, Rd, Rm, Rs} => UNPREDICTABLE],
2488 // setflags: S(20)=1,
2489 // shift_t: DecodeRegShift(type),
2490 // type: type(6:5),
2491 // uses: {Rn, Rm, Rs}}
2492 RegisterList EOR_register_shifted_register_cccc0000001snnnnddddssss0tt1mmmm_case_0::
defs(Instruction inst) const2493 defs(Instruction inst) const {
2494 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2495 // defs: '{inst(15:12), 16
2496 // if inst(20)=1
2497 // else 32}'
2498 return RegisterList().
2499 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
2500 Add(Register(((inst.Bits() & 0x00100000) ==
2501 0x00100000
2502 ? 16
2503 : 32)));
2504 }
2505
2506 SafetyLevel EOR_register_shifted_register_cccc0000001snnnnddddssss0tt1mmmm_case_0::
safety(Instruction inst) const2507 safety(Instruction inst) const {
2508 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2509
2510 // 15 ==
2511 // inst(19:16) ||
2512 // 15 ==
2513 // inst(15:12) ||
2514 // 15 ==
2515 // inst(3:0) ||
2516 // 15 ==
2517 // inst(11:8) => UNPREDICTABLE
2518 if ((((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
2519 (((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
2520 (((15) == ((inst.Bits() & 0x0000000F)))) ||
2521 (((15) == (((inst.Bits() & 0x00000F00) >> 8)))))
2522 return UNPREDICTABLE;
2523
2524 return MAY_BE_SAFE;
2525 }
2526
2527
2528 RegisterList EOR_register_shifted_register_cccc0000001snnnnddddssss0tt1mmmm_case_0::
uses(Instruction inst) const2529 uses(Instruction inst) const {
2530 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2531 // uses: '{inst(19:16), inst(3:0), inst(11:8)}'
2532 return RegisterList().
2533 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
2534 Add(Register((inst.Bits() & 0x0000000F))).
2535 Add(Register(((inst.Bits() & 0x00000F00) >> 8)));
2536 }
2537
2538 // ERET_cccc0001011000000000000001101110_case_0:
2539 //
2540 // {arch: v7VE,
2541 // defs: {},
2542 // pattern: cccc0001011000000000000001101110,
2543 // rule: ERET,
2544 // safety: [true => FORBIDDEN],
2545 // true: true,
2546 // uses: {}}
2547 RegisterList ERET_cccc0001011000000000000001101110_case_0::
defs(Instruction inst) const2548 defs(Instruction inst) const {
2549 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2550 // defs: '{}'
2551 return RegisterList();
2552 }
2553
2554 SafetyLevel ERET_cccc0001011000000000000001101110_case_0::
safety(Instruction inst) const2555 safety(Instruction inst) const {
2556 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2557
2558 // true => FORBIDDEN
2559 if (true)
2560 return FORBIDDEN;
2561
2562 return MAY_BE_SAFE;
2563 }
2564
2565
2566 RegisterList ERET_cccc0001011000000000000001101110_case_0::
uses(Instruction inst) const2567 uses(Instruction inst) const {
2568 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2569 // uses: '{}'
2570 return RegisterList();
2571 }
2572
2573 // FICTITIOUS_FIRST_case_0:
2574 //
2575 // {defs: {},
2576 // rule: FICTITIOUS_FIRST,
2577 // safety: [true => FORBIDDEN],
2578 // true: true,
2579 // uses: {}}
2580 RegisterList FICTITIOUS_FIRST_case_0::
defs(Instruction inst) const2581 defs(Instruction inst) const {
2582 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2583 // defs: '{}'
2584 return RegisterList();
2585 }
2586
2587 SafetyLevel FICTITIOUS_FIRST_case_0::
safety(Instruction inst) const2588 safety(Instruction inst) const {
2589 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2590
2591 // true => FORBIDDEN
2592 if (true)
2593 return FORBIDDEN;
2594
2595 return MAY_BE_SAFE;
2596 }
2597
2598
2599 RegisterList FICTITIOUS_FIRST_case_0::
uses(Instruction inst) const2600 uses(Instruction inst) const {
2601 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2602 // uses: '{}'
2603 return RegisterList();
2604 }
2605
2606 // HVC_cccc00010100iiiiiiiiiiii0111iiii_case_0:
2607 //
2608 // {arch: v7VE,
2609 // defs: {},
2610 // pattern: cccc00010100iiiiiiiiiiii0111iiii,
2611 // rule: HVC,
2612 // safety: [true => FORBIDDEN],
2613 // true: true,
2614 // uses: {}}
2615 RegisterList HVC_cccc00010100iiiiiiiiiiii0111iiii_case_0::
defs(Instruction inst) const2616 defs(Instruction inst) const {
2617 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2618 // defs: '{}'
2619 return RegisterList();
2620 }
2621
2622 SafetyLevel HVC_cccc00010100iiiiiiiiiiii0111iiii_case_0::
safety(Instruction inst) const2623 safety(Instruction inst) const {
2624 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2625
2626 // true => FORBIDDEN
2627 if (true)
2628 return FORBIDDEN;
2629
2630 return MAY_BE_SAFE;
2631 }
2632
2633
2634 RegisterList HVC_cccc00010100iiiiiiiiiiii0111iiii_case_0::
uses(Instruction inst) const2635 uses(Instruction inst) const {
2636 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2637 // uses: '{}'
2638 return RegisterList();
2639 }
2640
2641 // ISB_1111010101111111111100000110xxxx_case_0:
2642 //
2643 // {arch: v6T2,
2644 // defs: {},
2645 // fields: [option(3:0)],
2646 // option: option(3:0),
2647 // pattern: 1111010101111111111100000110xxxx,
2648 // rule: ISB,
2649 // safety: [option(3:0)=~1111 => FORBIDDEN_OPERANDS],
2650 // uses: {}}
2651 RegisterList ISB_1111010101111111111100000110xxxx_case_0::
defs(Instruction inst) const2652 defs(Instruction inst) const {
2653 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2654 // defs: '{}'
2655 return RegisterList();
2656 }
2657
2658 SafetyLevel ISB_1111010101111111111100000110xxxx_case_0::
safety(Instruction inst) const2659 safety(Instruction inst) const {
2660 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2661
2662 // inst(3:0)=~1111 => FORBIDDEN_OPERANDS
2663 if ((inst.Bits() & 0x0000000F) !=
2664 0x0000000F)
2665 return FORBIDDEN_OPERANDS;
2666
2667 return MAY_BE_SAFE;
2668 }
2669
2670
2671 RegisterList ISB_1111010101111111111100000110xxxx_case_0::
uses(Instruction inst) const2672 uses(Instruction inst) const {
2673 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2674 // uses: '{}'
2675 return RegisterList();
2676 }
2677
2678 // LDC2_immediate_1111110pudw1nnnniiiiiiiiiiiiiiii_case_0:
2679 //
2680 // {arch: v5,
2681 // defs: {},
2682 // pattern: 1111110pudw1nnnniiiiiiiiiiiiiiii,
2683 // rule: LDC2_immediate,
2684 // safety: [true => FORBIDDEN],
2685 // true: true,
2686 // uses: {}}
2687 RegisterList LDC2_immediate_1111110pudw1nnnniiiiiiiiiiiiiiii_case_0::
defs(Instruction inst) const2688 defs(Instruction inst) const {
2689 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2690 // defs: '{}'
2691 return RegisterList();
2692 }
2693
2694 SafetyLevel LDC2_immediate_1111110pudw1nnnniiiiiiiiiiiiiiii_case_0::
safety(Instruction inst) const2695 safety(Instruction inst) const {
2696 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2697
2698 // true => FORBIDDEN
2699 if (true)
2700 return FORBIDDEN;
2701
2702 return MAY_BE_SAFE;
2703 }
2704
2705
2706 RegisterList LDC2_immediate_1111110pudw1nnnniiiiiiiiiiiiiiii_case_0::
uses(Instruction inst) const2707 uses(Instruction inst) const {
2708 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2709 // uses: '{}'
2710 return RegisterList();
2711 }
2712
2713 // LDC2_literal_1111110pudw11111iiiiiiiiiiiiiiii_case_0:
2714 //
2715 // {arch: v5,
2716 // defs: {},
2717 // pattern: 1111110pudw11111iiiiiiiiiiiiiiii,
2718 // rule: LDC2_literal,
2719 // safety: [true => FORBIDDEN],
2720 // true: true,
2721 // uses: {}}
2722 RegisterList LDC2_literal_1111110pudw11111iiiiiiiiiiiiiiii_case_0::
defs(Instruction inst) const2723 defs(Instruction inst) const {
2724 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2725 // defs: '{}'
2726 return RegisterList();
2727 }
2728
2729 SafetyLevel LDC2_literal_1111110pudw11111iiiiiiiiiiiiiiii_case_0::
safety(Instruction inst) const2730 safety(Instruction inst) const {
2731 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2732
2733 // true => FORBIDDEN
2734 if (true)
2735 return FORBIDDEN;
2736
2737 return MAY_BE_SAFE;
2738 }
2739
2740
2741 RegisterList LDC2_literal_1111110pudw11111iiiiiiiiiiiiiiii_case_0::
uses(Instruction inst) const2742 uses(Instruction inst) const {
2743 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2744 // uses: '{}'
2745 return RegisterList();
2746 }
2747
2748 // LDC_immediate_cccc110pudw1nnnnddddcccciiiiiiii_case_0:
2749 //
2750 // {defs: {},
2751 // pattern: cccc110pudw1nnnnddddcccciiiiiiii,
2752 // rule: LDC_immediate,
2753 // safety: [true => FORBIDDEN],
2754 // true: true,
2755 // uses: {}}
2756 RegisterList LDC_immediate_cccc110pudw1nnnnddddcccciiiiiiii_case_0::
defs(Instruction inst) const2757 defs(Instruction inst) const {
2758 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2759 // defs: '{}'
2760 return RegisterList();
2761 }
2762
2763 SafetyLevel LDC_immediate_cccc110pudw1nnnnddddcccciiiiiiii_case_0::
safety(Instruction inst) const2764 safety(Instruction inst) const {
2765 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2766
2767 // true => FORBIDDEN
2768 if (true)
2769 return FORBIDDEN;
2770
2771 return MAY_BE_SAFE;
2772 }
2773
2774
2775 RegisterList LDC_immediate_cccc110pudw1nnnnddddcccciiiiiiii_case_0::
uses(Instruction inst) const2776 uses(Instruction inst) const {
2777 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2778 // uses: '{}'
2779 return RegisterList();
2780 }
2781
2782 // LDC_literal_cccc110pudw11111ddddcccciiiiiiii_case_0:
2783 //
2784 // {defs: {},
2785 // pattern: cccc110pudw11111ddddcccciiiiiiii,
2786 // rule: LDC_literal,
2787 // safety: [true => FORBIDDEN],
2788 // true: true,
2789 // uses: {}}
2790 RegisterList LDC_literal_cccc110pudw11111ddddcccciiiiiiii_case_0::
defs(Instruction inst) const2791 defs(Instruction inst) const {
2792 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2793 // defs: '{}'
2794 return RegisterList();
2795 }
2796
2797 SafetyLevel LDC_literal_cccc110pudw11111ddddcccciiiiiiii_case_0::
safety(Instruction inst) const2798 safety(Instruction inst) const {
2799 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2800
2801 // true => FORBIDDEN
2802 if (true)
2803 return FORBIDDEN;
2804
2805 return MAY_BE_SAFE;
2806 }
2807
2808
2809 RegisterList LDC_literal_cccc110pudw11111ddddcccciiiiiiii_case_0::
uses(Instruction inst) const2810 uses(Instruction inst) const {
2811 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2812 // uses: '{}'
2813 return RegisterList();
2814 }
2815
2816 // LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_0:
2817 //
2818 // {None: 32,
2819 // Pc: 15,
2820 // Rn: Rn(19:16),
2821 // W: W(21),
2822 // base: Rn,
2823 // cond: cond(31:28),
2824 // defs: Union({Rn
2825 // if wback
2826 // else None}, registers),
2827 // fields: [cond(31:28), W(21), Rn(19:16), register_list(15:0)],
2828 // pattern: cccc100000w1nnnnrrrrrrrrrrrrrrrr,
2829 // register_list: register_list(15:0),
2830 // registers: RegisterList(register_list),
2831 // rule: LDMDA_LDMFA,
2832 // safety: [Rn ==
2833 // Pc ||
2834 // NumGPRs(registers) <
2835 // 1 => UNPREDICTABLE,
2836 // wback &&
2837 // Contains(registers, Rn) => UNKNOWN,
2838 // Contains(registers, Pc) => FORBIDDEN_OPERANDS],
2839 // small_imm_base_wb: wback,
2840 // uses: {Rn},
2841 // violations: [implied by 'base'],
2842 // wback: W(21)=1}
2843 Register LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_0::
base_address_register(Instruction inst) const2844 base_address_register(Instruction inst) const {
2845 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2846 // base: 'inst(19:16)'
2847 return Register(((inst.Bits() & 0x000F0000) >> 16));
2848 }
2849
2850 RegisterList LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_0::
defs(Instruction inst) const2851 defs(Instruction inst) const {
2852 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2853 // defs: 'Union({inst(19:16)
2854 // if inst(21)=1
2855 // else 32}, RegisterList(inst(15:0)))'
2856 return nacl_arm_dec::Union(RegisterList().
2857 Add(Register(((inst.Bits() & 0x00200000) ==
2858 0x00200000
2859 ? ((inst.Bits() & 0x000F0000) >> 16)
2860 : 32))), nacl_arm_dec::RegisterList((inst.Bits() & 0x0000FFFF)));
2861 }
2862
2863 SafetyLevel LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_0::
safety(Instruction inst) const2864 safety(Instruction inst) const {
2865 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2866
2867 // 15 ==
2868 // inst(19:16) ||
2869 // NumGPRs(RegisterList(inst(15:0))) <
2870 // 1 => UNPREDICTABLE
2871 if ((((((inst.Bits() & 0x000F0000) >> 16)) == (15))) ||
2872 (((nacl_arm_dec::NumGPRs(nacl_arm_dec::RegisterList((inst.Bits() & 0x0000FFFF)))) < (1))))
2873 return UNPREDICTABLE;
2874
2875 // inst(21)=1 &&
2876 // Contains(RegisterList(inst(15:0)), inst(19:16)) => UNKNOWN
2877 if (((inst.Bits() & 0x00200000) ==
2878 0x00200000) &&
2879 (nacl_arm_dec::Contains(nacl_arm_dec::RegisterList((inst.Bits() & 0x0000FFFF)), Register(((inst.Bits() & 0x000F0000) >> 16)))))
2880 return UNKNOWN;
2881
2882 // Contains(RegisterList(inst(15:0)), 15) => FORBIDDEN_OPERANDS
2883 if (nacl_arm_dec::Contains(nacl_arm_dec::RegisterList((inst.Bits() & 0x0000FFFF)), Register(15)))
2884 return FORBIDDEN_OPERANDS;
2885
2886 return MAY_BE_SAFE;
2887 }
2888
2889
2890 bool LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_0::
base_address_register_writeback_small_immediate(Instruction inst) const2891 base_address_register_writeback_small_immediate(
2892 Instruction inst) const {
2893 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2894 // small_imm_base_wb: 'inst(21)=1'
2895 return (inst.Bits() & 0x00200000) ==
2896 0x00200000;
2897 }
2898
2899 RegisterList LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_0::
uses(Instruction inst) const2900 uses(Instruction inst) const {
2901 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2902 // uses: '{inst(19:16)}'
2903 return RegisterList().
2904 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
2905 }
2906
2907 ViolationSet LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const2908 get_violations(const nacl_arm_val::DecodedInstruction& first,
2909 const nacl_arm_val::DecodedInstruction& second,
2910 const nacl_arm_val::SfiValidator& sfi,
2911 nacl_arm_val::AddressSet* branches,
2912 nacl_arm_val::AddressSet* critical,
2913 uint32_t* next_inst_addr) const {
2914 ViolationSet violations = ClassDecoder::get_violations(
2915 first, second, sfi, branches, critical, next_inst_addr);
2916
2917 // Report unsafe loads/stores of a base address by the given instruction
2918 // pair.
2919 violations = ViolationUnion(
2920 violations, get_loadstore_violations(first, second, sfi, critical));
2921
2922 return violations;
2923 }
2924
2925
2926 // LDMDB_LDMEA_cccc100100w1nnnnrrrrrrrrrrrrrrrr_case_0:
2927 //
2928 // {None: 32,
2929 // Pc: 15,
2930 // Rn: Rn(19:16),
2931 // W: W(21),
2932 // base: Rn,
2933 // cond: cond(31:28),
2934 // defs: Union({Rn
2935 // if wback
2936 // else None}, registers),
2937 // fields: [cond(31:28), W(21), Rn(19:16), register_list(15:0)],
2938 // pattern: cccc100100w1nnnnrrrrrrrrrrrrrrrr,
2939 // register_list: register_list(15:0),
2940 // registers: RegisterList(register_list),
2941 // rule: LDMDB_LDMEA,
2942 // safety: [Rn ==
2943 // Pc ||
2944 // NumGPRs(registers) <
2945 // 1 => UNPREDICTABLE,
2946 // wback &&
2947 // Contains(registers, Rn) => UNKNOWN,
2948 // Contains(registers, Pc) => FORBIDDEN_OPERANDS],
2949 // small_imm_base_wb: wback,
2950 // uses: {Rn},
2951 // violations: [implied by 'base'],
2952 // wback: W(21)=1}
2953 Register LDMDB_LDMEA_cccc100100w1nnnnrrrrrrrrrrrrrrrr_case_0::
base_address_register(Instruction inst) const2954 base_address_register(Instruction inst) const {
2955 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2956 // base: 'inst(19:16)'
2957 return Register(((inst.Bits() & 0x000F0000) >> 16));
2958 }
2959
2960 RegisterList LDMDB_LDMEA_cccc100100w1nnnnrrrrrrrrrrrrrrrr_case_0::
defs(Instruction inst) const2961 defs(Instruction inst) const {
2962 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2963 // defs: 'Union({inst(19:16)
2964 // if inst(21)=1
2965 // else 32}, RegisterList(inst(15:0)))'
2966 return nacl_arm_dec::Union(RegisterList().
2967 Add(Register(((inst.Bits() & 0x00200000) ==
2968 0x00200000
2969 ? ((inst.Bits() & 0x000F0000) >> 16)
2970 : 32))), nacl_arm_dec::RegisterList((inst.Bits() & 0x0000FFFF)));
2971 }
2972
2973 SafetyLevel LDMDB_LDMEA_cccc100100w1nnnnrrrrrrrrrrrrrrrr_case_0::
safety(Instruction inst) const2974 safety(Instruction inst) const {
2975 UNREFERENCED_PARAMETER(inst); // To silence compiler.
2976
2977 // 15 ==
2978 // inst(19:16) ||
2979 // NumGPRs(RegisterList(inst(15:0))) <
2980 // 1 => UNPREDICTABLE
2981 if ((((((inst.Bits() & 0x000F0000) >> 16)) == (15))) ||
2982 (((nacl_arm_dec::NumGPRs(nacl_arm_dec::RegisterList((inst.Bits() & 0x0000FFFF)))) < (1))))
2983 return UNPREDICTABLE;
2984
2985 // inst(21)=1 &&
2986 // Contains(RegisterList(inst(15:0)), inst(19:16)) => UNKNOWN
2987 if (((inst.Bits() & 0x00200000) ==
2988 0x00200000) &&
2989 (nacl_arm_dec::Contains(nacl_arm_dec::RegisterList((inst.Bits() & 0x0000FFFF)), Register(((inst.Bits() & 0x000F0000) >> 16)))))
2990 return UNKNOWN;
2991
2992 // Contains(RegisterList(inst(15:0)), 15) => FORBIDDEN_OPERANDS
2993 if (nacl_arm_dec::Contains(nacl_arm_dec::RegisterList((inst.Bits() & 0x0000FFFF)), Register(15)))
2994 return FORBIDDEN_OPERANDS;
2995
2996 return MAY_BE_SAFE;
2997 }
2998
2999
3000 bool LDMDB_LDMEA_cccc100100w1nnnnrrrrrrrrrrrrrrrr_case_0::
base_address_register_writeback_small_immediate(Instruction inst) const3001 base_address_register_writeback_small_immediate(
3002 Instruction inst) const {
3003 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3004 // small_imm_base_wb: 'inst(21)=1'
3005 return (inst.Bits() & 0x00200000) ==
3006 0x00200000;
3007 }
3008
3009 RegisterList LDMDB_LDMEA_cccc100100w1nnnnrrrrrrrrrrrrrrrr_case_0::
uses(Instruction inst) const3010 uses(Instruction inst) const {
3011 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3012 // uses: '{inst(19:16)}'
3013 return RegisterList().
3014 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
3015 }
3016
3017 ViolationSet LDMDB_LDMEA_cccc100100w1nnnnrrrrrrrrrrrrrrrr_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const3018 get_violations(const nacl_arm_val::DecodedInstruction& first,
3019 const nacl_arm_val::DecodedInstruction& second,
3020 const nacl_arm_val::SfiValidator& sfi,
3021 nacl_arm_val::AddressSet* branches,
3022 nacl_arm_val::AddressSet* critical,
3023 uint32_t* next_inst_addr) const {
3024 ViolationSet violations = ClassDecoder::get_violations(
3025 first, second, sfi, branches, critical, next_inst_addr);
3026
3027 // Report unsafe loads/stores of a base address by the given instruction
3028 // pair.
3029 violations = ViolationUnion(
3030 violations, get_loadstore_violations(first, second, sfi, critical));
3031
3032 return violations;
3033 }
3034
3035
3036 // LDMIB_LDMED_cccc100110w1nnnnrrrrrrrrrrrrrrrr_case_0:
3037 //
3038 // {None: 32,
3039 // Pc: 15,
3040 // Rn: Rn(19:16),
3041 // W: W(21),
3042 // base: Rn,
3043 // cond: cond(31:28),
3044 // defs: Union({Rn
3045 // if wback
3046 // else None}, registers),
3047 // fields: [cond(31:28), W(21), Rn(19:16), register_list(15:0)],
3048 // pattern: cccc100110w1nnnnrrrrrrrrrrrrrrrr,
3049 // register_list: register_list(15:0),
3050 // registers: RegisterList(register_list),
3051 // rule: LDMIB_LDMED,
3052 // safety: [Rn ==
3053 // Pc ||
3054 // NumGPRs(registers) <
3055 // 1 => UNPREDICTABLE,
3056 // wback &&
3057 // Contains(registers, Rn) => UNKNOWN,
3058 // Contains(registers, Pc) => FORBIDDEN_OPERANDS],
3059 // small_imm_base_wb: wback,
3060 // uses: {Rn},
3061 // violations: [implied by 'base'],
3062 // wback: W(21)=1}
3063 Register LDMIB_LDMED_cccc100110w1nnnnrrrrrrrrrrrrrrrr_case_0::
base_address_register(Instruction inst) const3064 base_address_register(Instruction inst) const {
3065 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3066 // base: 'inst(19:16)'
3067 return Register(((inst.Bits() & 0x000F0000) >> 16));
3068 }
3069
3070 RegisterList LDMIB_LDMED_cccc100110w1nnnnrrrrrrrrrrrrrrrr_case_0::
defs(Instruction inst) const3071 defs(Instruction inst) const {
3072 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3073 // defs: 'Union({inst(19:16)
3074 // if inst(21)=1
3075 // else 32}, RegisterList(inst(15:0)))'
3076 return nacl_arm_dec::Union(RegisterList().
3077 Add(Register(((inst.Bits() & 0x00200000) ==
3078 0x00200000
3079 ? ((inst.Bits() & 0x000F0000) >> 16)
3080 : 32))), nacl_arm_dec::RegisterList((inst.Bits() & 0x0000FFFF)));
3081 }
3082
3083 SafetyLevel LDMIB_LDMED_cccc100110w1nnnnrrrrrrrrrrrrrrrr_case_0::
safety(Instruction inst) const3084 safety(Instruction inst) const {
3085 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3086
3087 // 15 ==
3088 // inst(19:16) ||
3089 // NumGPRs(RegisterList(inst(15:0))) <
3090 // 1 => UNPREDICTABLE
3091 if ((((((inst.Bits() & 0x000F0000) >> 16)) == (15))) ||
3092 (((nacl_arm_dec::NumGPRs(nacl_arm_dec::RegisterList((inst.Bits() & 0x0000FFFF)))) < (1))))
3093 return UNPREDICTABLE;
3094
3095 // inst(21)=1 &&
3096 // Contains(RegisterList(inst(15:0)), inst(19:16)) => UNKNOWN
3097 if (((inst.Bits() & 0x00200000) ==
3098 0x00200000) &&
3099 (nacl_arm_dec::Contains(nacl_arm_dec::RegisterList((inst.Bits() & 0x0000FFFF)), Register(((inst.Bits() & 0x000F0000) >> 16)))))
3100 return UNKNOWN;
3101
3102 // Contains(RegisterList(inst(15:0)), 15) => FORBIDDEN_OPERANDS
3103 if (nacl_arm_dec::Contains(nacl_arm_dec::RegisterList((inst.Bits() & 0x0000FFFF)), Register(15)))
3104 return FORBIDDEN_OPERANDS;
3105
3106 return MAY_BE_SAFE;
3107 }
3108
3109
3110 bool LDMIB_LDMED_cccc100110w1nnnnrrrrrrrrrrrrrrrr_case_0::
base_address_register_writeback_small_immediate(Instruction inst) const3111 base_address_register_writeback_small_immediate(
3112 Instruction inst) const {
3113 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3114 // small_imm_base_wb: 'inst(21)=1'
3115 return (inst.Bits() & 0x00200000) ==
3116 0x00200000;
3117 }
3118
3119 RegisterList LDMIB_LDMED_cccc100110w1nnnnrrrrrrrrrrrrrrrr_case_0::
uses(Instruction inst) const3120 uses(Instruction inst) const {
3121 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3122 // uses: '{inst(19:16)}'
3123 return RegisterList().
3124 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
3125 }
3126
3127 ViolationSet LDMIB_LDMED_cccc100110w1nnnnrrrrrrrrrrrrrrrr_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const3128 get_violations(const nacl_arm_val::DecodedInstruction& first,
3129 const nacl_arm_val::DecodedInstruction& second,
3130 const nacl_arm_val::SfiValidator& sfi,
3131 nacl_arm_val::AddressSet* branches,
3132 nacl_arm_val::AddressSet* critical,
3133 uint32_t* next_inst_addr) const {
3134 ViolationSet violations = ClassDecoder::get_violations(
3135 first, second, sfi, branches, critical, next_inst_addr);
3136
3137 // Report unsafe loads/stores of a base address by the given instruction
3138 // pair.
3139 violations = ViolationUnion(
3140 violations, get_loadstore_violations(first, second, sfi, critical));
3141
3142 return violations;
3143 }
3144
3145
3146 // LDM_LDMIA_LDMFD_cccc100010w1nnnnrrrrrrrrrrrrrrrr_case_0:
3147 //
3148 // {None: 32,
3149 // Pc: 15,
3150 // Rn: Rn(19:16),
3151 // W: W(21),
3152 // base: Rn,
3153 // cond: cond(31:28),
3154 // defs: Union({Rn
3155 // if wback
3156 // else None}, registers),
3157 // fields: [cond(31:28), W(21), Rn(19:16), register_list(15:0)],
3158 // pattern: cccc100010w1nnnnrrrrrrrrrrrrrrrr,
3159 // register_list: register_list(15:0),
3160 // registers: RegisterList(register_list),
3161 // rule: LDM_LDMIA_LDMFD,
3162 // safety: [Rn ==
3163 // Pc ||
3164 // NumGPRs(registers) <
3165 // 1 => UNPREDICTABLE,
3166 // wback &&
3167 // Contains(registers, Rn) => UNKNOWN,
3168 // Contains(registers, Pc) => FORBIDDEN_OPERANDS],
3169 // small_imm_base_wb: wback,
3170 // uses: {Rn},
3171 // violations: [implied by 'base'],
3172 // wback: W(21)=1}
3173 Register LDM_LDMIA_LDMFD_cccc100010w1nnnnrrrrrrrrrrrrrrrr_case_0::
base_address_register(Instruction inst) const3174 base_address_register(Instruction inst) const {
3175 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3176 // base: 'inst(19:16)'
3177 return Register(((inst.Bits() & 0x000F0000) >> 16));
3178 }
3179
3180 RegisterList LDM_LDMIA_LDMFD_cccc100010w1nnnnrrrrrrrrrrrrrrrr_case_0::
defs(Instruction inst) const3181 defs(Instruction inst) const {
3182 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3183 // defs: 'Union({inst(19:16)
3184 // if inst(21)=1
3185 // else 32}, RegisterList(inst(15:0)))'
3186 return nacl_arm_dec::Union(RegisterList().
3187 Add(Register(((inst.Bits() & 0x00200000) ==
3188 0x00200000
3189 ? ((inst.Bits() & 0x000F0000) >> 16)
3190 : 32))), nacl_arm_dec::RegisterList((inst.Bits() & 0x0000FFFF)));
3191 }
3192
3193 SafetyLevel LDM_LDMIA_LDMFD_cccc100010w1nnnnrrrrrrrrrrrrrrrr_case_0::
safety(Instruction inst) const3194 safety(Instruction inst) const {
3195 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3196
3197 // 15 ==
3198 // inst(19:16) ||
3199 // NumGPRs(RegisterList(inst(15:0))) <
3200 // 1 => UNPREDICTABLE
3201 if ((((((inst.Bits() & 0x000F0000) >> 16)) == (15))) ||
3202 (((nacl_arm_dec::NumGPRs(nacl_arm_dec::RegisterList((inst.Bits() & 0x0000FFFF)))) < (1))))
3203 return UNPREDICTABLE;
3204
3205 // inst(21)=1 &&
3206 // Contains(RegisterList(inst(15:0)), inst(19:16)) => UNKNOWN
3207 if (((inst.Bits() & 0x00200000) ==
3208 0x00200000) &&
3209 (nacl_arm_dec::Contains(nacl_arm_dec::RegisterList((inst.Bits() & 0x0000FFFF)), Register(((inst.Bits() & 0x000F0000) >> 16)))))
3210 return UNKNOWN;
3211
3212 // Contains(RegisterList(inst(15:0)), 15) => FORBIDDEN_OPERANDS
3213 if (nacl_arm_dec::Contains(nacl_arm_dec::RegisterList((inst.Bits() & 0x0000FFFF)), Register(15)))
3214 return FORBIDDEN_OPERANDS;
3215
3216 return MAY_BE_SAFE;
3217 }
3218
3219
3220 bool LDM_LDMIA_LDMFD_cccc100010w1nnnnrrrrrrrrrrrrrrrr_case_0::
base_address_register_writeback_small_immediate(Instruction inst) const3221 base_address_register_writeback_small_immediate(
3222 Instruction inst) const {
3223 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3224 // small_imm_base_wb: 'inst(21)=1'
3225 return (inst.Bits() & 0x00200000) ==
3226 0x00200000;
3227 }
3228
3229 RegisterList LDM_LDMIA_LDMFD_cccc100010w1nnnnrrrrrrrrrrrrrrrr_case_0::
uses(Instruction inst) const3230 uses(Instruction inst) const {
3231 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3232 // uses: '{inst(19:16)}'
3233 return RegisterList().
3234 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
3235 }
3236
3237 ViolationSet LDM_LDMIA_LDMFD_cccc100010w1nnnnrrrrrrrrrrrrrrrr_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const3238 get_violations(const nacl_arm_val::DecodedInstruction& first,
3239 const nacl_arm_val::DecodedInstruction& second,
3240 const nacl_arm_val::SfiValidator& sfi,
3241 nacl_arm_val::AddressSet* branches,
3242 nacl_arm_val::AddressSet* critical,
3243 uint32_t* next_inst_addr) const {
3244 ViolationSet violations = ClassDecoder::get_violations(
3245 first, second, sfi, branches, critical, next_inst_addr);
3246
3247 // Report unsafe loads/stores of a base address by the given instruction
3248 // pair.
3249 violations = ViolationUnion(
3250 violations, get_loadstore_violations(first, second, sfi, critical));
3251
3252 return violations;
3253 }
3254
3255
3256 // LDM_User_registers_cccc100pu101nnnn0rrrrrrrrrrrrrrr_case_0:
3257 //
3258 // {defs: {},
3259 // pattern: cccc100pu101nnnn0rrrrrrrrrrrrrrr,
3260 // rule: LDM_User_registers,
3261 // safety: [true => FORBIDDEN],
3262 // true: true,
3263 // uses: {}}
3264 RegisterList LDM_User_registers_cccc100pu101nnnn0rrrrrrrrrrrrrrr_case_0::
defs(Instruction inst) const3265 defs(Instruction inst) const {
3266 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3267 // defs: '{}'
3268 return RegisterList();
3269 }
3270
3271 SafetyLevel LDM_User_registers_cccc100pu101nnnn0rrrrrrrrrrrrrrr_case_0::
safety(Instruction inst) const3272 safety(Instruction inst) const {
3273 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3274
3275 // true => FORBIDDEN
3276 if (true)
3277 return FORBIDDEN;
3278
3279 return MAY_BE_SAFE;
3280 }
3281
3282
3283 RegisterList LDM_User_registers_cccc100pu101nnnn0rrrrrrrrrrrrrrr_case_0::
uses(Instruction inst) const3284 uses(Instruction inst) const {
3285 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3286 // uses: '{}'
3287 return RegisterList();
3288 }
3289
3290 // LDM_exception_return_cccc100pu1w1nnnn1rrrrrrrrrrrrrrr_case_0:
3291 //
3292 // {defs: {},
3293 // pattern: cccc100pu1w1nnnn1rrrrrrrrrrrrrrr,
3294 // rule: LDM_exception_return,
3295 // safety: [true => FORBIDDEN],
3296 // true: true,
3297 // uses: {}}
3298 RegisterList LDM_exception_return_cccc100pu1w1nnnn1rrrrrrrrrrrrrrr_case_0::
defs(Instruction inst) const3299 defs(Instruction inst) const {
3300 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3301 // defs: '{}'
3302 return RegisterList();
3303 }
3304
3305 SafetyLevel LDM_exception_return_cccc100pu1w1nnnn1rrrrrrrrrrrrrrr_case_0::
safety(Instruction inst) const3306 safety(Instruction inst) const {
3307 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3308
3309 // true => FORBIDDEN
3310 if (true)
3311 return FORBIDDEN;
3312
3313 return MAY_BE_SAFE;
3314 }
3315
3316
3317 RegisterList LDM_exception_return_cccc100pu1w1nnnn1rrrrrrrrrrrrrrr_case_0::
uses(Instruction inst) const3318 uses(Instruction inst) const {
3319 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3320 // uses: '{}'
3321 return RegisterList();
3322 }
3323
3324 // LDRBT_A1_cccc0100u111nnnnttttiiiiiiiiiiii_case_0:
3325 //
3326 // {defs: {},
3327 // pattern: cccc0100u111nnnnttttiiiiiiiiiiii,
3328 // rule: LDRBT_A1,
3329 // safety: [true => FORBIDDEN],
3330 // true: true,
3331 // uses: {}}
3332 RegisterList LDRBT_A1_cccc0100u111nnnnttttiiiiiiiiiiii_case_0::
defs(Instruction inst) const3333 defs(Instruction inst) const {
3334 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3335 // defs: '{}'
3336 return RegisterList();
3337 }
3338
3339 SafetyLevel LDRBT_A1_cccc0100u111nnnnttttiiiiiiiiiiii_case_0::
safety(Instruction inst) const3340 safety(Instruction inst) const {
3341 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3342
3343 // true => FORBIDDEN
3344 if (true)
3345 return FORBIDDEN;
3346
3347 return MAY_BE_SAFE;
3348 }
3349
3350
3351 RegisterList LDRBT_A1_cccc0100u111nnnnttttiiiiiiiiiiii_case_0::
uses(Instruction inst) const3352 uses(Instruction inst) const {
3353 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3354 // uses: '{}'
3355 return RegisterList();
3356 }
3357
3358 // LDRBT_A2_cccc0110u111nnnnttttiiiiitt0mmmm_case_0:
3359 //
3360 // {defs: {},
3361 // pattern: cccc0110u111nnnnttttiiiiitt0mmmm,
3362 // rule: LDRBT_A2,
3363 // safety: [true => FORBIDDEN],
3364 // true: true,
3365 // uses: {}}
3366 RegisterList LDRBT_A2_cccc0110u111nnnnttttiiiiitt0mmmm_case_0::
defs(Instruction inst) const3367 defs(Instruction inst) const {
3368 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3369 // defs: '{}'
3370 return RegisterList();
3371 }
3372
3373 SafetyLevel LDRBT_A2_cccc0110u111nnnnttttiiiiitt0mmmm_case_0::
safety(Instruction inst) const3374 safety(Instruction inst) const {
3375 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3376
3377 // true => FORBIDDEN
3378 if (true)
3379 return FORBIDDEN;
3380
3381 return MAY_BE_SAFE;
3382 }
3383
3384
3385 RegisterList LDRBT_A2_cccc0110u111nnnnttttiiiiitt0mmmm_case_0::
uses(Instruction inst) const3386 uses(Instruction inst) const {
3387 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3388 // uses: '{}'
3389 return RegisterList();
3390 }
3391
3392 // LDRB_immediate_cccc010pu1w1nnnnttttiiiiiiiiiiii_case_0:
3393 //
3394 // {None: 32,
3395 // P: P(24),
3396 // Pc: 15,
3397 // Rn: Rn(19:16),
3398 // Rt: Rt(15:12),
3399 // U: U(23),
3400 // W: W(21),
3401 // add: U(23)=1,
3402 // base: Rn,
3403 // cond: cond(31:28),
3404 // defs: {Rt, base
3405 // if wback
3406 // else None},
3407 // fields: [cond(31:28),
3408 // P(24),
3409 // U(23),
3410 // W(21),
3411 // Rn(19:16),
3412 // Rt(15:12),
3413 // imm12(11:0)],
3414 // imm12: imm12(11:0),
3415 // imm32: ZeroExtend(imm12, 32),
3416 // index: P(24)=1,
3417 // pattern: cccc010pu1w1nnnnttttiiiiiiiiiiii,
3418 // rule: LDRB_immediate,
3419 // safety: [Rn ==
3420 // Pc => DECODER_ERROR,
3421 // P(24)=0 &&
3422 // W(21)=1 => DECODER_ERROR,
3423 // Rt ==
3424 // Pc => UNPREDICTABLE,
3425 // wback &&
3426 // Rn ==
3427 // Rt => UNPREDICTABLE],
3428 // small_imm_base_wb: wback,
3429 // uses: {Rn},
3430 // violations: [implied by 'base'],
3431 // wback: P(24)=0 ||
3432 // W(21)=1}
3433 Register LDRB_immediate_cccc010pu1w1nnnnttttiiiiiiiiiiii_case_0::
base_address_register(Instruction inst) const3434 base_address_register(Instruction inst) const {
3435 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3436 // base: 'inst(19:16)'
3437 return Register(((inst.Bits() & 0x000F0000) >> 16));
3438 }
3439
3440 RegisterList LDRB_immediate_cccc010pu1w1nnnnttttiiiiiiiiiiii_case_0::
defs(Instruction inst) const3441 defs(Instruction inst) const {
3442 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3443 // defs: '{inst(15:12), inst(19:16)
3444 // if inst(24)=0 ||
3445 // inst(21)=1
3446 // else 32}'
3447 return RegisterList().
3448 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
3449 Add(Register((((inst.Bits() & 0x01000000) ==
3450 0x00000000) ||
3451 ((inst.Bits() & 0x00200000) ==
3452 0x00200000)
3453 ? ((inst.Bits() & 0x000F0000) >> 16)
3454 : 32)));
3455 }
3456
3457 SafetyLevel LDRB_immediate_cccc010pu1w1nnnnttttiiiiiiiiiiii_case_0::
safety(Instruction inst) const3458 safety(Instruction inst) const {
3459 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3460
3461 // 15 ==
3462 // inst(19:16) => DECODER_ERROR
3463 if (((((inst.Bits() & 0x000F0000) >> 16)) == (15)))
3464 return DECODER_ERROR;
3465
3466 // inst(24)=0 &&
3467 // inst(21)=1 => DECODER_ERROR
3468 if (((inst.Bits() & 0x01000000) ==
3469 0x00000000) &&
3470 ((inst.Bits() & 0x00200000) ==
3471 0x00200000))
3472 return DECODER_ERROR;
3473
3474 // 15 ==
3475 // inst(15:12) => UNPREDICTABLE
3476 if (((((inst.Bits() & 0x0000F000) >> 12)) == (15)))
3477 return UNPREDICTABLE;
3478
3479 // inst(24)=0 ||
3480 // inst(21)=1 &&
3481 // inst(15:12) ==
3482 // inst(19:16) => UNPREDICTABLE
3483 if ((((inst.Bits() & 0x01000000) ==
3484 0x00000000) ||
3485 ((inst.Bits() & 0x00200000) ==
3486 0x00200000)) &&
3487 (((((inst.Bits() & 0x000F0000) >> 16)) == (((inst.Bits() & 0x0000F000) >> 12)))))
3488 return UNPREDICTABLE;
3489
3490 return MAY_BE_SAFE;
3491 }
3492
3493
3494 bool LDRB_immediate_cccc010pu1w1nnnnttttiiiiiiiiiiii_case_0::
base_address_register_writeback_small_immediate(Instruction inst) const3495 base_address_register_writeback_small_immediate(
3496 Instruction inst) const {
3497 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3498 // small_imm_base_wb: 'inst(24)=0 ||
3499 // inst(21)=1'
3500 return ((inst.Bits() & 0x01000000) ==
3501 0x00000000) ||
3502 ((inst.Bits() & 0x00200000) ==
3503 0x00200000);
3504 }
3505
3506 RegisterList LDRB_immediate_cccc010pu1w1nnnnttttiiiiiiiiiiii_case_0::
uses(Instruction inst) const3507 uses(Instruction inst) const {
3508 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3509 // uses: '{inst(19:16)}'
3510 return RegisterList().
3511 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
3512 }
3513
3514 ViolationSet LDRB_immediate_cccc010pu1w1nnnnttttiiiiiiiiiiii_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const3515 get_violations(const nacl_arm_val::DecodedInstruction& first,
3516 const nacl_arm_val::DecodedInstruction& second,
3517 const nacl_arm_val::SfiValidator& sfi,
3518 nacl_arm_val::AddressSet* branches,
3519 nacl_arm_val::AddressSet* critical,
3520 uint32_t* next_inst_addr) const {
3521 ViolationSet violations = ClassDecoder::get_violations(
3522 first, second, sfi, branches, critical, next_inst_addr);
3523
3524 // Report unsafe loads/stores of a base address by the given instruction
3525 // pair.
3526 violations = ViolationUnion(
3527 violations, get_loadstore_violations(first, second, sfi, critical));
3528
3529 return violations;
3530 }
3531
3532
3533 // LDRB_literal_cccc0101u1011111ttttiiiiiiiiiiii_case_0:
3534 //
3535 // {Pc: 15,
3536 // Rt: Rt(15:12),
3537 // U: U(23),
3538 // add: U(23)=1,
3539 // base: Pc,
3540 // cond: cond(31:28),
3541 // defs: {Rt},
3542 // fields: [cond(31:28), U(23), Rt(15:12), imm12(11:0)],
3543 // imm12: imm12(11:0),
3544 // imm32: ZeroExtend(imm12, 32),
3545 // is_literal_load: true,
3546 // pattern: cccc0101u1011111ttttiiiiiiiiiiii,
3547 // rule: LDRB_literal,
3548 // safety: [Rt ==
3549 // Pc => UNPREDICTABLE],
3550 // true: true,
3551 // uses: {Pc},
3552 // violations: [implied by 'base']}
3553 Register LDRB_literal_cccc0101u1011111ttttiiiiiiiiiiii_case_0::
base_address_register(Instruction inst) const3554 base_address_register(Instruction inst) const {
3555 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3556 // base: '15'
3557 return Register(15);
3558 }
3559
3560 RegisterList LDRB_literal_cccc0101u1011111ttttiiiiiiiiiiii_case_0::
defs(Instruction inst) const3561 defs(Instruction inst) const {
3562 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3563 // defs: '{inst(15:12)}'
3564 return RegisterList().
3565 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
3566 }
3567
3568 bool LDRB_literal_cccc0101u1011111ttttiiiiiiiiiiii_case_0::
is_literal_load(Instruction inst) const3569 is_literal_load(Instruction inst) const {
3570 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3571 // is_literal_load: 'true'
3572 return true;
3573 }
3574
3575 SafetyLevel LDRB_literal_cccc0101u1011111ttttiiiiiiiiiiii_case_0::
safety(Instruction inst) const3576 safety(Instruction inst) const {
3577 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3578
3579 // 15 ==
3580 // inst(15:12) => UNPREDICTABLE
3581 if (((((inst.Bits() & 0x0000F000) >> 12)) == (15)))
3582 return UNPREDICTABLE;
3583
3584 return MAY_BE_SAFE;
3585 }
3586
3587
3588 RegisterList LDRB_literal_cccc0101u1011111ttttiiiiiiiiiiii_case_0::
uses(Instruction inst) const3589 uses(Instruction inst) const {
3590 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3591 // uses: '{15}'
3592 return RegisterList().
3593 Add(Register(15));
3594 }
3595
3596 ViolationSet LDRB_literal_cccc0101u1011111ttttiiiiiiiiiiii_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const3597 get_violations(const nacl_arm_val::DecodedInstruction& first,
3598 const nacl_arm_val::DecodedInstruction& second,
3599 const nacl_arm_val::SfiValidator& sfi,
3600 nacl_arm_val::AddressSet* branches,
3601 nacl_arm_val::AddressSet* critical,
3602 uint32_t* next_inst_addr) const {
3603 ViolationSet violations = ClassDecoder::get_violations(
3604 first, second, sfi, branches, critical, next_inst_addr);
3605
3606 // Report unsafe loads/stores of a base address by the given instruction
3607 // pair.
3608 violations = ViolationUnion(
3609 violations, get_loadstore_violations(first, second, sfi, critical));
3610
3611 return violations;
3612 }
3613
3614
3615 // LDRB_register_cccc011pu1w1nnnnttttiiiiitt0mmmm_case_0:
3616 //
3617 // {None: 32,
3618 // P: P(24),
3619 // Pc: 15,
3620 // Rm: Rm(3:0),
3621 // Rn: Rn(19:16),
3622 // Rt: Rt(15:12),
3623 // U: U(23),
3624 // W: W(21),
3625 // add: U(23)=1,
3626 // base: Rn,
3627 // cond: cond(31:28),
3628 // defs: {Rt, base
3629 // if wback
3630 // else None},
3631 // fields: [cond(31:28),
3632 // P(24),
3633 // U(23),
3634 // W(21),
3635 // Rn(19:16),
3636 // Rt(15:12),
3637 // imm5(11:7),
3638 // type(6:5),
3639 // Rm(3:0)],
3640 // imm5: imm5(11:7),
3641 // index: P(24)=1,
3642 // pattern: cccc011pu1w1nnnnttttiiiiitt0mmmm,
3643 // rule: LDRB_register,
3644 // safety: [P(24)=0 &&
3645 // W(21)=1 => DECODER_ERROR,
3646 // Pc in {Rt, Rm} => UNPREDICTABLE,
3647 // wback &&
3648 // (Rn ==
3649 // Pc ||
3650 // Rn ==
3651 // Rt) => UNPREDICTABLE,
3652 // ArchVersion() <
3653 // 6 &&
3654 // wback &&
3655 // Rn ==
3656 // Rm => UNPREDICTABLE,
3657 // index => FORBIDDEN],
3658 // shift: DecodeImmShift(type, imm5),
3659 // type: type(6:5),
3660 // uses: {Rm, Rn},
3661 // violations: [implied by 'base'],
3662 // wback: P(24)=0 ||
3663 // W(21)=1}
3664 Register LDRB_register_cccc011pu1w1nnnnttttiiiiitt0mmmm_case_0::
base_address_register(Instruction inst) const3665 base_address_register(Instruction inst) const {
3666 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3667 // base: 'inst(19:16)'
3668 return Register(((inst.Bits() & 0x000F0000) >> 16));
3669 }
3670
3671 RegisterList LDRB_register_cccc011pu1w1nnnnttttiiiiitt0mmmm_case_0::
defs(Instruction inst) const3672 defs(Instruction inst) const {
3673 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3674 // defs: '{inst(15:12), inst(19:16)
3675 // if inst(24)=0 ||
3676 // inst(21)=1
3677 // else 32}'
3678 return RegisterList().
3679 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
3680 Add(Register((((inst.Bits() & 0x01000000) ==
3681 0x00000000) ||
3682 ((inst.Bits() & 0x00200000) ==
3683 0x00200000)
3684 ? ((inst.Bits() & 0x000F0000) >> 16)
3685 : 32)));
3686 }
3687
3688 SafetyLevel LDRB_register_cccc011pu1w1nnnnttttiiiiitt0mmmm_case_0::
safety(Instruction inst) const3689 safety(Instruction inst) const {
3690 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3691
3692 // inst(24)=0 &&
3693 // inst(21)=1 => DECODER_ERROR
3694 if (((inst.Bits() & 0x01000000) ==
3695 0x00000000) &&
3696 ((inst.Bits() & 0x00200000) ==
3697 0x00200000))
3698 return DECODER_ERROR;
3699
3700 // 15 ==
3701 // inst(15:12) ||
3702 // 15 ==
3703 // inst(3:0) => UNPREDICTABLE
3704 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
3705 (((15) == ((inst.Bits() & 0x0000000F)))))
3706 return UNPREDICTABLE;
3707
3708 // inst(24)=0 ||
3709 // inst(21)=1 &&
3710 // (15 ==
3711 // inst(19:16) ||
3712 // inst(15:12) ==
3713 // inst(19:16)) => UNPREDICTABLE
3714 if ((((inst.Bits() & 0x01000000) ==
3715 0x00000000) ||
3716 ((inst.Bits() & 0x00200000) ==
3717 0x00200000)) &&
3718 (((((((inst.Bits() & 0x000F0000) >> 16)) == (15))) ||
3719 (((((inst.Bits() & 0x000F0000) >> 16)) == (((inst.Bits() & 0x0000F000) >> 12)))))))
3720 return UNPREDICTABLE;
3721
3722 // ArchVersion() <
3723 // 6 &&
3724 // inst(24)=0 ||
3725 // inst(21)=1 &&
3726 // inst(19:16) ==
3727 // inst(3:0) => UNPREDICTABLE
3728 if ((((nacl_arm_dec::ArchVersion()) < (6))) &&
3729 (((inst.Bits() & 0x01000000) ==
3730 0x00000000) ||
3731 ((inst.Bits() & 0x00200000) ==
3732 0x00200000)) &&
3733 (((((inst.Bits() & 0x000F0000) >> 16)) == ((inst.Bits() & 0x0000000F)))))
3734 return UNPREDICTABLE;
3735
3736 // inst(24)=1 => FORBIDDEN
3737 if ((inst.Bits() & 0x01000000) ==
3738 0x01000000)
3739 return FORBIDDEN;
3740
3741 return MAY_BE_SAFE;
3742 }
3743
3744
3745 RegisterList LDRB_register_cccc011pu1w1nnnnttttiiiiitt0mmmm_case_0::
uses(Instruction inst) const3746 uses(Instruction inst) const {
3747 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3748 // uses: '{inst(3:0), inst(19:16)}'
3749 return RegisterList().
3750 Add(Register((inst.Bits() & 0x0000000F))).
3751 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
3752 }
3753
3754 ViolationSet LDRB_register_cccc011pu1w1nnnnttttiiiiitt0mmmm_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const3755 get_violations(const nacl_arm_val::DecodedInstruction& first,
3756 const nacl_arm_val::DecodedInstruction& second,
3757 const nacl_arm_val::SfiValidator& sfi,
3758 nacl_arm_val::AddressSet* branches,
3759 nacl_arm_val::AddressSet* critical,
3760 uint32_t* next_inst_addr) const {
3761 ViolationSet violations = ClassDecoder::get_violations(
3762 first, second, sfi, branches, critical, next_inst_addr);
3763
3764 // Report unsafe loads/stores of a base address by the given instruction
3765 // pair.
3766 violations = ViolationUnion(
3767 violations, get_loadstore_violations(first, second, sfi, critical));
3768
3769 return violations;
3770 }
3771
3772
3773 // LDRD_immediate_cccc000pu1w0nnnnttttiiii1101iiii_case_0:
3774 //
3775 // {None: 32,
3776 // P: P(24),
3777 // Pc: 15,
3778 // Rn: Rn(19:16),
3779 // Rt: Rt(15:12),
3780 // Rt2: Rt + 1,
3781 // U: U(23),
3782 // W: W(21),
3783 // add: U(23)=1,
3784 // address: offset_addr
3785 // if index
3786 // else Rn,
3787 // arch: v5TE,
3788 // base: Rn,
3789 // cond: cond(31:28),
3790 // defs: {Rt, Rt2, base
3791 // if wback
3792 // else None},
3793 // fields: [cond(31:28),
3794 // P(24),
3795 // U(23),
3796 // W(21),
3797 // Rn(19:16),
3798 // Rt(15:12),
3799 // imm4H(11:8),
3800 // imm4L(3:0)],
3801 // imm32: ZeroExtend(imm4H:imm4L, 32),
3802 // imm4H: imm4H(11:8),
3803 // imm4L: imm4L(3:0),
3804 // index: P(24)=1,
3805 // offset_addr: Rn + imm32
3806 // if add
3807 // else Rn - imm32,
3808 // pattern: cccc000pu1w0nnnnttttiiii1101iiii,
3809 // rule: LDRD_immediate,
3810 // safety: [Rn(19:16)=1111 => DECODER_ERROR,
3811 // Rt(0)=1 => UNPREDICTABLE,
3812 // P(24)=0 &&
3813 // W(21)=1 => UNPREDICTABLE,
3814 // wback &&
3815 // (Rn ==
3816 // Rt ||
3817 // Rn ==
3818 // Rt2) => UNPREDICTABLE,
3819 // Rt2 ==
3820 // Pc => UNPREDICTABLE],
3821 // small_imm_base_wb: wback,
3822 // uses: {Rn},
3823 // violations: [implied by 'base'],
3824 // wback: (P(24)=0) ||
3825 // (W(21)=1)}
3826 Register LDRD_immediate_cccc000pu1w0nnnnttttiiii1101iiii_case_0::
base_address_register(Instruction inst) const3827 base_address_register(Instruction inst) const {
3828 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3829 // base: 'inst(19:16)'
3830 return Register(((inst.Bits() & 0x000F0000) >> 16));
3831 }
3832
3833 RegisterList LDRD_immediate_cccc000pu1w0nnnnttttiiii1101iiii_case_0::
defs(Instruction inst) const3834 defs(Instruction inst) const {
3835 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3836 // defs: '{inst(15:12), inst(15:12) + 1, inst(19:16)
3837 // if (inst(24)=0) ||
3838 // (inst(21)=1)
3839 // else 32}'
3840 return RegisterList().
3841 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
3842 Add(Register(((inst.Bits() & 0x0000F000) >> 12) + 1)).
3843 Add(Register(((((inst.Bits() & 0x01000000) ==
3844 0x00000000)) ||
3845 (((inst.Bits() & 0x00200000) ==
3846 0x00200000))
3847 ? ((inst.Bits() & 0x000F0000) >> 16)
3848 : 32)));
3849 }
3850
3851 SafetyLevel LDRD_immediate_cccc000pu1w0nnnnttttiiii1101iiii_case_0::
safety(Instruction inst) const3852 safety(Instruction inst) const {
3853 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3854
3855 // inst(19:16)=1111 => DECODER_ERROR
3856 if ((inst.Bits() & 0x000F0000) ==
3857 0x000F0000)
3858 return DECODER_ERROR;
3859
3860 // inst(15:12)(0)=1 => UNPREDICTABLE
3861 if ((((inst.Bits() & 0x0000F000) >> 12) & 0x00000001) ==
3862 0x00000001)
3863 return UNPREDICTABLE;
3864
3865 // inst(24)=0 &&
3866 // inst(21)=1 => UNPREDICTABLE
3867 if (((inst.Bits() & 0x01000000) ==
3868 0x00000000) &&
3869 ((inst.Bits() & 0x00200000) ==
3870 0x00200000))
3871 return UNPREDICTABLE;
3872
3873 // (inst(24)=0) ||
3874 // (inst(21)=1) &&
3875 // (inst(15:12) ==
3876 // inst(19:16) ||
3877 // inst(15:12) + 1 ==
3878 // inst(19:16)) => UNPREDICTABLE
3879 if (((((inst.Bits() & 0x01000000) ==
3880 0x00000000)) ||
3881 (((inst.Bits() & 0x00200000) ==
3882 0x00200000))) &&
3883 (((((((inst.Bits() & 0x000F0000) >> 16)) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
3884 (((((inst.Bits() & 0x000F0000) >> 16)) == (((inst.Bits() & 0x0000F000) >> 12) + 1))))))
3885 return UNPREDICTABLE;
3886
3887 // 15 ==
3888 // inst(15:12) + 1 => UNPREDICTABLE
3889 if (((((inst.Bits() & 0x0000F000) >> 12) + 1) == (15)))
3890 return UNPREDICTABLE;
3891
3892 return MAY_BE_SAFE;
3893 }
3894
3895
3896 bool LDRD_immediate_cccc000pu1w0nnnnttttiiii1101iiii_case_0::
base_address_register_writeback_small_immediate(Instruction inst) const3897 base_address_register_writeback_small_immediate(
3898 Instruction inst) const {
3899 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3900 // small_imm_base_wb: '(inst(24)=0) ||
3901 // (inst(21)=1)'
3902 return (((inst.Bits() & 0x01000000) ==
3903 0x00000000)) ||
3904 (((inst.Bits() & 0x00200000) ==
3905 0x00200000));
3906 }
3907
3908 RegisterList LDRD_immediate_cccc000pu1w0nnnnttttiiii1101iiii_case_0::
uses(Instruction inst) const3909 uses(Instruction inst) const {
3910 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3911 // uses: '{inst(19:16)}'
3912 return RegisterList().
3913 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
3914 }
3915
3916 ViolationSet LDRD_immediate_cccc000pu1w0nnnnttttiiii1101iiii_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const3917 get_violations(const nacl_arm_val::DecodedInstruction& first,
3918 const nacl_arm_val::DecodedInstruction& second,
3919 const nacl_arm_val::SfiValidator& sfi,
3920 nacl_arm_val::AddressSet* branches,
3921 nacl_arm_val::AddressSet* critical,
3922 uint32_t* next_inst_addr) const {
3923 ViolationSet violations = ClassDecoder::get_violations(
3924 first, second, sfi, branches, critical, next_inst_addr);
3925
3926 // Report unsafe loads/stores of a base address by the given instruction
3927 // pair.
3928 violations = ViolationUnion(
3929 violations, get_loadstore_violations(first, second, sfi, critical));
3930
3931 return violations;
3932 }
3933
3934
3935 // LDRD_literal_cccc0001u1001111ttttiiii1101iiii_case_0:
3936 //
3937 // {P: P(24),
3938 // Pc: 15,
3939 // Rt: Rt(15:12),
3940 // Rt2: Rt + 1,
3941 // U: U(23),
3942 // W: W(21),
3943 // add: U(23)=1,
3944 // arch: v5TE,
3945 // base: Pc,
3946 // cond: cond(31:28),
3947 // defs: {Rt, Rt2},
3948 // fields: [cond(31:28),
3949 // P(24),
3950 // U(23),
3951 // W(21),
3952 // Rt(15:12),
3953 // imm4H(11:8),
3954 // imm4L(3:0)],
3955 // imm32: ZeroExtend(imm4H:imm4L, 32),
3956 // imm4H: imm4H(11:8),
3957 // imm4L: imm4L(3:0),
3958 // is_literal_load: true,
3959 // pattern: cccc0001u1001111ttttiiii1101iiii,
3960 // rule: LDRD_literal,
3961 // safety: [Rt(0)=1 => UNPREDICTABLE,
3962 // Rt2 ==
3963 // Pc => UNPREDICTABLE],
3964 // true: true,
3965 // uses: {Pc},
3966 // violations: [implied by 'base']}
3967 Register LDRD_literal_cccc0001u1001111ttttiiii1101iiii_case_0::
base_address_register(Instruction inst) const3968 base_address_register(Instruction inst) const {
3969 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3970 // base: '15'
3971 return Register(15);
3972 }
3973
3974 RegisterList LDRD_literal_cccc0001u1001111ttttiiii1101iiii_case_0::
defs(Instruction inst) const3975 defs(Instruction inst) const {
3976 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3977 // defs: '{inst(15:12), inst(15:12) + 1}'
3978 return RegisterList().
3979 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
3980 Add(Register(((inst.Bits() & 0x0000F000) >> 12) + 1));
3981 }
3982
3983 bool LDRD_literal_cccc0001u1001111ttttiiii1101iiii_case_0::
is_literal_load(Instruction inst) const3984 is_literal_load(Instruction inst) const {
3985 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3986 // is_literal_load: 'true'
3987 return true;
3988 }
3989
3990 SafetyLevel LDRD_literal_cccc0001u1001111ttttiiii1101iiii_case_0::
safety(Instruction inst) const3991 safety(Instruction inst) const {
3992 UNREFERENCED_PARAMETER(inst); // To silence compiler.
3993
3994 // inst(15:12)(0)=1 => UNPREDICTABLE
3995 if ((((inst.Bits() & 0x0000F000) >> 12) & 0x00000001) ==
3996 0x00000001)
3997 return UNPREDICTABLE;
3998
3999 // 15 ==
4000 // inst(15:12) + 1 => UNPREDICTABLE
4001 if (((((inst.Bits() & 0x0000F000) >> 12) + 1) == (15)))
4002 return UNPREDICTABLE;
4003
4004 return MAY_BE_SAFE;
4005 }
4006
4007
4008 RegisterList LDRD_literal_cccc0001u1001111ttttiiii1101iiii_case_0::
uses(Instruction inst) const4009 uses(Instruction inst) const {
4010 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4011 // uses: '{15}'
4012 return RegisterList().
4013 Add(Register(15));
4014 }
4015
4016 ViolationSet LDRD_literal_cccc0001u1001111ttttiiii1101iiii_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const4017 get_violations(const nacl_arm_val::DecodedInstruction& first,
4018 const nacl_arm_val::DecodedInstruction& second,
4019 const nacl_arm_val::SfiValidator& sfi,
4020 nacl_arm_val::AddressSet* branches,
4021 nacl_arm_val::AddressSet* critical,
4022 uint32_t* next_inst_addr) const {
4023 ViolationSet violations = ClassDecoder::get_violations(
4024 first, second, sfi, branches, critical, next_inst_addr);
4025
4026 // Report unsafe loads/stores of a base address by the given instruction
4027 // pair.
4028 violations = ViolationUnion(
4029 violations, get_loadstore_violations(first, second, sfi, critical));
4030
4031 return violations;
4032 }
4033
4034
4035 // LDRD_register_cccc000pu0w0nnnntttt00001101mmmm_case_0:
4036 //
4037 // {None: 32,
4038 // P: P(24),
4039 // Pc: 15,
4040 // Rm: Rm(3:0),
4041 // Rn: Rn(19:16),
4042 // Rt: Rt(15:12),
4043 // Rt2: Rt + 1,
4044 // U: U(23),
4045 // W: W(21),
4046 // add: U(23)=1,
4047 // arch: v5TE,
4048 // base: Rn,
4049 // cond: cond(31:28),
4050 // defs: {Rt, Rt2, base
4051 // if wback
4052 // else None},
4053 // fields: [cond(31:28),
4054 // P(24),
4055 // U(23),
4056 // W(21),
4057 // Rn(19:16),
4058 // Rt(15:12),
4059 // Rm(3:0)],
4060 // index: P(24)=1,
4061 // pattern: cccc000pu0w0nnnntttt00001101mmmm,
4062 // rule: LDRD_register,
4063 // safety: [Rt(0)=1 => UNPREDICTABLE,
4064 // P(24)=0 &&
4065 // W(21)=1 => UNPREDICTABLE,
4066 // Rt2 ==
4067 // Pc ||
4068 // Rm ==
4069 // Pc ||
4070 // Rm ==
4071 // Rt ||
4072 // Rm ==
4073 // Rt2 => UNPREDICTABLE,
4074 // wback &&
4075 // (Rn ==
4076 // Pc ||
4077 // Rn ==
4078 // Rt ||
4079 // Rn ==
4080 // Rt2) => UNPREDICTABLE,
4081 // ArchVersion() <
4082 // 6 &&
4083 // wback &&
4084 // Rm ==
4085 // Rn => UNPREDICTABLE,
4086 // index => FORBIDDEN],
4087 // uses: {Rn, Rm},
4088 // violations: [implied by 'base'],
4089 // wback: (P(24)=0) ||
4090 // (W(21)=1)}
4091 Register LDRD_register_cccc000pu0w0nnnntttt00001101mmmm_case_0::
base_address_register(Instruction inst) const4092 base_address_register(Instruction inst) const {
4093 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4094 // base: 'inst(19:16)'
4095 return Register(((inst.Bits() & 0x000F0000) >> 16));
4096 }
4097
4098 RegisterList LDRD_register_cccc000pu0w0nnnntttt00001101mmmm_case_0::
defs(Instruction inst) const4099 defs(Instruction inst) const {
4100 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4101 // defs: '{inst(15:12), inst(15:12) + 1, inst(19:16)
4102 // if (inst(24)=0) ||
4103 // (inst(21)=1)
4104 // else 32}'
4105 return RegisterList().
4106 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
4107 Add(Register(((inst.Bits() & 0x0000F000) >> 12) + 1)).
4108 Add(Register(((((inst.Bits() & 0x01000000) ==
4109 0x00000000)) ||
4110 (((inst.Bits() & 0x00200000) ==
4111 0x00200000))
4112 ? ((inst.Bits() & 0x000F0000) >> 16)
4113 : 32)));
4114 }
4115
4116 SafetyLevel LDRD_register_cccc000pu0w0nnnntttt00001101mmmm_case_0::
safety(Instruction inst) const4117 safety(Instruction inst) const {
4118 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4119
4120 // inst(15:12)(0)=1 => UNPREDICTABLE
4121 if ((((inst.Bits() & 0x0000F000) >> 12) & 0x00000001) ==
4122 0x00000001)
4123 return UNPREDICTABLE;
4124
4125 // inst(24)=0 &&
4126 // inst(21)=1 => UNPREDICTABLE
4127 if (((inst.Bits() & 0x01000000) ==
4128 0x00000000) &&
4129 ((inst.Bits() & 0x00200000) ==
4130 0x00200000))
4131 return UNPREDICTABLE;
4132
4133 // 15 ==
4134 // inst(15:12) + 1 ||
4135 // 15 ==
4136 // inst(3:0) ||
4137 // inst(15:12) ==
4138 // inst(3:0) ||
4139 // inst(15:12) + 1 ==
4140 // inst(3:0) => UNPREDICTABLE
4141 if ((((((inst.Bits() & 0x0000F000) >> 12) + 1) == (15))) ||
4142 ((((inst.Bits() & 0x0000000F)) == (15))) ||
4143 ((((inst.Bits() & 0x0000000F)) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
4144 ((((inst.Bits() & 0x0000000F)) == (((inst.Bits() & 0x0000F000) >> 12) + 1))))
4145 return UNPREDICTABLE;
4146
4147 // (inst(24)=0) ||
4148 // (inst(21)=1) &&
4149 // (15 ==
4150 // inst(19:16) ||
4151 // inst(15:12) ==
4152 // inst(19:16) ||
4153 // inst(15:12) + 1 ==
4154 // inst(19:16)) => UNPREDICTABLE
4155 if (((((inst.Bits() & 0x01000000) ==
4156 0x00000000)) ||
4157 (((inst.Bits() & 0x00200000) ==
4158 0x00200000))) &&
4159 (((((((inst.Bits() & 0x000F0000) >> 16)) == (15))) ||
4160 (((((inst.Bits() & 0x000F0000) >> 16)) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
4161 (((((inst.Bits() & 0x000F0000) >> 16)) == (((inst.Bits() & 0x0000F000) >> 12) + 1))))))
4162 return UNPREDICTABLE;
4163
4164 // ArchVersion() <
4165 // 6 &&
4166 // (inst(24)=0) ||
4167 // (inst(21)=1) &&
4168 // inst(19:16) ==
4169 // inst(3:0) => UNPREDICTABLE
4170 if ((((nacl_arm_dec::ArchVersion()) < (6))) &&
4171 ((((inst.Bits() & 0x01000000) ==
4172 0x00000000)) ||
4173 (((inst.Bits() & 0x00200000) ==
4174 0x00200000))) &&
4175 ((((inst.Bits() & 0x0000000F)) == (((inst.Bits() & 0x000F0000) >> 16)))))
4176 return UNPREDICTABLE;
4177
4178 // inst(24)=1 => FORBIDDEN
4179 if ((inst.Bits() & 0x01000000) ==
4180 0x01000000)
4181 return FORBIDDEN;
4182
4183 return MAY_BE_SAFE;
4184 }
4185
4186
4187 RegisterList LDRD_register_cccc000pu0w0nnnntttt00001101mmmm_case_0::
uses(Instruction inst) const4188 uses(Instruction inst) const {
4189 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4190 // uses: '{inst(19:16), inst(3:0)}'
4191 return RegisterList().
4192 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
4193 Add(Register((inst.Bits() & 0x0000000F)));
4194 }
4195
4196 ViolationSet LDRD_register_cccc000pu0w0nnnntttt00001101mmmm_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const4197 get_violations(const nacl_arm_val::DecodedInstruction& first,
4198 const nacl_arm_val::DecodedInstruction& second,
4199 const nacl_arm_val::SfiValidator& sfi,
4200 nacl_arm_val::AddressSet* branches,
4201 nacl_arm_val::AddressSet* critical,
4202 uint32_t* next_inst_addr) const {
4203 ViolationSet violations = ClassDecoder::get_violations(
4204 first, second, sfi, branches, critical, next_inst_addr);
4205
4206 // Report unsafe loads/stores of a base address by the given instruction
4207 // pair.
4208 violations = ViolationUnion(
4209 violations, get_loadstore_violations(first, second, sfi, critical));
4210
4211 return violations;
4212 }
4213
4214
4215 // LDREXB_cccc00011101nnnntttt111110011111_case_0:
4216 //
4217 // {Pc: 15,
4218 // Rn: Rn(19:16),
4219 // Rt: Rt(15:12),
4220 // arch: v6K,
4221 // base: Rn,
4222 // cond: cond(31:28),
4223 // defs: {Rt},
4224 // fields: [cond(31:28), Rn(19:16), Rt(15:12)],
4225 // imm32: Zeros((32)),
4226 // pattern: cccc00011101nnnntttt111110011111,
4227 // rule: LDREXB,
4228 // safety: [Pc in {Rt, Rn} => UNPREDICTABLE],
4229 // uses: {Rn},
4230 // violations: [implied by 'base']}
4231 Register LDREXB_cccc00011101nnnntttt111110011111_case_0::
base_address_register(Instruction inst) const4232 base_address_register(Instruction inst) const {
4233 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4234 // base: 'inst(19:16)'
4235 return Register(((inst.Bits() & 0x000F0000) >> 16));
4236 }
4237
4238 RegisterList LDREXB_cccc00011101nnnntttt111110011111_case_0::
defs(Instruction inst) const4239 defs(Instruction inst) const {
4240 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4241 // defs: '{inst(15:12)}'
4242 return RegisterList().
4243 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
4244 }
4245
4246 SafetyLevel LDREXB_cccc00011101nnnntttt111110011111_case_0::
safety(Instruction inst) const4247 safety(Instruction inst) const {
4248 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4249
4250 // 15 ==
4251 // inst(15:12) ||
4252 // 15 ==
4253 // inst(19:16) => UNPREDICTABLE
4254 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
4255 (((15) == (((inst.Bits() & 0x000F0000) >> 16)))))
4256 return UNPREDICTABLE;
4257
4258 return MAY_BE_SAFE;
4259 }
4260
4261
4262 RegisterList LDREXB_cccc00011101nnnntttt111110011111_case_0::
uses(Instruction inst) const4263 uses(Instruction inst) const {
4264 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4265 // uses: '{inst(19:16)}'
4266 return RegisterList().
4267 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
4268 }
4269
4270 ViolationSet LDREXB_cccc00011101nnnntttt111110011111_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const4271 get_violations(const nacl_arm_val::DecodedInstruction& first,
4272 const nacl_arm_val::DecodedInstruction& second,
4273 const nacl_arm_val::SfiValidator& sfi,
4274 nacl_arm_val::AddressSet* branches,
4275 nacl_arm_val::AddressSet* critical,
4276 uint32_t* next_inst_addr) const {
4277 ViolationSet violations = ClassDecoder::get_violations(
4278 first, second, sfi, branches, critical, next_inst_addr);
4279
4280 // Report unsafe loads/stores of a base address by the given instruction
4281 // pair.
4282 violations = ViolationUnion(
4283 violations, get_loadstore_violations(first, second, sfi, critical));
4284
4285 return violations;
4286 }
4287
4288
4289 // LDREXD_cccc00011011nnnntttt111110011111_case_0:
4290 //
4291 // {Lr: 14,
4292 // Pc: 15,
4293 // Rn: Rn(19:16),
4294 // Rt: Rt(15:12),
4295 // Rt2: Rt + 1,
4296 // arch: v6K,
4297 // base: Rn,
4298 // cond: cond(31:28),
4299 // defs: {Rt, Rt2},
4300 // fields: [cond(31:28), Rn(19:16), Rt(15:12)],
4301 // imm32: Zeros((32)),
4302 // pattern: cccc00011011nnnntttt111110011111,
4303 // rule: LDREXD,
4304 // safety: [Rt(0)=1 ||
4305 // Rt ==
4306 // Lr ||
4307 // Rn ==
4308 // Pc => UNPREDICTABLE],
4309 // uses: {Rn},
4310 // violations: [implied by 'base']}
4311 Register LDREXD_cccc00011011nnnntttt111110011111_case_0::
base_address_register(Instruction inst) const4312 base_address_register(Instruction inst) const {
4313 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4314 // base: 'inst(19:16)'
4315 return Register(((inst.Bits() & 0x000F0000) >> 16));
4316 }
4317
4318 RegisterList LDREXD_cccc00011011nnnntttt111110011111_case_0::
defs(Instruction inst) const4319 defs(Instruction inst) const {
4320 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4321 // defs: '{inst(15:12), inst(15:12) + 1}'
4322 return RegisterList().
4323 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
4324 Add(Register(((inst.Bits() & 0x0000F000) >> 12) + 1));
4325 }
4326
4327 SafetyLevel LDREXD_cccc00011011nnnntttt111110011111_case_0::
safety(Instruction inst) const4328 safety(Instruction inst) const {
4329 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4330
4331 // inst(15:12)(0)=1 ||
4332 // 14 ==
4333 // inst(15:12) ||
4334 // 15 ==
4335 // inst(19:16) => UNPREDICTABLE
4336 if (((((inst.Bits() & 0x0000F000) >> 12) & 0x00000001) ==
4337 0x00000001) ||
4338 (((((inst.Bits() & 0x0000F000) >> 12)) == (14))) ||
4339 (((((inst.Bits() & 0x000F0000) >> 16)) == (15))))
4340 return UNPREDICTABLE;
4341
4342 return MAY_BE_SAFE;
4343 }
4344
4345
4346 RegisterList LDREXD_cccc00011011nnnntttt111110011111_case_0::
uses(Instruction inst) const4347 uses(Instruction inst) const {
4348 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4349 // uses: '{inst(19:16)}'
4350 return RegisterList().
4351 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
4352 }
4353
4354 ViolationSet LDREXD_cccc00011011nnnntttt111110011111_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const4355 get_violations(const nacl_arm_val::DecodedInstruction& first,
4356 const nacl_arm_val::DecodedInstruction& second,
4357 const nacl_arm_val::SfiValidator& sfi,
4358 nacl_arm_val::AddressSet* branches,
4359 nacl_arm_val::AddressSet* critical,
4360 uint32_t* next_inst_addr) const {
4361 ViolationSet violations = ClassDecoder::get_violations(
4362 first, second, sfi, branches, critical, next_inst_addr);
4363
4364 // Report unsafe loads/stores of a base address by the given instruction
4365 // pair.
4366 violations = ViolationUnion(
4367 violations, get_loadstore_violations(first, second, sfi, critical));
4368
4369 return violations;
4370 }
4371
4372
4373 // LDREX_cccc00011001nnnntttt111110011111_case_0:
4374 //
4375 // {Pc: 15,
4376 // Rn: Rn(19:16),
4377 // Rt: Rt(15:12),
4378 // arch: v6,
4379 // base: Rn,
4380 // cond: cond(31:28),
4381 // defs: {Rt},
4382 // fields: [cond(31:28), Rn(19:16), Rt(15:12)],
4383 // imm32: Zeros((32)),
4384 // pattern: cccc00011001nnnntttt111110011111,
4385 // rule: LDREX,
4386 // safety: [Pc in {Rt, Rn} => UNPREDICTABLE],
4387 // uses: {Rn},
4388 // violations: [implied by 'base']}
4389 Register LDREX_cccc00011001nnnntttt111110011111_case_0::
base_address_register(Instruction inst) const4390 base_address_register(Instruction inst) const {
4391 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4392 // base: 'inst(19:16)'
4393 return Register(((inst.Bits() & 0x000F0000) >> 16));
4394 }
4395
4396 RegisterList LDREX_cccc00011001nnnntttt111110011111_case_0::
defs(Instruction inst) const4397 defs(Instruction inst) const {
4398 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4399 // defs: '{inst(15:12)}'
4400 return RegisterList().
4401 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
4402 }
4403
4404 SafetyLevel LDREX_cccc00011001nnnntttt111110011111_case_0::
safety(Instruction inst) const4405 safety(Instruction inst) const {
4406 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4407
4408 // 15 ==
4409 // inst(15:12) ||
4410 // 15 ==
4411 // inst(19:16) => UNPREDICTABLE
4412 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
4413 (((15) == (((inst.Bits() & 0x000F0000) >> 16)))))
4414 return UNPREDICTABLE;
4415
4416 return MAY_BE_SAFE;
4417 }
4418
4419
4420 RegisterList LDREX_cccc00011001nnnntttt111110011111_case_0::
uses(Instruction inst) const4421 uses(Instruction inst) const {
4422 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4423 // uses: '{inst(19:16)}'
4424 return RegisterList().
4425 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
4426 }
4427
4428 ViolationSet LDREX_cccc00011001nnnntttt111110011111_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const4429 get_violations(const nacl_arm_val::DecodedInstruction& first,
4430 const nacl_arm_val::DecodedInstruction& second,
4431 const nacl_arm_val::SfiValidator& sfi,
4432 nacl_arm_val::AddressSet* branches,
4433 nacl_arm_val::AddressSet* critical,
4434 uint32_t* next_inst_addr) const {
4435 ViolationSet violations = ClassDecoder::get_violations(
4436 first, second, sfi, branches, critical, next_inst_addr);
4437
4438 // Report unsafe loads/stores of a base address by the given instruction
4439 // pair.
4440 violations = ViolationUnion(
4441 violations, get_loadstore_violations(first, second, sfi, critical));
4442
4443 return violations;
4444 }
4445
4446
4447 // LDRH_immediate_cccc000pu1w1nnnnttttiiii1011iiii_case_0:
4448 //
4449 // {None: 32,
4450 // P: P(24),
4451 // Pc: 15,
4452 // Rn: Rn(19:16),
4453 // Rt: Rt(15:12),
4454 // U: U(23),
4455 // W: W(21),
4456 // add: U(23)=1,
4457 // address: offset_addr
4458 // if index
4459 // else Rn,
4460 // base: Rn,
4461 // cond: cond(31:28),
4462 // defs: {Rt, base
4463 // if wback
4464 // else None},
4465 // fields: [cond(31:28),
4466 // P(24),
4467 // U(23),
4468 // W(21),
4469 // Rn(19:16),
4470 // Rt(15:12),
4471 // imm4H(11:8),
4472 // imm4L(3:0)],
4473 // imm32: ZeroExtend(imm4H:imm4L, 32),
4474 // imm4H: imm4H(11:8),
4475 // imm4L: imm4L(3:0),
4476 // index: P(24)=1,
4477 // offset_addr: Rn + imm32
4478 // if add
4479 // else Rn - imm32,
4480 // pattern: cccc000pu1w1nnnnttttiiii1011iiii,
4481 // rule: LDRH_immediate,
4482 // safety: [Rn(19:16)=1111 => DECODER_ERROR,
4483 // P(24)=0 &&
4484 // W(21)=1 => DECODER_ERROR,
4485 // Rt ==
4486 // Pc ||
4487 // (wback &&
4488 // Rn ==
4489 // Rt) => UNPREDICTABLE,
4490 // Rt ==
4491 // Pc => FORBIDDEN_OPERANDS],
4492 // small_imm_base_wb: wback,
4493 // uses: {Rn},
4494 // violations: [implied by 'base'],
4495 // wback: (P(24)=0) ||
4496 // (W(21)=1)}
4497 Register LDRH_immediate_cccc000pu1w1nnnnttttiiii1011iiii_case_0::
base_address_register(Instruction inst) const4498 base_address_register(Instruction inst) const {
4499 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4500 // base: 'inst(19:16)'
4501 return Register(((inst.Bits() & 0x000F0000) >> 16));
4502 }
4503
4504 RegisterList LDRH_immediate_cccc000pu1w1nnnnttttiiii1011iiii_case_0::
defs(Instruction inst) const4505 defs(Instruction inst) const {
4506 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4507 // defs: '{inst(15:12), inst(19:16)
4508 // if (inst(24)=0) ||
4509 // (inst(21)=1)
4510 // else 32}'
4511 return RegisterList().
4512 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
4513 Add(Register(((((inst.Bits() & 0x01000000) ==
4514 0x00000000)) ||
4515 (((inst.Bits() & 0x00200000) ==
4516 0x00200000))
4517 ? ((inst.Bits() & 0x000F0000) >> 16)
4518 : 32)));
4519 }
4520
4521 SafetyLevel LDRH_immediate_cccc000pu1w1nnnnttttiiii1011iiii_case_0::
safety(Instruction inst) const4522 safety(Instruction inst) const {
4523 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4524
4525 // inst(19:16)=1111 => DECODER_ERROR
4526 if ((inst.Bits() & 0x000F0000) ==
4527 0x000F0000)
4528 return DECODER_ERROR;
4529
4530 // inst(24)=0 &&
4531 // inst(21)=1 => DECODER_ERROR
4532 if (((inst.Bits() & 0x01000000) ==
4533 0x00000000) &&
4534 ((inst.Bits() & 0x00200000) ==
4535 0x00200000))
4536 return DECODER_ERROR;
4537
4538 // 15 ==
4539 // inst(15:12) ||
4540 // ((inst(24)=0) ||
4541 // (inst(21)=1) &&
4542 // inst(15:12) ==
4543 // inst(19:16)) => UNPREDICTABLE
4544 if ((((((inst.Bits() & 0x0000F000) >> 12)) == (15))) ||
4545 ((((((inst.Bits() & 0x01000000) ==
4546 0x00000000)) ||
4547 (((inst.Bits() & 0x00200000) ==
4548 0x00200000))) &&
4549 (((((inst.Bits() & 0x000F0000) >> 16)) == (((inst.Bits() & 0x0000F000) >> 12)))))))
4550 return UNPREDICTABLE;
4551
4552 // 15 ==
4553 // inst(15:12) => FORBIDDEN_OPERANDS
4554 if (((((inst.Bits() & 0x0000F000) >> 12)) == (15)))
4555 return FORBIDDEN_OPERANDS;
4556
4557 return MAY_BE_SAFE;
4558 }
4559
4560
4561 bool LDRH_immediate_cccc000pu1w1nnnnttttiiii1011iiii_case_0::
base_address_register_writeback_small_immediate(Instruction inst) const4562 base_address_register_writeback_small_immediate(
4563 Instruction inst) const {
4564 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4565 // small_imm_base_wb: '(inst(24)=0) ||
4566 // (inst(21)=1)'
4567 return (((inst.Bits() & 0x01000000) ==
4568 0x00000000)) ||
4569 (((inst.Bits() & 0x00200000) ==
4570 0x00200000));
4571 }
4572
4573 RegisterList LDRH_immediate_cccc000pu1w1nnnnttttiiii1011iiii_case_0::
uses(Instruction inst) const4574 uses(Instruction inst) const {
4575 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4576 // uses: '{inst(19:16)}'
4577 return RegisterList().
4578 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
4579 }
4580
4581 ViolationSet LDRH_immediate_cccc000pu1w1nnnnttttiiii1011iiii_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const4582 get_violations(const nacl_arm_val::DecodedInstruction& first,
4583 const nacl_arm_val::DecodedInstruction& second,
4584 const nacl_arm_val::SfiValidator& sfi,
4585 nacl_arm_val::AddressSet* branches,
4586 nacl_arm_val::AddressSet* critical,
4587 uint32_t* next_inst_addr) const {
4588 ViolationSet violations = ClassDecoder::get_violations(
4589 first, second, sfi, branches, critical, next_inst_addr);
4590
4591 // Report unsafe loads/stores of a base address by the given instruction
4592 // pair.
4593 violations = ViolationUnion(
4594 violations, get_loadstore_violations(first, second, sfi, critical));
4595
4596 return violations;
4597 }
4598
4599
4600 // LDRH_literal_cccc000pu1w11111ttttiiii1011iiii_case_0:
4601 //
4602 // {P: P(24),
4603 // Pc: 15,
4604 // Rt: Rt(15:12),
4605 // U: U(23),
4606 // W: W(21),
4607 // add: U(23)=1,
4608 // base: Pc,
4609 // cond: cond(31:28),
4610 // defs: {Rt},
4611 // fields: [cond(31:28),
4612 // P(24),
4613 // U(23),
4614 // W(21),
4615 // Rt(15:12),
4616 // imm4H(11:8),
4617 // imm4L(3:0)],
4618 // imm32: ZeroExtend(imm4H:imm4L, 32),
4619 // imm4H: imm4H(11:8),
4620 // imm4L: imm4L(3:0),
4621 // is_literal_load: true,
4622 // pattern: cccc000pu1w11111ttttiiii1011iiii,
4623 // rule: LDRH_literal,
4624 // safety: [P(24)=0 &&
4625 // W(21)=1 => DECODER_ERROR,
4626 // P ==
4627 // W => UNPREDICTABLE,
4628 // Rt ==
4629 // Pc => UNPREDICTABLE],
4630 // true: true,
4631 // uses: {Pc},
4632 // violations: [implied by 'base']}
4633 Register LDRH_literal_cccc000pu1w11111ttttiiii1011iiii_case_0::
base_address_register(Instruction inst) const4634 base_address_register(Instruction inst) const {
4635 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4636 // base: '15'
4637 return Register(15);
4638 }
4639
4640 RegisterList LDRH_literal_cccc000pu1w11111ttttiiii1011iiii_case_0::
defs(Instruction inst) const4641 defs(Instruction inst) const {
4642 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4643 // defs: '{inst(15:12)}'
4644 return RegisterList().
4645 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
4646 }
4647
4648 bool LDRH_literal_cccc000pu1w11111ttttiiii1011iiii_case_0::
is_literal_load(Instruction inst) const4649 is_literal_load(Instruction inst) const {
4650 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4651 // is_literal_load: 'true'
4652 return true;
4653 }
4654
4655 SafetyLevel LDRH_literal_cccc000pu1w11111ttttiiii1011iiii_case_0::
safety(Instruction inst) const4656 safety(Instruction inst) const {
4657 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4658
4659 // inst(24)=0 &&
4660 // inst(21)=1 => DECODER_ERROR
4661 if (((inst.Bits() & 0x01000000) ==
4662 0x00000000) &&
4663 ((inst.Bits() & 0x00200000) ==
4664 0x00200000))
4665 return DECODER_ERROR;
4666
4667 // inst(21) ==
4668 // inst(24) => UNPREDICTABLE
4669 if (((((inst.Bits() & 0x01000000) >> 24)) == (((inst.Bits() & 0x00200000) >> 21))))
4670 return UNPREDICTABLE;
4671
4672 // 15 ==
4673 // inst(15:12) => UNPREDICTABLE
4674 if (((((inst.Bits() & 0x0000F000) >> 12)) == (15)))
4675 return UNPREDICTABLE;
4676
4677 return MAY_BE_SAFE;
4678 }
4679
4680
4681 RegisterList LDRH_literal_cccc000pu1w11111ttttiiii1011iiii_case_0::
uses(Instruction inst) const4682 uses(Instruction inst) const {
4683 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4684 // uses: '{15}'
4685 return RegisterList().
4686 Add(Register(15));
4687 }
4688
4689 ViolationSet LDRH_literal_cccc000pu1w11111ttttiiii1011iiii_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const4690 get_violations(const nacl_arm_val::DecodedInstruction& first,
4691 const nacl_arm_val::DecodedInstruction& second,
4692 const nacl_arm_val::SfiValidator& sfi,
4693 nacl_arm_val::AddressSet* branches,
4694 nacl_arm_val::AddressSet* critical,
4695 uint32_t* next_inst_addr) const {
4696 ViolationSet violations = ClassDecoder::get_violations(
4697 first, second, sfi, branches, critical, next_inst_addr);
4698
4699 // Report unsafe loads/stores of a base address by the given instruction
4700 // pair.
4701 violations = ViolationUnion(
4702 violations, get_loadstore_violations(first, second, sfi, critical));
4703
4704 return violations;
4705 }
4706
4707
4708 // LDRH_register_cccc000pu0w1nnnntttt00001011mmmm_case_0:
4709 //
4710 // {None: 32,
4711 // P: P(24),
4712 // Pc: 15,
4713 // Rm: Rm(3:0),
4714 // Rn: Rn(19:16),
4715 // Rt: Rt(15:12),
4716 // U: U(23),
4717 // W: W(21),
4718 // add: U(23)=1,
4719 // base: Rn,
4720 // cond: cond(31:28),
4721 // defs: {Rt, base
4722 // if wback
4723 // else None},
4724 // fields: [cond(31:28),
4725 // P(24),
4726 // U(23),
4727 // W(21),
4728 // Rn(19:16),
4729 // Rt(15:12),
4730 // Rm(3:0)],
4731 // index: P(24)=1,
4732 // pattern: cccc000pu0w1nnnntttt00001011mmmm,
4733 // rule: LDRH_register,
4734 // safety: [P(24)=0 &&
4735 // W(21)=1 => DECODER_ERROR,
4736 // Pc in {Rt, Rm} => UNPREDICTABLE,
4737 // wback &&
4738 // (Rn ==
4739 // Pc ||
4740 // Rn ==
4741 // Rt) => UNPREDICTABLE,
4742 // ArchVersion() <
4743 // 6 &&
4744 // wback &&
4745 // Rm ==
4746 // Rn => UNPREDICTABLE,
4747 // index => FORBIDDEN],
4748 // shift_n: 0,
4749 // shift_t: SRType_LSL(),
4750 // uses: {Rn, Rm},
4751 // violations: [implied by 'base'],
4752 // wback: (P(24)=0) ||
4753 // (W(21)=1)}
4754 Register LDRH_register_cccc000pu0w1nnnntttt00001011mmmm_case_0::
base_address_register(Instruction inst) const4755 base_address_register(Instruction inst) const {
4756 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4757 // base: 'inst(19:16)'
4758 return Register(((inst.Bits() & 0x000F0000) >> 16));
4759 }
4760
4761 RegisterList LDRH_register_cccc000pu0w1nnnntttt00001011mmmm_case_0::
defs(Instruction inst) const4762 defs(Instruction inst) const {
4763 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4764 // defs: '{inst(15:12), inst(19:16)
4765 // if (inst(24)=0) ||
4766 // (inst(21)=1)
4767 // else 32}'
4768 return RegisterList().
4769 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
4770 Add(Register(((((inst.Bits() & 0x01000000) ==
4771 0x00000000)) ||
4772 (((inst.Bits() & 0x00200000) ==
4773 0x00200000))
4774 ? ((inst.Bits() & 0x000F0000) >> 16)
4775 : 32)));
4776 }
4777
4778 SafetyLevel LDRH_register_cccc000pu0w1nnnntttt00001011mmmm_case_0::
safety(Instruction inst) const4779 safety(Instruction inst) const {
4780 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4781
4782 // inst(24)=0 &&
4783 // inst(21)=1 => DECODER_ERROR
4784 if (((inst.Bits() & 0x01000000) ==
4785 0x00000000) &&
4786 ((inst.Bits() & 0x00200000) ==
4787 0x00200000))
4788 return DECODER_ERROR;
4789
4790 // 15 ==
4791 // inst(15:12) ||
4792 // 15 ==
4793 // inst(3:0) => UNPREDICTABLE
4794 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
4795 (((15) == ((inst.Bits() & 0x0000000F)))))
4796 return UNPREDICTABLE;
4797
4798 // (inst(24)=0) ||
4799 // (inst(21)=1) &&
4800 // (15 ==
4801 // inst(19:16) ||
4802 // inst(15:12) ==
4803 // inst(19:16)) => UNPREDICTABLE
4804 if (((((inst.Bits() & 0x01000000) ==
4805 0x00000000)) ||
4806 (((inst.Bits() & 0x00200000) ==
4807 0x00200000))) &&
4808 (((((((inst.Bits() & 0x000F0000) >> 16)) == (15))) ||
4809 (((((inst.Bits() & 0x000F0000) >> 16)) == (((inst.Bits() & 0x0000F000) >> 12)))))))
4810 return UNPREDICTABLE;
4811
4812 // ArchVersion() <
4813 // 6 &&
4814 // (inst(24)=0) ||
4815 // (inst(21)=1) &&
4816 // inst(19:16) ==
4817 // inst(3:0) => UNPREDICTABLE
4818 if ((((nacl_arm_dec::ArchVersion()) < (6))) &&
4819 ((((inst.Bits() & 0x01000000) ==
4820 0x00000000)) ||
4821 (((inst.Bits() & 0x00200000) ==
4822 0x00200000))) &&
4823 ((((inst.Bits() & 0x0000000F)) == (((inst.Bits() & 0x000F0000) >> 16)))))
4824 return UNPREDICTABLE;
4825
4826 // inst(24)=1 => FORBIDDEN
4827 if ((inst.Bits() & 0x01000000) ==
4828 0x01000000)
4829 return FORBIDDEN;
4830
4831 return MAY_BE_SAFE;
4832 }
4833
4834
4835 RegisterList LDRH_register_cccc000pu0w1nnnntttt00001011mmmm_case_0::
uses(Instruction inst) const4836 uses(Instruction inst) const {
4837 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4838 // uses: '{inst(19:16), inst(3:0)}'
4839 return RegisterList().
4840 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
4841 Add(Register((inst.Bits() & 0x0000000F)));
4842 }
4843
4844 ViolationSet LDRH_register_cccc000pu0w1nnnntttt00001011mmmm_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const4845 get_violations(const nacl_arm_val::DecodedInstruction& first,
4846 const nacl_arm_val::DecodedInstruction& second,
4847 const nacl_arm_val::SfiValidator& sfi,
4848 nacl_arm_val::AddressSet* branches,
4849 nacl_arm_val::AddressSet* critical,
4850 uint32_t* next_inst_addr) const {
4851 ViolationSet violations = ClassDecoder::get_violations(
4852 first, second, sfi, branches, critical, next_inst_addr);
4853
4854 // Report unsafe loads/stores of a base address by the given instruction
4855 // pair.
4856 violations = ViolationUnion(
4857 violations, get_loadstore_violations(first, second, sfi, critical));
4858
4859 return violations;
4860 }
4861
4862
4863 // LDRSB_immediate_cccc000pu1w1nnnnttttiiii1101iiii_case_0:
4864 //
4865 // {None: 32,
4866 // P: P(24),
4867 // Pc: 15,
4868 // Rn: Rn(19:16),
4869 // Rt: Rt(15:12),
4870 // U: U(23),
4871 // W: W(21),
4872 // add: U(23)=1,
4873 // address: offset_addr
4874 // if index
4875 // else Rn,
4876 // base: Rn,
4877 // cond: cond(31:28),
4878 // defs: {Rt, base
4879 // if wback
4880 // else None},
4881 // fields: [cond(31:28),
4882 // P(24),
4883 // U(23),
4884 // W(21),
4885 // Rn(19:16),
4886 // Rt(15:12),
4887 // imm4H(11:8),
4888 // imm4L(3:0)],
4889 // imm32: ZeroExtend(imm4H:imm4L, 32),
4890 // imm4H: imm4H(11:8),
4891 // imm4L: imm4L(3:0),
4892 // index: P(24)=1,
4893 // offset_addr: Rn + imm32
4894 // if add
4895 // else Rn - imm32,
4896 // pattern: cccc000pu1w1nnnnttttiiii1101iiii,
4897 // rule: LDRSB_immediate,
4898 // safety: [Rn(19:16)=1111 => DECODER_ERROR,
4899 // P(24)=0 &&
4900 // W(21)=1 => DECODER_ERROR,
4901 // Rt ==
4902 // Pc ||
4903 // (wback &&
4904 // Rn ==
4905 // Rt) => UNPREDICTABLE,
4906 // Rt ==
4907 // Pc => FORBIDDEN_OPERANDS],
4908 // small_imm_base_wb: wback,
4909 // uses: {Rn},
4910 // violations: [implied by 'base'],
4911 // wback: (P(24)=0) ||
4912 // (W(21)=1)}
4913 Register LDRSB_immediate_cccc000pu1w1nnnnttttiiii1101iiii_case_0::
base_address_register(Instruction inst) const4914 base_address_register(Instruction inst) const {
4915 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4916 // base: 'inst(19:16)'
4917 return Register(((inst.Bits() & 0x000F0000) >> 16));
4918 }
4919
4920 RegisterList LDRSB_immediate_cccc000pu1w1nnnnttttiiii1101iiii_case_0::
defs(Instruction inst) const4921 defs(Instruction inst) const {
4922 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4923 // defs: '{inst(15:12), inst(19:16)
4924 // if (inst(24)=0) ||
4925 // (inst(21)=1)
4926 // else 32}'
4927 return RegisterList().
4928 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
4929 Add(Register(((((inst.Bits() & 0x01000000) ==
4930 0x00000000)) ||
4931 (((inst.Bits() & 0x00200000) ==
4932 0x00200000))
4933 ? ((inst.Bits() & 0x000F0000) >> 16)
4934 : 32)));
4935 }
4936
4937 SafetyLevel LDRSB_immediate_cccc000pu1w1nnnnttttiiii1101iiii_case_0::
safety(Instruction inst) const4938 safety(Instruction inst) const {
4939 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4940
4941 // inst(19:16)=1111 => DECODER_ERROR
4942 if ((inst.Bits() & 0x000F0000) ==
4943 0x000F0000)
4944 return DECODER_ERROR;
4945
4946 // inst(24)=0 &&
4947 // inst(21)=1 => DECODER_ERROR
4948 if (((inst.Bits() & 0x01000000) ==
4949 0x00000000) &&
4950 ((inst.Bits() & 0x00200000) ==
4951 0x00200000))
4952 return DECODER_ERROR;
4953
4954 // 15 ==
4955 // inst(15:12) ||
4956 // ((inst(24)=0) ||
4957 // (inst(21)=1) &&
4958 // inst(15:12) ==
4959 // inst(19:16)) => UNPREDICTABLE
4960 if ((((((inst.Bits() & 0x0000F000) >> 12)) == (15))) ||
4961 ((((((inst.Bits() & 0x01000000) ==
4962 0x00000000)) ||
4963 (((inst.Bits() & 0x00200000) ==
4964 0x00200000))) &&
4965 (((((inst.Bits() & 0x000F0000) >> 16)) == (((inst.Bits() & 0x0000F000) >> 12)))))))
4966 return UNPREDICTABLE;
4967
4968 // 15 ==
4969 // inst(15:12) => FORBIDDEN_OPERANDS
4970 if (((((inst.Bits() & 0x0000F000) >> 12)) == (15)))
4971 return FORBIDDEN_OPERANDS;
4972
4973 return MAY_BE_SAFE;
4974 }
4975
4976
4977 bool LDRSB_immediate_cccc000pu1w1nnnnttttiiii1101iiii_case_0::
base_address_register_writeback_small_immediate(Instruction inst) const4978 base_address_register_writeback_small_immediate(
4979 Instruction inst) const {
4980 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4981 // small_imm_base_wb: '(inst(24)=0) ||
4982 // (inst(21)=1)'
4983 return (((inst.Bits() & 0x01000000) ==
4984 0x00000000)) ||
4985 (((inst.Bits() & 0x00200000) ==
4986 0x00200000));
4987 }
4988
4989 RegisterList LDRSB_immediate_cccc000pu1w1nnnnttttiiii1101iiii_case_0::
uses(Instruction inst) const4990 uses(Instruction inst) const {
4991 UNREFERENCED_PARAMETER(inst); // To silence compiler.
4992 // uses: '{inst(19:16)}'
4993 return RegisterList().
4994 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
4995 }
4996
4997 ViolationSet LDRSB_immediate_cccc000pu1w1nnnnttttiiii1101iiii_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const4998 get_violations(const nacl_arm_val::DecodedInstruction& first,
4999 const nacl_arm_val::DecodedInstruction& second,
5000 const nacl_arm_val::SfiValidator& sfi,
5001 nacl_arm_val::AddressSet* branches,
5002 nacl_arm_val::AddressSet* critical,
5003 uint32_t* next_inst_addr) const {
5004 ViolationSet violations = ClassDecoder::get_violations(
5005 first, second, sfi, branches, critical, next_inst_addr);
5006
5007 // Report unsafe loads/stores of a base address by the given instruction
5008 // pair.
5009 violations = ViolationUnion(
5010 violations, get_loadstore_violations(first, second, sfi, critical));
5011
5012 return violations;
5013 }
5014
5015
5016 // LDRSB_literal_cccc0001u1011111ttttiiii1101iiii_case_0:
5017 //
5018 // {P: P(24),
5019 // Pc: 15,
5020 // Rt: Rt(15:12),
5021 // U: U(23),
5022 // W: W(21),
5023 // add: U(23)=1,
5024 // base: Pc,
5025 // cond: cond(31:28),
5026 // defs: {Rt},
5027 // fields: [cond(31:28),
5028 // P(24),
5029 // U(23),
5030 // W(21),
5031 // Rt(15:12),
5032 // imm4H(11:8),
5033 // imm4L(3:0)],
5034 // imm32: ZeroExtend(imm4H:imm4L, 32),
5035 // imm4H: imm4H(11:8),
5036 // imm4L: imm4L(3:0),
5037 // is_literal_load: true,
5038 // pattern: cccc0001u1011111ttttiiii1101iiii,
5039 // rule: LDRSB_literal,
5040 // safety: [P(24)=0 &&
5041 // W(21)=1 => DECODER_ERROR,
5042 // P ==
5043 // W => UNPREDICTABLE,
5044 // Rt ==
5045 // Pc => UNPREDICTABLE],
5046 // true: true,
5047 // uses: {Pc},
5048 // violations: [implied by 'base']}
5049 Register LDRSB_literal_cccc0001u1011111ttttiiii1101iiii_case_0::
base_address_register(Instruction inst) const5050 base_address_register(Instruction inst) const {
5051 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5052 // base: '15'
5053 return Register(15);
5054 }
5055
5056 RegisterList LDRSB_literal_cccc0001u1011111ttttiiii1101iiii_case_0::
defs(Instruction inst) const5057 defs(Instruction inst) const {
5058 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5059 // defs: '{inst(15:12)}'
5060 return RegisterList().
5061 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
5062 }
5063
5064 bool LDRSB_literal_cccc0001u1011111ttttiiii1101iiii_case_0::
is_literal_load(Instruction inst) const5065 is_literal_load(Instruction inst) const {
5066 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5067 // is_literal_load: 'true'
5068 return true;
5069 }
5070
5071 SafetyLevel LDRSB_literal_cccc0001u1011111ttttiiii1101iiii_case_0::
safety(Instruction inst) const5072 safety(Instruction inst) const {
5073 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5074
5075 // inst(24)=0 &&
5076 // inst(21)=1 => DECODER_ERROR
5077 if (((inst.Bits() & 0x01000000) ==
5078 0x00000000) &&
5079 ((inst.Bits() & 0x00200000) ==
5080 0x00200000))
5081 return DECODER_ERROR;
5082
5083 // inst(21) ==
5084 // inst(24) => UNPREDICTABLE
5085 if (((((inst.Bits() & 0x01000000) >> 24)) == (((inst.Bits() & 0x00200000) >> 21))))
5086 return UNPREDICTABLE;
5087
5088 // 15 ==
5089 // inst(15:12) => UNPREDICTABLE
5090 if (((((inst.Bits() & 0x0000F000) >> 12)) == (15)))
5091 return UNPREDICTABLE;
5092
5093 return MAY_BE_SAFE;
5094 }
5095
5096
5097 RegisterList LDRSB_literal_cccc0001u1011111ttttiiii1101iiii_case_0::
uses(Instruction inst) const5098 uses(Instruction inst) const {
5099 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5100 // uses: '{15}'
5101 return RegisterList().
5102 Add(Register(15));
5103 }
5104
5105 ViolationSet LDRSB_literal_cccc0001u1011111ttttiiii1101iiii_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const5106 get_violations(const nacl_arm_val::DecodedInstruction& first,
5107 const nacl_arm_val::DecodedInstruction& second,
5108 const nacl_arm_val::SfiValidator& sfi,
5109 nacl_arm_val::AddressSet* branches,
5110 nacl_arm_val::AddressSet* critical,
5111 uint32_t* next_inst_addr) const {
5112 ViolationSet violations = ClassDecoder::get_violations(
5113 first, second, sfi, branches, critical, next_inst_addr);
5114
5115 // Report unsafe loads/stores of a base address by the given instruction
5116 // pair.
5117 violations = ViolationUnion(
5118 violations, get_loadstore_violations(first, second, sfi, critical));
5119
5120 return violations;
5121 }
5122
5123
5124 // LDRSB_register_cccc000pu0w1nnnntttt00001101mmmm_case_0:
5125 //
5126 // {None: 32,
5127 // P: P(24),
5128 // Pc: 15,
5129 // Rm: Rm(3:0),
5130 // Rn: Rn(19:16),
5131 // Rt: Rt(15:12),
5132 // U: U(23),
5133 // W: W(21),
5134 // add: U(23)=1,
5135 // base: Rn,
5136 // cond: cond(31:28),
5137 // defs: {Rt, base
5138 // if wback
5139 // else None},
5140 // fields: [cond(31:28),
5141 // P(24),
5142 // U(23),
5143 // W(21),
5144 // Rn(19:16),
5145 // Rt(15:12),
5146 // Rm(3:0)],
5147 // index: P(24)=1,
5148 // pattern: cccc000pu0w1nnnntttt00001101mmmm,
5149 // rule: LDRSB_register,
5150 // safety: [P(24)=0 &&
5151 // W(21)=1 => DECODER_ERROR,
5152 // Pc in {Rt, Rm} => UNPREDICTABLE,
5153 // wback &&
5154 // (Rn ==
5155 // Pc ||
5156 // Rn ==
5157 // Rt) => UNPREDICTABLE,
5158 // ArchVersion() <
5159 // 6 &&
5160 // wback &&
5161 // Rm ==
5162 // Rn => UNPREDICTABLE,
5163 // index => FORBIDDEN],
5164 // shift_n: 0,
5165 // shift_t: SRType_LSL(),
5166 // uses: {Rn, Rm},
5167 // violations: [implied by 'base'],
5168 // wback: (P(24)=0) ||
5169 // (W(21)=1)}
5170 Register LDRSB_register_cccc000pu0w1nnnntttt00001101mmmm_case_0::
base_address_register(Instruction inst) const5171 base_address_register(Instruction inst) const {
5172 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5173 // base: 'inst(19:16)'
5174 return Register(((inst.Bits() & 0x000F0000) >> 16));
5175 }
5176
5177 RegisterList LDRSB_register_cccc000pu0w1nnnntttt00001101mmmm_case_0::
defs(Instruction inst) const5178 defs(Instruction inst) const {
5179 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5180 // defs: '{inst(15:12), inst(19:16)
5181 // if (inst(24)=0) ||
5182 // (inst(21)=1)
5183 // else 32}'
5184 return RegisterList().
5185 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
5186 Add(Register(((((inst.Bits() & 0x01000000) ==
5187 0x00000000)) ||
5188 (((inst.Bits() & 0x00200000) ==
5189 0x00200000))
5190 ? ((inst.Bits() & 0x000F0000) >> 16)
5191 : 32)));
5192 }
5193
5194 SafetyLevel LDRSB_register_cccc000pu0w1nnnntttt00001101mmmm_case_0::
safety(Instruction inst) const5195 safety(Instruction inst) const {
5196 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5197
5198 // inst(24)=0 &&
5199 // inst(21)=1 => DECODER_ERROR
5200 if (((inst.Bits() & 0x01000000) ==
5201 0x00000000) &&
5202 ((inst.Bits() & 0x00200000) ==
5203 0x00200000))
5204 return DECODER_ERROR;
5205
5206 // 15 ==
5207 // inst(15:12) ||
5208 // 15 ==
5209 // inst(3:0) => UNPREDICTABLE
5210 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
5211 (((15) == ((inst.Bits() & 0x0000000F)))))
5212 return UNPREDICTABLE;
5213
5214 // (inst(24)=0) ||
5215 // (inst(21)=1) &&
5216 // (15 ==
5217 // inst(19:16) ||
5218 // inst(15:12) ==
5219 // inst(19:16)) => UNPREDICTABLE
5220 if (((((inst.Bits() & 0x01000000) ==
5221 0x00000000)) ||
5222 (((inst.Bits() & 0x00200000) ==
5223 0x00200000))) &&
5224 (((((((inst.Bits() & 0x000F0000) >> 16)) == (15))) ||
5225 (((((inst.Bits() & 0x000F0000) >> 16)) == (((inst.Bits() & 0x0000F000) >> 12)))))))
5226 return UNPREDICTABLE;
5227
5228 // ArchVersion() <
5229 // 6 &&
5230 // (inst(24)=0) ||
5231 // (inst(21)=1) &&
5232 // inst(19:16) ==
5233 // inst(3:0) => UNPREDICTABLE
5234 if ((((nacl_arm_dec::ArchVersion()) < (6))) &&
5235 ((((inst.Bits() & 0x01000000) ==
5236 0x00000000)) ||
5237 (((inst.Bits() & 0x00200000) ==
5238 0x00200000))) &&
5239 ((((inst.Bits() & 0x0000000F)) == (((inst.Bits() & 0x000F0000) >> 16)))))
5240 return UNPREDICTABLE;
5241
5242 // inst(24)=1 => FORBIDDEN
5243 if ((inst.Bits() & 0x01000000) ==
5244 0x01000000)
5245 return FORBIDDEN;
5246
5247 return MAY_BE_SAFE;
5248 }
5249
5250
5251 RegisterList LDRSB_register_cccc000pu0w1nnnntttt00001101mmmm_case_0::
uses(Instruction inst) const5252 uses(Instruction inst) const {
5253 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5254 // uses: '{inst(19:16), inst(3:0)}'
5255 return RegisterList().
5256 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
5257 Add(Register((inst.Bits() & 0x0000000F)));
5258 }
5259
5260 ViolationSet LDRSB_register_cccc000pu0w1nnnntttt00001101mmmm_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const5261 get_violations(const nacl_arm_val::DecodedInstruction& first,
5262 const nacl_arm_val::DecodedInstruction& second,
5263 const nacl_arm_val::SfiValidator& sfi,
5264 nacl_arm_val::AddressSet* branches,
5265 nacl_arm_val::AddressSet* critical,
5266 uint32_t* next_inst_addr) const {
5267 ViolationSet violations = ClassDecoder::get_violations(
5268 first, second, sfi, branches, critical, next_inst_addr);
5269
5270 // Report unsafe loads/stores of a base address by the given instruction
5271 // pair.
5272 violations = ViolationUnion(
5273 violations, get_loadstore_violations(first, second, sfi, critical));
5274
5275 return violations;
5276 }
5277
5278
5279 // LDRSH_immediate_cccc000pu1w1nnnnttttiiii1111iiii_case_0:
5280 //
5281 // {None: 32,
5282 // P: P(24),
5283 // Pc: 15,
5284 // Rn: Rn(19:16),
5285 // Rt: Rt(15:12),
5286 // U: U(23),
5287 // W: W(21),
5288 // add: U(23)=1,
5289 // address: offset_addr
5290 // if index
5291 // else Rn,
5292 // base: Rn,
5293 // cond: cond(31:28),
5294 // defs: {Rt, base
5295 // if wback
5296 // else None},
5297 // fields: [cond(31:28),
5298 // P(24),
5299 // U(23),
5300 // W(21),
5301 // Rn(19:16),
5302 // Rt(15:12),
5303 // imm4H(11:8),
5304 // imm4L(3:0)],
5305 // imm32: ZeroExtend(imm4H:imm4L, 32),
5306 // imm4H: imm4H(11:8),
5307 // imm4L: imm4L(3:0),
5308 // index: P(24)=1,
5309 // offset_addr: Rn + imm32
5310 // if add
5311 // else Rn - imm32,
5312 // pattern: cccc000pu1w1nnnnttttiiii1111iiii,
5313 // rule: LDRSH_immediate,
5314 // safety: [Rn(19:16)=1111 => DECODER_ERROR,
5315 // P(24)=0 &&
5316 // W(21)=1 => DECODER_ERROR,
5317 // Rt ==
5318 // Pc ||
5319 // (wback &&
5320 // Rn ==
5321 // Rt) => UNPREDICTABLE,
5322 // Rt ==
5323 // Pc => FORBIDDEN_OPERANDS],
5324 // small_imm_base_wb: wback,
5325 // uses: {Rn},
5326 // violations: [implied by 'base'],
5327 // wback: (P(24)=0) ||
5328 // (W(21)=1)}
5329 Register LDRSH_immediate_cccc000pu1w1nnnnttttiiii1111iiii_case_0::
base_address_register(Instruction inst) const5330 base_address_register(Instruction inst) const {
5331 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5332 // base: 'inst(19:16)'
5333 return Register(((inst.Bits() & 0x000F0000) >> 16));
5334 }
5335
5336 RegisterList LDRSH_immediate_cccc000pu1w1nnnnttttiiii1111iiii_case_0::
defs(Instruction inst) const5337 defs(Instruction inst) const {
5338 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5339 // defs: '{inst(15:12), inst(19:16)
5340 // if (inst(24)=0) ||
5341 // (inst(21)=1)
5342 // else 32}'
5343 return RegisterList().
5344 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
5345 Add(Register(((((inst.Bits() & 0x01000000) ==
5346 0x00000000)) ||
5347 (((inst.Bits() & 0x00200000) ==
5348 0x00200000))
5349 ? ((inst.Bits() & 0x000F0000) >> 16)
5350 : 32)));
5351 }
5352
5353 SafetyLevel LDRSH_immediate_cccc000pu1w1nnnnttttiiii1111iiii_case_0::
safety(Instruction inst) const5354 safety(Instruction inst) const {
5355 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5356
5357 // inst(19:16)=1111 => DECODER_ERROR
5358 if ((inst.Bits() & 0x000F0000) ==
5359 0x000F0000)
5360 return DECODER_ERROR;
5361
5362 // inst(24)=0 &&
5363 // inst(21)=1 => DECODER_ERROR
5364 if (((inst.Bits() & 0x01000000) ==
5365 0x00000000) &&
5366 ((inst.Bits() & 0x00200000) ==
5367 0x00200000))
5368 return DECODER_ERROR;
5369
5370 // 15 ==
5371 // inst(15:12) ||
5372 // ((inst(24)=0) ||
5373 // (inst(21)=1) &&
5374 // inst(15:12) ==
5375 // inst(19:16)) => UNPREDICTABLE
5376 if ((((((inst.Bits() & 0x0000F000) >> 12)) == (15))) ||
5377 ((((((inst.Bits() & 0x01000000) ==
5378 0x00000000)) ||
5379 (((inst.Bits() & 0x00200000) ==
5380 0x00200000))) &&
5381 (((((inst.Bits() & 0x000F0000) >> 16)) == (((inst.Bits() & 0x0000F000) >> 12)))))))
5382 return UNPREDICTABLE;
5383
5384 // 15 ==
5385 // inst(15:12) => FORBIDDEN_OPERANDS
5386 if (((((inst.Bits() & 0x0000F000) >> 12)) == (15)))
5387 return FORBIDDEN_OPERANDS;
5388
5389 return MAY_BE_SAFE;
5390 }
5391
5392
5393 bool LDRSH_immediate_cccc000pu1w1nnnnttttiiii1111iiii_case_0::
base_address_register_writeback_small_immediate(Instruction inst) const5394 base_address_register_writeback_small_immediate(
5395 Instruction inst) const {
5396 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5397 // small_imm_base_wb: '(inst(24)=0) ||
5398 // (inst(21)=1)'
5399 return (((inst.Bits() & 0x01000000) ==
5400 0x00000000)) ||
5401 (((inst.Bits() & 0x00200000) ==
5402 0x00200000));
5403 }
5404
5405 RegisterList LDRSH_immediate_cccc000pu1w1nnnnttttiiii1111iiii_case_0::
uses(Instruction inst) const5406 uses(Instruction inst) const {
5407 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5408 // uses: '{inst(19:16)}'
5409 return RegisterList().
5410 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
5411 }
5412
5413 ViolationSet LDRSH_immediate_cccc000pu1w1nnnnttttiiii1111iiii_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const5414 get_violations(const nacl_arm_val::DecodedInstruction& first,
5415 const nacl_arm_val::DecodedInstruction& second,
5416 const nacl_arm_val::SfiValidator& sfi,
5417 nacl_arm_val::AddressSet* branches,
5418 nacl_arm_val::AddressSet* critical,
5419 uint32_t* next_inst_addr) const {
5420 ViolationSet violations = ClassDecoder::get_violations(
5421 first, second, sfi, branches, critical, next_inst_addr);
5422
5423 // Report unsafe loads/stores of a base address by the given instruction
5424 // pair.
5425 violations = ViolationUnion(
5426 violations, get_loadstore_violations(first, second, sfi, critical));
5427
5428 return violations;
5429 }
5430
5431
5432 // LDRSH_literal_cccc0001u1011111ttttiiii1111iiii_case_0:
5433 //
5434 // {P: P(24),
5435 // Pc: 15,
5436 // Rt: Rt(15:12),
5437 // U: U(23),
5438 // W: W(21),
5439 // add: U(23)=1,
5440 // base: Pc,
5441 // cond: cond(31:28),
5442 // defs: {Rt},
5443 // fields: [cond(31:28),
5444 // P(24),
5445 // U(23),
5446 // W(21),
5447 // Rt(15:12),
5448 // imm4H(11:8),
5449 // imm4L(3:0)],
5450 // imm32: ZeroExtend(imm4H:imm4L, 32),
5451 // imm4H: imm4H(11:8),
5452 // imm4L: imm4L(3:0),
5453 // is_literal_load: true,
5454 // pattern: cccc0001u1011111ttttiiii1111iiii,
5455 // rule: LDRSH_literal,
5456 // safety: [P(24)=0 &&
5457 // W(21)=1 => DECODER_ERROR,
5458 // P ==
5459 // W => UNPREDICTABLE,
5460 // Rt ==
5461 // Pc => UNPREDICTABLE],
5462 // true: true,
5463 // uses: {Pc},
5464 // violations: [implied by 'base']}
5465 Register LDRSH_literal_cccc0001u1011111ttttiiii1111iiii_case_0::
base_address_register(Instruction inst) const5466 base_address_register(Instruction inst) const {
5467 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5468 // base: '15'
5469 return Register(15);
5470 }
5471
5472 RegisterList LDRSH_literal_cccc0001u1011111ttttiiii1111iiii_case_0::
defs(Instruction inst) const5473 defs(Instruction inst) const {
5474 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5475 // defs: '{inst(15:12)}'
5476 return RegisterList().
5477 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
5478 }
5479
5480 bool LDRSH_literal_cccc0001u1011111ttttiiii1111iiii_case_0::
is_literal_load(Instruction inst) const5481 is_literal_load(Instruction inst) const {
5482 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5483 // is_literal_load: 'true'
5484 return true;
5485 }
5486
5487 SafetyLevel LDRSH_literal_cccc0001u1011111ttttiiii1111iiii_case_0::
safety(Instruction inst) const5488 safety(Instruction inst) const {
5489 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5490
5491 // inst(24)=0 &&
5492 // inst(21)=1 => DECODER_ERROR
5493 if (((inst.Bits() & 0x01000000) ==
5494 0x00000000) &&
5495 ((inst.Bits() & 0x00200000) ==
5496 0x00200000))
5497 return DECODER_ERROR;
5498
5499 // inst(21) ==
5500 // inst(24) => UNPREDICTABLE
5501 if (((((inst.Bits() & 0x01000000) >> 24)) == (((inst.Bits() & 0x00200000) >> 21))))
5502 return UNPREDICTABLE;
5503
5504 // 15 ==
5505 // inst(15:12) => UNPREDICTABLE
5506 if (((((inst.Bits() & 0x0000F000) >> 12)) == (15)))
5507 return UNPREDICTABLE;
5508
5509 return MAY_BE_SAFE;
5510 }
5511
5512
5513 RegisterList LDRSH_literal_cccc0001u1011111ttttiiii1111iiii_case_0::
uses(Instruction inst) const5514 uses(Instruction inst) const {
5515 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5516 // uses: '{15}'
5517 return RegisterList().
5518 Add(Register(15));
5519 }
5520
5521 ViolationSet LDRSH_literal_cccc0001u1011111ttttiiii1111iiii_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const5522 get_violations(const nacl_arm_val::DecodedInstruction& first,
5523 const nacl_arm_val::DecodedInstruction& second,
5524 const nacl_arm_val::SfiValidator& sfi,
5525 nacl_arm_val::AddressSet* branches,
5526 nacl_arm_val::AddressSet* critical,
5527 uint32_t* next_inst_addr) const {
5528 ViolationSet violations = ClassDecoder::get_violations(
5529 first, second, sfi, branches, critical, next_inst_addr);
5530
5531 // Report unsafe loads/stores of a base address by the given instruction
5532 // pair.
5533 violations = ViolationUnion(
5534 violations, get_loadstore_violations(first, second, sfi, critical));
5535
5536 return violations;
5537 }
5538
5539
5540 // LDRSH_register_cccc000pu0w1nnnntttt00001111mmmm_case_0:
5541 //
5542 // {None: 32,
5543 // P: P(24),
5544 // Pc: 15,
5545 // Rm: Rm(3:0),
5546 // Rn: Rn(19:16),
5547 // Rt: Rt(15:12),
5548 // U: U(23),
5549 // W: W(21),
5550 // add: U(23)=1,
5551 // base: Rn,
5552 // cond: cond(31:28),
5553 // defs: {Rt, base
5554 // if wback
5555 // else None},
5556 // fields: [cond(31:28),
5557 // P(24),
5558 // U(23),
5559 // W(21),
5560 // Rn(19:16),
5561 // Rt(15:12),
5562 // Rm(3:0)],
5563 // index: P(24)=1,
5564 // pattern: cccc000pu0w1nnnntttt00001111mmmm,
5565 // rule: LDRSH_register,
5566 // safety: [P(24)=0 &&
5567 // W(21)=1 => DECODER_ERROR,
5568 // Pc in {Rt, Rm} => UNPREDICTABLE,
5569 // wback &&
5570 // (Rn ==
5571 // Pc ||
5572 // Rn ==
5573 // Rt) => UNPREDICTABLE,
5574 // ArchVersion() <
5575 // 6 &&
5576 // wback &&
5577 // Rm ==
5578 // Rn => UNPREDICTABLE,
5579 // index => FORBIDDEN],
5580 // shift_n: 0,
5581 // shift_t: SRType_LSL(),
5582 // uses: {Rn, Rm},
5583 // violations: [implied by 'base'],
5584 // wback: (P(24)=0) ||
5585 // (W(21)=1)}
5586 Register LDRSH_register_cccc000pu0w1nnnntttt00001111mmmm_case_0::
base_address_register(Instruction inst) const5587 base_address_register(Instruction inst) const {
5588 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5589 // base: 'inst(19:16)'
5590 return Register(((inst.Bits() & 0x000F0000) >> 16));
5591 }
5592
5593 RegisterList LDRSH_register_cccc000pu0w1nnnntttt00001111mmmm_case_0::
defs(Instruction inst) const5594 defs(Instruction inst) const {
5595 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5596 // defs: '{inst(15:12), inst(19:16)
5597 // if (inst(24)=0) ||
5598 // (inst(21)=1)
5599 // else 32}'
5600 return RegisterList().
5601 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
5602 Add(Register(((((inst.Bits() & 0x01000000) ==
5603 0x00000000)) ||
5604 (((inst.Bits() & 0x00200000) ==
5605 0x00200000))
5606 ? ((inst.Bits() & 0x000F0000) >> 16)
5607 : 32)));
5608 }
5609
5610 SafetyLevel LDRSH_register_cccc000pu0w1nnnntttt00001111mmmm_case_0::
safety(Instruction inst) const5611 safety(Instruction inst) const {
5612 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5613
5614 // inst(24)=0 &&
5615 // inst(21)=1 => DECODER_ERROR
5616 if (((inst.Bits() & 0x01000000) ==
5617 0x00000000) &&
5618 ((inst.Bits() & 0x00200000) ==
5619 0x00200000))
5620 return DECODER_ERROR;
5621
5622 // 15 ==
5623 // inst(15:12) ||
5624 // 15 ==
5625 // inst(3:0) => UNPREDICTABLE
5626 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
5627 (((15) == ((inst.Bits() & 0x0000000F)))))
5628 return UNPREDICTABLE;
5629
5630 // (inst(24)=0) ||
5631 // (inst(21)=1) &&
5632 // (15 ==
5633 // inst(19:16) ||
5634 // inst(15:12) ==
5635 // inst(19:16)) => UNPREDICTABLE
5636 if (((((inst.Bits() & 0x01000000) ==
5637 0x00000000)) ||
5638 (((inst.Bits() & 0x00200000) ==
5639 0x00200000))) &&
5640 (((((((inst.Bits() & 0x000F0000) >> 16)) == (15))) ||
5641 (((((inst.Bits() & 0x000F0000) >> 16)) == (((inst.Bits() & 0x0000F000) >> 12)))))))
5642 return UNPREDICTABLE;
5643
5644 // ArchVersion() <
5645 // 6 &&
5646 // (inst(24)=0) ||
5647 // (inst(21)=1) &&
5648 // inst(19:16) ==
5649 // inst(3:0) => UNPREDICTABLE
5650 if ((((nacl_arm_dec::ArchVersion()) < (6))) &&
5651 ((((inst.Bits() & 0x01000000) ==
5652 0x00000000)) ||
5653 (((inst.Bits() & 0x00200000) ==
5654 0x00200000))) &&
5655 ((((inst.Bits() & 0x0000000F)) == (((inst.Bits() & 0x000F0000) >> 16)))))
5656 return UNPREDICTABLE;
5657
5658 // inst(24)=1 => FORBIDDEN
5659 if ((inst.Bits() & 0x01000000) ==
5660 0x01000000)
5661 return FORBIDDEN;
5662
5663 return MAY_BE_SAFE;
5664 }
5665
5666
5667 RegisterList LDRSH_register_cccc000pu0w1nnnntttt00001111mmmm_case_0::
uses(Instruction inst) const5668 uses(Instruction inst) const {
5669 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5670 // uses: '{inst(19:16), inst(3:0)}'
5671 return RegisterList().
5672 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
5673 Add(Register((inst.Bits() & 0x0000000F)));
5674 }
5675
5676 ViolationSet LDRSH_register_cccc000pu0w1nnnntttt00001111mmmm_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const5677 get_violations(const nacl_arm_val::DecodedInstruction& first,
5678 const nacl_arm_val::DecodedInstruction& second,
5679 const nacl_arm_val::SfiValidator& sfi,
5680 nacl_arm_val::AddressSet* branches,
5681 nacl_arm_val::AddressSet* critical,
5682 uint32_t* next_inst_addr) const {
5683 ViolationSet violations = ClassDecoder::get_violations(
5684 first, second, sfi, branches, critical, next_inst_addr);
5685
5686 // Report unsafe loads/stores of a base address by the given instruction
5687 // pair.
5688 violations = ViolationUnion(
5689 violations, get_loadstore_violations(first, second, sfi, critical));
5690
5691 return violations;
5692 }
5693
5694
5695 // LDRT_A1_cccc0100u011nnnnttttiiiiiiiiiiii_case_0:
5696 //
5697 // {defs: {},
5698 // pattern: cccc0100u011nnnnttttiiiiiiiiiiii,
5699 // rule: LDRT_A1,
5700 // safety: [true => FORBIDDEN],
5701 // true: true,
5702 // uses: {}}
5703 RegisterList LDRT_A1_cccc0100u011nnnnttttiiiiiiiiiiii_case_0::
defs(Instruction inst) const5704 defs(Instruction inst) const {
5705 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5706 // defs: '{}'
5707 return RegisterList();
5708 }
5709
5710 SafetyLevel LDRT_A1_cccc0100u011nnnnttttiiiiiiiiiiii_case_0::
safety(Instruction inst) const5711 safety(Instruction inst) const {
5712 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5713
5714 // true => FORBIDDEN
5715 if (true)
5716 return FORBIDDEN;
5717
5718 return MAY_BE_SAFE;
5719 }
5720
5721
5722 RegisterList LDRT_A1_cccc0100u011nnnnttttiiiiiiiiiiii_case_0::
uses(Instruction inst) const5723 uses(Instruction inst) const {
5724 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5725 // uses: '{}'
5726 return RegisterList();
5727 }
5728
5729 // LDRT_A2_cccc0110u011nnnnttttiiiiitt0mmmm_case_0:
5730 //
5731 // {defs: {},
5732 // pattern: cccc0110u011nnnnttttiiiiitt0mmmm,
5733 // rule: LDRT_A2,
5734 // safety: [true => FORBIDDEN],
5735 // true: true,
5736 // uses: {}}
5737 RegisterList LDRT_A2_cccc0110u011nnnnttttiiiiitt0mmmm_case_0::
defs(Instruction inst) const5738 defs(Instruction inst) const {
5739 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5740 // defs: '{}'
5741 return RegisterList();
5742 }
5743
5744 SafetyLevel LDRT_A2_cccc0110u011nnnnttttiiiiitt0mmmm_case_0::
safety(Instruction inst) const5745 safety(Instruction inst) const {
5746 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5747
5748 // true => FORBIDDEN
5749 if (true)
5750 return FORBIDDEN;
5751
5752 return MAY_BE_SAFE;
5753 }
5754
5755
5756 RegisterList LDRT_A2_cccc0110u011nnnnttttiiiiitt0mmmm_case_0::
uses(Instruction inst) const5757 uses(Instruction inst) const {
5758 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5759 // uses: '{}'
5760 return RegisterList();
5761 }
5762
5763 // LDR_immediate_cccc010pu0w1nnnnttttiiiiiiiiiiii_case_0:
5764 //
5765 // {None: 32,
5766 // P: P(24),
5767 // Pc: 15,
5768 // Rn: Rn(19:16),
5769 // Rt: Rt(15:12),
5770 // Tp: 9,
5771 // U: U(23),
5772 // W: W(21),
5773 // add: U(23)=1,
5774 // base: Rn,
5775 // cond: cond(31:28),
5776 // defs: {Rt, base
5777 // if wback
5778 // else None},
5779 // fields: [cond(31:28),
5780 // P(24),
5781 // U(23),
5782 // W(21),
5783 // Rn(19:16),
5784 // Rt(15:12),
5785 // imm12(11:0)],
5786 // imm12: imm12(11:0),
5787 // imm32: ZeroExtend(imm12, 32),
5788 // index: P(24)=1,
5789 // is_load_tp: Rn ==
5790 // Tp &&
5791 // index &&
5792 // not wback &&
5793 // add &&
5794 // imm12 in {0, 4},
5795 // pattern: cccc010pu0w1nnnnttttiiiiiiiiiiii,
5796 // rule: LDR_immediate,
5797 // safety: [Rn ==
5798 // Pc => DECODER_ERROR,
5799 // P(24)=0 &&
5800 // W(21)=1 => DECODER_ERROR,
5801 // wback &&
5802 // Rn ==
5803 // Rt => UNPREDICTABLE,
5804 // Rt ==
5805 // Pc => FORBIDDEN_OPERANDS],
5806 // small_imm_base_wb: wback,
5807 // uses: {Rn},
5808 // violations: [implied by 'base'],
5809 // wback: P(24)=0 ||
5810 // W(21)=1}
5811 Register LDR_immediate_cccc010pu0w1nnnnttttiiiiiiiiiiii_case_0::
base_address_register(Instruction inst) const5812 base_address_register(Instruction inst) const {
5813 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5814 // base: 'inst(19:16)'
5815 return Register(((inst.Bits() & 0x000F0000) >> 16));
5816 }
5817
5818 RegisterList LDR_immediate_cccc010pu0w1nnnnttttiiiiiiiiiiii_case_0::
defs(Instruction inst) const5819 defs(Instruction inst) const {
5820 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5821 // defs: '{inst(15:12), inst(19:16)
5822 // if inst(24)=0 ||
5823 // inst(21)=1
5824 // else 32}'
5825 return RegisterList().
5826 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
5827 Add(Register((((inst.Bits() & 0x01000000) ==
5828 0x00000000) ||
5829 ((inst.Bits() & 0x00200000) ==
5830 0x00200000)
5831 ? ((inst.Bits() & 0x000F0000) >> 16)
5832 : 32)));
5833 }
5834
5835 bool LDR_immediate_cccc010pu0w1nnnnttttiiiiiiiiiiii_case_0::
is_load_thread_address_pointer(Instruction inst) const5836 is_load_thread_address_pointer(Instruction inst) const {
5837 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5838 // is_load_tp: '9 ==
5839 // inst(19:16) &&
5840 // inst(24)=1 &&
5841 // not inst(24)=0 ||
5842 // inst(21)=1 &&
5843 // inst(23)=1 &&
5844 // 0 ==
5845 // inst(11:0) ||
5846 // 4 ==
5847 // inst(11:0)'
5848 return (((((inst.Bits() & 0x000F0000) >> 16)) == (9))) &&
5849 ((inst.Bits() & 0x01000000) ==
5850 0x01000000) &&
5851 (!(((inst.Bits() & 0x01000000) ==
5852 0x00000000) ||
5853 ((inst.Bits() & 0x00200000) ==
5854 0x00200000))) &&
5855 ((inst.Bits() & 0x00800000) ==
5856 0x00800000) &&
5857 (((((inst.Bits() & 0x00000FFF)) == (0))) ||
5858 ((((inst.Bits() & 0x00000FFF)) == (4))));
5859 }
5860
5861 SafetyLevel LDR_immediate_cccc010pu0w1nnnnttttiiiiiiiiiiii_case_0::
safety(Instruction inst) const5862 safety(Instruction inst) const {
5863 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5864
5865 // 15 ==
5866 // inst(19:16) => DECODER_ERROR
5867 if (((((inst.Bits() & 0x000F0000) >> 16)) == (15)))
5868 return DECODER_ERROR;
5869
5870 // inst(24)=0 &&
5871 // inst(21)=1 => DECODER_ERROR
5872 if (((inst.Bits() & 0x01000000) ==
5873 0x00000000) &&
5874 ((inst.Bits() & 0x00200000) ==
5875 0x00200000))
5876 return DECODER_ERROR;
5877
5878 // inst(24)=0 ||
5879 // inst(21)=1 &&
5880 // inst(15:12) ==
5881 // inst(19:16) => UNPREDICTABLE
5882 if ((((inst.Bits() & 0x01000000) ==
5883 0x00000000) ||
5884 ((inst.Bits() & 0x00200000) ==
5885 0x00200000)) &&
5886 (((((inst.Bits() & 0x000F0000) >> 16)) == (((inst.Bits() & 0x0000F000) >> 12)))))
5887 return UNPREDICTABLE;
5888
5889 // 15 ==
5890 // inst(15:12) => FORBIDDEN_OPERANDS
5891 if (((((inst.Bits() & 0x0000F000) >> 12)) == (15)))
5892 return FORBIDDEN_OPERANDS;
5893
5894 return MAY_BE_SAFE;
5895 }
5896
5897
5898 bool LDR_immediate_cccc010pu0w1nnnnttttiiiiiiiiiiii_case_0::
base_address_register_writeback_small_immediate(Instruction inst) const5899 base_address_register_writeback_small_immediate(
5900 Instruction inst) const {
5901 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5902 // small_imm_base_wb: 'inst(24)=0 ||
5903 // inst(21)=1'
5904 return ((inst.Bits() & 0x01000000) ==
5905 0x00000000) ||
5906 ((inst.Bits() & 0x00200000) ==
5907 0x00200000);
5908 }
5909
5910 RegisterList LDR_immediate_cccc010pu0w1nnnnttttiiiiiiiiiiii_case_0::
uses(Instruction inst) const5911 uses(Instruction inst) const {
5912 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5913 // uses: '{inst(19:16)}'
5914 return RegisterList().
5915 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
5916 }
5917
5918 ViolationSet LDR_immediate_cccc010pu0w1nnnnttttiiiiiiiiiiii_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const5919 get_violations(const nacl_arm_val::DecodedInstruction& first,
5920 const nacl_arm_val::DecodedInstruction& second,
5921 const nacl_arm_val::SfiValidator& sfi,
5922 nacl_arm_val::AddressSet* branches,
5923 nacl_arm_val::AddressSet* critical,
5924 uint32_t* next_inst_addr) const {
5925 ViolationSet violations = ClassDecoder::get_violations(
5926 first, second, sfi, branches, critical, next_inst_addr);
5927
5928 // Report unsafe loads/stores of a base address by the given instruction
5929 // pair.
5930 violations = ViolationUnion(
5931 violations, get_loadstore_violations(first, second, sfi, critical));
5932
5933 return violations;
5934 }
5935
5936
5937 // LDR_literal_cccc0101u0011111ttttiiiiiiiiiiii_case_0:
5938 //
5939 // {Pc: 15,
5940 // Rt: Rt(15:12),
5941 // U: U(23),
5942 // add: U(23)=1,
5943 // base: Pc,
5944 // cond: cond(31:28),
5945 // defs: {Rt},
5946 // fields: [cond(31:28), U(23), Rt(15:12), imm12(11:0)],
5947 // imm12: imm12(11:0),
5948 // imm32: ZeroExtend(imm12, 32),
5949 // is_literal_load: true,
5950 // pattern: cccc0101u0011111ttttiiiiiiiiiiii,
5951 // rule: LDR_literal,
5952 // safety: [Rt ==
5953 // Pc => FORBIDDEN_OPERANDS],
5954 // true: true,
5955 // uses: {Pc},
5956 // violations: [implied by 'base']}
5957 Register LDR_literal_cccc0101u0011111ttttiiiiiiiiiiii_case_0::
base_address_register(Instruction inst) const5958 base_address_register(Instruction inst) const {
5959 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5960 // base: '15'
5961 return Register(15);
5962 }
5963
5964 RegisterList LDR_literal_cccc0101u0011111ttttiiiiiiiiiiii_case_0::
defs(Instruction inst) const5965 defs(Instruction inst) const {
5966 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5967 // defs: '{inst(15:12)}'
5968 return RegisterList().
5969 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
5970 }
5971
5972 bool LDR_literal_cccc0101u0011111ttttiiiiiiiiiiii_case_0::
is_literal_load(Instruction inst) const5973 is_literal_load(Instruction inst) const {
5974 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5975 // is_literal_load: 'true'
5976 return true;
5977 }
5978
5979 SafetyLevel LDR_literal_cccc0101u0011111ttttiiiiiiiiiiii_case_0::
safety(Instruction inst) const5980 safety(Instruction inst) const {
5981 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5982
5983 // 15 ==
5984 // inst(15:12) => FORBIDDEN_OPERANDS
5985 if (((((inst.Bits() & 0x0000F000) >> 12)) == (15)))
5986 return FORBIDDEN_OPERANDS;
5987
5988 return MAY_BE_SAFE;
5989 }
5990
5991
5992 RegisterList LDR_literal_cccc0101u0011111ttttiiiiiiiiiiii_case_0::
uses(Instruction inst) const5993 uses(Instruction inst) const {
5994 UNREFERENCED_PARAMETER(inst); // To silence compiler.
5995 // uses: '{15}'
5996 return RegisterList().
5997 Add(Register(15));
5998 }
5999
6000 ViolationSet LDR_literal_cccc0101u0011111ttttiiiiiiiiiiii_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const6001 get_violations(const nacl_arm_val::DecodedInstruction& first,
6002 const nacl_arm_val::DecodedInstruction& second,
6003 const nacl_arm_val::SfiValidator& sfi,
6004 nacl_arm_val::AddressSet* branches,
6005 nacl_arm_val::AddressSet* critical,
6006 uint32_t* next_inst_addr) const {
6007 ViolationSet violations = ClassDecoder::get_violations(
6008 first, second, sfi, branches, critical, next_inst_addr);
6009
6010 // Report unsafe loads/stores of a base address by the given instruction
6011 // pair.
6012 violations = ViolationUnion(
6013 violations, get_loadstore_violations(first, second, sfi, critical));
6014
6015 return violations;
6016 }
6017
6018
6019 // LDR_register_cccc011pu0w1nnnnttttiiiiitt0mmmm_case_0:
6020 //
6021 // {None: 32,
6022 // P: P(24),
6023 // Pc: 15,
6024 // Rm: Rm(3:0),
6025 // Rn: Rn(19:16),
6026 // Rt: Rt(15:12),
6027 // U: U(23),
6028 // W: W(21),
6029 // add: U(23)=1,
6030 // base: Rn,
6031 // cond: cond(31:28),
6032 // defs: {Rt, base
6033 // if wback
6034 // else None},
6035 // fields: [cond(31:28),
6036 // P(24),
6037 // U(23),
6038 // W(21),
6039 // Rn(19:16),
6040 // Rt(15:12),
6041 // imm5(11:7),
6042 // type(6:5),
6043 // Rm(3:0)],
6044 // imm5: imm5(11:7),
6045 // index: P(24)=1,
6046 // pattern: cccc011pu0w1nnnnttttiiiiitt0mmmm,
6047 // rule: LDR_register,
6048 // safety: [P(24)=0 &&
6049 // W(21)=1 => DECODER_ERROR,
6050 // Rm ==
6051 // Pc => UNPREDICTABLE,
6052 // wback &&
6053 // (Rn ==
6054 // Pc ||
6055 // Rn ==
6056 // Rt) => UNPREDICTABLE,
6057 // ArchVersion() <
6058 // 6 &&
6059 // wback &&
6060 // Rn ==
6061 // Rm => UNPREDICTABLE,
6062 // index => FORBIDDEN,
6063 // Rt ==
6064 // Pc => FORBIDDEN_OPERANDS],
6065 // shift: DecodeImmShift(type, imm5),
6066 // type: type(6:5),
6067 // uses: {Rm, Rn},
6068 // violations: [implied by 'base'],
6069 // wback: P(24)=0 ||
6070 // W(21)=1}
6071 Register LDR_register_cccc011pu0w1nnnnttttiiiiitt0mmmm_case_0::
base_address_register(Instruction inst) const6072 base_address_register(Instruction inst) const {
6073 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6074 // base: 'inst(19:16)'
6075 return Register(((inst.Bits() & 0x000F0000) >> 16));
6076 }
6077
6078 RegisterList LDR_register_cccc011pu0w1nnnnttttiiiiitt0mmmm_case_0::
defs(Instruction inst) const6079 defs(Instruction inst) const {
6080 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6081 // defs: '{inst(15:12), inst(19:16)
6082 // if inst(24)=0 ||
6083 // inst(21)=1
6084 // else 32}'
6085 return RegisterList().
6086 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
6087 Add(Register((((inst.Bits() & 0x01000000) ==
6088 0x00000000) ||
6089 ((inst.Bits() & 0x00200000) ==
6090 0x00200000)
6091 ? ((inst.Bits() & 0x000F0000) >> 16)
6092 : 32)));
6093 }
6094
6095 SafetyLevel LDR_register_cccc011pu0w1nnnnttttiiiiitt0mmmm_case_0::
safety(Instruction inst) const6096 safety(Instruction inst) const {
6097 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6098
6099 // inst(24)=0 &&
6100 // inst(21)=1 => DECODER_ERROR
6101 if (((inst.Bits() & 0x01000000) ==
6102 0x00000000) &&
6103 ((inst.Bits() & 0x00200000) ==
6104 0x00200000))
6105 return DECODER_ERROR;
6106
6107 // 15 ==
6108 // inst(3:0) => UNPREDICTABLE
6109 if ((((inst.Bits() & 0x0000000F)) == (15)))
6110 return UNPREDICTABLE;
6111
6112 // inst(24)=0 ||
6113 // inst(21)=1 &&
6114 // (15 ==
6115 // inst(19:16) ||
6116 // inst(15:12) ==
6117 // inst(19:16)) => UNPREDICTABLE
6118 if ((((inst.Bits() & 0x01000000) ==
6119 0x00000000) ||
6120 ((inst.Bits() & 0x00200000) ==
6121 0x00200000)) &&
6122 (((((((inst.Bits() & 0x000F0000) >> 16)) == (15))) ||
6123 (((((inst.Bits() & 0x000F0000) >> 16)) == (((inst.Bits() & 0x0000F000) >> 12)))))))
6124 return UNPREDICTABLE;
6125
6126 // ArchVersion() <
6127 // 6 &&
6128 // inst(24)=0 ||
6129 // inst(21)=1 &&
6130 // inst(19:16) ==
6131 // inst(3:0) => UNPREDICTABLE
6132 if ((((nacl_arm_dec::ArchVersion()) < (6))) &&
6133 (((inst.Bits() & 0x01000000) ==
6134 0x00000000) ||
6135 ((inst.Bits() & 0x00200000) ==
6136 0x00200000)) &&
6137 (((((inst.Bits() & 0x000F0000) >> 16)) == ((inst.Bits() & 0x0000000F)))))
6138 return UNPREDICTABLE;
6139
6140 // inst(24)=1 => FORBIDDEN
6141 if ((inst.Bits() & 0x01000000) ==
6142 0x01000000)
6143 return FORBIDDEN;
6144
6145 // 15 ==
6146 // inst(15:12) => FORBIDDEN_OPERANDS
6147 if (((((inst.Bits() & 0x0000F000) >> 12)) == (15)))
6148 return FORBIDDEN_OPERANDS;
6149
6150 return MAY_BE_SAFE;
6151 }
6152
6153
6154 RegisterList LDR_register_cccc011pu0w1nnnnttttiiiiitt0mmmm_case_0::
uses(Instruction inst) const6155 uses(Instruction inst) const {
6156 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6157 // uses: '{inst(3:0), inst(19:16)}'
6158 return RegisterList().
6159 Add(Register((inst.Bits() & 0x0000000F))).
6160 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
6161 }
6162
6163 ViolationSet LDR_register_cccc011pu0w1nnnnttttiiiiitt0mmmm_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const6164 get_violations(const nacl_arm_val::DecodedInstruction& first,
6165 const nacl_arm_val::DecodedInstruction& second,
6166 const nacl_arm_val::SfiValidator& sfi,
6167 nacl_arm_val::AddressSet* branches,
6168 nacl_arm_val::AddressSet* critical,
6169 uint32_t* next_inst_addr) const {
6170 ViolationSet violations = ClassDecoder::get_violations(
6171 first, second, sfi, branches, critical, next_inst_addr);
6172
6173 // Report unsafe loads/stores of a base address by the given instruction
6174 // pair.
6175 violations = ViolationUnion(
6176 violations, get_loadstore_violations(first, second, sfi, critical));
6177
6178 return violations;
6179 }
6180
6181
6182 // LSL_immediate_cccc0001101s0000ddddiiiii000mmmm_case_0:
6183 //
6184 // {NZCV: 16,
6185 // None: 32,
6186 // Rd: Rd(15:12),
6187 // Rm: Rm(3:0),
6188 // S: S(20),
6189 // cond: cond(31:28),
6190 // defs: {Rd, NZCV
6191 // if S
6192 // else None},
6193 // fields: [cond(31:28),
6194 // S(20),
6195 // Rd(15:12),
6196 // imm5(11:7),
6197 // type(6:5),
6198 // Rm(3:0)],
6199 // imm5: imm5(11:7),
6200 // pattern: cccc0001101s0000ddddiiiii000mmmm,
6201 // rule: LSL_immediate,
6202 // safety: [(Rd(15:12)=1111 &&
6203 // S(20)=1) => DECODER_ERROR,
6204 // imm5(11:7)=00000 => DECODER_ERROR,
6205 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS],
6206 // shift: DecodeImmShift(type, imm5),
6207 // type: type(6:5),
6208 // uses: {Rm}}
6209 RegisterList LSL_immediate_cccc0001101s0000ddddiiiii000mmmm_case_0::
defs(Instruction inst) const6210 defs(Instruction inst) const {
6211 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6212 // defs: '{inst(15:12), 16
6213 // if inst(20)
6214 // else 32}'
6215 return RegisterList().
6216 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
6217 Add(Register(((((inst.Bits() & 0x00100000) >> 20) != 0)
6218 ? 16
6219 : 32)));
6220 }
6221
6222 SafetyLevel LSL_immediate_cccc0001101s0000ddddiiiii000mmmm_case_0::
safety(Instruction inst) const6223 safety(Instruction inst) const {
6224 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6225
6226 // (inst(15:12)=1111 &&
6227 // inst(20)=1) => DECODER_ERROR
6228 if ((((inst.Bits() & 0x0000F000) ==
6229 0x0000F000) &&
6230 ((inst.Bits() & 0x00100000) ==
6231 0x00100000)))
6232 return DECODER_ERROR;
6233
6234 // inst(11:7)=00000 => DECODER_ERROR
6235 if ((inst.Bits() & 0x00000F80) ==
6236 0x00000000)
6237 return DECODER_ERROR;
6238
6239 // inst(15:12)=1111 => FORBIDDEN_OPERANDS
6240 if ((inst.Bits() & 0x0000F000) ==
6241 0x0000F000)
6242 return FORBIDDEN_OPERANDS;
6243
6244 return MAY_BE_SAFE;
6245 }
6246
6247
6248 RegisterList LSL_immediate_cccc0001101s0000ddddiiiii000mmmm_case_0::
uses(Instruction inst) const6249 uses(Instruction inst) const {
6250 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6251 // uses: '{inst(3:0)}'
6252 return RegisterList().
6253 Add(Register((inst.Bits() & 0x0000000F)));
6254 }
6255
6256 // LSL_register_cccc0001101s0000ddddmmmm0001nnnn_case_0:
6257 //
6258 // {NZCV: 16,
6259 // None: 32,
6260 // Pc: 15,
6261 // Rd: Rd(15:12),
6262 // Rm: Rm(11:8),
6263 // Rn: Rn(3:0),
6264 // S: S(20),
6265 // cond: cond(31:28),
6266 // defs: {Rd, NZCV
6267 // if setflags
6268 // else None},
6269 // fields: [cond(31:28), S(20), Rd(15:12), Rm(11:8), Rn(3:0)],
6270 // pattern: cccc0001101s0000ddddmmmm0001nnnn,
6271 // rule: LSL_register,
6272 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE],
6273 // setflags: S(20)=1,
6274 // uses: {Rn, Rm}}
6275 RegisterList LSL_register_cccc0001101s0000ddddmmmm0001nnnn_case_0::
defs(Instruction inst) const6276 defs(Instruction inst) const {
6277 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6278 // defs: '{inst(15:12), 16
6279 // if inst(20)=1
6280 // else 32}'
6281 return RegisterList().
6282 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
6283 Add(Register(((inst.Bits() & 0x00100000) ==
6284 0x00100000
6285 ? 16
6286 : 32)));
6287 }
6288
6289 SafetyLevel LSL_register_cccc0001101s0000ddddmmmm0001nnnn_case_0::
safety(Instruction inst) const6290 safety(Instruction inst) const {
6291 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6292
6293 // 15 ==
6294 // inst(15:12) ||
6295 // 15 ==
6296 // inst(3:0) ||
6297 // 15 ==
6298 // inst(11:8) => UNPREDICTABLE
6299 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
6300 (((15) == ((inst.Bits() & 0x0000000F)))) ||
6301 (((15) == (((inst.Bits() & 0x00000F00) >> 8)))))
6302 return UNPREDICTABLE;
6303
6304 return MAY_BE_SAFE;
6305 }
6306
6307
6308 RegisterList LSL_register_cccc0001101s0000ddddmmmm0001nnnn_case_0::
uses(Instruction inst) const6309 uses(Instruction inst) const {
6310 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6311 // uses: '{inst(3:0), inst(11:8)}'
6312 return RegisterList().
6313 Add(Register((inst.Bits() & 0x0000000F))).
6314 Add(Register(((inst.Bits() & 0x00000F00) >> 8)));
6315 }
6316
6317 // LSR_immediate_cccc0001101s0000ddddiiiii010mmmm_case_0:
6318 //
6319 // {NZCV: 16,
6320 // None: 32,
6321 // Rd: Rd(15:12),
6322 // Rm: Rm(3:0),
6323 // S: S(20),
6324 // cond: cond(31:28),
6325 // defs: {Rd, NZCV
6326 // if S
6327 // else None},
6328 // fields: [cond(31:28),
6329 // S(20),
6330 // Rd(15:12),
6331 // imm5(11:7),
6332 // type(6:5),
6333 // Rm(3:0)],
6334 // imm5: imm5(11:7),
6335 // pattern: cccc0001101s0000ddddiiiii010mmmm,
6336 // rule: LSR_immediate,
6337 // safety: [(Rd(15:12)=1111 &&
6338 // S(20)=1) => DECODER_ERROR,
6339 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS],
6340 // shift: DecodeImmShift(type, imm5),
6341 // type: type(6:5),
6342 // uses: {Rm}}
6343 RegisterList LSR_immediate_cccc0001101s0000ddddiiiii010mmmm_case_0::
defs(Instruction inst) const6344 defs(Instruction inst) const {
6345 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6346 // defs: '{inst(15:12), 16
6347 // if inst(20)
6348 // else 32}'
6349 return RegisterList().
6350 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
6351 Add(Register(((((inst.Bits() & 0x00100000) >> 20) != 0)
6352 ? 16
6353 : 32)));
6354 }
6355
6356 SafetyLevel LSR_immediate_cccc0001101s0000ddddiiiii010mmmm_case_0::
safety(Instruction inst) const6357 safety(Instruction inst) const {
6358 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6359
6360 // (inst(15:12)=1111 &&
6361 // inst(20)=1) => DECODER_ERROR
6362 if ((((inst.Bits() & 0x0000F000) ==
6363 0x0000F000) &&
6364 ((inst.Bits() & 0x00100000) ==
6365 0x00100000)))
6366 return DECODER_ERROR;
6367
6368 // inst(15:12)=1111 => FORBIDDEN_OPERANDS
6369 if ((inst.Bits() & 0x0000F000) ==
6370 0x0000F000)
6371 return FORBIDDEN_OPERANDS;
6372
6373 return MAY_BE_SAFE;
6374 }
6375
6376
6377 RegisterList LSR_immediate_cccc0001101s0000ddddiiiii010mmmm_case_0::
uses(Instruction inst) const6378 uses(Instruction inst) const {
6379 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6380 // uses: '{inst(3:0)}'
6381 return RegisterList().
6382 Add(Register((inst.Bits() & 0x0000000F)));
6383 }
6384
6385 // LSR_register_cccc0001101s0000ddddmmmm0011nnnn_case_0:
6386 //
6387 // {NZCV: 16,
6388 // None: 32,
6389 // Pc: 15,
6390 // Rd: Rd(15:12),
6391 // Rm: Rm(11:8),
6392 // Rn: Rn(3:0),
6393 // S: S(20),
6394 // cond: cond(31:28),
6395 // defs: {Rd, NZCV
6396 // if setflags
6397 // else None},
6398 // fields: [cond(31:28), S(20), Rd(15:12), Rm(11:8), Rn(3:0)],
6399 // pattern: cccc0001101s0000ddddmmmm0011nnnn,
6400 // rule: LSR_register,
6401 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE],
6402 // setflags: S(20)=1,
6403 // uses: {Rn, Rm}}
6404 RegisterList LSR_register_cccc0001101s0000ddddmmmm0011nnnn_case_0::
defs(Instruction inst) const6405 defs(Instruction inst) const {
6406 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6407 // defs: '{inst(15:12), 16
6408 // if inst(20)=1
6409 // else 32}'
6410 return RegisterList().
6411 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
6412 Add(Register(((inst.Bits() & 0x00100000) ==
6413 0x00100000
6414 ? 16
6415 : 32)));
6416 }
6417
6418 SafetyLevel LSR_register_cccc0001101s0000ddddmmmm0011nnnn_case_0::
safety(Instruction inst) const6419 safety(Instruction inst) const {
6420 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6421
6422 // 15 ==
6423 // inst(15:12) ||
6424 // 15 ==
6425 // inst(3:0) ||
6426 // 15 ==
6427 // inst(11:8) => UNPREDICTABLE
6428 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
6429 (((15) == ((inst.Bits() & 0x0000000F)))) ||
6430 (((15) == (((inst.Bits() & 0x00000F00) >> 8)))))
6431 return UNPREDICTABLE;
6432
6433 return MAY_BE_SAFE;
6434 }
6435
6436
6437 RegisterList LSR_register_cccc0001101s0000ddddmmmm0011nnnn_case_0::
uses(Instruction inst) const6438 uses(Instruction inst) const {
6439 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6440 // uses: '{inst(3:0), inst(11:8)}'
6441 return RegisterList().
6442 Add(Register((inst.Bits() & 0x0000000F))).
6443 Add(Register(((inst.Bits() & 0x00000F00) >> 8)));
6444 }
6445
6446 // MCR2_11111110iii0iiiittttiiiiiii1iiii_case_0:
6447 //
6448 // {arch: v5,
6449 // defs: {},
6450 // pattern: 11111110iii0iiiittttiiiiiii1iiii,
6451 // rule: MCR2,
6452 // safety: [true => FORBIDDEN],
6453 // true: true,
6454 // uses: {}}
6455 RegisterList MCR2_11111110iii0iiiittttiiiiiii1iiii_case_0::
defs(Instruction inst) const6456 defs(Instruction inst) const {
6457 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6458 // defs: '{}'
6459 return RegisterList();
6460 }
6461
6462 SafetyLevel MCR2_11111110iii0iiiittttiiiiiii1iiii_case_0::
safety(Instruction inst) const6463 safety(Instruction inst) const {
6464 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6465
6466 // true => FORBIDDEN
6467 if (true)
6468 return FORBIDDEN;
6469
6470 return MAY_BE_SAFE;
6471 }
6472
6473
6474 RegisterList MCR2_11111110iii0iiiittttiiiiiii1iiii_case_0::
uses(Instruction inst) const6475 uses(Instruction inst) const {
6476 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6477 // uses: '{}'
6478 return RegisterList();
6479 }
6480
6481 // MCRR2_111111000100ssssttttiiiiiiiiiiii_case_0:
6482 //
6483 // {arch: v6,
6484 // defs: {},
6485 // pattern: 111111000100ssssttttiiiiiiiiiiii,
6486 // rule: MCRR2,
6487 // safety: [true => FORBIDDEN],
6488 // true: true,
6489 // uses: {}}
6490 RegisterList MCRR2_111111000100ssssttttiiiiiiiiiiii_case_0::
defs(Instruction inst) const6491 defs(Instruction inst) const {
6492 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6493 // defs: '{}'
6494 return RegisterList();
6495 }
6496
6497 SafetyLevel MCRR2_111111000100ssssttttiiiiiiiiiiii_case_0::
safety(Instruction inst) const6498 safety(Instruction inst) const {
6499 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6500
6501 // true => FORBIDDEN
6502 if (true)
6503 return FORBIDDEN;
6504
6505 return MAY_BE_SAFE;
6506 }
6507
6508
6509 RegisterList MCRR2_111111000100ssssttttiiiiiiiiiiii_case_0::
uses(Instruction inst) const6510 uses(Instruction inst) const {
6511 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6512 // uses: '{}'
6513 return RegisterList();
6514 }
6515
6516 // MCRR_cccc11000100ttttttttccccoooommmm_case_0:
6517 //
6518 // {arch: v5TE,
6519 // defs: {},
6520 // pattern: cccc11000100ttttttttccccoooommmm,
6521 // rule: MCRR,
6522 // safety: [true => FORBIDDEN],
6523 // true: true,
6524 // uses: {}}
6525 RegisterList MCRR_cccc11000100ttttttttccccoooommmm_case_0::
defs(Instruction inst) const6526 defs(Instruction inst) const {
6527 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6528 // defs: '{}'
6529 return RegisterList();
6530 }
6531
6532 SafetyLevel MCRR_cccc11000100ttttttttccccoooommmm_case_0::
safety(Instruction inst) const6533 safety(Instruction inst) const {
6534 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6535
6536 // true => FORBIDDEN
6537 if (true)
6538 return FORBIDDEN;
6539
6540 return MAY_BE_SAFE;
6541 }
6542
6543
6544 RegisterList MCRR_cccc11000100ttttttttccccoooommmm_case_0::
uses(Instruction inst) const6545 uses(Instruction inst) const {
6546 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6547 // uses: '{}'
6548 return RegisterList();
6549 }
6550
6551 // MCR_cccc1110ooo0nnnnttttccccooo1mmmm_case_0:
6552 //
6553 // {defs: {},
6554 // diagnostics: [inst(31:0)=xxxx111000000111xxxx111110111010 =>
6555 // error('Consider using DSB (defined in ARMv7) for memory barrier')],
6556 // inst: inst,
6557 // pattern: cccc1110ooo0nnnnttttccccooo1mmmm,
6558 // rule: MCR,
6559 // safety: [true => FORBIDDEN],
6560 // true: true,
6561 // uses: {},
6562 // violations: [inst(31:0)=xxxx111000000111xxxx111110111010 =>
6563 // error('Consider using DSB (defined in ARMv7) for memory barrier')]}
6564 RegisterList MCR_cccc1110ooo0nnnnttttccccooo1mmmm_case_0::
defs(Instruction inst) const6565 defs(Instruction inst) const {
6566 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6567 // defs: '{}'
6568 return RegisterList();
6569 }
6570
6571 void MCR_cccc1110ooo0nnnnttttccccooo1mmmm_case_0::
generate_diagnostics(ViolationSet violations,const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::ProblemSink * out) const6572 generate_diagnostics(ViolationSet violations,
6573 const nacl_arm_val::DecodedInstruction& first,
6574 const nacl_arm_val::DecodedInstruction& second,
6575 const nacl_arm_val::SfiValidator& sfi,
6576 nacl_arm_val::ProblemSink* out) const {
6577 ClassDecoder::generate_diagnostics(violations, first, second, sfi, out);
6578 const Instruction& inst = second.inst();
6579 if (ContainsViolation(violations, OTHER_VIOLATION)) {
6580
6581 // inst(31:0)=xxxx111000000111xxxx111110111010 =>
6582 // error('Consider using DSB (defined in ARMv7) for memory barrier')
6583 if ((inst.Bits() & 0x0FFF0FFF) ==
6584 0x0E070FBA) {
6585 out->ReportProblemDiagnostic(OTHER_VIOLATION, second.addr(),
6586 "Consider using DSB (defined in ARMv7) for memory barrier");
6587 }
6588
6589 }
6590 }
6591
6592
6593 SafetyLevel MCR_cccc1110ooo0nnnnttttccccooo1mmmm_case_0::
safety(Instruction inst) const6594 safety(Instruction inst) const {
6595 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6596
6597 // true => FORBIDDEN
6598 if (true)
6599 return FORBIDDEN;
6600
6601 return MAY_BE_SAFE;
6602 }
6603
6604
6605 RegisterList MCR_cccc1110ooo0nnnnttttccccooo1mmmm_case_0::
uses(Instruction inst) const6606 uses(Instruction inst) const {
6607 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6608 // uses: '{}'
6609 return RegisterList();
6610 }
6611
6612 ViolationSet MCR_cccc1110ooo0nnnnttttccccooo1mmmm_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const6613 get_violations(const nacl_arm_val::DecodedInstruction& first,
6614 const nacl_arm_val::DecodedInstruction& second,
6615 const nacl_arm_val::SfiValidator& sfi,
6616 nacl_arm_val::AddressSet* branches,
6617 nacl_arm_val::AddressSet* critical,
6618 uint32_t* next_inst_addr) const {
6619 ViolationSet violations = ClassDecoder::get_violations(
6620 first, second, sfi, branches, critical, next_inst_addr);
6621 const Instruction& inst = second.inst();
6622
6623 // inst(31:0)=xxxx111000000111xxxx111110111010 =>
6624 // error('Consider using DSB (defined in ARMv7) for memory barrier')
6625 if ((inst.Bits() & 0x0FFF0FFF) ==
6626 0x0E070FBA)
6627 violations = ViolationUnion(violations, ViolationBit(OTHER_VIOLATION));
6628
6629 return violations;
6630 }
6631
6632
6633 // MLA_A1_cccc0000001sddddaaaammmm1001nnnn_case_0:
6634 //
6635 // {NZCV: 16,
6636 // None: 32,
6637 // Pc: 15,
6638 // Ra: Ra(15:12),
6639 // Rd: Rd(19:16),
6640 // Rm: Rm(11:8),
6641 // Rn: Rn(3:0),
6642 // S: S(20),
6643 // cond: cond(31:28),
6644 // defs: {Rd, NZCV
6645 // if setflags
6646 // else None},
6647 // fields: [cond(31:28),
6648 // S(20),
6649 // Rd(19:16),
6650 // Ra(15:12),
6651 // Rm(11:8),
6652 // Rn(3:0)],
6653 // pattern: cccc0000001sddddaaaammmm1001nnnn,
6654 // rule: MLA_A1,
6655 // safety: [Pc in {Rd, Rn, Rm, Ra} => UNPREDICTABLE,
6656 // (ArchVersion() <
6657 // 6 &&
6658 // Rd ==
6659 // Rn) => UNPREDICTABLE],
6660 // setflags: S(20)=1,
6661 // uses: {Rn, Rm, Ra}}
6662 RegisterList MLA_A1_cccc0000001sddddaaaammmm1001nnnn_case_0::
defs(Instruction inst) const6663 defs(Instruction inst) const {
6664 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6665 // defs: '{inst(19:16), 16
6666 // if inst(20)=1
6667 // else 32}'
6668 return RegisterList().
6669 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
6670 Add(Register(((inst.Bits() & 0x00100000) ==
6671 0x00100000
6672 ? 16
6673 : 32)));
6674 }
6675
6676 SafetyLevel MLA_A1_cccc0000001sddddaaaammmm1001nnnn_case_0::
safety(Instruction inst) const6677 safety(Instruction inst) const {
6678 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6679
6680 // 15 ==
6681 // inst(19:16) ||
6682 // 15 ==
6683 // inst(3:0) ||
6684 // 15 ==
6685 // inst(11:8) ||
6686 // 15 ==
6687 // inst(15:12) => UNPREDICTABLE
6688 if ((((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
6689 (((15) == ((inst.Bits() & 0x0000000F)))) ||
6690 (((15) == (((inst.Bits() & 0x00000F00) >> 8)))) ||
6691 (((15) == (((inst.Bits() & 0x0000F000) >> 12)))))
6692 return UNPREDICTABLE;
6693
6694 // (ArchVersion() <
6695 // 6 &&
6696 // inst(19:16) ==
6697 // inst(3:0)) => UNPREDICTABLE
6698 if (((((nacl_arm_dec::ArchVersion()) < (6))) &&
6699 (((((inst.Bits() & 0x000F0000) >> 16)) == ((inst.Bits() & 0x0000000F))))))
6700 return UNPREDICTABLE;
6701
6702 return MAY_BE_SAFE;
6703 }
6704
6705
6706 RegisterList MLA_A1_cccc0000001sddddaaaammmm1001nnnn_case_0::
uses(Instruction inst) const6707 uses(Instruction inst) const {
6708 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6709 // uses: '{inst(3:0), inst(11:8), inst(15:12)}'
6710 return RegisterList().
6711 Add(Register((inst.Bits() & 0x0000000F))).
6712 Add(Register(((inst.Bits() & 0x00000F00) >> 8))).
6713 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
6714 }
6715
6716 // MLS_A1_cccc00000110ddddaaaammmm1001nnnn_case_0:
6717 //
6718 // {Pc: 15,
6719 // Ra: Ra(15:12),
6720 // Rd: Rd(19:16),
6721 // Rm: Rm(11:8),
6722 // Rn: Rn(3:0),
6723 // arch: v6T2,
6724 // cond: cond(31:28),
6725 // defs: {Rd},
6726 // fields: [cond(31:28), Rd(19:16), Ra(15:12), Rm(11:8), Rn(3:0)],
6727 // pattern: cccc00000110ddddaaaammmm1001nnnn,
6728 // rule: MLS_A1,
6729 // safety: [Pc in {Rd, Rn, Rm, Ra} => UNPREDICTABLE],
6730 // uses: {Rn, Rm, Ra}}
6731 RegisterList MLS_A1_cccc00000110ddddaaaammmm1001nnnn_case_0::
defs(Instruction inst) const6732 defs(Instruction inst) const {
6733 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6734 // defs: '{inst(19:16)}'
6735 return RegisterList().
6736 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
6737 }
6738
6739 SafetyLevel MLS_A1_cccc00000110ddddaaaammmm1001nnnn_case_0::
safety(Instruction inst) const6740 safety(Instruction inst) const {
6741 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6742
6743 // 15 ==
6744 // inst(19:16) ||
6745 // 15 ==
6746 // inst(3:0) ||
6747 // 15 ==
6748 // inst(11:8) ||
6749 // 15 ==
6750 // inst(15:12) => UNPREDICTABLE
6751 if ((((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
6752 (((15) == ((inst.Bits() & 0x0000000F)))) ||
6753 (((15) == (((inst.Bits() & 0x00000F00) >> 8)))) ||
6754 (((15) == (((inst.Bits() & 0x0000F000) >> 12)))))
6755 return UNPREDICTABLE;
6756
6757 return MAY_BE_SAFE;
6758 }
6759
6760
6761 RegisterList MLS_A1_cccc00000110ddddaaaammmm1001nnnn_case_0::
uses(Instruction inst) const6762 uses(Instruction inst) const {
6763 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6764 // uses: '{inst(3:0), inst(11:8), inst(15:12)}'
6765 return RegisterList().
6766 Add(Register((inst.Bits() & 0x0000000F))).
6767 Add(Register(((inst.Bits() & 0x00000F00) >> 8))).
6768 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
6769 }
6770
6771 // MOVE_scalar_to_ARM_core_register_cccc1110iii1nnnntttt1011nii10000_case_0:
6772 //
6773 // {N: N(7),
6774 // Pc: 15,
6775 // Rt: Rt(15:12),
6776 // U: U(23),
6777 // Vn: Vn(19:16),
6778 // advsimd: sel in bitset {'x1xxx', 'x0xx1'},
6779 // arch: ['VFPv2', 'AdvSIMD'],
6780 // cond: cond(31:28),
6781 // defs: {Rt},
6782 // esize: 8
6783 // if U:opc1:opc2(4:0)=x1xxx
6784 // else 16
6785 // if U:opc1:opc2(4:0)=x0xx1
6786 // else 32
6787 // if U:opc1:opc2(4:0)=00x00
6788 // else 0,
6789 // fields: [cond(31:28),
6790 // U(23),
6791 // opc1(22:21),
6792 // Vn(19:16),
6793 // Rt(15:12),
6794 // N(7),
6795 // opc2(6:5)],
6796 // index: opc1(0):opc2
6797 // if U:opc1:opc2(4:0)=x1xxx
6798 // else opc1(0):opc2(1)
6799 // if U:opc1:opc2(4:0)=x0xx1
6800 // else opc1(0)
6801 // if U:opc1:opc2(4:0)=00x00
6802 // else 0,
6803 // n: N:Vn,
6804 // opc1: opc1(22:21),
6805 // opc2: opc2(6:5),
6806 // pattern: cccc1110iii1nnnntttt1011nii10000,
6807 // rule: MOVE_scalar_to_ARM_core_register,
6808 // safety: [sel in bitset {'10x00', 'x0x10'} => UNDEFINED,
6809 // t ==
6810 // Pc => UNPREDICTABLE],
6811 // sel: U:opc1:opc2,
6812 // t: Rt,
6813 // unsigned: U(23)=1}
6814 RegisterList MOVE_scalar_to_ARM_core_register_cccc1110iii1nnnntttt1011nii10000_case_0::
defs(Instruction inst) const6815 defs(Instruction inst) const {
6816 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6817 // defs: '{inst(15:12)}'
6818 return RegisterList().
6819 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
6820 }
6821
6822 SafetyLevel MOVE_scalar_to_ARM_core_register_cccc1110iii1nnnntttt1011nii10000_case_0::
safety(Instruction inst) const6823 safety(Instruction inst) const {
6824 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6825
6826 // inst(23):inst(22:21):inst(6:5)(4:0)=10x00 ||
6827 // inst(23):inst(22:21):inst(6:5)(4:0)=x0x10 => UNDEFINED
6828 if (((((((((((inst.Bits() & 0x00800000) >> 23)) << 2) | ((inst.Bits() & 0x00600000) >> 21))) << 2) | ((inst.Bits() & 0x00000060) >> 5)) & 0x0000001B) ==
6829 0x00000010) ||
6830 ((((((((((inst.Bits() & 0x00800000) >> 23)) << 2) | ((inst.Bits() & 0x00600000) >> 21))) << 2) | ((inst.Bits() & 0x00000060) >> 5)) & 0x0000000B) ==
6831 0x00000002))
6832 return UNDEFINED;
6833
6834 // 15 ==
6835 // inst(15:12) => UNPREDICTABLE
6836 if (((((inst.Bits() & 0x0000F000) >> 12)) == (15)))
6837 return UNPREDICTABLE;
6838
6839 return MAY_BE_SAFE;
6840 }
6841
6842
6843 // MOVT_cccc00110100iiiiddddiiiiiiiiiiii_case_0:
6844 //
6845 // {NZCV: 16,
6846 // None: 32,
6847 // Rd: Rd(15:12),
6848 // S: S(20),
6849 // arch: v6T2,
6850 // cond: cond(31:28),
6851 // defs: {Rd, NZCV
6852 // if S
6853 // else None},
6854 // dynamic_code_replace_immediates: {imm4, imm12},
6855 // fields: [cond(31:28), S(20), imm4(19:16), Rd(15:12), imm12(11:0)],
6856 // imm: imm4:imm12,
6857 // imm12: imm12(11:0),
6858 // imm4: imm4(19:16),
6859 // pattern: cccc00110100iiiiddddiiiiiiiiiiii,
6860 // rule: MOVT,
6861 // safety: [Rd(15:12)=1111 => UNPREDICTABLE],
6862 // uses: {}}
6863 RegisterList MOVT_cccc00110100iiiiddddiiiiiiiiiiii_case_0::
defs(Instruction inst) const6864 defs(Instruction inst) const {
6865 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6866 // defs: '{inst(15:12), 16
6867 // if inst(20)
6868 // else 32}'
6869 return RegisterList().
6870 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
6871 Add(Register(((((inst.Bits() & 0x00100000) >> 20) != 0)
6872 ? 16
6873 : 32)));
6874 }
6875
6876 Instruction MOVT_cccc00110100iiiiddddiiiiiiiiiiii_case_0::
dynamic_code_replacement_sentinel(Instruction inst) const6877 dynamic_code_replacement_sentinel(
6878 Instruction inst) const {
6879 if (!defs(inst).ContainsAny(RegisterList::DynCodeReplaceFrozenRegs())) {
6880 // inst(19:16)
6881 inst.SetBits(19, 16, 0);
6882 // inst(11:0)
6883 inst.SetBits(11, 0, 0);
6884 }
6885 return inst;
6886 }
6887
6888 SafetyLevel MOVT_cccc00110100iiiiddddiiiiiiiiiiii_case_0::
safety(Instruction inst) const6889 safety(Instruction inst) const {
6890 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6891
6892 // inst(15:12)=1111 => UNPREDICTABLE
6893 if ((inst.Bits() & 0x0000F000) ==
6894 0x0000F000)
6895 return UNPREDICTABLE;
6896
6897 return MAY_BE_SAFE;
6898 }
6899
6900
6901 RegisterList MOVT_cccc00110100iiiiddddiiiiiiiiiiii_case_0::
uses(Instruction inst) const6902 uses(Instruction inst) const {
6903 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6904 // uses: '{}'
6905 return RegisterList();
6906 }
6907
6908 // MOVW_cccc00110000iiiiddddiiiiiiiiiiii_case_0:
6909 //
6910 // {NZCV: 16,
6911 // None: 32,
6912 // Rd: Rd(15:12),
6913 // S: S(20),
6914 // arch: v6T2,
6915 // cond: cond(31:28),
6916 // defs: {Rd, NZCV
6917 // if S
6918 // else None},
6919 // dynamic_code_replace_immediates: {imm4, imm12},
6920 // fields: [cond(31:28), S(20), imm4(19:16), Rd(15:12), imm12(11:0)],
6921 // imm: imm4:imm12,
6922 // imm12: imm12(11:0),
6923 // imm4: imm4(19:16),
6924 // pattern: cccc00110000iiiiddddiiiiiiiiiiii,
6925 // rule: MOVW,
6926 // safety: [Rd(15:12)=1111 => UNPREDICTABLE],
6927 // uses: {}}
6928 RegisterList MOVW_cccc00110000iiiiddddiiiiiiiiiiii_case_0::
defs(Instruction inst) const6929 defs(Instruction inst) const {
6930 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6931 // defs: '{inst(15:12), 16
6932 // if inst(20)
6933 // else 32}'
6934 return RegisterList().
6935 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
6936 Add(Register(((((inst.Bits() & 0x00100000) >> 20) != 0)
6937 ? 16
6938 : 32)));
6939 }
6940
6941 Instruction MOVW_cccc00110000iiiiddddiiiiiiiiiiii_case_0::
dynamic_code_replacement_sentinel(Instruction inst) const6942 dynamic_code_replacement_sentinel(
6943 Instruction inst) const {
6944 if (!defs(inst).ContainsAny(RegisterList::DynCodeReplaceFrozenRegs())) {
6945 // inst(19:16)
6946 inst.SetBits(19, 16, 0);
6947 // inst(11:0)
6948 inst.SetBits(11, 0, 0);
6949 }
6950 return inst;
6951 }
6952
6953 SafetyLevel MOVW_cccc00110000iiiiddddiiiiiiiiiiii_case_0::
safety(Instruction inst) const6954 safety(Instruction inst) const {
6955 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6956
6957 // inst(15:12)=1111 => UNPREDICTABLE
6958 if ((inst.Bits() & 0x0000F000) ==
6959 0x0000F000)
6960 return UNPREDICTABLE;
6961
6962 return MAY_BE_SAFE;
6963 }
6964
6965
6966 RegisterList MOVW_cccc00110000iiiiddddiiiiiiiiiiii_case_0::
uses(Instruction inst) const6967 uses(Instruction inst) const {
6968 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6969 // uses: '{}'
6970 return RegisterList();
6971 }
6972
6973 // MOV_immediate_A1_cccc0011101s0000ddddiiiiiiiiiiii_case_0:
6974 //
6975 // {NZCV: 16,
6976 // None: 32,
6977 // Rd: Rd(15:12),
6978 // S: S(20),
6979 // cond: cond(31:28),
6980 // defs: {Rd, NZCV
6981 // if setflags
6982 // else None},
6983 // dynamic_code_replace_immediates: {imm12},
6984 // fields: [cond(31:28), S(20), Rd(15:12), imm12(11:0)],
6985 // imm12: imm12(11:0),
6986 // imm32: ARMExpandImm(imm12),
6987 // pattern: cccc0011101s0000ddddiiiiiiiiiiii,
6988 // rule: MOV_immediate_A1,
6989 // safety: [(Rd(15:12)=1111 &&
6990 // S(20)=1) => DECODER_ERROR,
6991 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS],
6992 // setflags: S(20)=1,
6993 // uses: {}}
6994 RegisterList MOV_immediate_A1_cccc0011101s0000ddddiiiiiiiiiiii_case_0::
defs(Instruction inst) const6995 defs(Instruction inst) const {
6996 UNREFERENCED_PARAMETER(inst); // To silence compiler.
6997 // defs: '{inst(15:12), 16
6998 // if inst(20)=1
6999 // else 32}'
7000 return RegisterList().
7001 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
7002 Add(Register(((inst.Bits() & 0x00100000) ==
7003 0x00100000
7004 ? 16
7005 : 32)));
7006 }
7007
7008 Instruction MOV_immediate_A1_cccc0011101s0000ddddiiiiiiiiiiii_case_0::
dynamic_code_replacement_sentinel(Instruction inst) const7009 dynamic_code_replacement_sentinel(
7010 Instruction inst) const {
7011 if (!defs(inst).ContainsAny(RegisterList::DynCodeReplaceFrozenRegs())) {
7012 // inst(11:0)
7013 inst.SetBits(11, 0, 0);
7014 }
7015 return inst;
7016 }
7017
7018 SafetyLevel MOV_immediate_A1_cccc0011101s0000ddddiiiiiiiiiiii_case_0::
safety(Instruction inst) const7019 safety(Instruction inst) const {
7020 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7021
7022 // (inst(15:12)=1111 &&
7023 // inst(20)=1) => DECODER_ERROR
7024 if ((((inst.Bits() & 0x0000F000) ==
7025 0x0000F000) &&
7026 ((inst.Bits() & 0x00100000) ==
7027 0x00100000)))
7028 return DECODER_ERROR;
7029
7030 // inst(15:12)=1111 => FORBIDDEN_OPERANDS
7031 if ((inst.Bits() & 0x0000F000) ==
7032 0x0000F000)
7033 return FORBIDDEN_OPERANDS;
7034
7035 return MAY_BE_SAFE;
7036 }
7037
7038
7039 RegisterList MOV_immediate_A1_cccc0011101s0000ddddiiiiiiiiiiii_case_0::
uses(Instruction inst) const7040 uses(Instruction inst) const {
7041 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7042 // uses: '{}'
7043 return RegisterList();
7044 }
7045
7046 // MOV_register_cccc0001101s0000dddd00000000mmmm_case_0:
7047 //
7048 // {NZCV: 16,
7049 // None: 32,
7050 // Rd: Rd(15:12),
7051 // Rm: Rm(3:0),
7052 // S: S(20),
7053 // cond: cond(31:28),
7054 // defs: {Rd, NZCV
7055 // if S
7056 // else None},
7057 // fields: [cond(31:28), S(20), Rd(15:12), Rm(3:0)],
7058 // pattern: cccc0001101s0000dddd00000000mmmm,
7059 // rule: MOV_register,
7060 // safety: [(Rd(15:12)=1111 &&
7061 // S(20)=1) => DECODER_ERROR,
7062 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS],
7063 // uses: {Rm}}
7064 RegisterList MOV_register_cccc0001101s0000dddd00000000mmmm_case_0::
defs(Instruction inst) const7065 defs(Instruction inst) const {
7066 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7067 // defs: '{inst(15:12), 16
7068 // if inst(20)
7069 // else 32}'
7070 return RegisterList().
7071 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
7072 Add(Register(((((inst.Bits() & 0x00100000) >> 20) != 0)
7073 ? 16
7074 : 32)));
7075 }
7076
7077 SafetyLevel MOV_register_cccc0001101s0000dddd00000000mmmm_case_0::
safety(Instruction inst) const7078 safety(Instruction inst) const {
7079 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7080
7081 // (inst(15:12)=1111 &&
7082 // inst(20)=1) => DECODER_ERROR
7083 if ((((inst.Bits() & 0x0000F000) ==
7084 0x0000F000) &&
7085 ((inst.Bits() & 0x00100000) ==
7086 0x00100000)))
7087 return DECODER_ERROR;
7088
7089 // inst(15:12)=1111 => FORBIDDEN_OPERANDS
7090 if ((inst.Bits() & 0x0000F000) ==
7091 0x0000F000)
7092 return FORBIDDEN_OPERANDS;
7093
7094 return MAY_BE_SAFE;
7095 }
7096
7097
7098 RegisterList MOV_register_cccc0001101s0000dddd00000000mmmm_case_0::
uses(Instruction inst) const7099 uses(Instruction inst) const {
7100 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7101 // uses: '{inst(3:0)}'
7102 return RegisterList().
7103 Add(Register((inst.Bits() & 0x0000000F)));
7104 }
7105
7106 // MRC2_11111110iii1iiiittttiiiiiii1iiii_case_0:
7107 //
7108 // {arch: v5,
7109 // defs: {},
7110 // pattern: 11111110iii1iiiittttiiiiiii1iiii,
7111 // rule: MRC2,
7112 // safety: [true => FORBIDDEN],
7113 // true: true,
7114 // uses: {}}
7115 RegisterList MRC2_11111110iii1iiiittttiiiiiii1iiii_case_0::
defs(Instruction inst) const7116 defs(Instruction inst) const {
7117 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7118 // defs: '{}'
7119 return RegisterList();
7120 }
7121
7122 SafetyLevel MRC2_11111110iii1iiiittttiiiiiii1iiii_case_0::
safety(Instruction inst) const7123 safety(Instruction inst) const {
7124 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7125
7126 // true => FORBIDDEN
7127 if (true)
7128 return FORBIDDEN;
7129
7130 return MAY_BE_SAFE;
7131 }
7132
7133
7134 RegisterList MRC2_11111110iii1iiiittttiiiiiii1iiii_case_0::
uses(Instruction inst) const7135 uses(Instruction inst) const {
7136 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7137 // uses: '{}'
7138 return RegisterList();
7139 }
7140
7141 // MRC_cccc1110ooo1nnnnttttccccooo1mmmm_case_0:
7142 //
7143 // {defs: {},
7144 // pattern: cccc1110ooo1nnnnttttccccooo1mmmm,
7145 // rule: MRC,
7146 // safety: [true => FORBIDDEN],
7147 // true: true,
7148 // uses: {}}
7149 RegisterList MRC_cccc1110ooo1nnnnttttccccooo1mmmm_case_0::
defs(Instruction inst) const7150 defs(Instruction inst) const {
7151 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7152 // defs: '{}'
7153 return RegisterList();
7154 }
7155
7156 SafetyLevel MRC_cccc1110ooo1nnnnttttccccooo1mmmm_case_0::
safety(Instruction inst) const7157 safety(Instruction inst) const {
7158 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7159
7160 // true => FORBIDDEN
7161 if (true)
7162 return FORBIDDEN;
7163
7164 return MAY_BE_SAFE;
7165 }
7166
7167
7168 RegisterList MRC_cccc1110ooo1nnnnttttccccooo1mmmm_case_0::
uses(Instruction inst) const7169 uses(Instruction inst) const {
7170 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7171 // uses: '{}'
7172 return RegisterList();
7173 }
7174
7175 // MRRC2_111111000101ssssttttiiiiiiiiiiii_case_0:
7176 //
7177 // {arch: v6,
7178 // defs: {},
7179 // pattern: 111111000101ssssttttiiiiiiiiiiii,
7180 // rule: MRRC2,
7181 // safety: [true => FORBIDDEN],
7182 // true: true,
7183 // uses: {}}
7184 RegisterList MRRC2_111111000101ssssttttiiiiiiiiiiii_case_0::
defs(Instruction inst) const7185 defs(Instruction inst) const {
7186 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7187 // defs: '{}'
7188 return RegisterList();
7189 }
7190
7191 SafetyLevel MRRC2_111111000101ssssttttiiiiiiiiiiii_case_0::
safety(Instruction inst) const7192 safety(Instruction inst) const {
7193 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7194
7195 // true => FORBIDDEN
7196 if (true)
7197 return FORBIDDEN;
7198
7199 return MAY_BE_SAFE;
7200 }
7201
7202
7203 RegisterList MRRC2_111111000101ssssttttiiiiiiiiiiii_case_0::
uses(Instruction inst) const7204 uses(Instruction inst) const {
7205 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7206 // uses: '{}'
7207 return RegisterList();
7208 }
7209
7210 // MRRC_cccc11000101ttttttttccccoooommmm_case_0:
7211 //
7212 // {arch: v5TE,
7213 // defs: {},
7214 // pattern: cccc11000101ttttttttccccoooommmm,
7215 // rule: MRRC,
7216 // safety: [true => FORBIDDEN],
7217 // true: true,
7218 // uses: {}}
7219 RegisterList MRRC_cccc11000101ttttttttccccoooommmm_case_0::
defs(Instruction inst) const7220 defs(Instruction inst) const {
7221 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7222 // defs: '{}'
7223 return RegisterList();
7224 }
7225
7226 SafetyLevel MRRC_cccc11000101ttttttttccccoooommmm_case_0::
safety(Instruction inst) const7227 safety(Instruction inst) const {
7228 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7229
7230 // true => FORBIDDEN
7231 if (true)
7232 return FORBIDDEN;
7233
7234 return MAY_BE_SAFE;
7235 }
7236
7237
7238 RegisterList MRRC_cccc11000101ttttttttccccoooommmm_case_0::
uses(Instruction inst) const7239 uses(Instruction inst) const {
7240 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7241 // uses: '{}'
7242 return RegisterList();
7243 }
7244
7245 // MRS_Banked_register_cccc00010r00mmmmdddd001m00000000_case_0:
7246 //
7247 // {arch: v7VE,
7248 // defs: {},
7249 // pattern: cccc00010r00mmmmdddd001m00000000,
7250 // rule: MRS_Banked_register,
7251 // safety: [true => FORBIDDEN],
7252 // true: true,
7253 // uses: {}}
7254 RegisterList MRS_Banked_register_cccc00010r00mmmmdddd001m00000000_case_0::
defs(Instruction inst) const7255 defs(Instruction inst) const {
7256 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7257 // defs: '{}'
7258 return RegisterList();
7259 }
7260
7261 SafetyLevel MRS_Banked_register_cccc00010r00mmmmdddd001m00000000_case_0::
safety(Instruction inst) const7262 safety(Instruction inst) const {
7263 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7264
7265 // true => FORBIDDEN
7266 if (true)
7267 return FORBIDDEN;
7268
7269 return MAY_BE_SAFE;
7270 }
7271
7272
7273 RegisterList MRS_Banked_register_cccc00010r00mmmmdddd001m00000000_case_0::
uses(Instruction inst) const7274 uses(Instruction inst) const {
7275 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7276 // uses: '{}'
7277 return RegisterList();
7278 }
7279
7280 // MRS_Banked_register_cccc00010r10mmmm1111001m0000nnnn_case_0:
7281 //
7282 // {arch: v7VE,
7283 // defs: {},
7284 // pattern: cccc00010r10mmmm1111001m0000nnnn,
7285 // rule: MRS_Banked_register,
7286 // safety: [true => FORBIDDEN],
7287 // true: true,
7288 // uses: {}}
7289 RegisterList MRS_Banked_register_cccc00010r10mmmm1111001m0000nnnn_case_0::
defs(Instruction inst) const7290 defs(Instruction inst) const {
7291 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7292 // defs: '{}'
7293 return RegisterList();
7294 }
7295
7296 SafetyLevel MRS_Banked_register_cccc00010r10mmmm1111001m0000nnnn_case_0::
safety(Instruction inst) const7297 safety(Instruction inst) const {
7298 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7299
7300 // true => FORBIDDEN
7301 if (true)
7302 return FORBIDDEN;
7303
7304 return MAY_BE_SAFE;
7305 }
7306
7307
7308 RegisterList MRS_Banked_register_cccc00010r10mmmm1111001m0000nnnn_case_0::
uses(Instruction inst) const7309 uses(Instruction inst) const {
7310 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7311 // uses: '{}'
7312 return RegisterList();
7313 }
7314
7315 // MRS_cccc00010r001111dddd000000000000_case_0:
7316 //
7317 // {R: R(22),
7318 // Rd: Rd(15:12),
7319 // cond: cond(31:28),
7320 // defs: {Rd},
7321 // fields: [cond(31:28), R(22), Rd(15:12)],
7322 // pattern: cccc00010r001111dddd000000000000,
7323 // read_spsr: R(22)=1,
7324 // rule: MRS,
7325 // safety: [R(22)=1 => FORBIDDEN_OPERANDS,
7326 // Rd(15:12)=1111 => UNPREDICTABLE],
7327 // uses: {}}
7328 RegisterList MRS_cccc00010r001111dddd000000000000_case_0::
defs(Instruction inst) const7329 defs(Instruction inst) const {
7330 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7331 // defs: '{inst(15:12)}'
7332 return RegisterList().
7333 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
7334 }
7335
7336 SafetyLevel MRS_cccc00010r001111dddd000000000000_case_0::
safety(Instruction inst) const7337 safety(Instruction inst) const {
7338 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7339
7340 // inst(22)=1 => FORBIDDEN_OPERANDS
7341 if ((inst.Bits() & 0x00400000) ==
7342 0x00400000)
7343 return FORBIDDEN_OPERANDS;
7344
7345 // inst(15:12)=1111 => UNPREDICTABLE
7346 if ((inst.Bits() & 0x0000F000) ==
7347 0x0000F000)
7348 return UNPREDICTABLE;
7349
7350 return MAY_BE_SAFE;
7351 }
7352
7353
7354 RegisterList MRS_cccc00010r001111dddd000000000000_case_0::
uses(Instruction inst) const7355 uses(Instruction inst) const {
7356 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7357 // uses: '{}'
7358 return RegisterList();
7359 }
7360
7361 // MSR_immediate_cccc00110010mm001111iiiiiiiiiiii_case_0:
7362 //
7363 // {NZCV: 16,
7364 // None: 32,
7365 // cond: cond(31:28),
7366 // defs: {NZCV
7367 // if write_nzcvq
7368 // else None},
7369 // fields: [cond(31:28), mask(19:18), imm12(11:0)],
7370 // imm12: imm12(11:0),
7371 // imm32: ARMExpandImm(imm12),
7372 // mask: mask(19:18),
7373 // pattern: cccc00110010mm001111iiiiiiiiiiii,
7374 // rule: MSR_immediate,
7375 // safety: [mask(19:18)=00 => DECODER_ERROR],
7376 // uses: {},
7377 // write_g: mask(0)=1,
7378 // write_nzcvq: mask(1)=1}
7379 RegisterList MSR_immediate_cccc00110010mm001111iiiiiiiiiiii_case_0::
defs(Instruction inst) const7380 defs(Instruction inst) const {
7381 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7382 // defs: '{16
7383 // if inst(19:18)(1)=1
7384 // else 32}'
7385 return RegisterList().
7386 Add(Register(((((inst.Bits() & 0x000C0000) >> 18) & 0x00000002) ==
7387 0x00000002
7388 ? 16
7389 : 32)));
7390 }
7391
7392 SafetyLevel MSR_immediate_cccc00110010mm001111iiiiiiiiiiii_case_0::
safety(Instruction inst) const7393 safety(Instruction inst) const {
7394 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7395
7396 // inst(19:18)=00 => DECODER_ERROR
7397 if ((inst.Bits() & 0x000C0000) ==
7398 0x00000000)
7399 return DECODER_ERROR;
7400
7401 return MAY_BE_SAFE;
7402 }
7403
7404
7405 RegisterList MSR_immediate_cccc00110010mm001111iiiiiiiiiiii_case_0::
uses(Instruction inst) const7406 uses(Instruction inst) const {
7407 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7408 // uses: '{}'
7409 return RegisterList();
7410 }
7411
7412 // MSR_immediate_cccc00110r10mmmm1111iiiiiiiiiiii_case_0:
7413 //
7414 // {defs: {},
7415 // pattern: cccc00110r10mmmm1111iiiiiiiiiiii,
7416 // rule: MSR_immediate,
7417 // safety: [true => FORBIDDEN],
7418 // true: true,
7419 // uses: {}}
7420 RegisterList MSR_immediate_cccc00110r10mmmm1111iiiiiiiiiiii_case_0::
defs(Instruction inst) const7421 defs(Instruction inst) const {
7422 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7423 // defs: '{}'
7424 return RegisterList();
7425 }
7426
7427 SafetyLevel MSR_immediate_cccc00110r10mmmm1111iiiiiiiiiiii_case_0::
safety(Instruction inst) const7428 safety(Instruction inst) const {
7429 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7430
7431 // true => FORBIDDEN
7432 if (true)
7433 return FORBIDDEN;
7434
7435 return MAY_BE_SAFE;
7436 }
7437
7438
7439 RegisterList MSR_immediate_cccc00110r10mmmm1111iiiiiiiiiiii_case_0::
uses(Instruction inst) const7440 uses(Instruction inst) const {
7441 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7442 // uses: '{}'
7443 return RegisterList();
7444 }
7445
7446 // MSR_register_cccc00010010mm00111100000000nnnn_case_0:
7447 //
7448 // {NZCV: 16,
7449 // None: 32,
7450 // Pc: 15,
7451 // Rn: Rn(3:0),
7452 // cond: cond(31:28),
7453 // defs: {NZCV
7454 // if write_nzcvq
7455 // else None},
7456 // fields: [cond(31:28), mask(19:18), Rn(3:0)],
7457 // mask: mask(19:18),
7458 // pattern: cccc00010010mm00111100000000nnnn,
7459 // rule: MSR_register,
7460 // safety: [mask(19:18)=00 => UNPREDICTABLE,
7461 // Rn ==
7462 // Pc => UNPREDICTABLE],
7463 // uses: {Rn},
7464 // write_g: mask(0)=1,
7465 // write_nzcvq: mask(1)=1}
7466 RegisterList MSR_register_cccc00010010mm00111100000000nnnn_case_0::
defs(Instruction inst) const7467 defs(Instruction inst) const {
7468 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7469 // defs: '{16
7470 // if inst(19:18)(1)=1
7471 // else 32}'
7472 return RegisterList().
7473 Add(Register(((((inst.Bits() & 0x000C0000) >> 18) & 0x00000002) ==
7474 0x00000002
7475 ? 16
7476 : 32)));
7477 }
7478
7479 SafetyLevel MSR_register_cccc00010010mm00111100000000nnnn_case_0::
safety(Instruction inst) const7480 safety(Instruction inst) const {
7481 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7482
7483 // inst(19:18)=00 => UNPREDICTABLE
7484 if ((inst.Bits() & 0x000C0000) ==
7485 0x00000000)
7486 return UNPREDICTABLE;
7487
7488 // 15 ==
7489 // inst(3:0) => UNPREDICTABLE
7490 if ((((inst.Bits() & 0x0000000F)) == (15)))
7491 return UNPREDICTABLE;
7492
7493 return MAY_BE_SAFE;
7494 }
7495
7496
7497 RegisterList MSR_register_cccc00010010mm00111100000000nnnn_case_0::
uses(Instruction inst) const7498 uses(Instruction inst) const {
7499 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7500 // uses: '{inst(3:0)}'
7501 return RegisterList().
7502 Add(Register((inst.Bits() & 0x0000000F)));
7503 }
7504
7505 // MSR_register_cccc00010r10mmmm111100000000nnnn_case_0:
7506 //
7507 // {defs: {},
7508 // pattern: cccc00010r10mmmm111100000000nnnn,
7509 // rule: MSR_register,
7510 // safety: [true => FORBIDDEN],
7511 // true: true,
7512 // uses: {}}
7513 RegisterList MSR_register_cccc00010r10mmmm111100000000nnnn_case_0::
defs(Instruction inst) const7514 defs(Instruction inst) const {
7515 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7516 // defs: '{}'
7517 return RegisterList();
7518 }
7519
7520 SafetyLevel MSR_register_cccc00010r10mmmm111100000000nnnn_case_0::
safety(Instruction inst) const7521 safety(Instruction inst) const {
7522 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7523
7524 // true => FORBIDDEN
7525 if (true)
7526 return FORBIDDEN;
7527
7528 return MAY_BE_SAFE;
7529 }
7530
7531
7532 RegisterList MSR_register_cccc00010r10mmmm111100000000nnnn_case_0::
uses(Instruction inst) const7533 uses(Instruction inst) const {
7534 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7535 // uses: '{}'
7536 return RegisterList();
7537 }
7538
7539 // MUL_A1_cccc0000000sdddd0000mmmm1001nnnn_case_0:
7540 //
7541 // {NZCV: 16,
7542 // None: 32,
7543 // Pc: 15,
7544 // Rd: Rd(19:16),
7545 // Rm: Rm(11:8),
7546 // Rn: Rn(3:0),
7547 // S: S(20),
7548 // cond: cond(31:28),
7549 // defs: {Rd, NZCV
7550 // if setflags
7551 // else None},
7552 // fields: [cond(31:28), S(20), Rd(19:16), Rm(11:8), Rn(3:0)],
7553 // pattern: cccc0000000sdddd0000mmmm1001nnnn,
7554 // rule: MUL_A1,
7555 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE,
7556 // (ArchVersion() <
7557 // 6 &&
7558 // Rd ==
7559 // Rn) => UNPREDICTABLE],
7560 // setflags: S(20)=1,
7561 // uses: {Rm, Rn}}
7562 RegisterList MUL_A1_cccc0000000sdddd0000mmmm1001nnnn_case_0::
defs(Instruction inst) const7563 defs(Instruction inst) const {
7564 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7565 // defs: '{inst(19:16), 16
7566 // if inst(20)=1
7567 // else 32}'
7568 return RegisterList().
7569 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
7570 Add(Register(((inst.Bits() & 0x00100000) ==
7571 0x00100000
7572 ? 16
7573 : 32)));
7574 }
7575
7576 SafetyLevel MUL_A1_cccc0000000sdddd0000mmmm1001nnnn_case_0::
safety(Instruction inst) const7577 safety(Instruction inst) const {
7578 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7579
7580 // 15 ==
7581 // inst(19:16) ||
7582 // 15 ==
7583 // inst(3:0) ||
7584 // 15 ==
7585 // inst(11:8) => UNPREDICTABLE
7586 if ((((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
7587 (((15) == ((inst.Bits() & 0x0000000F)))) ||
7588 (((15) == (((inst.Bits() & 0x00000F00) >> 8)))))
7589 return UNPREDICTABLE;
7590
7591 // (ArchVersion() <
7592 // 6 &&
7593 // inst(19:16) ==
7594 // inst(3:0)) => UNPREDICTABLE
7595 if (((((nacl_arm_dec::ArchVersion()) < (6))) &&
7596 (((((inst.Bits() & 0x000F0000) >> 16)) == ((inst.Bits() & 0x0000000F))))))
7597 return UNPREDICTABLE;
7598
7599 return MAY_BE_SAFE;
7600 }
7601
7602
7603 RegisterList MUL_A1_cccc0000000sdddd0000mmmm1001nnnn_case_0::
uses(Instruction inst) const7604 uses(Instruction inst) const {
7605 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7606 // uses: '{inst(11:8), inst(3:0)}'
7607 return RegisterList().
7608 Add(Register(((inst.Bits() & 0x00000F00) >> 8))).
7609 Add(Register((inst.Bits() & 0x0000000F)));
7610 }
7611
7612 // MVN_immediate_cccc0011111s0000ddddiiiiiiiiiiii_case_0:
7613 //
7614 // {NZCV: 16,
7615 // None: 32,
7616 // Rd: Rd(15:12),
7617 // S: S(20),
7618 // cond: cond(31:28),
7619 // defs: {Rd, NZCV
7620 // if setflags
7621 // else None},
7622 // dynamic_code_replace_immediates: {imm12},
7623 // fields: [cond(31:28), S(20), Rd(15:12), imm12(11:0)],
7624 // imm12: imm12(11:0),
7625 // imm32: ARMExpandImm(imm12),
7626 // pattern: cccc0011111s0000ddddiiiiiiiiiiii,
7627 // rule: MVN_immediate,
7628 // safety: [(Rd(15:12)=1111 &&
7629 // S(20)=1) => DECODER_ERROR,
7630 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS],
7631 // setflags: S(20)=1,
7632 // uses: {}}
7633 RegisterList MVN_immediate_cccc0011111s0000ddddiiiiiiiiiiii_case_0::
defs(Instruction inst) const7634 defs(Instruction inst) const {
7635 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7636 // defs: '{inst(15:12), 16
7637 // if inst(20)=1
7638 // else 32}'
7639 return RegisterList().
7640 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
7641 Add(Register(((inst.Bits() & 0x00100000) ==
7642 0x00100000
7643 ? 16
7644 : 32)));
7645 }
7646
7647 Instruction MVN_immediate_cccc0011111s0000ddddiiiiiiiiiiii_case_0::
dynamic_code_replacement_sentinel(Instruction inst) const7648 dynamic_code_replacement_sentinel(
7649 Instruction inst) const {
7650 if (!defs(inst).ContainsAny(RegisterList::DynCodeReplaceFrozenRegs())) {
7651 // inst(11:0)
7652 inst.SetBits(11, 0, 0);
7653 }
7654 return inst;
7655 }
7656
7657 SafetyLevel MVN_immediate_cccc0011111s0000ddddiiiiiiiiiiii_case_0::
safety(Instruction inst) const7658 safety(Instruction inst) const {
7659 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7660
7661 // (inst(15:12)=1111 &&
7662 // inst(20)=1) => DECODER_ERROR
7663 if ((((inst.Bits() & 0x0000F000) ==
7664 0x0000F000) &&
7665 ((inst.Bits() & 0x00100000) ==
7666 0x00100000)))
7667 return DECODER_ERROR;
7668
7669 // inst(15:12)=1111 => FORBIDDEN_OPERANDS
7670 if ((inst.Bits() & 0x0000F000) ==
7671 0x0000F000)
7672 return FORBIDDEN_OPERANDS;
7673
7674 return MAY_BE_SAFE;
7675 }
7676
7677
7678 RegisterList MVN_immediate_cccc0011111s0000ddddiiiiiiiiiiii_case_0::
uses(Instruction inst) const7679 uses(Instruction inst) const {
7680 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7681 // uses: '{}'
7682 return RegisterList();
7683 }
7684
7685 // MVN_register_cccc0001111s0000ddddiiiiitt0mmmm_case_0:
7686 //
7687 // {NZCV: 16,
7688 // None: 32,
7689 // Rd: Rd(15:12),
7690 // Rm: Rm(3:0),
7691 // S: S(20),
7692 // cond: cond(31:28),
7693 // defs: {Rd, NZCV
7694 // if S
7695 // else None},
7696 // fields: [cond(31:28),
7697 // S(20),
7698 // Rd(15:12),
7699 // imm5(11:7),
7700 // type(6:5),
7701 // Rm(3:0)],
7702 // imm5: imm5(11:7),
7703 // pattern: cccc0001111s0000ddddiiiiitt0mmmm,
7704 // rule: MVN_register,
7705 // safety: [(Rd(15:12)=1111 &&
7706 // S(20)=1) => DECODER_ERROR,
7707 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS],
7708 // shift: DecodeImmShift(type, imm5),
7709 // type: type(6:5),
7710 // uses: {Rm}}
7711 RegisterList MVN_register_cccc0001111s0000ddddiiiiitt0mmmm_case_0::
defs(Instruction inst) const7712 defs(Instruction inst) const {
7713 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7714 // defs: '{inst(15:12), 16
7715 // if inst(20)
7716 // else 32}'
7717 return RegisterList().
7718 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
7719 Add(Register(((((inst.Bits() & 0x00100000) >> 20) != 0)
7720 ? 16
7721 : 32)));
7722 }
7723
7724 SafetyLevel MVN_register_cccc0001111s0000ddddiiiiitt0mmmm_case_0::
safety(Instruction inst) const7725 safety(Instruction inst) const {
7726 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7727
7728 // (inst(15:12)=1111 &&
7729 // inst(20)=1) => DECODER_ERROR
7730 if ((((inst.Bits() & 0x0000F000) ==
7731 0x0000F000) &&
7732 ((inst.Bits() & 0x00100000) ==
7733 0x00100000)))
7734 return DECODER_ERROR;
7735
7736 // inst(15:12)=1111 => FORBIDDEN_OPERANDS
7737 if ((inst.Bits() & 0x0000F000) ==
7738 0x0000F000)
7739 return FORBIDDEN_OPERANDS;
7740
7741 return MAY_BE_SAFE;
7742 }
7743
7744
7745 RegisterList MVN_register_cccc0001111s0000ddddiiiiitt0mmmm_case_0::
uses(Instruction inst) const7746 uses(Instruction inst) const {
7747 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7748 // uses: '{inst(3:0)}'
7749 return RegisterList().
7750 Add(Register((inst.Bits() & 0x0000000F)));
7751 }
7752
7753 // MVN_register_shifted_register_cccc0001111s0000ddddssss0tt1mmmm_case_0:
7754 //
7755 // {NZCV: 16,
7756 // None: 32,
7757 // Pc: 15,
7758 // Rd: Rd(15:12),
7759 // Rm: Rm(3:0),
7760 // Rs: Rs(11:8),
7761 // S: S(20),
7762 // cond: cond(31:28),
7763 // defs: {Rd, NZCV
7764 // if setflags
7765 // else None},
7766 // fields: [cond(31:28),
7767 // S(20),
7768 // Rd(15:12),
7769 // Rs(11:8),
7770 // type(6:5),
7771 // Rm(3:0)],
7772 // pattern: cccc0001111s0000ddddssss0tt1mmmm,
7773 // rule: MVN_register_shifted_register,
7774 // safety: [Pc in {Rd, Rm, Rs} => UNPREDICTABLE],
7775 // setflags: S(20)=1,
7776 // shift_t: DecodeRegShift(type),
7777 // type: type(6:5),
7778 // uses: {Rm, Rs}}
7779 RegisterList MVN_register_shifted_register_cccc0001111s0000ddddssss0tt1mmmm_case_0::
defs(Instruction inst) const7780 defs(Instruction inst) const {
7781 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7782 // defs: '{inst(15:12), 16
7783 // if inst(20)=1
7784 // else 32}'
7785 return RegisterList().
7786 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
7787 Add(Register(((inst.Bits() & 0x00100000) ==
7788 0x00100000
7789 ? 16
7790 : 32)));
7791 }
7792
7793 SafetyLevel MVN_register_shifted_register_cccc0001111s0000ddddssss0tt1mmmm_case_0::
safety(Instruction inst) const7794 safety(Instruction inst) const {
7795 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7796
7797 // 15 ==
7798 // inst(15:12) ||
7799 // 15 ==
7800 // inst(3:0) ||
7801 // 15 ==
7802 // inst(11:8) => UNPREDICTABLE
7803 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
7804 (((15) == ((inst.Bits() & 0x0000000F)))) ||
7805 (((15) == (((inst.Bits() & 0x00000F00) >> 8)))))
7806 return UNPREDICTABLE;
7807
7808 return MAY_BE_SAFE;
7809 }
7810
7811
7812 RegisterList MVN_register_shifted_register_cccc0001111s0000ddddssss0tt1mmmm_case_0::
uses(Instruction inst) const7813 uses(Instruction inst) const {
7814 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7815 // uses: '{inst(3:0), inst(11:8)}'
7816 return RegisterList().
7817 Add(Register((inst.Bits() & 0x0000000F))).
7818 Add(Register(((inst.Bits() & 0x00000F00) >> 8)));
7819 }
7820
7821 // NOP_cccc0011001000001111000000000000_case_0:
7822 //
7823 // {arch: ['v6K', 'v6T2'],
7824 // defs: {},
7825 // pattern: cccc0011001000001111000000000000,
7826 // rule: NOP,
7827 // uses: {}}
7828 RegisterList NOP_cccc0011001000001111000000000000_case_0::
defs(Instruction inst) const7829 defs(Instruction inst) const {
7830 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7831 // defs: '{}'
7832 return RegisterList();
7833 }
7834
7835 SafetyLevel NOP_cccc0011001000001111000000000000_case_0::
safety(Instruction inst) const7836 safety(Instruction inst) const {
7837 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7838
7839 return MAY_BE_SAFE;
7840 }
7841
7842
7843 RegisterList NOP_cccc0011001000001111000000000000_case_0::
uses(Instruction inst) const7844 uses(Instruction inst) const {
7845 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7846 // uses: '{}'
7847 return RegisterList();
7848 }
7849
7850 // NOT_IMPLEMENTED_case_0:
7851 //
7852 // {defs: {},
7853 // rule: NOT_IMPLEMENTED,
7854 // safety: [true => NOT_IMPLEMENTED],
7855 // true: true,
7856 // uses: {}}
7857 RegisterList NOT_IMPLEMENTED_case_0::
defs(Instruction inst) const7858 defs(Instruction inst) const {
7859 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7860 // defs: '{}'
7861 return RegisterList();
7862 }
7863
7864 SafetyLevel NOT_IMPLEMENTED_case_0::
safety(Instruction inst) const7865 safety(Instruction inst) const {
7866 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7867
7868 // true => NOT_IMPLEMENTED
7869 if (true)
7870 return NOT_IMPLEMENTED;
7871
7872 return MAY_BE_SAFE;
7873 }
7874
7875
7876 RegisterList NOT_IMPLEMENTED_case_0::
uses(Instruction inst) const7877 uses(Instruction inst) const {
7878 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7879 // uses: '{}'
7880 return RegisterList();
7881 }
7882
7883 // ORR_immediate_cccc0011100snnnnddddiiiiiiiiiiii_case_0:
7884 //
7885 // {NZCV: 16,
7886 // None: 32,
7887 // Rd: Rd(15:12),
7888 // Rn: Rn(19:16),
7889 // S: S(20),
7890 // cond: cond(31:28),
7891 // defs: {Rd, NZCV
7892 // if setflags
7893 // else None},
7894 // dynamic_code_replace_immediates: {imm12},
7895 // fields: [cond(31:28), S(20), Rn(19:16), Rd(15:12), imm12(11:0)],
7896 // imm12: imm12(11:0),
7897 // imm32: ARMExpandImm(imm12),
7898 // pattern: cccc0011100snnnnddddiiiiiiiiiiii,
7899 // rule: ORR_immediate,
7900 // safety: [(Rd(15:12)=1111 &&
7901 // S(20)=1) => DECODER_ERROR,
7902 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS],
7903 // setflags: S(20)=1,
7904 // uses: {Rn}}
7905 RegisterList ORR_immediate_cccc0011100snnnnddddiiiiiiiiiiii_case_0::
defs(Instruction inst) const7906 defs(Instruction inst) const {
7907 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7908 // defs: '{inst(15:12), 16
7909 // if inst(20)=1
7910 // else 32}'
7911 return RegisterList().
7912 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
7913 Add(Register(((inst.Bits() & 0x00100000) ==
7914 0x00100000
7915 ? 16
7916 : 32)));
7917 }
7918
7919 Instruction ORR_immediate_cccc0011100snnnnddddiiiiiiiiiiii_case_0::
dynamic_code_replacement_sentinel(Instruction inst) const7920 dynamic_code_replacement_sentinel(
7921 Instruction inst) const {
7922 if (!defs(inst).ContainsAny(RegisterList::DynCodeReplaceFrozenRegs())) {
7923 // inst(11:0)
7924 inst.SetBits(11, 0, 0);
7925 }
7926 return inst;
7927 }
7928
7929 SafetyLevel ORR_immediate_cccc0011100snnnnddddiiiiiiiiiiii_case_0::
safety(Instruction inst) const7930 safety(Instruction inst) const {
7931 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7932
7933 // (inst(15:12)=1111 &&
7934 // inst(20)=1) => DECODER_ERROR
7935 if ((((inst.Bits() & 0x0000F000) ==
7936 0x0000F000) &&
7937 ((inst.Bits() & 0x00100000) ==
7938 0x00100000)))
7939 return DECODER_ERROR;
7940
7941 // inst(15:12)=1111 => FORBIDDEN_OPERANDS
7942 if ((inst.Bits() & 0x0000F000) ==
7943 0x0000F000)
7944 return FORBIDDEN_OPERANDS;
7945
7946 return MAY_BE_SAFE;
7947 }
7948
7949
7950 RegisterList ORR_immediate_cccc0011100snnnnddddiiiiiiiiiiii_case_0::
uses(Instruction inst) const7951 uses(Instruction inst) const {
7952 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7953 // uses: '{inst(19:16)}'
7954 return RegisterList().
7955 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
7956 }
7957
7958 // ORR_register_cccc0001100snnnnddddiiiiitt0mmmm_case_0:
7959 //
7960 // {NZCV: 16,
7961 // None: 32,
7962 // Rd: Rd(15:12),
7963 // Rm: Rm(3:0),
7964 // Rn: Rn(19:16),
7965 // S: S(20),
7966 // cond: cond(31:28),
7967 // defs: {Rd, NZCV
7968 // if S
7969 // else None},
7970 // fields: [cond(31:28),
7971 // S(20),
7972 // Rn(19:16),
7973 // Rd(15:12),
7974 // imm5(11:7),
7975 // type(6:5),
7976 // Rm(3:0)],
7977 // imm5: imm5(11:7),
7978 // pattern: cccc0001100snnnnddddiiiiitt0mmmm,
7979 // rule: ORR_register,
7980 // safety: [(Rd(15:12)=1111 &&
7981 // S(20)=1) => DECODER_ERROR,
7982 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS],
7983 // shift: DecodeImmShift(type, imm5),
7984 // type: type(6:5),
7985 // uses: {Rn, Rm}}
7986 RegisterList ORR_register_cccc0001100snnnnddddiiiiitt0mmmm_case_0::
defs(Instruction inst) const7987 defs(Instruction inst) const {
7988 UNREFERENCED_PARAMETER(inst); // To silence compiler.
7989 // defs: '{inst(15:12), 16
7990 // if inst(20)
7991 // else 32}'
7992 return RegisterList().
7993 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
7994 Add(Register(((((inst.Bits() & 0x00100000) >> 20) != 0)
7995 ? 16
7996 : 32)));
7997 }
7998
7999 SafetyLevel ORR_register_cccc0001100snnnnddddiiiiitt0mmmm_case_0::
safety(Instruction inst) const8000 safety(Instruction inst) const {
8001 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8002
8003 // (inst(15:12)=1111 &&
8004 // inst(20)=1) => DECODER_ERROR
8005 if ((((inst.Bits() & 0x0000F000) ==
8006 0x0000F000) &&
8007 ((inst.Bits() & 0x00100000) ==
8008 0x00100000)))
8009 return DECODER_ERROR;
8010
8011 // inst(15:12)=1111 => FORBIDDEN_OPERANDS
8012 if ((inst.Bits() & 0x0000F000) ==
8013 0x0000F000)
8014 return FORBIDDEN_OPERANDS;
8015
8016 return MAY_BE_SAFE;
8017 }
8018
8019
8020 RegisterList ORR_register_cccc0001100snnnnddddiiiiitt0mmmm_case_0::
uses(Instruction inst) const8021 uses(Instruction inst) const {
8022 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8023 // uses: '{inst(19:16), inst(3:0)}'
8024 return RegisterList().
8025 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
8026 Add(Register((inst.Bits() & 0x0000000F)));
8027 }
8028
8029 // ORR_register_shifted_register_cccc0001100snnnnddddssss0tt1mmmm_case_0:
8030 //
8031 // {NZCV: 16,
8032 // None: 32,
8033 // Pc: 15,
8034 // Rd: Rd(15:12),
8035 // Rm: Rm(3:0),
8036 // Rn: Rn(19:16),
8037 // Rs: Rs(11:8),
8038 // S: S(20),
8039 // cond: cond(31:28),
8040 // defs: {Rd, NZCV
8041 // if setflags
8042 // else None},
8043 // fields: [cond(31:28),
8044 // S(20),
8045 // Rn(19:16),
8046 // Rd(15:12),
8047 // Rs(11:8),
8048 // type(6:5),
8049 // Rm(3:0)],
8050 // pattern: cccc0001100snnnnddddssss0tt1mmmm,
8051 // rule: ORR_register_shifted_register,
8052 // safety: [Pc in {Rn, Rd, Rm, Rs} => UNPREDICTABLE],
8053 // setflags: S(20)=1,
8054 // shift_t: DecodeRegShift(type),
8055 // type: type(6:5),
8056 // uses: {Rn, Rm, Rs}}
8057 RegisterList ORR_register_shifted_register_cccc0001100snnnnddddssss0tt1mmmm_case_0::
defs(Instruction inst) const8058 defs(Instruction inst) const {
8059 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8060 // defs: '{inst(15:12), 16
8061 // if inst(20)=1
8062 // else 32}'
8063 return RegisterList().
8064 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
8065 Add(Register(((inst.Bits() & 0x00100000) ==
8066 0x00100000
8067 ? 16
8068 : 32)));
8069 }
8070
8071 SafetyLevel ORR_register_shifted_register_cccc0001100snnnnddddssss0tt1mmmm_case_0::
safety(Instruction inst) const8072 safety(Instruction inst) const {
8073 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8074
8075 // 15 ==
8076 // inst(19:16) ||
8077 // 15 ==
8078 // inst(15:12) ||
8079 // 15 ==
8080 // inst(3:0) ||
8081 // 15 ==
8082 // inst(11:8) => UNPREDICTABLE
8083 if ((((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
8084 (((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
8085 (((15) == ((inst.Bits() & 0x0000000F)))) ||
8086 (((15) == (((inst.Bits() & 0x00000F00) >> 8)))))
8087 return UNPREDICTABLE;
8088
8089 return MAY_BE_SAFE;
8090 }
8091
8092
8093 RegisterList ORR_register_shifted_register_cccc0001100snnnnddddssss0tt1mmmm_case_0::
uses(Instruction inst) const8094 uses(Instruction inst) const {
8095 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8096 // uses: '{inst(19:16), inst(3:0), inst(11:8)}'
8097 return RegisterList().
8098 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
8099 Add(Register((inst.Bits() & 0x0000000F))).
8100 Add(Register(((inst.Bits() & 0x00000F00) >> 8)));
8101 }
8102
8103 // PKH_cccc01101000nnnnddddiiiiit01mmmm_case_0:
8104 //
8105 // {Pc: 15,
8106 // Rd: Rd(15:12),
8107 // Rm: Rm(3:0),
8108 // Rn: Rn(19:16),
8109 // arch: v6,
8110 // cond: cond(31:28),
8111 // defs: {Rd},
8112 // fields: [cond(31:28),
8113 // Rn(19:16),
8114 // Rd(15:12),
8115 // imm5(11:7),
8116 // tb(6),
8117 // Rm(3:0)],
8118 // imm5: imm5(11:7),
8119 // pattern: cccc01101000nnnnddddiiiiit01mmmm,
8120 // rule: PKH,
8121 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE],
8122 // shift: DecodeImmShift(tb:'0'(0), imm5),
8123 // tb: tb(6),
8124 // tbform: tb(6)=1,
8125 // uses: {Rn, Rm}}
8126 RegisterList PKH_cccc01101000nnnnddddiiiiit01mmmm_case_0::
defs(Instruction inst) const8127 defs(Instruction inst) const {
8128 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8129 // defs: '{inst(15:12)}'
8130 return RegisterList().
8131 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
8132 }
8133
8134 SafetyLevel PKH_cccc01101000nnnnddddiiiiit01mmmm_case_0::
safety(Instruction inst) const8135 safety(Instruction inst) const {
8136 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8137
8138 // 15 ==
8139 // inst(15:12) ||
8140 // 15 ==
8141 // inst(19:16) ||
8142 // 15 ==
8143 // inst(3:0) => UNPREDICTABLE
8144 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
8145 (((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
8146 (((15) == ((inst.Bits() & 0x0000000F)))))
8147 return UNPREDICTABLE;
8148
8149 return MAY_BE_SAFE;
8150 }
8151
8152
8153 RegisterList PKH_cccc01101000nnnnddddiiiiit01mmmm_case_0::
uses(Instruction inst) const8154 uses(Instruction inst) const {
8155 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8156 // uses: '{inst(19:16), inst(3:0)}'
8157 return RegisterList().
8158 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
8159 Add(Register((inst.Bits() & 0x0000000F)));
8160 }
8161
8162 // PLD_PLDW_immediate_11110101ur01nnnn1111iiiiiiiiiiii_case_0:
8163 //
8164 // {Pc: 15,
8165 // R: R(22),
8166 // Rn: Rn(19:16),
8167 // U: U(23),
8168 // add: U(23)=1,
8169 // arch: MPExt,
8170 // base: Rn,
8171 // defs: {},
8172 // fields: [U(23), R(22), Rn(19:16), imm12(11:0)],
8173 // imm12: imm12(11:0),
8174 // imm32: ZeroExtend(imm12, 32),
8175 // is_literal_load: base ==
8176 // Pc,
8177 // is_pldw: R(22)=0,
8178 // pattern: 11110101ur01nnnn1111iiiiiiiiiiii,
8179 // rule: PLD_PLDW_immediate,
8180 // safety: [Rn(19:16)=1111 => DECODER_ERROR],
8181 // true: true,
8182 // uses: {Rn},
8183 // violations: [implied by 'base']}
8184 Register PLD_PLDW_immediate_11110101ur01nnnn1111iiiiiiiiiiii_case_0::
base_address_register(Instruction inst) const8185 base_address_register(Instruction inst) const {
8186 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8187 // base: 'inst(19:16)'
8188 return Register(((inst.Bits() & 0x000F0000) >> 16));
8189 }
8190
8191 RegisterList PLD_PLDW_immediate_11110101ur01nnnn1111iiiiiiiiiiii_case_0::
defs(Instruction inst) const8192 defs(Instruction inst) const {
8193 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8194 // defs: '{}'
8195 return RegisterList();
8196 }
8197
8198 bool PLD_PLDW_immediate_11110101ur01nnnn1111iiiiiiiiiiii_case_0::
is_literal_load(Instruction inst) const8199 is_literal_load(Instruction inst) const {
8200 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8201 // is_literal_load: '15 ==
8202 // inst(19:16)'
8203 return ((((inst.Bits() & 0x000F0000) >> 16)) == (15));
8204 }
8205
8206 SafetyLevel PLD_PLDW_immediate_11110101ur01nnnn1111iiiiiiiiiiii_case_0::
safety(Instruction inst) const8207 safety(Instruction inst) const {
8208 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8209
8210 // inst(19:16)=1111 => DECODER_ERROR
8211 if ((inst.Bits() & 0x000F0000) ==
8212 0x000F0000)
8213 return DECODER_ERROR;
8214
8215 return MAY_BE_SAFE;
8216 }
8217
8218
8219 RegisterList PLD_PLDW_immediate_11110101ur01nnnn1111iiiiiiiiiiii_case_0::
uses(Instruction inst) const8220 uses(Instruction inst) const {
8221 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8222 // uses: '{inst(19:16)}'
8223 return RegisterList().
8224 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
8225 }
8226
8227 ViolationSet PLD_PLDW_immediate_11110101ur01nnnn1111iiiiiiiiiiii_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const8228 get_violations(const nacl_arm_val::DecodedInstruction& first,
8229 const nacl_arm_val::DecodedInstruction& second,
8230 const nacl_arm_val::SfiValidator& sfi,
8231 nacl_arm_val::AddressSet* branches,
8232 nacl_arm_val::AddressSet* critical,
8233 uint32_t* next_inst_addr) const {
8234 ViolationSet violations = ClassDecoder::get_violations(
8235 first, second, sfi, branches, critical, next_inst_addr);
8236
8237 // Report unsafe loads/stores of a base address by the given instruction
8238 // pair.
8239 violations = ViolationUnion(
8240 violations, get_loadstore_violations(first, second, sfi, critical));
8241
8242 return violations;
8243 }
8244
8245
8246 // PLD_PLDW_immediate_11110101ur01nnnn1111iiiiiiiiiiii_case_1:
8247 //
8248 // {Pc: 15,
8249 // R: R(22),
8250 // Rn: Rn(19:16),
8251 // U: U(23),
8252 // add: U(23)=1,
8253 // arch: v5TE,
8254 // base: Rn,
8255 // defs: {},
8256 // fields: [U(23), R(22), Rn(19:16), imm12(11:0)],
8257 // imm12: imm12(11:0),
8258 // imm32: ZeroExtend(imm12, 32),
8259 // is_literal_load: base ==
8260 // Pc,
8261 // is_pldw: R(22)=0,
8262 // pattern: 11110101ur01nnnn1111iiiiiiiiiiii,
8263 // rule: PLD_PLDW_immediate,
8264 // safety: [Rn(19:16)=1111 => DECODER_ERROR],
8265 // true: true,
8266 // uses: {Rn},
8267 // violations: [implied by 'base']}
8268 Register PLD_PLDW_immediate_11110101ur01nnnn1111iiiiiiiiiiii_case_1::
base_address_register(Instruction inst) const8269 base_address_register(Instruction inst) const {
8270 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8271 // base: 'inst(19:16)'
8272 return Register(((inst.Bits() & 0x000F0000) >> 16));
8273 }
8274
8275 RegisterList PLD_PLDW_immediate_11110101ur01nnnn1111iiiiiiiiiiii_case_1::
defs(Instruction inst) const8276 defs(Instruction inst) const {
8277 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8278 // defs: '{}'
8279 return RegisterList();
8280 }
8281
8282 bool PLD_PLDW_immediate_11110101ur01nnnn1111iiiiiiiiiiii_case_1::
is_literal_load(Instruction inst) const8283 is_literal_load(Instruction inst) const {
8284 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8285 // is_literal_load: '15 ==
8286 // inst(19:16)'
8287 return ((((inst.Bits() & 0x000F0000) >> 16)) == (15));
8288 }
8289
8290 SafetyLevel PLD_PLDW_immediate_11110101ur01nnnn1111iiiiiiiiiiii_case_1::
safety(Instruction inst) const8291 safety(Instruction inst) const {
8292 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8293
8294 // inst(19:16)=1111 => DECODER_ERROR
8295 if ((inst.Bits() & 0x000F0000) ==
8296 0x000F0000)
8297 return DECODER_ERROR;
8298
8299 return MAY_BE_SAFE;
8300 }
8301
8302
8303 RegisterList PLD_PLDW_immediate_11110101ur01nnnn1111iiiiiiiiiiii_case_1::
uses(Instruction inst) const8304 uses(Instruction inst) const {
8305 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8306 // uses: '{inst(19:16)}'
8307 return RegisterList().
8308 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
8309 }
8310
8311 ViolationSet PLD_PLDW_immediate_11110101ur01nnnn1111iiiiiiiiiiii_case_1::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const8312 get_violations(const nacl_arm_val::DecodedInstruction& first,
8313 const nacl_arm_val::DecodedInstruction& second,
8314 const nacl_arm_val::SfiValidator& sfi,
8315 nacl_arm_val::AddressSet* branches,
8316 nacl_arm_val::AddressSet* critical,
8317 uint32_t* next_inst_addr) const {
8318 ViolationSet violations = ClassDecoder::get_violations(
8319 first, second, sfi, branches, critical, next_inst_addr);
8320
8321 // Report unsafe loads/stores of a base address by the given instruction
8322 // pair.
8323 violations = ViolationUnion(
8324 violations, get_loadstore_violations(first, second, sfi, critical));
8325
8326 return violations;
8327 }
8328
8329
8330 // PLD_PLDW_register_11110111u001nnnn1111iiiiitt0mmmm_case_0:
8331 //
8332 // {Pc: 15,
8333 // R: R(22),
8334 // Rm: Rm(3:0),
8335 // Rn: Rn(19:16),
8336 // U: U(23),
8337 // add: U(23)=1,
8338 // arch: MPExt,
8339 // base: Rn,
8340 // defs: {},
8341 // fields: [U(23), R(22), Rn(19:16), imm5(11:7), type(6:5), Rm(3:0)],
8342 // imm5: imm5(11:7),
8343 // is_pldw: R(22)=1,
8344 // pattern: 11110111u001nnnn1111iiiiitt0mmmm,
8345 // rule: PLD_PLDW_register,
8346 // safety: [Rm ==
8347 // Pc ||
8348 // (Rn ==
8349 // Pc &&
8350 // is_pldw) => UNPREDICTABLE,
8351 // true => FORBIDDEN_OPERANDS],
8352 // shift: DecodeImmShift(type, imm5),
8353 // true: true,
8354 // type: type(6:5),
8355 // uses: {Rm, Rn},
8356 // violations: [implied by 'base']}
8357 Register PLD_PLDW_register_11110111u001nnnn1111iiiiitt0mmmm_case_0::
base_address_register(Instruction inst) const8358 base_address_register(Instruction inst) const {
8359 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8360 // base: 'inst(19:16)'
8361 return Register(((inst.Bits() & 0x000F0000) >> 16));
8362 }
8363
8364 RegisterList PLD_PLDW_register_11110111u001nnnn1111iiiiitt0mmmm_case_0::
defs(Instruction inst) const8365 defs(Instruction inst) const {
8366 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8367 // defs: '{}'
8368 return RegisterList();
8369 }
8370
8371 SafetyLevel PLD_PLDW_register_11110111u001nnnn1111iiiiitt0mmmm_case_0::
safety(Instruction inst) const8372 safety(Instruction inst) const {
8373 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8374
8375 // 15 ==
8376 // inst(3:0) ||
8377 // (15 ==
8378 // inst(19:16) &&
8379 // inst(22)=1) => UNPREDICTABLE
8380 if (((((inst.Bits() & 0x0000000F)) == (15))) ||
8381 (((((((inst.Bits() & 0x000F0000) >> 16)) == (15))) &&
8382 ((inst.Bits() & 0x00400000) ==
8383 0x00400000))))
8384 return UNPREDICTABLE;
8385
8386 // true => FORBIDDEN_OPERANDS
8387 if (true)
8388 return FORBIDDEN_OPERANDS;
8389
8390 return MAY_BE_SAFE;
8391 }
8392
8393
8394 RegisterList PLD_PLDW_register_11110111u001nnnn1111iiiiitt0mmmm_case_0::
uses(Instruction inst) const8395 uses(Instruction inst) const {
8396 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8397 // uses: '{inst(3:0), inst(19:16)}'
8398 return RegisterList().
8399 Add(Register((inst.Bits() & 0x0000000F))).
8400 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
8401 }
8402
8403 ViolationSet PLD_PLDW_register_11110111u001nnnn1111iiiiitt0mmmm_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const8404 get_violations(const nacl_arm_val::DecodedInstruction& first,
8405 const nacl_arm_val::DecodedInstruction& second,
8406 const nacl_arm_val::SfiValidator& sfi,
8407 nacl_arm_val::AddressSet* branches,
8408 nacl_arm_val::AddressSet* critical,
8409 uint32_t* next_inst_addr) const {
8410 ViolationSet violations = ClassDecoder::get_violations(
8411 first, second, sfi, branches, critical, next_inst_addr);
8412
8413 // Report unsafe loads/stores of a base address by the given instruction
8414 // pair.
8415 violations = ViolationUnion(
8416 violations, get_loadstore_violations(first, second, sfi, critical));
8417
8418 return violations;
8419 }
8420
8421
8422 // PLD_PLDW_register_11110111u101nnnn1111iiiiitt0mmmm_case_0:
8423 //
8424 // {Pc: 15,
8425 // R: R(22),
8426 // Rm: Rm(3:0),
8427 // Rn: Rn(19:16),
8428 // U: U(23),
8429 // add: U(23)=1,
8430 // arch: v5TE,
8431 // base: Rn,
8432 // defs: {},
8433 // fields: [U(23), R(22), Rn(19:16), imm5(11:7), type(6:5), Rm(3:0)],
8434 // imm5: imm5(11:7),
8435 // is_pldw: R(22)=1,
8436 // pattern: 11110111u101nnnn1111iiiiitt0mmmm,
8437 // rule: PLD_PLDW_register,
8438 // safety: [Rm ==
8439 // Pc ||
8440 // (Rn ==
8441 // Pc &&
8442 // is_pldw) => UNPREDICTABLE,
8443 // true => FORBIDDEN_OPERANDS],
8444 // shift: DecodeImmShift(type, imm5),
8445 // true: true,
8446 // type: type(6:5),
8447 // uses: {Rm, Rn},
8448 // violations: [implied by 'base']}
8449 Register PLD_PLDW_register_11110111u101nnnn1111iiiiitt0mmmm_case_0::
base_address_register(Instruction inst) const8450 base_address_register(Instruction inst) const {
8451 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8452 // base: 'inst(19:16)'
8453 return Register(((inst.Bits() & 0x000F0000) >> 16));
8454 }
8455
8456 RegisterList PLD_PLDW_register_11110111u101nnnn1111iiiiitt0mmmm_case_0::
defs(Instruction inst) const8457 defs(Instruction inst) const {
8458 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8459 // defs: '{}'
8460 return RegisterList();
8461 }
8462
8463 SafetyLevel PLD_PLDW_register_11110111u101nnnn1111iiiiitt0mmmm_case_0::
safety(Instruction inst) const8464 safety(Instruction inst) const {
8465 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8466
8467 // 15 ==
8468 // inst(3:0) ||
8469 // (15 ==
8470 // inst(19:16) &&
8471 // inst(22)=1) => UNPREDICTABLE
8472 if (((((inst.Bits() & 0x0000000F)) == (15))) ||
8473 (((((((inst.Bits() & 0x000F0000) >> 16)) == (15))) &&
8474 ((inst.Bits() & 0x00400000) ==
8475 0x00400000))))
8476 return UNPREDICTABLE;
8477
8478 // true => FORBIDDEN_OPERANDS
8479 if (true)
8480 return FORBIDDEN_OPERANDS;
8481
8482 return MAY_BE_SAFE;
8483 }
8484
8485
8486 RegisterList PLD_PLDW_register_11110111u101nnnn1111iiiiitt0mmmm_case_0::
uses(Instruction inst) const8487 uses(Instruction inst) const {
8488 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8489 // uses: '{inst(3:0), inst(19:16)}'
8490 return RegisterList().
8491 Add(Register((inst.Bits() & 0x0000000F))).
8492 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
8493 }
8494
8495 ViolationSet PLD_PLDW_register_11110111u101nnnn1111iiiiitt0mmmm_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const8496 get_violations(const nacl_arm_val::DecodedInstruction& first,
8497 const nacl_arm_val::DecodedInstruction& second,
8498 const nacl_arm_val::SfiValidator& sfi,
8499 nacl_arm_val::AddressSet* branches,
8500 nacl_arm_val::AddressSet* critical,
8501 uint32_t* next_inst_addr) const {
8502 ViolationSet violations = ClassDecoder::get_violations(
8503 first, second, sfi, branches, critical, next_inst_addr);
8504
8505 // Report unsafe loads/stores of a base address by the given instruction
8506 // pair.
8507 violations = ViolationUnion(
8508 violations, get_loadstore_violations(first, second, sfi, critical));
8509
8510 return violations;
8511 }
8512
8513
8514 // PLD_literal_11110101u10111111111iiiiiiiiiiii_case_0:
8515 //
8516 // {Pc: 15,
8517 // U: U(23),
8518 // add: U(23)=1,
8519 // arch: v5TE,
8520 // base: Pc,
8521 // defs: {},
8522 // fields: [U(23), imm12(11:0)],
8523 // imm12: imm12(11:0),
8524 // imm32: ZeroExtend(imm12, 32),
8525 // is_literal_load: true,
8526 // pattern: 11110101u10111111111iiiiiiiiiiii,
8527 // rule: PLD_literal,
8528 // safety: [true => MAY_BE_SAFE],
8529 // true: true,
8530 // uses: {Pc},
8531 // violations: [implied by 'base']}
8532 Register PLD_literal_11110101u10111111111iiiiiiiiiiii_case_0::
base_address_register(Instruction inst) const8533 base_address_register(Instruction inst) const {
8534 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8535 // base: '15'
8536 return Register(15);
8537 }
8538
8539 RegisterList PLD_literal_11110101u10111111111iiiiiiiiiiii_case_0::
defs(Instruction inst) const8540 defs(Instruction inst) const {
8541 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8542 // defs: '{}'
8543 return RegisterList();
8544 }
8545
8546 bool PLD_literal_11110101u10111111111iiiiiiiiiiii_case_0::
is_literal_load(Instruction inst) const8547 is_literal_load(Instruction inst) const {
8548 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8549 // is_literal_load: 'true'
8550 return true;
8551 }
8552
8553 SafetyLevel PLD_literal_11110101u10111111111iiiiiiiiiiii_case_0::
safety(Instruction inst) const8554 safety(Instruction inst) const {
8555 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8556
8557 // true => MAY_BE_SAFE
8558 if (true)
8559 return MAY_BE_SAFE;
8560
8561 return MAY_BE_SAFE;
8562 }
8563
8564
8565 RegisterList PLD_literal_11110101u10111111111iiiiiiiiiiii_case_0::
uses(Instruction inst) const8566 uses(Instruction inst) const {
8567 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8568 // uses: '{15}'
8569 return RegisterList().
8570 Add(Register(15));
8571 }
8572
8573 ViolationSet PLD_literal_11110101u10111111111iiiiiiiiiiii_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const8574 get_violations(const nacl_arm_val::DecodedInstruction& first,
8575 const nacl_arm_val::DecodedInstruction& second,
8576 const nacl_arm_val::SfiValidator& sfi,
8577 nacl_arm_val::AddressSet* branches,
8578 nacl_arm_val::AddressSet* critical,
8579 uint32_t* next_inst_addr) const {
8580 ViolationSet violations = ClassDecoder::get_violations(
8581 first, second, sfi, branches, critical, next_inst_addr);
8582
8583 // Report unsafe loads/stores of a base address by the given instruction
8584 // pair.
8585 violations = ViolationUnion(
8586 violations, get_loadstore_violations(first, second, sfi, critical));
8587
8588 return violations;
8589 }
8590
8591
8592 // PLI_immediate_literal_11110100u101nnnn1111iiiiiiiiiiii_case_0:
8593 //
8594 // {Pc: 15,
8595 // Rn: Rn(19:16),
8596 // U: U(23),
8597 // add: U(23)=1,
8598 // arch: v7,
8599 // base: Rn,
8600 // defs: {},
8601 // fields: [U(23), Rn(19:16), imm12(11:0)],
8602 // imm12: imm12(11:0),
8603 // imm32: ZeroExtend(imm12, 32),
8604 // is_literal_load: Rn ==
8605 // Pc,
8606 // pattern: 11110100u101nnnn1111iiiiiiiiiiii,
8607 // rule: PLI_immediate_literal,
8608 // safety: [true => MAY_BE_SAFE],
8609 // true: true,
8610 // uses: {Rn},
8611 // violations: [implied by 'base']}
8612 Register PLI_immediate_literal_11110100u101nnnn1111iiiiiiiiiiii_case_0::
base_address_register(Instruction inst) const8613 base_address_register(Instruction inst) const {
8614 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8615 // base: 'inst(19:16)'
8616 return Register(((inst.Bits() & 0x000F0000) >> 16));
8617 }
8618
8619 RegisterList PLI_immediate_literal_11110100u101nnnn1111iiiiiiiiiiii_case_0::
defs(Instruction inst) const8620 defs(Instruction inst) const {
8621 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8622 // defs: '{}'
8623 return RegisterList();
8624 }
8625
8626 bool PLI_immediate_literal_11110100u101nnnn1111iiiiiiiiiiii_case_0::
is_literal_load(Instruction inst) const8627 is_literal_load(Instruction inst) const {
8628 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8629 // is_literal_load: '15 ==
8630 // inst(19:16)'
8631 return ((((inst.Bits() & 0x000F0000) >> 16)) == (15));
8632 }
8633
8634 SafetyLevel PLI_immediate_literal_11110100u101nnnn1111iiiiiiiiiiii_case_0::
safety(Instruction inst) const8635 safety(Instruction inst) const {
8636 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8637
8638 // true => MAY_BE_SAFE
8639 if (true)
8640 return MAY_BE_SAFE;
8641
8642 return MAY_BE_SAFE;
8643 }
8644
8645
8646 RegisterList PLI_immediate_literal_11110100u101nnnn1111iiiiiiiiiiii_case_0::
uses(Instruction inst) const8647 uses(Instruction inst) const {
8648 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8649 // uses: '{inst(19:16)}'
8650 return RegisterList().
8651 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
8652 }
8653
8654 ViolationSet PLI_immediate_literal_11110100u101nnnn1111iiiiiiiiiiii_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const8655 get_violations(const nacl_arm_val::DecodedInstruction& first,
8656 const nacl_arm_val::DecodedInstruction& second,
8657 const nacl_arm_val::SfiValidator& sfi,
8658 nacl_arm_val::AddressSet* branches,
8659 nacl_arm_val::AddressSet* critical,
8660 uint32_t* next_inst_addr) const {
8661 ViolationSet violations = ClassDecoder::get_violations(
8662 first, second, sfi, branches, critical, next_inst_addr);
8663
8664 // Report unsafe loads/stores of a base address by the given instruction
8665 // pair.
8666 violations = ViolationUnion(
8667 violations, get_loadstore_violations(first, second, sfi, critical));
8668
8669 return violations;
8670 }
8671
8672
8673 // PLI_register_11110110u101nnnn1111iiiiitt0mmmm_case_0:
8674 //
8675 // {Pc: 15,
8676 // Rm: Rm(3:0),
8677 // Rn: Rn(19:16),
8678 // U: U(23),
8679 // add: U(23)=1,
8680 // arch: v7,
8681 // base: Rn,
8682 // defs: {},
8683 // fields: [U(23), Rn(19:16), imm5(11:7), type(6:5), Rm(3:0)],
8684 // imm5: imm5(11:7),
8685 // pattern: 11110110u101nnnn1111iiiiitt0mmmm,
8686 // rule: PLI_register,
8687 // safety: [Rm ==
8688 // Pc => UNPREDICTABLE,
8689 // true => FORBIDDEN_OPERANDS],
8690 // shift: DecodeImmShift(type, imm5),
8691 // true: true,
8692 // type: type(6:5),
8693 // uses: {Rm, Rn},
8694 // violations: [implied by 'base']}
8695 Register PLI_register_11110110u101nnnn1111iiiiitt0mmmm_case_0::
base_address_register(Instruction inst) const8696 base_address_register(Instruction inst) const {
8697 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8698 // base: 'inst(19:16)'
8699 return Register(((inst.Bits() & 0x000F0000) >> 16));
8700 }
8701
8702 RegisterList PLI_register_11110110u101nnnn1111iiiiitt0mmmm_case_0::
defs(Instruction inst) const8703 defs(Instruction inst) const {
8704 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8705 // defs: '{}'
8706 return RegisterList();
8707 }
8708
8709 SafetyLevel PLI_register_11110110u101nnnn1111iiiiitt0mmmm_case_0::
safety(Instruction inst) const8710 safety(Instruction inst) const {
8711 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8712
8713 // 15 ==
8714 // inst(3:0) => UNPREDICTABLE
8715 if ((((inst.Bits() & 0x0000000F)) == (15)))
8716 return UNPREDICTABLE;
8717
8718 // true => FORBIDDEN_OPERANDS
8719 if (true)
8720 return FORBIDDEN_OPERANDS;
8721
8722 return MAY_BE_SAFE;
8723 }
8724
8725
8726 RegisterList PLI_register_11110110u101nnnn1111iiiiitt0mmmm_case_0::
uses(Instruction inst) const8727 uses(Instruction inst) const {
8728 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8729 // uses: '{inst(3:0), inst(19:16)}'
8730 return RegisterList().
8731 Add(Register((inst.Bits() & 0x0000000F))).
8732 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
8733 }
8734
8735 ViolationSet PLI_register_11110110u101nnnn1111iiiiitt0mmmm_case_0::
get_violations(const nacl_arm_val::DecodedInstruction & first,const nacl_arm_val::DecodedInstruction & second,const nacl_arm_val::SfiValidator & sfi,nacl_arm_val::AddressSet * branches,nacl_arm_val::AddressSet * critical,uint32_t * next_inst_addr) const8736 get_violations(const nacl_arm_val::DecodedInstruction& first,
8737 const nacl_arm_val::DecodedInstruction& second,
8738 const nacl_arm_val::SfiValidator& sfi,
8739 nacl_arm_val::AddressSet* branches,
8740 nacl_arm_val::AddressSet* critical,
8741 uint32_t* next_inst_addr) const {
8742 ViolationSet violations = ClassDecoder::get_violations(
8743 first, second, sfi, branches, critical, next_inst_addr);
8744
8745 // Report unsafe loads/stores of a base address by the given instruction
8746 // pair.
8747 violations = ViolationUnion(
8748 violations, get_loadstore_violations(first, second, sfi, critical));
8749
8750 return violations;
8751 }
8752
8753
8754 // QADD16_cccc01100010nnnndddd11110001mmmm_case_0:
8755 //
8756 // {Pc: 15,
8757 // Rd: Rd(15:12),
8758 // Rm: Rm(3:0),
8759 // Rn: Rn(19:16),
8760 // arch: v6,
8761 // cond: cond(31:28),
8762 // defs: {Rd},
8763 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)],
8764 // pattern: cccc01100010nnnndddd11110001mmmm,
8765 // rule: QADD16,
8766 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE],
8767 // uses: {Rn, Rm}}
8768 RegisterList QADD16_cccc01100010nnnndddd11110001mmmm_case_0::
defs(Instruction inst) const8769 defs(Instruction inst) const {
8770 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8771 // defs: '{inst(15:12)}'
8772 return RegisterList().
8773 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
8774 }
8775
8776 SafetyLevel QADD16_cccc01100010nnnndddd11110001mmmm_case_0::
safety(Instruction inst) const8777 safety(Instruction inst) const {
8778 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8779
8780 // 15 ==
8781 // inst(15:12) ||
8782 // 15 ==
8783 // inst(19:16) ||
8784 // 15 ==
8785 // inst(3:0) => UNPREDICTABLE
8786 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
8787 (((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
8788 (((15) == ((inst.Bits() & 0x0000000F)))))
8789 return UNPREDICTABLE;
8790
8791 return MAY_BE_SAFE;
8792 }
8793
8794
8795 RegisterList QADD16_cccc01100010nnnndddd11110001mmmm_case_0::
uses(Instruction inst) const8796 uses(Instruction inst) const {
8797 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8798 // uses: '{inst(19:16), inst(3:0)}'
8799 return RegisterList().
8800 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
8801 Add(Register((inst.Bits() & 0x0000000F)));
8802 }
8803
8804 // QADD8_cccc01100010nnnndddd11111001mmmm_case_0:
8805 //
8806 // {Pc: 15,
8807 // Rd: Rd(15:12),
8808 // Rm: Rm(3:0),
8809 // Rn: Rn(19:16),
8810 // arch: v6,
8811 // cond: cond(31:28),
8812 // defs: {Rd},
8813 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)],
8814 // pattern: cccc01100010nnnndddd11111001mmmm,
8815 // rule: QADD8,
8816 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE],
8817 // uses: {Rn, Rm}}
8818 RegisterList QADD8_cccc01100010nnnndddd11111001mmmm_case_0::
defs(Instruction inst) const8819 defs(Instruction inst) const {
8820 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8821 // defs: '{inst(15:12)}'
8822 return RegisterList().
8823 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
8824 }
8825
8826 SafetyLevel QADD8_cccc01100010nnnndddd11111001mmmm_case_0::
safety(Instruction inst) const8827 safety(Instruction inst) const {
8828 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8829
8830 // 15 ==
8831 // inst(15:12) ||
8832 // 15 ==
8833 // inst(19:16) ||
8834 // 15 ==
8835 // inst(3:0) => UNPREDICTABLE
8836 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
8837 (((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
8838 (((15) == ((inst.Bits() & 0x0000000F)))))
8839 return UNPREDICTABLE;
8840
8841 return MAY_BE_SAFE;
8842 }
8843
8844
8845 RegisterList QADD8_cccc01100010nnnndddd11111001mmmm_case_0::
uses(Instruction inst) const8846 uses(Instruction inst) const {
8847 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8848 // uses: '{inst(19:16), inst(3:0)}'
8849 return RegisterList().
8850 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
8851 Add(Register((inst.Bits() & 0x0000000F)));
8852 }
8853
8854 // QADD_cccc00010000nnnndddd00000101mmmm_case_0:
8855 //
8856 // {Cond: Cond(31:28),
8857 // Pc: 15,
8858 // Rd: Rd(15:12),
8859 // Rm: Rm(3:0),
8860 // Rn: Rn(19:16),
8861 // arch: v5TE,
8862 // defs: {Rd},
8863 // fields: [Cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)],
8864 // pattern: cccc00010000nnnndddd00000101mmmm,
8865 // rule: QADD,
8866 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE],
8867 // uses: {Rn, Rm}}
8868 RegisterList QADD_cccc00010000nnnndddd00000101mmmm_case_0::
defs(Instruction inst) const8869 defs(Instruction inst) const {
8870 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8871 // defs: '{inst(15:12)}'
8872 return RegisterList().
8873 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
8874 }
8875
8876 SafetyLevel QADD_cccc00010000nnnndddd00000101mmmm_case_0::
safety(Instruction inst) const8877 safety(Instruction inst) const {
8878 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8879
8880 // 15 ==
8881 // inst(15:12) ||
8882 // 15 ==
8883 // inst(19:16) ||
8884 // 15 ==
8885 // inst(3:0) => UNPREDICTABLE
8886 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
8887 (((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
8888 (((15) == ((inst.Bits() & 0x0000000F)))))
8889 return UNPREDICTABLE;
8890
8891 return MAY_BE_SAFE;
8892 }
8893
8894
8895 RegisterList QADD_cccc00010000nnnndddd00000101mmmm_case_0::
uses(Instruction inst) const8896 uses(Instruction inst) const {
8897 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8898 // uses: '{inst(19:16), inst(3:0)}'
8899 return RegisterList().
8900 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
8901 Add(Register((inst.Bits() & 0x0000000F)));
8902 }
8903
8904 // QASX_cccc01100010nnnndddd11110011mmmm_case_0:
8905 //
8906 // {Pc: 15,
8907 // Rd: Rd(15:12),
8908 // Rm: Rm(3:0),
8909 // Rn: Rn(19:16),
8910 // arch: v6,
8911 // cond: cond(31:28),
8912 // defs: {Rd},
8913 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)],
8914 // pattern: cccc01100010nnnndddd11110011mmmm,
8915 // rule: QASX,
8916 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE],
8917 // uses: {Rn, Rm}}
8918 RegisterList QASX_cccc01100010nnnndddd11110011mmmm_case_0::
defs(Instruction inst) const8919 defs(Instruction inst) const {
8920 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8921 // defs: '{inst(15:12)}'
8922 return RegisterList().
8923 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
8924 }
8925
8926 SafetyLevel QASX_cccc01100010nnnndddd11110011mmmm_case_0::
safety(Instruction inst) const8927 safety(Instruction inst) const {
8928 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8929
8930 // 15 ==
8931 // inst(15:12) ||
8932 // 15 ==
8933 // inst(19:16) ||
8934 // 15 ==
8935 // inst(3:0) => UNPREDICTABLE
8936 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
8937 (((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
8938 (((15) == ((inst.Bits() & 0x0000000F)))))
8939 return UNPREDICTABLE;
8940
8941 return MAY_BE_SAFE;
8942 }
8943
8944
8945 RegisterList QASX_cccc01100010nnnndddd11110011mmmm_case_0::
uses(Instruction inst) const8946 uses(Instruction inst) const {
8947 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8948 // uses: '{inst(19:16), inst(3:0)}'
8949 return RegisterList().
8950 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
8951 Add(Register((inst.Bits() & 0x0000000F)));
8952 }
8953
8954 // QDADD_cccc00010100nnnndddd00000101mmmm_case_0:
8955 //
8956 // {Cond: Cond(31:28),
8957 // Pc: 15,
8958 // Rd: Rd(15:12),
8959 // Rm: Rm(3:0),
8960 // Rn: Rn(19:16),
8961 // arch: v5TE,
8962 // defs: {Rd},
8963 // fields: [Cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)],
8964 // pattern: cccc00010100nnnndddd00000101mmmm,
8965 // rule: QDADD,
8966 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE],
8967 // uses: {Rn, Rm}}
8968 RegisterList QDADD_cccc00010100nnnndddd00000101mmmm_case_0::
defs(Instruction inst) const8969 defs(Instruction inst) const {
8970 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8971 // defs: '{inst(15:12)}'
8972 return RegisterList().
8973 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
8974 }
8975
8976 SafetyLevel QDADD_cccc00010100nnnndddd00000101mmmm_case_0::
safety(Instruction inst) const8977 safety(Instruction inst) const {
8978 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8979
8980 // 15 ==
8981 // inst(15:12) ||
8982 // 15 ==
8983 // inst(19:16) ||
8984 // 15 ==
8985 // inst(3:0) => UNPREDICTABLE
8986 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
8987 (((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
8988 (((15) == ((inst.Bits() & 0x0000000F)))))
8989 return UNPREDICTABLE;
8990
8991 return MAY_BE_SAFE;
8992 }
8993
8994
8995 RegisterList QDADD_cccc00010100nnnndddd00000101mmmm_case_0::
uses(Instruction inst) const8996 uses(Instruction inst) const {
8997 UNREFERENCED_PARAMETER(inst); // To silence compiler.
8998 // uses: '{inst(19:16), inst(3:0)}'
8999 return RegisterList().
9000 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
9001 Add(Register((inst.Bits() & 0x0000000F)));
9002 }
9003
9004 // QDSUB_cccc00010110nnnndddd00000101mmmm_case_0:
9005 //
9006 // {Cond: Cond(31:28),
9007 // Pc: 15,
9008 // Rd: Rd(15:12),
9009 // Rm: Rm(3:0),
9010 // Rn: Rn(19:16),
9011 // arch: v5TE,
9012 // defs: {Rd},
9013 // fields: [Cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)],
9014 // pattern: cccc00010110nnnndddd00000101mmmm,
9015 // rule: QDSUB,
9016 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE],
9017 // uses: {Rn, Rm}}
9018 RegisterList QDSUB_cccc00010110nnnndddd00000101mmmm_case_0::
defs(Instruction inst) const9019 defs(Instruction inst) const {
9020 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9021 // defs: '{inst(15:12)}'
9022 return RegisterList().
9023 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
9024 }
9025
9026 SafetyLevel QDSUB_cccc00010110nnnndddd00000101mmmm_case_0::
safety(Instruction inst) const9027 safety(Instruction inst) const {
9028 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9029
9030 // 15 ==
9031 // inst(15:12) ||
9032 // 15 ==
9033 // inst(19:16) ||
9034 // 15 ==
9035 // inst(3:0) => UNPREDICTABLE
9036 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
9037 (((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
9038 (((15) == ((inst.Bits() & 0x0000000F)))))
9039 return UNPREDICTABLE;
9040
9041 return MAY_BE_SAFE;
9042 }
9043
9044
9045 RegisterList QDSUB_cccc00010110nnnndddd00000101mmmm_case_0::
uses(Instruction inst) const9046 uses(Instruction inst) const {
9047 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9048 // uses: '{inst(19:16), inst(3:0)}'
9049 return RegisterList().
9050 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
9051 Add(Register((inst.Bits() & 0x0000000F)));
9052 }
9053
9054 // QSAX_cccc01100010nnnndddd11110101mmmm_case_0:
9055 //
9056 // {Pc: 15,
9057 // Rd: Rd(15:12),
9058 // Rm: Rm(3:0),
9059 // Rn: Rn(19:16),
9060 // arch: v6,
9061 // cond: cond(31:28),
9062 // defs: {Rd},
9063 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)],
9064 // pattern: cccc01100010nnnndddd11110101mmmm,
9065 // rule: QSAX,
9066 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE],
9067 // uses: {Rn, Rm}}
9068 RegisterList QSAX_cccc01100010nnnndddd11110101mmmm_case_0::
defs(Instruction inst) const9069 defs(Instruction inst) const {
9070 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9071 // defs: '{inst(15:12)}'
9072 return RegisterList().
9073 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
9074 }
9075
9076 SafetyLevel QSAX_cccc01100010nnnndddd11110101mmmm_case_0::
safety(Instruction inst) const9077 safety(Instruction inst) const {
9078 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9079
9080 // 15 ==
9081 // inst(15:12) ||
9082 // 15 ==
9083 // inst(19:16) ||
9084 // 15 ==
9085 // inst(3:0) => UNPREDICTABLE
9086 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
9087 (((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
9088 (((15) == ((inst.Bits() & 0x0000000F)))))
9089 return UNPREDICTABLE;
9090
9091 return MAY_BE_SAFE;
9092 }
9093
9094
9095 RegisterList QSAX_cccc01100010nnnndddd11110101mmmm_case_0::
uses(Instruction inst) const9096 uses(Instruction inst) const {
9097 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9098 // uses: '{inst(19:16), inst(3:0)}'
9099 return RegisterList().
9100 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
9101 Add(Register((inst.Bits() & 0x0000000F)));
9102 }
9103
9104 // QSUB16_cccc01100010nnnndddd11110111mmmm_case_0:
9105 //
9106 // {Pc: 15,
9107 // Rd: Rd(15:12),
9108 // Rm: Rm(3:0),
9109 // Rn: Rn(19:16),
9110 // arch: v6,
9111 // cond: cond(31:28),
9112 // defs: {Rd},
9113 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)],
9114 // pattern: cccc01100010nnnndddd11110111mmmm,
9115 // rule: QSUB16,
9116 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE],
9117 // uses: {Rn, Rm}}
9118 RegisterList QSUB16_cccc01100010nnnndddd11110111mmmm_case_0::
defs(Instruction inst) const9119 defs(Instruction inst) const {
9120 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9121 // defs: '{inst(15:12)}'
9122 return RegisterList().
9123 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
9124 }
9125
9126 SafetyLevel QSUB16_cccc01100010nnnndddd11110111mmmm_case_0::
safety(Instruction inst) const9127 safety(Instruction inst) const {
9128 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9129
9130 // 15 ==
9131 // inst(15:12) ||
9132 // 15 ==
9133 // inst(19:16) ||
9134 // 15 ==
9135 // inst(3:0) => UNPREDICTABLE
9136 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
9137 (((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
9138 (((15) == ((inst.Bits() & 0x0000000F)))))
9139 return UNPREDICTABLE;
9140
9141 return MAY_BE_SAFE;
9142 }
9143
9144
9145 RegisterList QSUB16_cccc01100010nnnndddd11110111mmmm_case_0::
uses(Instruction inst) const9146 uses(Instruction inst) const {
9147 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9148 // uses: '{inst(19:16), inst(3:0)}'
9149 return RegisterList().
9150 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
9151 Add(Register((inst.Bits() & 0x0000000F)));
9152 }
9153
9154 // QSUB8_cccc01100010nnnndddd11111111mmmm_case_0:
9155 //
9156 // {Pc: 15,
9157 // Rd: Rd(15:12),
9158 // Rm: Rm(3:0),
9159 // Rn: Rn(19:16),
9160 // arch: v6,
9161 // cond: cond(31:28),
9162 // defs: {Rd},
9163 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)],
9164 // pattern: cccc01100010nnnndddd11111111mmmm,
9165 // rule: QSUB8,
9166 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE],
9167 // uses: {Rn, Rm}}
9168 RegisterList QSUB8_cccc01100010nnnndddd11111111mmmm_case_0::
defs(Instruction inst) const9169 defs(Instruction inst) const {
9170 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9171 // defs: '{inst(15:12)}'
9172 return RegisterList().
9173 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
9174 }
9175
9176 SafetyLevel QSUB8_cccc01100010nnnndddd11111111mmmm_case_0::
safety(Instruction inst) const9177 safety(Instruction inst) const {
9178 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9179
9180 // 15 ==
9181 // inst(15:12) ||
9182 // 15 ==
9183 // inst(19:16) ||
9184 // 15 ==
9185 // inst(3:0) => UNPREDICTABLE
9186 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
9187 (((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
9188 (((15) == ((inst.Bits() & 0x0000000F)))))
9189 return UNPREDICTABLE;
9190
9191 return MAY_BE_SAFE;
9192 }
9193
9194
9195 RegisterList QSUB8_cccc01100010nnnndddd11111111mmmm_case_0::
uses(Instruction inst) const9196 uses(Instruction inst) const {
9197 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9198 // uses: '{inst(19:16), inst(3:0)}'
9199 return RegisterList().
9200 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
9201 Add(Register((inst.Bits() & 0x0000000F)));
9202 }
9203
9204 // QSUB_cccc00010010nnnndddd00000101mmmm_case_0:
9205 //
9206 // {Cond: Cond(31:28),
9207 // Pc: 15,
9208 // Rd: Rd(15:12),
9209 // Rm: Rm(3:0),
9210 // Rn: Rn(19:16),
9211 // arch: v5TE,
9212 // defs: {Rd},
9213 // fields: [Cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)],
9214 // pattern: cccc00010010nnnndddd00000101mmmm,
9215 // rule: QSUB,
9216 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE],
9217 // uses: {Rn, Rm}}
9218 RegisterList QSUB_cccc00010010nnnndddd00000101mmmm_case_0::
defs(Instruction inst) const9219 defs(Instruction inst) const {
9220 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9221 // defs: '{inst(15:12)}'
9222 return RegisterList().
9223 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
9224 }
9225
9226 SafetyLevel QSUB_cccc00010010nnnndddd00000101mmmm_case_0::
safety(Instruction inst) const9227 safety(Instruction inst) const {
9228 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9229
9230 // 15 ==
9231 // inst(15:12) ||
9232 // 15 ==
9233 // inst(19:16) ||
9234 // 15 ==
9235 // inst(3:0) => UNPREDICTABLE
9236 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
9237 (((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
9238 (((15) == ((inst.Bits() & 0x0000000F)))))
9239 return UNPREDICTABLE;
9240
9241 return MAY_BE_SAFE;
9242 }
9243
9244
9245 RegisterList QSUB_cccc00010010nnnndddd00000101mmmm_case_0::
uses(Instruction inst) const9246 uses(Instruction inst) const {
9247 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9248 // uses: '{inst(19:16), inst(3:0)}'
9249 return RegisterList().
9250 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
9251 Add(Register((inst.Bits() & 0x0000000F)));
9252 }
9253
9254 // RBIT_cccc011011111111dddd11110011mmmm_case_0:
9255 //
9256 // {Pc: 15,
9257 // Rd: Rd(15:12),
9258 // Rm: Rm(3:0),
9259 // arch: v6T2,
9260 // cond: cond(31:28),
9261 // defs: {Rd},
9262 // fields: [cond(31:28), Rd(15:12), Rm(3:0)],
9263 // pattern: cccc011011111111dddd11110011mmmm,
9264 // rule: RBIT,
9265 // safety: [Pc in {Rd, Rm} => UNPREDICTABLE],
9266 // uses: {Rm}}
9267 RegisterList RBIT_cccc011011111111dddd11110011mmmm_case_0::
defs(Instruction inst) const9268 defs(Instruction inst) const {
9269 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9270 // defs: '{inst(15:12)}'
9271 return RegisterList().
9272 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
9273 }
9274
9275 SafetyLevel RBIT_cccc011011111111dddd11110011mmmm_case_0::
safety(Instruction inst) const9276 safety(Instruction inst) const {
9277 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9278
9279 // 15 ==
9280 // inst(15:12) ||
9281 // 15 ==
9282 // inst(3:0) => UNPREDICTABLE
9283 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
9284 (((15) == ((inst.Bits() & 0x0000000F)))))
9285 return UNPREDICTABLE;
9286
9287 return MAY_BE_SAFE;
9288 }
9289
9290
9291 RegisterList RBIT_cccc011011111111dddd11110011mmmm_case_0::
uses(Instruction inst) const9292 uses(Instruction inst) const {
9293 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9294 // uses: '{inst(3:0)}'
9295 return RegisterList().
9296 Add(Register((inst.Bits() & 0x0000000F)));
9297 }
9298
9299 // REV16_cccc011010111111dddd11111011mmmm_case_0:
9300 //
9301 // {Pc: 15,
9302 // Rd: Rd(15:12),
9303 // Rm: Rm(3:0),
9304 // arch: v6,
9305 // cond: cond(31:28),
9306 // defs: {Rd},
9307 // fields: [cond(31:28), Rd(15:12), Rm(3:0)],
9308 // pattern: cccc011010111111dddd11111011mmmm,
9309 // rule: REV16,
9310 // safety: [Pc in {Rd, Rm} => UNPREDICTABLE],
9311 // uses: {Rm}}
9312 RegisterList REV16_cccc011010111111dddd11111011mmmm_case_0::
defs(Instruction inst) const9313 defs(Instruction inst) const {
9314 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9315 // defs: '{inst(15:12)}'
9316 return RegisterList().
9317 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
9318 }
9319
9320 SafetyLevel REV16_cccc011010111111dddd11111011mmmm_case_0::
safety(Instruction inst) const9321 safety(Instruction inst) const {
9322 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9323
9324 // 15 ==
9325 // inst(15:12) ||
9326 // 15 ==
9327 // inst(3:0) => UNPREDICTABLE
9328 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
9329 (((15) == ((inst.Bits() & 0x0000000F)))))
9330 return UNPREDICTABLE;
9331
9332 return MAY_BE_SAFE;
9333 }
9334
9335
9336 RegisterList REV16_cccc011010111111dddd11111011mmmm_case_0::
uses(Instruction inst) const9337 uses(Instruction inst) const {
9338 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9339 // uses: '{inst(3:0)}'
9340 return RegisterList().
9341 Add(Register((inst.Bits() & 0x0000000F)));
9342 }
9343
9344 // REVSH_cccc011011111111dddd11111011mmmm_case_0:
9345 //
9346 // {Pc: 15,
9347 // Rd: Rd(15:12),
9348 // Rm: Rm(3:0),
9349 // arch: v6,
9350 // cond: cond(31:28),
9351 // defs: {Rd},
9352 // fields: [cond(31:28), Rd(15:12), Rm(3:0)],
9353 // pattern: cccc011011111111dddd11111011mmmm,
9354 // rule: REVSH,
9355 // safety: [Pc in {Rd, Rm} => UNPREDICTABLE],
9356 // uses: {Rm}}
9357 RegisterList REVSH_cccc011011111111dddd11111011mmmm_case_0::
defs(Instruction inst) const9358 defs(Instruction inst) const {
9359 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9360 // defs: '{inst(15:12)}'
9361 return RegisterList().
9362 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
9363 }
9364
9365 SafetyLevel REVSH_cccc011011111111dddd11111011mmmm_case_0::
safety(Instruction inst) const9366 safety(Instruction inst) const {
9367 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9368
9369 // 15 ==
9370 // inst(15:12) ||
9371 // 15 ==
9372 // inst(3:0) => UNPREDICTABLE
9373 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
9374 (((15) == ((inst.Bits() & 0x0000000F)))))
9375 return UNPREDICTABLE;
9376
9377 return MAY_BE_SAFE;
9378 }
9379
9380
9381 RegisterList REVSH_cccc011011111111dddd11111011mmmm_case_0::
uses(Instruction inst) const9382 uses(Instruction inst) const {
9383 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9384 // uses: '{inst(3:0)}'
9385 return RegisterList().
9386 Add(Register((inst.Bits() & 0x0000000F)));
9387 }
9388
9389 // REV_cccc011010111111dddd11110011mmmm_case_0:
9390 //
9391 // {Pc: 15,
9392 // Rd: Rd(15:12),
9393 // Rm: Rm(3:0),
9394 // arch: v6,
9395 // cond: cond(31:28),
9396 // defs: {Rd},
9397 // fields: [cond(31:28), Rd(15:12), Rm(3:0)],
9398 // pattern: cccc011010111111dddd11110011mmmm,
9399 // rule: REV,
9400 // safety: [Pc in {Rd, Rm} => UNPREDICTABLE],
9401 // uses: {Rm}}
9402 RegisterList REV_cccc011010111111dddd11110011mmmm_case_0::
defs(Instruction inst) const9403 defs(Instruction inst) const {
9404 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9405 // defs: '{inst(15:12)}'
9406 return RegisterList().
9407 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
9408 }
9409
9410 SafetyLevel REV_cccc011010111111dddd11110011mmmm_case_0::
safety(Instruction inst) const9411 safety(Instruction inst) const {
9412 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9413
9414 // 15 ==
9415 // inst(15:12) ||
9416 // 15 ==
9417 // inst(3:0) => UNPREDICTABLE
9418 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
9419 (((15) == ((inst.Bits() & 0x0000000F)))))
9420 return UNPREDICTABLE;
9421
9422 return MAY_BE_SAFE;
9423 }
9424
9425
9426 RegisterList REV_cccc011010111111dddd11110011mmmm_case_0::
uses(Instruction inst) const9427 uses(Instruction inst) const {
9428 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9429 // uses: '{inst(3:0)}'
9430 return RegisterList().
9431 Add(Register((inst.Bits() & 0x0000000F)));
9432 }
9433
9434 // RFE_1111100pu0w1nnnn0000101000000000_case_0:
9435 //
9436 // {arch: v6,
9437 // defs: {},
9438 // pattern: 1111100pu0w1nnnn0000101000000000,
9439 // rule: RFE,
9440 // safety: [true => FORBIDDEN],
9441 // true: true,
9442 // uses: {}}
9443 RegisterList RFE_1111100pu0w1nnnn0000101000000000_case_0::
defs(Instruction inst) const9444 defs(Instruction inst) const {
9445 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9446 // defs: '{}'
9447 return RegisterList();
9448 }
9449
9450 SafetyLevel RFE_1111100pu0w1nnnn0000101000000000_case_0::
safety(Instruction inst) const9451 safety(Instruction inst) const {
9452 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9453
9454 // true => FORBIDDEN
9455 if (true)
9456 return FORBIDDEN;
9457
9458 return MAY_BE_SAFE;
9459 }
9460
9461
9462 RegisterList RFE_1111100pu0w1nnnn0000101000000000_case_0::
uses(Instruction inst) const9463 uses(Instruction inst) const {
9464 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9465 // uses: '{}'
9466 return RegisterList();
9467 }
9468
9469 // ROR_immediate_cccc0001101s0000ddddiiiii110mmmm_case_0:
9470 //
9471 // {NZCV: 16,
9472 // None: 32,
9473 // Rd: Rd(15:12),
9474 // Rm: Rm(3:0),
9475 // S: S(20),
9476 // cond: cond(31:28),
9477 // defs: {Rd, NZCV
9478 // if S
9479 // else None},
9480 // fields: [cond(31:28),
9481 // S(20),
9482 // Rd(15:12),
9483 // imm5(11:7),
9484 // type(6:5),
9485 // Rm(3:0)],
9486 // imm5: imm5(11:7),
9487 // pattern: cccc0001101s0000ddddiiiii110mmmm,
9488 // rule: ROR_immediate,
9489 // safety: [(Rd(15:12)=1111 &&
9490 // S(20)=1) => DECODER_ERROR,
9491 // imm5(11:7)=00000 => DECODER_ERROR,
9492 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS],
9493 // shift: DecodeImmShift(type, imm5),
9494 // type: type(6:5),
9495 // uses: {Rm}}
9496 RegisterList ROR_immediate_cccc0001101s0000ddddiiiii110mmmm_case_0::
defs(Instruction inst) const9497 defs(Instruction inst) const {
9498 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9499 // defs: '{inst(15:12), 16
9500 // if inst(20)
9501 // else 32}'
9502 return RegisterList().
9503 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
9504 Add(Register(((((inst.Bits() & 0x00100000) >> 20) != 0)
9505 ? 16
9506 : 32)));
9507 }
9508
9509 SafetyLevel ROR_immediate_cccc0001101s0000ddddiiiii110mmmm_case_0::
safety(Instruction inst) const9510 safety(Instruction inst) const {
9511 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9512
9513 // (inst(15:12)=1111 &&
9514 // inst(20)=1) => DECODER_ERROR
9515 if ((((inst.Bits() & 0x0000F000) ==
9516 0x0000F000) &&
9517 ((inst.Bits() & 0x00100000) ==
9518 0x00100000)))
9519 return DECODER_ERROR;
9520
9521 // inst(11:7)=00000 => DECODER_ERROR
9522 if ((inst.Bits() & 0x00000F80) ==
9523 0x00000000)
9524 return DECODER_ERROR;
9525
9526 // inst(15:12)=1111 => FORBIDDEN_OPERANDS
9527 if ((inst.Bits() & 0x0000F000) ==
9528 0x0000F000)
9529 return FORBIDDEN_OPERANDS;
9530
9531 return MAY_BE_SAFE;
9532 }
9533
9534
9535 RegisterList ROR_immediate_cccc0001101s0000ddddiiiii110mmmm_case_0::
uses(Instruction inst) const9536 uses(Instruction inst) const {
9537 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9538 // uses: '{inst(3:0)}'
9539 return RegisterList().
9540 Add(Register((inst.Bits() & 0x0000000F)));
9541 }
9542
9543 // ROR_register_cccc0001101s0000ddddmmmm0111nnnn_case_0:
9544 //
9545 // {NZCV: 16,
9546 // None: 32,
9547 // Pc: 15,
9548 // Rd: Rd(15:12),
9549 // Rm: Rm(11:8),
9550 // Rn: Rn(3:0),
9551 // S: S(20),
9552 // cond: cond(31:28),
9553 // defs: {Rd, NZCV
9554 // if setflags
9555 // else None},
9556 // fields: [cond(31:28), S(20), Rd(15:12), Rm(11:8), Rn(3:0)],
9557 // pattern: cccc0001101s0000ddddmmmm0111nnnn,
9558 // rule: ROR_register,
9559 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE],
9560 // setflags: S(20)=1,
9561 // uses: {Rn, Rm}}
9562 RegisterList ROR_register_cccc0001101s0000ddddmmmm0111nnnn_case_0::
defs(Instruction inst) const9563 defs(Instruction inst) const {
9564 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9565 // defs: '{inst(15:12), 16
9566 // if inst(20)=1
9567 // else 32}'
9568 return RegisterList().
9569 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
9570 Add(Register(((inst.Bits() & 0x00100000) ==
9571 0x00100000
9572 ? 16
9573 : 32)));
9574 }
9575
9576 SafetyLevel ROR_register_cccc0001101s0000ddddmmmm0111nnnn_case_0::
safety(Instruction inst) const9577 safety(Instruction inst) const {
9578 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9579
9580 // 15 ==
9581 // inst(15:12) ||
9582 // 15 ==
9583 // inst(3:0) ||
9584 // 15 ==
9585 // inst(11:8) => UNPREDICTABLE
9586 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
9587 (((15) == ((inst.Bits() & 0x0000000F)))) ||
9588 (((15) == (((inst.Bits() & 0x00000F00) >> 8)))))
9589 return UNPREDICTABLE;
9590
9591 return MAY_BE_SAFE;
9592 }
9593
9594
9595 RegisterList ROR_register_cccc0001101s0000ddddmmmm0111nnnn_case_0::
uses(Instruction inst) const9596 uses(Instruction inst) const {
9597 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9598 // uses: '{inst(3:0), inst(11:8)}'
9599 return RegisterList().
9600 Add(Register((inst.Bits() & 0x0000000F))).
9601 Add(Register(((inst.Bits() & 0x00000F00) >> 8)));
9602 }
9603
9604 // RRX_cccc0001101s0000dddd00000110mmmm_case_0:
9605 //
9606 // {NZCV: 16,
9607 // None: 32,
9608 // Rd: Rd(15:12),
9609 // Rm: Rm(3:0),
9610 // S: S(20),
9611 // cond: cond(31:28),
9612 // defs: {Rd, NZCV
9613 // if S
9614 // else None},
9615 // fields: [cond(31:28), S(20), Rd(15:12), Rm(3:0)],
9616 // pattern: cccc0001101s0000dddd00000110mmmm,
9617 // rule: RRX,
9618 // safety: [(Rd(15:12)=1111 &&
9619 // S(20)=1) => DECODER_ERROR,
9620 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS],
9621 // uses: {Rm}}
9622 RegisterList RRX_cccc0001101s0000dddd00000110mmmm_case_0::
defs(Instruction inst) const9623 defs(Instruction inst) const {
9624 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9625 // defs: '{inst(15:12), 16
9626 // if inst(20)
9627 // else 32}'
9628 return RegisterList().
9629 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
9630 Add(Register(((((inst.Bits() & 0x00100000) >> 20) != 0)
9631 ? 16
9632 : 32)));
9633 }
9634
9635 SafetyLevel RRX_cccc0001101s0000dddd00000110mmmm_case_0::
safety(Instruction inst) const9636 safety(Instruction inst) const {
9637 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9638
9639 // (inst(15:12)=1111 &&
9640 // inst(20)=1) => DECODER_ERROR
9641 if ((((inst.Bits() & 0x0000F000) ==
9642 0x0000F000) &&
9643 ((inst.Bits() & 0x00100000) ==
9644 0x00100000)))
9645 return DECODER_ERROR;
9646
9647 // inst(15:12)=1111 => FORBIDDEN_OPERANDS
9648 if ((inst.Bits() & 0x0000F000) ==
9649 0x0000F000)
9650 return FORBIDDEN_OPERANDS;
9651
9652 return MAY_BE_SAFE;
9653 }
9654
9655
9656 RegisterList RRX_cccc0001101s0000dddd00000110mmmm_case_0::
uses(Instruction inst) const9657 uses(Instruction inst) const {
9658 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9659 // uses: '{inst(3:0)}'
9660 return RegisterList().
9661 Add(Register((inst.Bits() & 0x0000000F)));
9662 }
9663
9664 // RSB_immediate_cccc0010011snnnnddddiiiiiiiiiiii_case_0:
9665 //
9666 // {NZCV: 16,
9667 // None: 32,
9668 // Rd: Rd(15:12),
9669 // Rn: Rn(19:16),
9670 // S: S(20),
9671 // cond: cond(31:28),
9672 // defs: {Rd, NZCV
9673 // if setflags
9674 // else None},
9675 // fields: [cond(31:28), S(20), Rn(19:16), Rd(15:12), imm12(11:0)],
9676 // imm12: imm12(11:0),
9677 // imm32: ARMExpandImm(imm12),
9678 // pattern: cccc0010011snnnnddddiiiiiiiiiiii,
9679 // rule: RSB_immediate,
9680 // safety: [(Rd(15:12)=1111 &&
9681 // S(20)=1) => DECODER_ERROR,
9682 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS],
9683 // setflags: S(20)=1,
9684 // uses: {Rn}}
9685 RegisterList RSB_immediate_cccc0010011snnnnddddiiiiiiiiiiii_case_0::
defs(Instruction inst) const9686 defs(Instruction inst) const {
9687 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9688 // defs: '{inst(15:12), 16
9689 // if inst(20)=1
9690 // else 32}'
9691 return RegisterList().
9692 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
9693 Add(Register(((inst.Bits() & 0x00100000) ==
9694 0x00100000
9695 ? 16
9696 : 32)));
9697 }
9698
9699 SafetyLevel RSB_immediate_cccc0010011snnnnddddiiiiiiiiiiii_case_0::
safety(Instruction inst) const9700 safety(Instruction inst) const {
9701 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9702
9703 // (inst(15:12)=1111 &&
9704 // inst(20)=1) => DECODER_ERROR
9705 if ((((inst.Bits() & 0x0000F000) ==
9706 0x0000F000) &&
9707 ((inst.Bits() & 0x00100000) ==
9708 0x00100000)))
9709 return DECODER_ERROR;
9710
9711 // inst(15:12)=1111 => FORBIDDEN_OPERANDS
9712 if ((inst.Bits() & 0x0000F000) ==
9713 0x0000F000)
9714 return FORBIDDEN_OPERANDS;
9715
9716 return MAY_BE_SAFE;
9717 }
9718
9719
9720 RegisterList RSB_immediate_cccc0010011snnnnddddiiiiiiiiiiii_case_0::
uses(Instruction inst) const9721 uses(Instruction inst) const {
9722 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9723 // uses: '{inst(19:16)}'
9724 return RegisterList().
9725 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
9726 }
9727
9728 // RSB_register_cccc0000011snnnnddddiiiiitt0mmmm_case_0:
9729 //
9730 // {NZCV: 16,
9731 // None: 32,
9732 // Rd: Rd(15:12),
9733 // Rm: Rm(3:0),
9734 // Rn: Rn(19:16),
9735 // S: S(20),
9736 // cond: cond(31:28),
9737 // defs: {Rd, NZCV
9738 // if S
9739 // else None},
9740 // fields: [cond(31:28),
9741 // S(20),
9742 // Rn(19:16),
9743 // Rd(15:12),
9744 // imm5(11:7),
9745 // type(6:5),
9746 // Rm(3:0)],
9747 // imm5: imm5(11:7),
9748 // pattern: cccc0000011snnnnddddiiiiitt0mmmm,
9749 // rule: RSB_register,
9750 // safety: [(Rd(15:12)=1111 &&
9751 // S(20)=1) => DECODER_ERROR,
9752 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS],
9753 // shift: DecodeImmShift(type, imm5),
9754 // type: type(6:5),
9755 // uses: {Rn, Rm}}
9756 RegisterList RSB_register_cccc0000011snnnnddddiiiiitt0mmmm_case_0::
defs(Instruction inst) const9757 defs(Instruction inst) const {
9758 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9759 // defs: '{inst(15:12), 16
9760 // if inst(20)
9761 // else 32}'
9762 return RegisterList().
9763 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
9764 Add(Register(((((inst.Bits() & 0x00100000) >> 20) != 0)
9765 ? 16
9766 : 32)));
9767 }
9768
9769 SafetyLevel RSB_register_cccc0000011snnnnddddiiiiitt0mmmm_case_0::
safety(Instruction inst) const9770 safety(Instruction inst) const {
9771 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9772
9773 // (inst(15:12)=1111 &&
9774 // inst(20)=1) => DECODER_ERROR
9775 if ((((inst.Bits() & 0x0000F000) ==
9776 0x0000F000) &&
9777 ((inst.Bits() & 0x00100000) ==
9778 0x00100000)))
9779 return DECODER_ERROR;
9780
9781 // inst(15:12)=1111 => FORBIDDEN_OPERANDS
9782 if ((inst.Bits() & 0x0000F000) ==
9783 0x0000F000)
9784 return FORBIDDEN_OPERANDS;
9785
9786 return MAY_BE_SAFE;
9787 }
9788
9789
9790 RegisterList RSB_register_cccc0000011snnnnddddiiiiitt0mmmm_case_0::
uses(Instruction inst) const9791 uses(Instruction inst) const {
9792 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9793 // uses: '{inst(19:16), inst(3:0)}'
9794 return RegisterList().
9795 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
9796 Add(Register((inst.Bits() & 0x0000000F)));
9797 }
9798
9799 // RSB_register_shfited_register_cccc0000011snnnnddddssss0tt1mmmm_case_0:
9800 //
9801 // {NZCV: 16,
9802 // None: 32,
9803 // Pc: 15,
9804 // Rd: Rd(15:12),
9805 // Rm: Rm(3:0),
9806 // Rn: Rn(19:16),
9807 // Rs: Rs(11:8),
9808 // S: S(20),
9809 // cond: cond(31:28),
9810 // defs: {Rd, NZCV
9811 // if setflags
9812 // else None},
9813 // fields: [cond(31:28),
9814 // S(20),
9815 // Rn(19:16),
9816 // Rd(15:12),
9817 // Rs(11:8),
9818 // type(6:5),
9819 // Rm(3:0)],
9820 // pattern: cccc0000011snnnnddddssss0tt1mmmm,
9821 // rule: RSB_register_shfited_register,
9822 // safety: [Pc in {Rn, Rd, Rm, Rs} => UNPREDICTABLE],
9823 // setflags: S(20)=1,
9824 // shift_t: DecodeRegShift(type),
9825 // type: type(6:5),
9826 // uses: {Rn, Rm, Rs}}
9827 RegisterList RSB_register_shfited_register_cccc0000011snnnnddddssss0tt1mmmm_case_0::
defs(Instruction inst) const9828 defs(Instruction inst) const {
9829 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9830 // defs: '{inst(15:12), 16
9831 // if inst(20)=1
9832 // else 32}'
9833 return RegisterList().
9834 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
9835 Add(Register(((inst.Bits() & 0x00100000) ==
9836 0x00100000
9837 ? 16
9838 : 32)));
9839 }
9840
9841 SafetyLevel RSB_register_shfited_register_cccc0000011snnnnddddssss0tt1mmmm_case_0::
safety(Instruction inst) const9842 safety(Instruction inst) const {
9843 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9844
9845 // 15 ==
9846 // inst(19:16) ||
9847 // 15 ==
9848 // inst(15:12) ||
9849 // 15 ==
9850 // inst(3:0) ||
9851 // 15 ==
9852 // inst(11:8) => UNPREDICTABLE
9853 if ((((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
9854 (((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
9855 (((15) == ((inst.Bits() & 0x0000000F)))) ||
9856 (((15) == (((inst.Bits() & 0x00000F00) >> 8)))))
9857 return UNPREDICTABLE;
9858
9859 return MAY_BE_SAFE;
9860 }
9861
9862
9863 RegisterList RSB_register_shfited_register_cccc0000011snnnnddddssss0tt1mmmm_case_0::
uses(Instruction inst) const9864 uses(Instruction inst) const {
9865 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9866 // uses: '{inst(19:16), inst(3:0), inst(11:8)}'
9867 return RegisterList().
9868 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
9869 Add(Register((inst.Bits() & 0x0000000F))).
9870 Add(Register(((inst.Bits() & 0x00000F00) >> 8)));
9871 }
9872
9873 // RSC_immediate_cccc0010111snnnnddddiiiiiiiiiiii_case_0:
9874 //
9875 // {NZCV: 16,
9876 // None: 32,
9877 // Rd: Rd(15:12),
9878 // Rn: Rn(19:16),
9879 // S: S(20),
9880 // cond: cond(31:28),
9881 // defs: {Rd, NZCV
9882 // if setflags
9883 // else None},
9884 // fields: [cond(31:28), S(20), Rn(19:16), Rd(15:12), imm12(11:0)],
9885 // imm12: imm12(11:0),
9886 // imm32: ARMExpandImm(imm12),
9887 // pattern: cccc0010111snnnnddddiiiiiiiiiiii,
9888 // rule: RSC_immediate,
9889 // safety: [(Rd(15:12)=1111 &&
9890 // S(20)=1) => DECODER_ERROR,
9891 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS],
9892 // setflags: S(20)=1,
9893 // uses: {Rn}}
9894 RegisterList RSC_immediate_cccc0010111snnnnddddiiiiiiiiiiii_case_0::
defs(Instruction inst) const9895 defs(Instruction inst) const {
9896 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9897 // defs: '{inst(15:12), 16
9898 // if inst(20)=1
9899 // else 32}'
9900 return RegisterList().
9901 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
9902 Add(Register(((inst.Bits() & 0x00100000) ==
9903 0x00100000
9904 ? 16
9905 : 32)));
9906 }
9907
9908 SafetyLevel RSC_immediate_cccc0010111snnnnddddiiiiiiiiiiii_case_0::
safety(Instruction inst) const9909 safety(Instruction inst) const {
9910 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9911
9912 // (inst(15:12)=1111 &&
9913 // inst(20)=1) => DECODER_ERROR
9914 if ((((inst.Bits() & 0x0000F000) ==
9915 0x0000F000) &&
9916 ((inst.Bits() & 0x00100000) ==
9917 0x00100000)))
9918 return DECODER_ERROR;
9919
9920 // inst(15:12)=1111 => FORBIDDEN_OPERANDS
9921 if ((inst.Bits() & 0x0000F000) ==
9922 0x0000F000)
9923 return FORBIDDEN_OPERANDS;
9924
9925 return MAY_BE_SAFE;
9926 }
9927
9928
9929 RegisterList RSC_immediate_cccc0010111snnnnddddiiiiiiiiiiii_case_0::
uses(Instruction inst) const9930 uses(Instruction inst) const {
9931 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9932 // uses: '{inst(19:16)}'
9933 return RegisterList().
9934 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
9935 }
9936
9937 // RSC_register_cccc0000111snnnnddddiiiiitt0mmmm_case_0:
9938 //
9939 // {NZCV: 16,
9940 // None: 32,
9941 // Rd: Rd(15:12),
9942 // Rm: Rm(3:0),
9943 // Rn: Rn(19:16),
9944 // S: S(20),
9945 // cond: cond(31:28),
9946 // defs: {Rd, NZCV
9947 // if S
9948 // else None},
9949 // fields: [cond(31:28),
9950 // S(20),
9951 // Rn(19:16),
9952 // Rd(15:12),
9953 // imm5(11:7),
9954 // type(6:5),
9955 // Rm(3:0)],
9956 // imm5: imm5(11:7),
9957 // pattern: cccc0000111snnnnddddiiiiitt0mmmm,
9958 // rule: RSC_register,
9959 // safety: [(Rd(15:12)=1111 &&
9960 // S(20)=1) => DECODER_ERROR,
9961 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS],
9962 // shift: DecodeImmShift(type, imm5),
9963 // type: type(6:5),
9964 // uses: {Rn, Rm}}
9965 RegisterList RSC_register_cccc0000111snnnnddddiiiiitt0mmmm_case_0::
defs(Instruction inst) const9966 defs(Instruction inst) const {
9967 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9968 // defs: '{inst(15:12), 16
9969 // if inst(20)
9970 // else 32}'
9971 return RegisterList().
9972 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
9973 Add(Register(((((inst.Bits() & 0x00100000) >> 20) != 0)
9974 ? 16
9975 : 32)));
9976 }
9977
9978 SafetyLevel RSC_register_cccc0000111snnnnddddiiiiitt0mmmm_case_0::
safety(Instruction inst) const9979 safety(Instruction inst) const {
9980 UNREFERENCED_PARAMETER(inst); // To silence compiler.
9981
9982 // (inst(15:12)=1111 &&
9983 // inst(20)=1) => DECODER_ERROR
9984 if ((((inst.Bits() & 0x0000F000) ==
9985 0x0000F000) &&
9986 ((inst.Bits() & 0x00100000) ==
9987 0x00100000)))
9988 return DECODER_ERROR;
9989
9990 // inst(15:12)=1111 => FORBIDDEN_OPERANDS
9991 if ((inst.Bits() & 0x0000F000) ==
9992 0x0000F000)
9993 return FORBIDDEN_OPERANDS;
9994
9995 return MAY_BE_SAFE;
9996 }
9997
9998
9999 RegisterList RSC_register_cccc0000111snnnnddddiiiiitt0mmmm_case_0::
uses(Instruction inst) const10000 uses(Instruction inst) const {
10001 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10002 // uses: '{inst(19:16), inst(3:0)}'
10003 return RegisterList().
10004 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
10005 Add(Register((inst.Bits() & 0x0000000F)));
10006 }
10007
10008 // RSC_register_shifted_register_cccc0000111snnnnddddssss0tt1mmmm_case_0:
10009 //
10010 // {NZCV: 16,
10011 // None: 32,
10012 // Pc: 15,
10013 // Rd: Rd(15:12),
10014 // Rm: Rm(3:0),
10015 // Rn: Rn(19:16),
10016 // Rs: Rs(11:8),
10017 // S: S(20),
10018 // cond: cond(31:28),
10019 // defs: {Rd, NZCV
10020 // if setflags
10021 // else None},
10022 // fields: [cond(31:28),
10023 // S(20),
10024 // Rn(19:16),
10025 // Rd(15:12),
10026 // Rs(11:8),
10027 // type(6:5),
10028 // Rm(3:0)],
10029 // pattern: cccc0000111snnnnddddssss0tt1mmmm,
10030 // rule: RSC_register_shifted_register,
10031 // safety: [Pc in {Rn, Rd, Rm, Rs} => UNPREDICTABLE],
10032 // setflags: S(20)=1,
10033 // shift_t: DecodeRegShift(type),
10034 // type: type(6:5),
10035 // uses: {Rn, Rm, Rs}}
10036 RegisterList RSC_register_shifted_register_cccc0000111snnnnddddssss0tt1mmmm_case_0::
defs(Instruction inst) const10037 defs(Instruction inst) const {
10038 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10039 // defs: '{inst(15:12), 16
10040 // if inst(20)=1
10041 // else 32}'
10042 return RegisterList().
10043 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
10044 Add(Register(((inst.Bits() & 0x00100000) ==
10045 0x00100000
10046 ? 16
10047 : 32)));
10048 }
10049
10050 SafetyLevel RSC_register_shifted_register_cccc0000111snnnnddddssss0tt1mmmm_case_0::
safety(Instruction inst) const10051 safety(Instruction inst) const {
10052 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10053
10054 // 15 ==
10055 // inst(19:16) ||
10056 // 15 ==
10057 // inst(15:12) ||
10058 // 15 ==
10059 // inst(3:0) ||
10060 // 15 ==
10061 // inst(11:8) => UNPREDICTABLE
10062 if ((((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
10063 (((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
10064 (((15) == ((inst.Bits() & 0x0000000F)))) ||
10065 (((15) == (((inst.Bits() & 0x00000F00) >> 8)))))
10066 return UNPREDICTABLE;
10067
10068 return MAY_BE_SAFE;
10069 }
10070
10071
10072 RegisterList RSC_register_shifted_register_cccc0000111snnnnddddssss0tt1mmmm_case_0::
uses(Instruction inst) const10073 uses(Instruction inst) const {
10074 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10075 // uses: '{inst(19:16), inst(3:0), inst(11:8)}'
10076 return RegisterList().
10077 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
10078 Add(Register((inst.Bits() & 0x0000000F))).
10079 Add(Register(((inst.Bits() & 0x00000F00) >> 8)));
10080 }
10081
10082 // SADD16_cccc01100001nnnndddd11110001mmmm_case_0:
10083 //
10084 // {Pc: 15,
10085 // Rd: Rd(15:12),
10086 // Rm: Rm(3:0),
10087 // Rn: Rn(19:16),
10088 // arch: v6,
10089 // cond: cond(31:28),
10090 // defs: {Rd},
10091 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)],
10092 // pattern: cccc01100001nnnndddd11110001mmmm,
10093 // rule: SADD16,
10094 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE],
10095 // uses: {Rn, Rm}}
10096 RegisterList SADD16_cccc01100001nnnndddd11110001mmmm_case_0::
defs(Instruction inst) const10097 defs(Instruction inst) const {
10098 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10099 // defs: '{inst(15:12)}'
10100 return RegisterList().
10101 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
10102 }
10103
10104 SafetyLevel SADD16_cccc01100001nnnndddd11110001mmmm_case_0::
safety(Instruction inst) const10105 safety(Instruction inst) const {
10106 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10107
10108 // 15 ==
10109 // inst(15:12) ||
10110 // 15 ==
10111 // inst(19:16) ||
10112 // 15 ==
10113 // inst(3:0) => UNPREDICTABLE
10114 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
10115 (((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
10116 (((15) == ((inst.Bits() & 0x0000000F)))))
10117 return UNPREDICTABLE;
10118
10119 return MAY_BE_SAFE;
10120 }
10121
10122
10123 RegisterList SADD16_cccc01100001nnnndddd11110001mmmm_case_0::
uses(Instruction inst) const10124 uses(Instruction inst) const {
10125 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10126 // uses: '{inst(19:16), inst(3:0)}'
10127 return RegisterList().
10128 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
10129 Add(Register((inst.Bits() & 0x0000000F)));
10130 }
10131
10132 // SADD8_cccc01100001nnnndddd11111001mmmm_case_0:
10133 //
10134 // {Pc: 15,
10135 // Rd: Rd(15:12),
10136 // Rm: Rm(3:0),
10137 // Rn: Rn(19:16),
10138 // arch: v6,
10139 // cond: cond(31:28),
10140 // defs: {Rd},
10141 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)],
10142 // pattern: cccc01100001nnnndddd11111001mmmm,
10143 // rule: SADD8,
10144 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE],
10145 // uses: {Rn, Rm}}
10146 RegisterList SADD8_cccc01100001nnnndddd11111001mmmm_case_0::
defs(Instruction inst) const10147 defs(Instruction inst) const {
10148 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10149 // defs: '{inst(15:12)}'
10150 return RegisterList().
10151 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
10152 }
10153
10154 SafetyLevel SADD8_cccc01100001nnnndddd11111001mmmm_case_0::
safety(Instruction inst) const10155 safety(Instruction inst) const {
10156 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10157
10158 // 15 ==
10159 // inst(15:12) ||
10160 // 15 ==
10161 // inst(19:16) ||
10162 // 15 ==
10163 // inst(3:0) => UNPREDICTABLE
10164 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
10165 (((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
10166 (((15) == ((inst.Bits() & 0x0000000F)))))
10167 return UNPREDICTABLE;
10168
10169 return MAY_BE_SAFE;
10170 }
10171
10172
10173 RegisterList SADD8_cccc01100001nnnndddd11111001mmmm_case_0::
uses(Instruction inst) const10174 uses(Instruction inst) const {
10175 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10176 // uses: '{inst(19:16), inst(3:0)}'
10177 return RegisterList().
10178 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
10179 Add(Register((inst.Bits() & 0x0000000F)));
10180 }
10181
10182 // SASX_cccc01100001nnnndddd11110011mmmm_case_0:
10183 //
10184 // {Pc: 15,
10185 // Rd: Rd(15:12),
10186 // Rm: Rm(3:0),
10187 // Rn: Rn(19:16),
10188 // arch: v6,
10189 // cond: cond(31:28),
10190 // defs: {Rd},
10191 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)],
10192 // pattern: cccc01100001nnnndddd11110011mmmm,
10193 // rule: SASX,
10194 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE],
10195 // uses: {Rn, Rm}}
10196 RegisterList SASX_cccc01100001nnnndddd11110011mmmm_case_0::
defs(Instruction inst) const10197 defs(Instruction inst) const {
10198 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10199 // defs: '{inst(15:12)}'
10200 return RegisterList().
10201 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
10202 }
10203
10204 SafetyLevel SASX_cccc01100001nnnndddd11110011mmmm_case_0::
safety(Instruction inst) const10205 safety(Instruction inst) const {
10206 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10207
10208 // 15 ==
10209 // inst(15:12) ||
10210 // 15 ==
10211 // inst(19:16) ||
10212 // 15 ==
10213 // inst(3:0) => UNPREDICTABLE
10214 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
10215 (((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
10216 (((15) == ((inst.Bits() & 0x0000000F)))))
10217 return UNPREDICTABLE;
10218
10219 return MAY_BE_SAFE;
10220 }
10221
10222
10223 RegisterList SASX_cccc01100001nnnndddd11110011mmmm_case_0::
uses(Instruction inst) const10224 uses(Instruction inst) const {
10225 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10226 // uses: '{inst(19:16), inst(3:0)}'
10227 return RegisterList().
10228 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
10229 Add(Register((inst.Bits() & 0x0000000F)));
10230 }
10231
10232 // SBC_immediate_cccc0010110snnnnddddiiiiiiiiiiii_case_0:
10233 //
10234 // {NZCV: 16,
10235 // None: 32,
10236 // Rd: Rd(15:12),
10237 // Rn: Rn(19:16),
10238 // S: S(20),
10239 // cond: cond(31:28),
10240 // defs: {Rd, NZCV
10241 // if setflags
10242 // else None},
10243 // fields: [cond(31:28), S(20), Rn(19:16), Rd(15:12), imm12(11:0)],
10244 // imm12: imm12(11:0),
10245 // imm32: ARMExpandImm(imm12),
10246 // pattern: cccc0010110snnnnddddiiiiiiiiiiii,
10247 // rule: SBC_immediate,
10248 // safety: [(Rd(15:12)=1111 &&
10249 // S(20)=1) => DECODER_ERROR,
10250 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS],
10251 // setflags: S(20)=1,
10252 // uses: {Rn}}
10253 RegisterList SBC_immediate_cccc0010110snnnnddddiiiiiiiiiiii_case_0::
defs(Instruction inst) const10254 defs(Instruction inst) const {
10255 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10256 // defs: '{inst(15:12), 16
10257 // if inst(20)=1
10258 // else 32}'
10259 return RegisterList().
10260 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
10261 Add(Register(((inst.Bits() & 0x00100000) ==
10262 0x00100000
10263 ? 16
10264 : 32)));
10265 }
10266
10267 SafetyLevel SBC_immediate_cccc0010110snnnnddddiiiiiiiiiiii_case_0::
safety(Instruction inst) const10268 safety(Instruction inst) const {
10269 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10270
10271 // (inst(15:12)=1111 &&
10272 // inst(20)=1) => DECODER_ERROR
10273 if ((((inst.Bits() & 0x0000F000) ==
10274 0x0000F000) &&
10275 ((inst.Bits() & 0x00100000) ==
10276 0x00100000)))
10277 return DECODER_ERROR;
10278
10279 // inst(15:12)=1111 => FORBIDDEN_OPERANDS
10280 if ((inst.Bits() & 0x0000F000) ==
10281 0x0000F000)
10282 return FORBIDDEN_OPERANDS;
10283
10284 return MAY_BE_SAFE;
10285 }
10286
10287
10288 RegisterList SBC_immediate_cccc0010110snnnnddddiiiiiiiiiiii_case_0::
uses(Instruction inst) const10289 uses(Instruction inst) const {
10290 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10291 // uses: '{inst(19:16)}'
10292 return RegisterList().
10293 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
10294 }
10295
10296 // SBC_register_cccc0000110snnnnddddiiiiitt0mmmm_case_0:
10297 //
10298 // {NZCV: 16,
10299 // None: 32,
10300 // Rd: Rd(15:12),
10301 // Rm: Rm(3:0),
10302 // Rn: Rn(19:16),
10303 // S: S(20),
10304 // cond: cond(31:28),
10305 // defs: {Rd, NZCV
10306 // if S
10307 // else None},
10308 // fields: [cond(31:28),
10309 // S(20),
10310 // Rn(19:16),
10311 // Rd(15:12),
10312 // imm5(11:7),
10313 // type(6:5),
10314 // Rm(3:0)],
10315 // imm5: imm5(11:7),
10316 // pattern: cccc0000110snnnnddddiiiiitt0mmmm,
10317 // rule: SBC_register,
10318 // safety: [(Rd(15:12)=1111 &&
10319 // S(20)=1) => DECODER_ERROR,
10320 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS],
10321 // shift: DecodeImmShift(type, imm5),
10322 // type: type(6:5),
10323 // uses: {Rn, Rm}}
10324 RegisterList SBC_register_cccc0000110snnnnddddiiiiitt0mmmm_case_0::
defs(Instruction inst) const10325 defs(Instruction inst) const {
10326 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10327 // defs: '{inst(15:12), 16
10328 // if inst(20)
10329 // else 32}'
10330 return RegisterList().
10331 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
10332 Add(Register(((((inst.Bits() & 0x00100000) >> 20) != 0)
10333 ? 16
10334 : 32)));
10335 }
10336
10337 SafetyLevel SBC_register_cccc0000110snnnnddddiiiiitt0mmmm_case_0::
safety(Instruction inst) const10338 safety(Instruction inst) const {
10339 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10340
10341 // (inst(15:12)=1111 &&
10342 // inst(20)=1) => DECODER_ERROR
10343 if ((((inst.Bits() & 0x0000F000) ==
10344 0x0000F000) &&
10345 ((inst.Bits() & 0x00100000) ==
10346 0x00100000)))
10347 return DECODER_ERROR;
10348
10349 // inst(15:12)=1111 => FORBIDDEN_OPERANDS
10350 if ((inst.Bits() & 0x0000F000) ==
10351 0x0000F000)
10352 return FORBIDDEN_OPERANDS;
10353
10354 return MAY_BE_SAFE;
10355 }
10356
10357
10358 RegisterList SBC_register_cccc0000110snnnnddddiiiiitt0mmmm_case_0::
uses(Instruction inst) const10359 uses(Instruction inst) const {
10360 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10361 // uses: '{inst(19:16), inst(3:0)}'
10362 return RegisterList().
10363 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
10364 Add(Register((inst.Bits() & 0x0000000F)));
10365 }
10366
10367 // SBC_register_shifted_register_cccc0000110snnnnddddssss0tt1mmmm_case_0:
10368 //
10369 // {NZCV: 16,
10370 // None: 32,
10371 // Pc: 15,
10372 // Rd: Rd(15:12),
10373 // Rm: Rm(3:0),
10374 // Rn: Rn(19:16),
10375 // Rs: Rs(11:8),
10376 // S: S(20),
10377 // cond: cond(31:28),
10378 // defs: {Rd, NZCV
10379 // if setflags
10380 // else None},
10381 // fields: [cond(31:28),
10382 // S(20),
10383 // Rn(19:16),
10384 // Rd(15:12),
10385 // Rs(11:8),
10386 // type(6:5),
10387 // Rm(3:0)],
10388 // pattern: cccc0000110snnnnddddssss0tt1mmmm,
10389 // rule: SBC_register_shifted_register,
10390 // safety: [Pc in {Rn, Rd, Rm, Rs} => UNPREDICTABLE],
10391 // setflags: S(20)=1,
10392 // shift_t: DecodeRegShift(type),
10393 // type: type(6:5),
10394 // uses: {Rn, Rm, Rs}}
10395 RegisterList SBC_register_shifted_register_cccc0000110snnnnddddssss0tt1mmmm_case_0::
defs(Instruction inst) const10396 defs(Instruction inst) const {
10397 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10398 // defs: '{inst(15:12), 16
10399 // if inst(20)=1
10400 // else 32}'
10401 return RegisterList().
10402 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
10403 Add(Register(((inst.Bits() & 0x00100000) ==
10404 0x00100000
10405 ? 16
10406 : 32)));
10407 }
10408
10409 SafetyLevel SBC_register_shifted_register_cccc0000110snnnnddddssss0tt1mmmm_case_0::
safety(Instruction inst) const10410 safety(Instruction inst) const {
10411 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10412
10413 // 15 ==
10414 // inst(19:16) ||
10415 // 15 ==
10416 // inst(15:12) ||
10417 // 15 ==
10418 // inst(3:0) ||
10419 // 15 ==
10420 // inst(11:8) => UNPREDICTABLE
10421 if ((((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
10422 (((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
10423 (((15) == ((inst.Bits() & 0x0000000F)))) ||
10424 (((15) == (((inst.Bits() & 0x00000F00) >> 8)))))
10425 return UNPREDICTABLE;
10426
10427 return MAY_BE_SAFE;
10428 }
10429
10430
10431 RegisterList SBC_register_shifted_register_cccc0000110snnnnddddssss0tt1mmmm_case_0::
uses(Instruction inst) const10432 uses(Instruction inst) const {
10433 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10434 // uses: '{inst(19:16), inst(3:0), inst(11:8)}'
10435 return RegisterList().
10436 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
10437 Add(Register((inst.Bits() & 0x0000000F))).
10438 Add(Register(((inst.Bits() & 0x00000F00) >> 8)));
10439 }
10440
10441 // SBFX_cccc0111101wwwwwddddlllll101nnnn_case_0:
10442 //
10443 // {Pc: 15,
10444 // Rd: Rd(15:12),
10445 // Rn: Rn(3:0),
10446 // arch: v6T2,
10447 // cond: cond(31:28),
10448 // defs: {Rd},
10449 // fields: [cond(31:28), widthm1(20:16), Rd(15:12), lsb(11:7), Rn(3:0)],
10450 // lsb: lsb(11:7),
10451 // pattern: cccc0111101wwwwwddddlllll101nnnn,
10452 // rule: SBFX,
10453 // safety: [Pc in {Rd, Rn} => UNPREDICTABLE,
10454 // lsb + widthm1 >
10455 // 31 => UNPREDICTABLE],
10456 // uses: {Rn},
10457 // widthm1: widthm1(20:16)}
10458 RegisterList SBFX_cccc0111101wwwwwddddlllll101nnnn_case_0::
defs(Instruction inst) const10459 defs(Instruction inst) const {
10460 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10461 // defs: '{inst(15:12)}'
10462 return RegisterList().
10463 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
10464 }
10465
10466 SafetyLevel SBFX_cccc0111101wwwwwddddlllll101nnnn_case_0::
safety(Instruction inst) const10467 safety(Instruction inst) const {
10468 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10469
10470 // 15 ==
10471 // inst(15:12) ||
10472 // 15 ==
10473 // inst(3:0) => UNPREDICTABLE
10474 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
10475 (((15) == ((inst.Bits() & 0x0000000F)))))
10476 return UNPREDICTABLE;
10477
10478 // 31 <=
10479 // inst(11:7) + inst(20:16) => UNPREDICTABLE
10480 if (((((inst.Bits() & 0x00000F80) >> 7) + ((inst.Bits() & 0x001F0000) >> 16)) > (31)))
10481 return UNPREDICTABLE;
10482
10483 return MAY_BE_SAFE;
10484 }
10485
10486
10487 RegisterList SBFX_cccc0111101wwwwwddddlllll101nnnn_case_0::
uses(Instruction inst) const10488 uses(Instruction inst) const {
10489 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10490 // uses: '{inst(3:0)}'
10491 return RegisterList().
10492 Add(Register((inst.Bits() & 0x0000000F)));
10493 }
10494
10495 // SDIV_cccc01110001dddd1111mmmm0001nnnn_case_0:
10496 //
10497 // {M: M(5),
10498 // Pc: 15,
10499 // Rd: Rd(19:16),
10500 // Rm: Rm(11:8),
10501 // Rn: Rn(3:0),
10502 // arch: v7VEoptv7A_v7R,
10503 // cond: cond(31:28),
10504 // defs: {Rd},
10505 // fields: [cond(31:28), Rd(19:16), Rm(11:8), M(5), Rn(3:0)],
10506 // pattern: cccc01110001dddd1111mmmm0001nnnn,
10507 // rule: SDIV,
10508 // safety: [Pc in {Rd, Rm, Rn} => UNPREDICTABLE],
10509 // uses: {Rm, Rn}}
10510 RegisterList SDIV_cccc01110001dddd1111mmmm0001nnnn_case_0::
defs(Instruction inst) const10511 defs(Instruction inst) const {
10512 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10513 // defs: '{inst(19:16)}'
10514 return RegisterList().
10515 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
10516 }
10517
10518 SafetyLevel SDIV_cccc01110001dddd1111mmmm0001nnnn_case_0::
safety(Instruction inst) const10519 safety(Instruction inst) const {
10520 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10521
10522 // 15 ==
10523 // inst(19:16) ||
10524 // 15 ==
10525 // inst(11:8) ||
10526 // 15 ==
10527 // inst(3:0) => UNPREDICTABLE
10528 if ((((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
10529 (((15) == (((inst.Bits() & 0x00000F00) >> 8)))) ||
10530 (((15) == ((inst.Bits() & 0x0000000F)))))
10531 return UNPREDICTABLE;
10532
10533 return MAY_BE_SAFE;
10534 }
10535
10536
10537 RegisterList SDIV_cccc01110001dddd1111mmmm0001nnnn_case_0::
uses(Instruction inst) const10538 uses(Instruction inst) const {
10539 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10540 // uses: '{inst(11:8), inst(3:0)}'
10541 return RegisterList().
10542 Add(Register(((inst.Bits() & 0x00000F00) >> 8))).
10543 Add(Register((inst.Bits() & 0x0000000F)));
10544 }
10545
10546 // SEL_cccc01101000nnnndddd11111011mmmm_case_0:
10547 //
10548 // {Pc: 15,
10549 // Rd: Rd(15:12),
10550 // Rm: Rm(3:0),
10551 // Rn: Rn(19:16),
10552 // arch: v6,
10553 // cond: cond(31:28),
10554 // defs: {Rd},
10555 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)],
10556 // pattern: cccc01101000nnnndddd11111011mmmm,
10557 // rule: SEL,
10558 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE],
10559 // uses: {Rn, Rm}}
10560 RegisterList SEL_cccc01101000nnnndddd11111011mmmm_case_0::
defs(Instruction inst) const10561 defs(Instruction inst) const {
10562 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10563 // defs: '{inst(15:12)}'
10564 return RegisterList().
10565 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
10566 }
10567
10568 SafetyLevel SEL_cccc01101000nnnndddd11111011mmmm_case_0::
safety(Instruction inst) const10569 safety(Instruction inst) const {
10570 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10571
10572 // 15 ==
10573 // inst(15:12) ||
10574 // 15 ==
10575 // inst(19:16) ||
10576 // 15 ==
10577 // inst(3:0) => UNPREDICTABLE
10578 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
10579 (((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
10580 (((15) == ((inst.Bits() & 0x0000000F)))))
10581 return UNPREDICTABLE;
10582
10583 return MAY_BE_SAFE;
10584 }
10585
10586
10587 RegisterList SEL_cccc01101000nnnndddd11111011mmmm_case_0::
uses(Instruction inst) const10588 uses(Instruction inst) const {
10589 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10590 // uses: '{inst(19:16), inst(3:0)}'
10591 return RegisterList().
10592 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
10593 Add(Register((inst.Bits() & 0x0000000F)));
10594 }
10595
10596 // SETEND_1111000100000001000000i000000000_case_0:
10597 //
10598 // {arch: v6,
10599 // defs: {},
10600 // pattern: 1111000100000001000000i000000000,
10601 // rule: SETEND,
10602 // safety: [true => FORBIDDEN],
10603 // true: true,
10604 // uses: {}}
10605 RegisterList SETEND_1111000100000001000000i000000000_case_0::
defs(Instruction inst) const10606 defs(Instruction inst) const {
10607 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10608 // defs: '{}'
10609 return RegisterList();
10610 }
10611
10612 SafetyLevel SETEND_1111000100000001000000i000000000_case_0::
safety(Instruction inst) const10613 safety(Instruction inst) const {
10614 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10615
10616 // true => FORBIDDEN
10617 if (true)
10618 return FORBIDDEN;
10619
10620 return MAY_BE_SAFE;
10621 }
10622
10623
10624 RegisterList SETEND_1111000100000001000000i000000000_case_0::
uses(Instruction inst) const10625 uses(Instruction inst) const {
10626 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10627 // uses: '{}'
10628 return RegisterList();
10629 }
10630
10631 // SEV_cccc0011001000001111000000000100_case_0:
10632 //
10633 // {arch: v6K,
10634 // defs: {},
10635 // pattern: cccc0011001000001111000000000100,
10636 // rule: SEV,
10637 // safety: [true => FORBIDDEN],
10638 // true: true,
10639 // uses: {}}
10640 RegisterList SEV_cccc0011001000001111000000000100_case_0::
defs(Instruction inst) const10641 defs(Instruction inst) const {
10642 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10643 // defs: '{}'
10644 return RegisterList();
10645 }
10646
10647 SafetyLevel SEV_cccc0011001000001111000000000100_case_0::
safety(Instruction inst) const10648 safety(Instruction inst) const {
10649 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10650
10651 // true => FORBIDDEN
10652 if (true)
10653 return FORBIDDEN;
10654
10655 return MAY_BE_SAFE;
10656 }
10657
10658
10659 RegisterList SEV_cccc0011001000001111000000000100_case_0::
uses(Instruction inst) const10660 uses(Instruction inst) const {
10661 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10662 // uses: '{}'
10663 return RegisterList();
10664 }
10665
10666 // SHADD16_cccc01100011nnnndddd11110001mmmm_case_0:
10667 //
10668 // {Pc: 15,
10669 // Rd: Rd(15:12),
10670 // Rm: Rm(3:0),
10671 // Rn: Rn(19:16),
10672 // arch: v6,
10673 // cond: cond(31:28),
10674 // defs: {Rd},
10675 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)],
10676 // pattern: cccc01100011nnnndddd11110001mmmm,
10677 // rule: SHADD16,
10678 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE],
10679 // uses: {Rn, Rm}}
10680 RegisterList SHADD16_cccc01100011nnnndddd11110001mmmm_case_0::
defs(Instruction inst) const10681 defs(Instruction inst) const {
10682 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10683 // defs: '{inst(15:12)}'
10684 return RegisterList().
10685 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
10686 }
10687
10688 SafetyLevel SHADD16_cccc01100011nnnndddd11110001mmmm_case_0::
safety(Instruction inst) const10689 safety(Instruction inst) const {
10690 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10691
10692 // 15 ==
10693 // inst(15:12) ||
10694 // 15 ==
10695 // inst(19:16) ||
10696 // 15 ==
10697 // inst(3:0) => UNPREDICTABLE
10698 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
10699 (((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
10700 (((15) == ((inst.Bits() & 0x0000000F)))))
10701 return UNPREDICTABLE;
10702
10703 return MAY_BE_SAFE;
10704 }
10705
10706
10707 RegisterList SHADD16_cccc01100011nnnndddd11110001mmmm_case_0::
uses(Instruction inst) const10708 uses(Instruction inst) const {
10709 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10710 // uses: '{inst(19:16), inst(3:0)}'
10711 return RegisterList().
10712 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
10713 Add(Register((inst.Bits() & 0x0000000F)));
10714 }
10715
10716 // SHADD8_cccc01100011nnnndddd11111001mmmm_case_0:
10717 //
10718 // {Pc: 15,
10719 // Rd: Rd(15:12),
10720 // Rm: Rm(3:0),
10721 // Rn: Rn(19:16),
10722 // arch: v6,
10723 // cond: cond(31:28),
10724 // defs: {Rd},
10725 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)],
10726 // pattern: cccc01100011nnnndddd11111001mmmm,
10727 // rule: SHADD8,
10728 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE],
10729 // uses: {Rn, Rm}}
10730 RegisterList SHADD8_cccc01100011nnnndddd11111001mmmm_case_0::
defs(Instruction inst) const10731 defs(Instruction inst) const {
10732 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10733 // defs: '{inst(15:12)}'
10734 return RegisterList().
10735 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
10736 }
10737
10738 SafetyLevel SHADD8_cccc01100011nnnndddd11111001mmmm_case_0::
safety(Instruction inst) const10739 safety(Instruction inst) const {
10740 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10741
10742 // 15 ==
10743 // inst(15:12) ||
10744 // 15 ==
10745 // inst(19:16) ||
10746 // 15 ==
10747 // inst(3:0) => UNPREDICTABLE
10748 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
10749 (((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
10750 (((15) == ((inst.Bits() & 0x0000000F)))))
10751 return UNPREDICTABLE;
10752
10753 return MAY_BE_SAFE;
10754 }
10755
10756
10757 RegisterList SHADD8_cccc01100011nnnndddd11111001mmmm_case_0::
uses(Instruction inst) const10758 uses(Instruction inst) const {
10759 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10760 // uses: '{inst(19:16), inst(3:0)}'
10761 return RegisterList().
10762 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
10763 Add(Register((inst.Bits() & 0x0000000F)));
10764 }
10765
10766 // SHASX_cccc01100011nnnndddd11110011mmmm_case_0:
10767 //
10768 // {Pc: 15,
10769 // Rd: Rd(15:12),
10770 // Rm: Rm(3:0),
10771 // Rn: Rn(19:16),
10772 // arch: v6,
10773 // cond: cond(31:28),
10774 // defs: {Rd},
10775 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)],
10776 // pattern: cccc01100011nnnndddd11110011mmmm,
10777 // rule: SHASX,
10778 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE],
10779 // uses: {Rn, Rm}}
10780 RegisterList SHASX_cccc01100011nnnndddd11110011mmmm_case_0::
defs(Instruction inst) const10781 defs(Instruction inst) const {
10782 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10783 // defs: '{inst(15:12)}'
10784 return RegisterList().
10785 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
10786 }
10787
10788 SafetyLevel SHASX_cccc01100011nnnndddd11110011mmmm_case_0::
safety(Instruction inst) const10789 safety(Instruction inst) const {
10790 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10791
10792 // 15 ==
10793 // inst(15:12) ||
10794 // 15 ==
10795 // inst(19:16) ||
10796 // 15 ==
10797 // inst(3:0) => UNPREDICTABLE
10798 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
10799 (((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
10800 (((15) == ((inst.Bits() & 0x0000000F)))))
10801 return UNPREDICTABLE;
10802
10803 return MAY_BE_SAFE;
10804 }
10805
10806
10807 RegisterList SHASX_cccc01100011nnnndddd11110011mmmm_case_0::
uses(Instruction inst) const10808 uses(Instruction inst) const {
10809 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10810 // uses: '{inst(19:16), inst(3:0)}'
10811 return RegisterList().
10812 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
10813 Add(Register((inst.Bits() & 0x0000000F)));
10814 }
10815
10816 // SHSAX_cccc01100011nnnndddd11110101mmmm_case_0:
10817 //
10818 // {Pc: 15,
10819 // Rd: Rd(15:12),
10820 // Rm: Rm(3:0),
10821 // Rn: Rn(19:16),
10822 // arch: v6,
10823 // cond: cond(31:28),
10824 // defs: {Rd},
10825 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)],
10826 // pattern: cccc01100011nnnndddd11110101mmmm,
10827 // rule: SHSAX,
10828 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE],
10829 // uses: {Rn, Rm}}
10830 RegisterList SHSAX_cccc01100011nnnndddd11110101mmmm_case_0::
defs(Instruction inst) const10831 defs(Instruction inst) const {
10832 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10833 // defs: '{inst(15:12)}'
10834 return RegisterList().
10835 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
10836 }
10837
10838 SafetyLevel SHSAX_cccc01100011nnnndddd11110101mmmm_case_0::
safety(Instruction inst) const10839 safety(Instruction inst) const {
10840 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10841
10842 // 15 ==
10843 // inst(15:12) ||
10844 // 15 ==
10845 // inst(19:16) ||
10846 // 15 ==
10847 // inst(3:0) => UNPREDICTABLE
10848 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
10849 (((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
10850 (((15) == ((inst.Bits() & 0x0000000F)))))
10851 return UNPREDICTABLE;
10852
10853 return MAY_BE_SAFE;
10854 }
10855
10856
10857 RegisterList SHSAX_cccc01100011nnnndddd11110101mmmm_case_0::
uses(Instruction inst) const10858 uses(Instruction inst) const {
10859 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10860 // uses: '{inst(19:16), inst(3:0)}'
10861 return RegisterList().
10862 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
10863 Add(Register((inst.Bits() & 0x0000000F)));
10864 }
10865
10866 // SHSUB16_cccc01100011nnnndddd11110111mmmm_case_0:
10867 //
10868 // {Pc: 15,
10869 // Rd: Rd(15:12),
10870 // Rm: Rm(3:0),
10871 // Rn: Rn(19:16),
10872 // arch: v6,
10873 // cond: cond(31:28),
10874 // defs: {Rd},
10875 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)],
10876 // pattern: cccc01100011nnnndddd11110111mmmm,
10877 // rule: SHSUB16,
10878 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE],
10879 // uses: {Rn, Rm}}
10880 RegisterList SHSUB16_cccc01100011nnnndddd11110111mmmm_case_0::
defs(Instruction inst) const10881 defs(Instruction inst) const {
10882 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10883 // defs: '{inst(15:12)}'
10884 return RegisterList().
10885 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
10886 }
10887
10888 SafetyLevel SHSUB16_cccc01100011nnnndddd11110111mmmm_case_0::
safety(Instruction inst) const10889 safety(Instruction inst) const {
10890 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10891
10892 // 15 ==
10893 // inst(15:12) ||
10894 // 15 ==
10895 // inst(19:16) ||
10896 // 15 ==
10897 // inst(3:0) => UNPREDICTABLE
10898 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
10899 (((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
10900 (((15) == ((inst.Bits() & 0x0000000F)))))
10901 return UNPREDICTABLE;
10902
10903 return MAY_BE_SAFE;
10904 }
10905
10906
10907 RegisterList SHSUB16_cccc01100011nnnndddd11110111mmmm_case_0::
uses(Instruction inst) const10908 uses(Instruction inst) const {
10909 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10910 // uses: '{inst(19:16), inst(3:0)}'
10911 return RegisterList().
10912 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
10913 Add(Register((inst.Bits() & 0x0000000F)));
10914 }
10915
10916 // SHSUB8_cccc01100011nnnndddd11111111mmmm_case_0:
10917 //
10918 // {Pc: 15,
10919 // Rd: Rd(15:12),
10920 // Rm: Rm(3:0),
10921 // Rn: Rn(19:16),
10922 // arch: v6,
10923 // cond: cond(31:28),
10924 // defs: {Rd},
10925 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)],
10926 // pattern: cccc01100011nnnndddd11111111mmmm,
10927 // rule: SHSUB8,
10928 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE],
10929 // uses: {Rn, Rm}}
10930 RegisterList SHSUB8_cccc01100011nnnndddd11111111mmmm_case_0::
defs(Instruction inst) const10931 defs(Instruction inst) const {
10932 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10933 // defs: '{inst(15:12)}'
10934 return RegisterList().
10935 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
10936 }
10937
10938 SafetyLevel SHSUB8_cccc01100011nnnndddd11111111mmmm_case_0::
safety(Instruction inst) const10939 safety(Instruction inst) const {
10940 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10941
10942 // 15 ==
10943 // inst(15:12) ||
10944 // 15 ==
10945 // inst(19:16) ||
10946 // 15 ==
10947 // inst(3:0) => UNPREDICTABLE
10948 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
10949 (((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
10950 (((15) == ((inst.Bits() & 0x0000000F)))))
10951 return UNPREDICTABLE;
10952
10953 return MAY_BE_SAFE;
10954 }
10955
10956
10957 RegisterList SHSUB8_cccc01100011nnnndddd11111111mmmm_case_0::
uses(Instruction inst) const10958 uses(Instruction inst) const {
10959 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10960 // uses: '{inst(19:16), inst(3:0)}'
10961 return RegisterList().
10962 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
10963 Add(Register((inst.Bits() & 0x0000000F)));
10964 }
10965
10966 // SMC_cccc000101100000000000000111iiii_case_0:
10967 //
10968 // {arch: SE,
10969 // defs: {},
10970 // pattern: cccc000101100000000000000111iiii,
10971 // rule: SMC,
10972 // safety: [true => FORBIDDEN],
10973 // true: true,
10974 // uses: {}}
10975 RegisterList SMC_cccc000101100000000000000111iiii_case_0::
defs(Instruction inst) const10976 defs(Instruction inst) const {
10977 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10978 // defs: '{}'
10979 return RegisterList();
10980 }
10981
10982 SafetyLevel SMC_cccc000101100000000000000111iiii_case_0::
safety(Instruction inst) const10983 safety(Instruction inst) const {
10984 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10985
10986 // true => FORBIDDEN
10987 if (true)
10988 return FORBIDDEN;
10989
10990 return MAY_BE_SAFE;
10991 }
10992
10993
10994 RegisterList SMC_cccc000101100000000000000111iiii_case_0::
uses(Instruction inst) const10995 uses(Instruction inst) const {
10996 UNREFERENCED_PARAMETER(inst); // To silence compiler.
10997 // uses: '{}'
10998 return RegisterList();
10999 }
11000
11001 // SMLABB_SMLABT_SMLATB_SMLATT_cccc00010000ddddaaaammmm1xx0nnnn_case_0:
11002 //
11003 // {M: M(6),
11004 // N: N(5),
11005 // Pc: 15,
11006 // Ra: Ra(15:12),
11007 // Rd: Rd(19:16),
11008 // Rm: Rm(11:8),
11009 // Rn: Rn(3:0),
11010 // arch: v5TE,
11011 // cond: cond(31:28),
11012 // defs: {Rd},
11013 // fields: [cond(31:28),
11014 // Rd(19:16),
11015 // Ra(15:12),
11016 // Rm(11:8),
11017 // M(6),
11018 // N(5),
11019 // Rn(3:0)],
11020 // m_high: M(6)=1,
11021 // n_high: N(5)=1,
11022 // pattern: cccc00010000ddddaaaammmm1xx0nnnn,
11023 // rule: SMLABB_SMLABT_SMLATB_SMLATT,
11024 // safety: [Pc in {Rd, Rn, Rm, Ra} => UNPREDICTABLE],
11025 // uses: {Rn, Rm, Ra}}
11026 RegisterList SMLABB_SMLABT_SMLATB_SMLATT_cccc00010000ddddaaaammmm1xx0nnnn_case_0::
defs(Instruction inst) const11027 defs(Instruction inst) const {
11028 UNREFERENCED_PARAMETER(inst); // To silence compiler.
11029 // defs: '{inst(19:16)}'
11030 return RegisterList().
11031 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
11032 }
11033
11034 SafetyLevel SMLABB_SMLABT_SMLATB_SMLATT_cccc00010000ddddaaaammmm1xx0nnnn_case_0::
safety(Instruction inst) const11035 safety(Instruction inst) const {
11036 UNREFERENCED_PARAMETER(inst); // To silence compiler.
11037
11038 // 15 ==
11039 // inst(19:16) ||
11040 // 15 ==
11041 // inst(3:0) ||
11042 // 15 ==
11043 // inst(11:8) ||
11044 // 15 ==
11045 // inst(15:12) => UNPREDICTABLE
11046 if ((((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
11047 (((15) == ((inst.Bits() & 0x0000000F)))) ||
11048 (((15) == (((inst.Bits() & 0x00000F00) >> 8)))) ||
11049 (((15) == (((inst.Bits() & 0x0000F000) >> 12)))))
11050 return UNPREDICTABLE;
11051
11052 return MAY_BE_SAFE;
11053 }
11054
11055
11056 RegisterList SMLABB_SMLABT_SMLATB_SMLATT_cccc00010000ddddaaaammmm1xx0nnnn_case_0::
uses(Instruction inst) const11057 uses(Instruction inst) const {
11058 UNREFERENCED_PARAMETER(inst); // To silence compiler.
11059 // uses: '{inst(3:0), inst(11:8), inst(15:12)}'
11060 return RegisterList().
11061 Add(Register((inst.Bits() & 0x0000000F))).
11062 Add(Register(((inst.Bits() & 0x00000F00) >> 8))).
11063 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
11064 }
11065
11066 // SMLAD_cccc01110000ddddaaaammmm00m1nnnn_case_0:
11067 //
11068 // {M: M(5),
11069 // Pc: 15,
11070 // Ra: Ra(15:12),
11071 // Rd: Rd(19:16),
11072 // Rm: Rm(11:8),
11073 // Rn: Rn(3:0),
11074 // arch: v6,
11075 // cond: cond(31:28),
11076 // defs: {Rd},
11077 // fields: [cond(31:28), Rd(19:16), Ra(15:12), Rm(11:8), M(5), Rn(3:0)],
11078 // pattern: cccc01110000ddddaaaammmm00m1nnnn,
11079 // rule: SMLAD,
11080 // safety: [Ra ==
11081 // Pc => DECODER_ERROR,
11082 // Pc in {Rd, Rn, Rm} => UNPREDICTABLE],
11083 // uses: {Rn, Rm, Ra}}
11084 RegisterList SMLAD_cccc01110000ddddaaaammmm00m1nnnn_case_0::
defs(Instruction inst) const11085 defs(Instruction inst) const {
11086 UNREFERENCED_PARAMETER(inst); // To silence compiler.
11087 // defs: '{inst(19:16)}'
11088 return RegisterList().
11089 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
11090 }
11091
11092 SafetyLevel SMLAD_cccc01110000ddddaaaammmm00m1nnnn_case_0::
safety(Instruction inst) const11093 safety(Instruction inst) const {
11094 UNREFERENCED_PARAMETER(inst); // To silence compiler.
11095
11096 // 15 ==
11097 // inst(15:12) => DECODER_ERROR
11098 if (((((inst.Bits() & 0x0000F000) >> 12)) == (15)))
11099 return DECODER_ERROR;
11100
11101 // 15 ==
11102 // inst(19:16) ||
11103 // 15 ==
11104 // inst(3:0) ||
11105 // 15 ==
11106 // inst(11:8) => UNPREDICTABLE
11107 if ((((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
11108 (((15) == ((inst.Bits() & 0x0000000F)))) ||
11109 (((15) == (((inst.Bits() & 0x00000F00) >> 8)))))
11110 return UNPREDICTABLE;
11111
11112 return MAY_BE_SAFE;
11113 }
11114
11115
11116 RegisterList SMLAD_cccc01110000ddddaaaammmm00m1nnnn_case_0::
uses(Instruction inst) const11117 uses(Instruction inst) const {
11118 UNREFERENCED_PARAMETER(inst); // To silence compiler.
11119 // uses: '{inst(3:0), inst(11:8), inst(15:12)}'
11120 return RegisterList().
11121 Add(Register((inst.Bits() & 0x0000000F))).
11122 Add(Register(((inst.Bits() & 0x00000F00) >> 8))).
11123 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
11124 }
11125
11126 // SMLALBB_SMLALBT_SMLALTB_SMLALTT_cccc00010100hhhhllllmmmm1xx0nnnn_case_0:
11127 //
11128 // {M: M(6),
11129 // N: N(5),
11130 // Pc: 15,
11131 // Rd: Rd(19:16),
11132 // RdHi: RdHi(19:16),
11133 // RdLo: RdLo(15:12),
11134 // Rm: Rm(11:8),
11135 // Rn: Rn(3:0),
11136 // arch: v5TE,
11137 // cond: cond(31:28),
11138 // defs: {RdLo, RdHi},
11139 // fields: [cond(31:28),
11140 // RdHi(19:16),
11141 // RdLo(15:12),
11142 // Rm(11:8),
11143 // M(6),
11144 // N(5),
11145 // Rn(3:0)],
11146 // m_high: M(6)=1,
11147 // n_high: N(5)=1,
11148 // pattern: cccc00010100hhhhllllmmmm1xx0nnnn,
11149 // rule: SMLALBB_SMLALBT_SMLALTB_SMLALTT,
11150 // safety: [Pc in {RdLo, RdHi, Rn, Rm} => UNPREDICTABLE,
11151 // RdHi ==
11152 // RdLo => UNPREDICTABLE],
11153 // uses: {RdLo, RdHi, Rn, Rm}}
11154 RegisterList SMLALBB_SMLALBT_SMLALTB_SMLALTT_cccc00010100hhhhllllmmmm1xx0nnnn_case_0::
defs(Instruction inst) const11155 defs(Instruction inst) const {
11156 UNREFERENCED_PARAMETER(inst); // To silence compiler.
11157 // defs: '{inst(15:12), inst(19:16)}'
11158 return RegisterList().
11159 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
11160 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
11161 }
11162
11163 SafetyLevel SMLALBB_SMLALBT_SMLALTB_SMLALTT_cccc00010100hhhhllllmmmm1xx0nnnn_case_0::
safety(Instruction inst) const11164 safety(Instruction inst) const {
11165 UNREFERENCED_PARAMETER(inst); // To silence compiler.
11166
11167 // 15 ==
11168 // inst(15:12) ||
11169 // 15 ==
11170 // inst(19:16) ||
11171 // 15 ==
11172 // inst(3:0) ||
11173 // 15 ==
11174 // inst(11:8) => UNPREDICTABLE
11175 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
11176 (((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
11177 (((15) == ((inst.Bits() & 0x0000000F)))) ||
11178 (((15) == (((inst.Bits() & 0x00000F00) >> 8)))))
11179 return UNPREDICTABLE;
11180
11181 // inst(15:12) ==
11182 // inst(19:16) => UNPREDICTABLE
11183 if (((((inst.Bits() & 0x000F0000) >> 16)) == (((inst.Bits() & 0x0000F000) >> 12))))
11184 return UNPREDICTABLE;
11185
11186 return MAY_BE_SAFE;
11187 }
11188
11189
11190 RegisterList SMLALBB_SMLALBT_SMLALTB_SMLALTT_cccc00010100hhhhllllmmmm1xx0nnnn_case_0::
uses(Instruction inst) const11191 uses(Instruction inst) const {
11192 UNREFERENCED_PARAMETER(inst); // To silence compiler.
11193 // uses: '{inst(15:12), inst(19:16), inst(3:0), inst(11:8)}'
11194 return RegisterList().
11195 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
11196 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
11197 Add(Register((inst.Bits() & 0x0000000F))).
11198 Add(Register(((inst.Bits() & 0x00000F00) >> 8)));
11199 }
11200
11201 // SMLALD_cccc01110100hhhhllllmmmm00m1nnnn_case_0:
11202 //
11203 // {M: M(5),
11204 // Pc: 15,
11205 // RdHi: RdHi(19:16),
11206 // RdLo: RdLo(15:12),
11207 // Rm: Rm(11:8),
11208 // Rn: Rn(3:0),
11209 // arch: v6,
11210 // cond: cond(31:28),
11211 // defs: {RdHi, RdLo},
11212 // fields: [cond(31:28),
11213 // RdHi(19:16),
11214 // RdLo(15:12),
11215 // Rm(11:8),
11216 // M(5),
11217 // Rn(3:0)],
11218 // pattern: cccc01110100hhhhllllmmmm00m1nnnn,
11219 // rule: SMLALD,
11220 // safety: [Pc in {RdHi, RdLo, Rn, Rm} => UNPREDICTABLE,
11221 // RdHi ==
11222 // RdLo => UNPREDICTABLE],
11223 // uses: {RdHi, RdLo, Rm, Rn}}
11224 RegisterList SMLALD_cccc01110100hhhhllllmmmm00m1nnnn_case_0::
defs(Instruction inst) const11225 defs(Instruction inst) const {
11226 UNREFERENCED_PARAMETER(inst); // To silence compiler.
11227 // defs: '{inst(19:16), inst(15:12)}'
11228 return RegisterList().
11229 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
11230 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
11231 }
11232
11233 SafetyLevel SMLALD_cccc01110100hhhhllllmmmm00m1nnnn_case_0::
safety(Instruction inst) const11234 safety(Instruction inst) const {
11235 UNREFERENCED_PARAMETER(inst); // To silence compiler.
11236
11237 // 15 ==
11238 // inst(19:16) ||
11239 // 15 ==
11240 // inst(15:12) ||
11241 // 15 ==
11242 // inst(3:0) ||
11243 // 15 ==
11244 // inst(11:8) => UNPREDICTABLE
11245 if ((((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
11246 (((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
11247 (((15) == ((inst.Bits() & 0x0000000F)))) ||
11248 (((15) == (((inst.Bits() & 0x00000F00) >> 8)))))
11249 return UNPREDICTABLE;
11250
11251 // inst(15:12) ==
11252 // inst(19:16) => UNPREDICTABLE
11253 if (((((inst.Bits() & 0x000F0000) >> 16)) == (((inst.Bits() & 0x0000F000) >> 12))))
11254 return UNPREDICTABLE;
11255
11256 return MAY_BE_SAFE;
11257 }
11258
11259
11260 RegisterList SMLALD_cccc01110100hhhhllllmmmm00m1nnnn_case_0::
uses(Instruction inst) const11261 uses(Instruction inst) const {
11262 UNREFERENCED_PARAMETER(inst); // To silence compiler.
11263 // uses: '{inst(19:16), inst(15:12), inst(11:8), inst(3:0)}'
11264 return RegisterList().
11265 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
11266 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
11267 Add(Register(((inst.Bits() & 0x00000F00) >> 8))).
11268 Add(Register((inst.Bits() & 0x0000000F)));
11269 }
11270
11271 // SMLAL_A1_cccc0000111shhhhllllmmmm1001nnnn_case_0:
11272 //
11273 // {NZCV: 16,
11274 // None: 32,
11275 // Pc: 15,
11276 // RdHi: RdHi(19:16),
11277 // RdLo: RdLo(15:12),
11278 // Rm: Rm(11:8),
11279 // Rn: Rn(3:0),
11280 // S: S(20),
11281 // cond: cond(31:28),
11282 // defs: {RdLo, RdHi, NZCV
11283 // if setflags
11284 // else None},
11285 // fields: [cond(31:28),
11286 // S(20),
11287 // RdHi(19:16),
11288 // RdLo(15:12),
11289 // Rm(11:8),
11290 // Rn(3:0)],
11291 // pattern: cccc0000111shhhhllllmmmm1001nnnn,
11292 // rule: SMLAL_A1,
11293 // safety: [Pc in {RdLo, RdHi, Rn, Rm} => UNPREDICTABLE,
11294 // RdHi ==
11295 // RdLo => UNPREDICTABLE,
11296 // (ArchVersion() <
11297 // 6 &&
11298 // (RdHi ==
11299 // Rn ||
11300 // RdLo ==
11301 // Rn)) => UNPREDICTABLE],
11302 // setflags: S(20)=1,
11303 // uses: {RdLo, RdHi, Rn, Rm}}
11304 RegisterList SMLAL_A1_cccc0000111shhhhllllmmmm1001nnnn_case_0::
defs(Instruction inst) const11305 defs(Instruction inst) const {
11306 UNREFERENCED_PARAMETER(inst); // To silence compiler.
11307 // defs: '{inst(15:12), inst(19:16), 16
11308 // if inst(20)=1
11309 // else 32}'
11310 return RegisterList().
11311 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
11312 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
11313 Add(Register(((inst.Bits() & 0x00100000) ==
11314 0x00100000
11315 ? 16
11316 : 32)));
11317 }
11318
11319 SafetyLevel SMLAL_A1_cccc0000111shhhhllllmmmm1001nnnn_case_0::
safety(Instruction inst) const11320 safety(Instruction inst) const {
11321 UNREFERENCED_PARAMETER(inst); // To silence compiler.
11322
11323 // 15 ==
11324 // inst(15:12) ||
11325 // 15 ==
11326 // inst(19:16) ||
11327 // 15 ==
11328 // inst(3:0) ||
11329 // 15 ==
11330 // inst(11:8) => UNPREDICTABLE
11331 if ((((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
11332 (((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
11333 (((15) == ((inst.Bits() & 0x0000000F)))) ||
11334 (((15) == (((inst.Bits() & 0x00000F00) >> 8)))))
11335 return UNPREDICTABLE;
11336
11337 // inst(15:12) ==
11338 // inst(19:16) => UNPREDICTABLE
11339 if (((((inst.Bits() & 0x000F0000) >> 16)) == (((inst.Bits() & 0x0000F000) >> 12))))
11340 return UNPREDICTABLE;
11341
11342 // (ArchVersion() <
11343 // 6 &&
11344 // (inst(19:16) ==
11345 // inst(3:0) ||
11346 // inst(15:12) ==
11347 // inst(3:0))) => UNPREDICTABLE
11348 if (((((nacl_arm_dec::ArchVersion()) < (6))) &&
11349 (((((((inst.Bits() & 0x000F0000) >> 16)) == ((inst.Bits() & 0x0000000F)))) ||
11350 (((((inst.Bits() & 0x0000F000) >> 12)) == ((inst.Bits() & 0x0000000F))))))))
11351 return UNPREDICTABLE;
11352
11353 return MAY_BE_SAFE;
11354 }
11355
11356
11357 RegisterList SMLAL_A1_cccc0000111shhhhllllmmmm1001nnnn_case_0::
uses(Instruction inst) const11358 uses(Instruction inst) const {
11359 UNREFERENCED_PARAMETER(inst); // To silence compiler.
11360 // uses: '{inst(15:12), inst(19:16), inst(3:0), inst(11:8)}'
11361 return RegisterList().
11362 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
11363 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
11364 Add(Register((inst.Bits() & 0x0000000F))).
11365 Add(Register(((inst.Bits() & 0x00000F00) >> 8)));
11366 }
11367
11368 // SMLAWB_SMLAWT_cccc00010010ddddaaaammmm1x00nnnn_case_0:
11369 //
11370 // {M: M(6),
11371 // N: N(5),
11372 // Pc: 15,
11373 // Ra: Ra(15:12),
11374 // Rd: Rd(19:16),
11375 // Rm: Rm(11:8),
11376 // Rn: Rn(3:0),
11377 // arch: v5TE,
11378 // cond: cond(31:28),
11379 // defs: {Rd},
11380 // fields: [cond(31:28),
11381 // Rd(19:16),
11382 // Ra(15:12),
11383 // Rm(11:8),
11384 // M(6),
11385 // N(5),
11386 // Rn(3:0)],
11387 // m_high: M(6)=1,
11388 // n_high: N(5)=1,
11389 // pattern: cccc00010010ddddaaaammmm1x00nnnn,
11390 // rule: SMLAWB_SMLAWT,
11391 // safety: [Pc in {Rd, Rn, Rm, Ra} => UNPREDICTABLE],
11392 // uses: {Rn, Rm, Ra}}
11393 RegisterList SMLAWB_SMLAWT_cccc00010010ddddaaaammmm1x00nnnn_case_0::
defs(Instruction inst) const11394 defs(Instruction inst) const {
11395 UNREFERENCED_PARAMETER(inst); // To silence compiler.
11396 // defs: '{inst(19:16)}'
11397 return RegisterList().
11398 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
11399 }
11400
11401 SafetyLevel SMLAWB_SMLAWT_cccc00010010ddddaaaammmm1x00nnnn_case_0::
safety(Instruction inst) const11402 safety(Instruction inst) const {
11403 UNREFERENCED_PARAMETER(inst); // To silence compiler.
11404
11405 // 15 ==
11406 // inst(19:16) ||
11407 // 15 ==
11408 // inst(3:0) ||
11409 // 15 ==
11410 // inst(11:8) ||
11411 // 15 ==
11412 // inst(15:12) => UNPREDICTABLE
11413 if ((((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
11414 (((15) == ((inst.Bits() & 0x0000000F)))) ||
11415 (((15) == (((inst.Bits() & 0x00000F00) >> 8)))) ||
11416 (((15) == (((inst.Bits() & 0x0000F000) >> 12)))))
11417 return UNPREDICTABLE;
11418
11419 return MAY_BE_SAFE;
11420 }
11421
11422
11423 RegisterList SMLAWB_SMLAWT_cccc00010010ddddaaaammmm1x00nnnn_case_0::
uses(Instruction inst) const11424 uses(Instruction inst) const {
11425 UNREFERENCED_PARAMETER(inst); // To silence compiler.
11426 // uses: '{inst(3:0), inst(11:8), inst(15:12)}'
11427 return RegisterList().
11428 Add(Register((inst.Bits() & 0x0000000F))).
11429 Add(Register(((inst.Bits() & 0x00000F00) >> 8))).
11430 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
11431 }
11432
11433 // SMLSD_cccc01110000ddddaaaammmm01m1nnnn_case_0:
11434 //
11435 // {M: M(5),
11436 // Pc: 15,
11437 // Ra: Ra(15:12),
11438 // Rd: Rd(19:16),
11439 // Rm: Rm(11:8),
11440 // Rn: Rn(3:0),
11441 // arch: v6,
11442 // cond: cond(31:28),
11443 // defs: {Rd},
11444 // fields: [cond(31:28), Rd(19:16), Ra(15:12), Rm(11:8), M(5), Rn(3:0)],
11445 // pattern: cccc01110000ddddaaaammmm01m1nnnn,
11446 // rule: SMLSD,
11447 // safety: [Ra ==
11448 // Pc => DECODER_ERROR,
11449 // Pc in {Rd, Rn, Rm} => UNPREDICTABLE],
11450 // uses: {Rn, Rm, Ra}}
11451 RegisterList SMLSD_cccc01110000ddddaaaammmm01m1nnnn_case_0::
defs(Instruction inst) const11452 defs(Instruction inst) const {
11453 UNREFERENCED_PARAMETER(inst); // To silence compiler.
11454 // defs: '{inst(19:16)}'
11455 return RegisterList().
11456 Add(Register(((inst.Bits() & 0x000F0000) >> 16)));
11457 }
11458
11459 SafetyLevel SMLSD_cccc01110000ddddaaaammmm01m1nnnn_case_0::
safety(Instruction inst) const11460 safety(Instruction inst) const {
11461 UNREFERENCED_PARAMETER(inst); // To silence compiler.
11462
11463 // 15 ==
11464 // inst(15:12) => DECODER_ERROR
11465 if (((((inst.Bits() & 0x0000F000) >> 12)) == (15)))
11466 return DECODER_ERROR;
11467
11468 // 15 ==
11469 // inst(19:16) ||
11470 // 15 ==
11471 // inst(3:0) ||
11472 // 15 ==
11473 // inst(11:8) => UNPREDICTABLE
11474 if ((((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
11475 (((15) == ((inst.Bits() & 0x0000000F)))) ||
11476 (((15) == (((inst.Bits() & 0x00000F00) >> 8)))))
11477 return UNPREDICTABLE;
11478
11479 return MAY_BE_SAFE;
11480 }
11481
11482
11483 RegisterList SMLSD_cccc01110000ddddaaaammmm01m1nnnn_case_0::
uses(Instruction inst) const11484 uses(Instruction inst) const {
11485 UNREFERENCED_PARAMETER(inst); // To silence compiler.
11486 // uses: '{inst(3:0), inst(11:8), inst(15:12)}'
11487 return RegisterList().
11488 Add(Register((inst.Bits() & 0x0000000F))).
11489 Add(Register(((inst.Bits() & 0x00000F00) >> 8))).
11490 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
11491 }
11492
11493 // SMLSLD_cccc01110100hhhhllllmmmm01m1nnnn_case_0:
11494 //
11495 // {M: M(5),
11496 // Pc: 15,
11497 // RdHi: RdHi(19:16),
11498 // RdLo: RdLo(15:12),
11499 // Rm: Rm(11:8),
11500 // Rn: Rn(3:0),
11501 // arch: v6,
11502 // cond: cond(31:28),
11503 // defs: {RdHi, RdLo},
11504 // fields: [cond(31:28),
11505 // RdHi(19:16),
11506 // RdLo(15:12),
11507 // Rm(11:8),
11508 // M(5),
11509 // Rn(3:0)],
11510 // pattern: cccc01110100hhhhllllmmmm01m1nnnn,
11511 // rule: SMLSLD,
11512 // safety: [Pc in {RdHi, RdLo, Rn, Rm} => UNPREDICTABLE,
11513 // RdHi ==
11514 // RdLo => UNPREDICTABLE],
11515 // uses: {RdHi, RdLo, Rm, Rn}}
11516 RegisterList SMLSLD_cccc01110100hhhhllllmmmm01m1nnnn_case_0::
defs(Instruction inst) const11517 defs(Instruction inst) const {
11518 UNREFERENCED_PARAMETER(inst); // To silence compiler.
11519 // defs: '{inst(19:16), inst(15:12)}'
11520 return RegisterList().
11521 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
11522 Add(Register(((inst.Bits() & 0x0000F000) >> 12)));
11523 }
11524
11525 SafetyLevel SMLSLD_cccc01110100hhhhllllmmmm01m1nnnn_case_0::
safety(Instruction inst) const11526 safety(Instruction inst) const {
11527 UNREFERENCED_PARAMETER(inst); // To silence compiler.
11528
11529 // 15 ==
11530 // inst(19:16) ||
11531 // 15 ==
11532 // inst(15:12) ||
11533 // 15 ==
11534 // inst(3:0) ||
11535 // 15 ==
11536 // inst(11:8) => UNPREDICTABLE
11537 if ((((15) == (((inst.Bits() & 0x000F0000) >> 16)))) ||
11538 (((15) == (((inst.Bits() & 0x0000F000) >> 12)))) ||
11539 (((15) == ((inst.Bits() & 0x0000000F)))) ||
11540 (((15) == (((inst.Bits() & 0x00000F00) >> 8)))))
11541 return UNPREDICTABLE;
11542
11543 // inst(15:12) ==
11544 // inst(19:16) => UNPREDICTABLE
11545 if (((((inst.Bits() & 0x000F0000) >> 16)) == (((inst.Bits() & 0x0000F000) >> 12))))
11546 return UNPREDICTABLE;
11547
11548 return MAY_BE_SAFE;
11549 }
11550
11551
11552 RegisterList SMLSLD_cccc01110100hhhhllllmmmm01m1nnnn_case_0::
uses(Instruction inst) const11553 uses(Instruction inst) const {
11554 UNREFERENCED_PARAMETER(inst); // To silence compiler.
11555 // uses: '{inst(19:16), inst(15:12), inst(11:8), inst(3:0)}'
11556 return RegisterList().
11557 Add(Register(((inst.Bits() & 0x000F0000) >> 16))).
11558 Add(Register(((inst.Bits() & 0x0000F000) >> 12))).
11559 Add(Register(((inst.Bits() & 0x00000F00) >> 8))).
11560 Add(Register((inst.Bits() & 0x0000000F)));
11561 }
11562
11563 } // namespace nacl_arm_dec
11564