1 // REQUIRES: aarch64-registered-target
2 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
3 // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
4 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -o - %s >/dev/null 2>%t
5 // RUN: FileCheck --check-prefix=ASM --allow-empty %s <%t
6
7 // If this check fails please read test/CodeGen/aarch64-sve-intrinsics/README for instructions on how to resolve it.
8 // ASM-NOT: warning
9 #include <arm_sve.h>
10
11 #ifdef SVE_OVERLOADED_FORMS
12 // A simple used,unused... macro, long enough to represent any SVE builtin.
13 #define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
14 #else
15 #define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
16 #endif
17
test_svasrd_n_s8_z(svbool_t pg,svint8_t op1)18 svint8_t test_svasrd_n_s8_z(svbool_t pg, svint8_t op1)
19 {
20 // CHECK-LABEL: test_svasrd_n_s8_z
21 // CHECK: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
22 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], i32 1)
23 // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
24 return SVE_ACLE_FUNC(svasrd,_n_s8,_z,)(pg, op1, 1);
25 }
26
test_svasrd_n_s8_z_1(svbool_t pg,svint8_t op1)27 svint8_t test_svasrd_n_s8_z_1(svbool_t pg, svint8_t op1)
28 {
29 // CHECK-LABEL: test_svasrd_n_s8_z_1
30 // CHECK: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
31 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], i32 8)
32 // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
33 return SVE_ACLE_FUNC(svasrd,_n_s8,_z,)(pg, op1, 8);
34 }
35
test_svasrd_n_s16_z(svbool_t pg,svint16_t op1)36 svint16_t test_svasrd_n_s16_z(svbool_t pg, svint16_t op1)
37 {
38 // CHECK-LABEL: test_svasrd_n_s16_z
39 // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
40 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
41 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], i32 1)
42 // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
43 return SVE_ACLE_FUNC(svasrd,_n_s16,_z,)(pg, op1, 1);
44 }
45
test_svasrd_n_s16_z_1(svbool_t pg,svint16_t op1)46 svint16_t test_svasrd_n_s16_z_1(svbool_t pg, svint16_t op1)
47 {
48 // CHECK-LABEL: test_svasrd_n_s16_z_1
49 // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
50 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
51 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], i32 16)
52 // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
53 return SVE_ACLE_FUNC(svasrd,_n_s16,_z,)(pg, op1, 16);
54 }
55
test_svasrd_n_s32_z(svbool_t pg,svint32_t op1)56 svint32_t test_svasrd_n_s32_z(svbool_t pg, svint32_t op1)
57 {
58 // CHECK-LABEL: test_svasrd_n_s32_z
59 // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
60 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
61 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], i32 1)
62 // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
63 return SVE_ACLE_FUNC(svasrd,_n_s32,_z,)(pg, op1, 1);
64 }
65
test_svasrd_n_s32_z_1(svbool_t pg,svint32_t op1)66 svint32_t test_svasrd_n_s32_z_1(svbool_t pg, svint32_t op1)
67 {
68 // CHECK-LABEL: test_svasrd_n_s32_z_1
69 // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
70 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
71 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], i32 32)
72 // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
73 return SVE_ACLE_FUNC(svasrd,_n_s32,_z,)(pg, op1, 32);
74 }
75
test_svasrd_n_s64_z(svbool_t pg,svint64_t op1)76 svint64_t test_svasrd_n_s64_z(svbool_t pg, svint64_t op1)
77 {
78 // CHECK-LABEL: test_svasrd_n_s64_z
79 // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
80 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
81 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], i32 1)
82 // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
83 return SVE_ACLE_FUNC(svasrd,_n_s64,_z,)(pg, op1, 1);
84 }
85
test_svasrd_n_s64_z_1(svbool_t pg,svint64_t op1)86 svint64_t test_svasrd_n_s64_z_1(svbool_t pg, svint64_t op1)
87 {
88 // CHECK-LABEL: test_svasrd_n_s64_z_1
89 // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
90 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
91 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], i32 64)
92 // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
93 return SVE_ACLE_FUNC(svasrd,_n_s64,_z,)(pg, op1, 64);
94 }
95
test_svasrd_n_s8_m(svbool_t pg,svint8_t op1)96 svint8_t test_svasrd_n_s8_m(svbool_t pg, svint8_t op1)
97 {
98 // CHECK-LABEL: test_svasrd_n_s8_m
99 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, i32 1)
100 // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
101 return SVE_ACLE_FUNC(svasrd,_n_s8,_m,)(pg, op1, 1);
102 }
103
test_svasrd_n_s16_m(svbool_t pg,svint16_t op1)104 svint16_t test_svasrd_n_s16_m(svbool_t pg, svint16_t op1)
105 {
106 // CHECK-LABEL: test_svasrd_n_s16_m
107 // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
108 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, i32 1)
109 // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
110 return SVE_ACLE_FUNC(svasrd,_n_s16,_m,)(pg, op1, 1);
111 }
112
test_svasrd_n_s32_m(svbool_t pg,svint32_t op1)113 svint32_t test_svasrd_n_s32_m(svbool_t pg, svint32_t op1)
114 {
115 // CHECK-LABEL: test_svasrd_n_s32_m
116 // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
117 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, i32 1)
118 // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
119 return SVE_ACLE_FUNC(svasrd,_n_s32,_m,)(pg, op1, 1);
120 }
121
test_svasrd_n_s64_m(svbool_t pg,svint64_t op1)122 svint64_t test_svasrd_n_s64_m(svbool_t pg, svint64_t op1)
123 {
124 // CHECK-LABEL: test_svasrd_n_s64_m
125 // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
126 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, i32 1)
127 // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
128 return SVE_ACLE_FUNC(svasrd,_n_s64,_m,)(pg, op1, 1);
129 }
130
test_svasrd_n_s8_x(svbool_t pg,svint8_t op1)131 svint8_t test_svasrd_n_s8_x(svbool_t pg, svint8_t op1)
132 {
133 // CHECK-LABEL: test_svasrd_n_s8_x
134 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, i32 8)
135 // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
136 return SVE_ACLE_FUNC(svasrd,_n_s8,_x,)(pg, op1, 8);
137 }
138
test_svasrd_n_s16_x(svbool_t pg,svint16_t op1)139 svint16_t test_svasrd_n_s16_x(svbool_t pg, svint16_t op1)
140 {
141 // CHECK-LABEL: test_svasrd_n_s16_x
142 // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
143 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, i32 16)
144 // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
145 return SVE_ACLE_FUNC(svasrd,_n_s16,_x,)(pg, op1, 16);
146 }
147
test_svasrd_n_s32_x(svbool_t pg,svint32_t op1)148 svint32_t test_svasrd_n_s32_x(svbool_t pg, svint32_t op1)
149 {
150 // CHECK-LABEL: test_svasrd_n_s32_x
151 // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
152 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, i32 32)
153 // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
154 return SVE_ACLE_FUNC(svasrd,_n_s32,_x,)(pg, op1, 32);
155 }
156
test_svasrd_n_s64_x(svbool_t pg,svint64_t op1)157 svint64_t test_svasrd_n_s64_x(svbool_t pg, svint64_t op1)
158 {
159 // CHECK-LABEL: test_svasrd_n_s64_x
160 // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
161 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, i32 64)
162 // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
163 return SVE_ACLE_FUNC(svasrd,_n_s64,_x,)(pg, op1, 64);
164 }
165