1 // REQUIRES: aarch64-registered-target
2 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
3 // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
4 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -o - %s >/dev/null 2>%t
5 // RUN: FileCheck --check-prefix=ASM --allow-empty %s <%t
6
7 // If this check fails please read test/CodeGen/aarch64-sve-intrinsics/README for instructions on how to resolve it.
8 // ASM-NOT: warning
9 #include <arm_sve.h>
10
11 #ifdef SVE_OVERLOADED_FORMS
12 // A simple used,unused... macro, long enough to represent any SVE builtin.
13 #define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
14 #else
15 #define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
16 #endif
17
test_svnmad_f16_z(svbool_t pg,svfloat16_t op1,svfloat16_t op2,svfloat16_t op3)18 svfloat16_t test_svnmad_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfloat16_t op3)
19 {
20 // CHECK-LABEL: test_svnmad_f16_z
21 // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
22 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.sel.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %op1, <vscale x 8 x half> zeroinitializer)
23 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fnmad.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %[[SEL]], <vscale x 8 x half> %op2, <vscale x 8 x half> %op3)
24 // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
25 return SVE_ACLE_FUNC(svnmad,_f16,_z,)(pg, op1, op2, op3);
26 }
27
test_svnmad_f32_z(svbool_t pg,svfloat32_t op1,svfloat32_t op2,svfloat32_t op3)28 svfloat32_t test_svnmad_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svfloat32_t op3)
29 {
30 // CHECK-LABEL: test_svnmad_f32_z
31 // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
32 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.sel.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op1, <vscale x 4 x float> zeroinitializer)
33 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fnmad.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %[[SEL]], <vscale x 4 x float> %op2, <vscale x 4 x float> %op3)
34 // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
35 return SVE_ACLE_FUNC(svnmad,_f32,_z,)(pg, op1, op2, op3);
36 }
37
test_svnmad_f64_z(svbool_t pg,svfloat64_t op1,svfloat64_t op2,svfloat64_t op3)38 svfloat64_t test_svnmad_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svfloat64_t op3)
39 {
40 // CHECK-LABEL: test_svnmad_f64_z
41 // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
42 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.sel.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op1, <vscale x 2 x double> zeroinitializer)
43 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fnmad.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %[[SEL]], <vscale x 2 x double> %op2, <vscale x 2 x double> %op3)
44 // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
45 return SVE_ACLE_FUNC(svnmad,_f64,_z,)(pg, op1, op2, op3);
46 }
47
test_svnmad_f16_m(svbool_t pg,svfloat16_t op1,svfloat16_t op2,svfloat16_t op3)48 svfloat16_t test_svnmad_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfloat16_t op3)
49 {
50 // CHECK-LABEL: test_svnmad_f16_m
51 // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
52 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fnmad.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3)
53 // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
54 return SVE_ACLE_FUNC(svnmad,_f16,_m,)(pg, op1, op2, op3);
55 }
56
test_svnmad_f32_m(svbool_t pg,svfloat32_t op1,svfloat32_t op2,svfloat32_t op3)57 svfloat32_t test_svnmad_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svfloat32_t op3)
58 {
59 // CHECK-LABEL: test_svnmad_f32_m
60 // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
61 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fnmad.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3)
62 // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
63 return SVE_ACLE_FUNC(svnmad,_f32,_m,)(pg, op1, op2, op3);
64 }
65
test_svnmad_f64_m(svbool_t pg,svfloat64_t op1,svfloat64_t op2,svfloat64_t op3)66 svfloat64_t test_svnmad_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svfloat64_t op3)
67 {
68 // CHECK-LABEL: test_svnmad_f64_m
69 // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
70 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fnmad.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3)
71 // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
72 return SVE_ACLE_FUNC(svnmad,_f64,_m,)(pg, op1, op2, op3);
73 }
74
test_svnmad_f16_x(svbool_t pg,svfloat16_t op1,svfloat16_t op2,svfloat16_t op3)75 svfloat16_t test_svnmad_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfloat16_t op3)
76 {
77 // CHECK-LABEL: test_svnmad_f16_x
78 // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
79 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fnmad.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3)
80 // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
81 return SVE_ACLE_FUNC(svnmad,_f16,_x,)(pg, op1, op2, op3);
82 }
83
test_svnmad_f32_x(svbool_t pg,svfloat32_t op1,svfloat32_t op2,svfloat32_t op3)84 svfloat32_t test_svnmad_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svfloat32_t op3)
85 {
86 // CHECK-LABEL: test_svnmad_f32_x
87 // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
88 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fnmad.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3)
89 // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
90 return SVE_ACLE_FUNC(svnmad,_f32,_x,)(pg, op1, op2, op3);
91 }
92
test_svnmad_f64_x(svbool_t pg,svfloat64_t op1,svfloat64_t op2,svfloat64_t op3)93 svfloat64_t test_svnmad_f64_x(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svfloat64_t op3)
94 {
95 // CHECK-LABEL: test_svnmad_f64_x
96 // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
97 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fnmad.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3)
98 // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
99 return SVE_ACLE_FUNC(svnmad,_f64,_x,)(pg, op1, op2, op3);
100 }
101
test_svnmad_n_f16_z(svbool_t pg,svfloat16_t op1,svfloat16_t op2,float16_t op3)102 svfloat16_t test_svnmad_n_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2, float16_t op3)
103 {
104 // CHECK-LABEL: test_svnmad_n_f16_z
105 // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
106 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half %op3)
107 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.sel.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %op1, <vscale x 8 x half> zeroinitializer)
108 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fnmad.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %[[SEL]], <vscale x 8 x half> %op2, <vscale x 8 x half> %[[DUP]])
109 // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
110 return SVE_ACLE_FUNC(svnmad,_n_f16,_z,)(pg, op1, op2, op3);
111 }
112
test_svnmad_n_f32_z(svbool_t pg,svfloat32_t op1,svfloat32_t op2,float32_t op3)113 svfloat32_t test_svnmad_n_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2, float32_t op3)
114 {
115 // CHECK-LABEL: test_svnmad_n_f32_z
116 // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
117 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float %op3)
118 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.sel.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op1, <vscale x 4 x float> zeroinitializer)
119 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fnmad.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %[[SEL]], <vscale x 4 x float> %op2, <vscale x 4 x float> %[[DUP]])
120 // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
121 return SVE_ACLE_FUNC(svnmad,_n_f32,_z,)(pg, op1, op2, op3);
122 }
123
test_svnmad_n_f64_z(svbool_t pg,svfloat64_t op1,svfloat64_t op2,float64_t op3)124 svfloat64_t test_svnmad_n_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2, float64_t op3)
125 {
126 // CHECK-LABEL: test_svnmad_n_f64_z
127 // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
128 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double %op3)
129 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.sel.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op1, <vscale x 2 x double> zeroinitializer)
130 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fnmad.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %[[SEL]], <vscale x 2 x double> %op2, <vscale x 2 x double> %[[DUP]])
131 // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
132 return SVE_ACLE_FUNC(svnmad,_n_f64,_z,)(pg, op1, op2, op3);
133 }
134
test_svnmad_n_f16_m(svbool_t pg,svfloat16_t op1,svfloat16_t op2,float16_t op3)135 svfloat16_t test_svnmad_n_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2, float16_t op3)
136 {
137 // CHECK-LABEL: test_svnmad_n_f16_m
138 // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
139 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half %op3)
140 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fnmad.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %[[DUP]])
141 // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
142 return SVE_ACLE_FUNC(svnmad,_n_f16,_m,)(pg, op1, op2, op3);
143 }
144
test_svnmad_n_f32_m(svbool_t pg,svfloat32_t op1,svfloat32_t op2,float32_t op3)145 svfloat32_t test_svnmad_n_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2, float32_t op3)
146 {
147 // CHECK-LABEL: test_svnmad_n_f32_m
148 // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
149 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float %op3)
150 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fnmad.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %[[DUP]])
151 // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
152 return SVE_ACLE_FUNC(svnmad,_n_f32,_m,)(pg, op1, op2, op3);
153 }
154
test_svnmad_n_f64_m(svbool_t pg,svfloat64_t op1,svfloat64_t op2,float64_t op3)155 svfloat64_t test_svnmad_n_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, float64_t op3)
156 {
157 // CHECK-LABEL: test_svnmad_n_f64_m
158 // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
159 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double %op3)
160 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fnmad.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %[[DUP]])
161 // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
162 return SVE_ACLE_FUNC(svnmad,_n_f64,_m,)(pg, op1, op2, op3);
163 }
164
test_svnmad_n_f16_x(svbool_t pg,svfloat16_t op1,svfloat16_t op2,float16_t op3)165 svfloat16_t test_svnmad_n_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2, float16_t op3)
166 {
167 // CHECK-LABEL: test_svnmad_n_f16_x
168 // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
169 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half %op3)
170 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fnmad.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %[[DUP]])
171 // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
172 return SVE_ACLE_FUNC(svnmad,_n_f16,_x,)(pg, op1, op2, op3);
173 }
174
test_svnmad_n_f32_x(svbool_t pg,svfloat32_t op1,svfloat32_t op2,float32_t op3)175 svfloat32_t test_svnmad_n_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2, float32_t op3)
176 {
177 // CHECK-LABEL: test_svnmad_n_f32_x
178 // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
179 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float %op3)
180 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fnmad.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %[[DUP]])
181 // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
182 return SVE_ACLE_FUNC(svnmad,_n_f32,_x,)(pg, op1, op2, op3);
183 }
184
test_svnmad_n_f64_x(svbool_t pg,svfloat64_t op1,svfloat64_t op2,float64_t op3)185 svfloat64_t test_svnmad_n_f64_x(svbool_t pg, svfloat64_t op1, svfloat64_t op2, float64_t op3)
186 {
187 // CHECK-LABEL: test_svnmad_n_f64_x
188 // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
189 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double %op3)
190 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fnmad.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %[[DUP]])
191 // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
192 return SVE_ACLE_FUNC(svnmad,_n_f64,_x,)(pg, op1, op2, op3);
193 }
194