1 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file Methods common to all machine operands.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "llvm/CodeGen/MachineOperand.h"
14 #include "llvm/ADT/FoldingSet.h"
15 #include "llvm/ADT/StringExtras.h"
16 #include "llvm/Analysis/Loads.h"
17 #include "llvm/Analysis/MemoryLocation.h"
18 #include "llvm/CodeGen/MIRFormatter.h"
19 #include "llvm/CodeGen/MIRPrinter.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineJumpTableInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/TargetInstrInfo.h"
24 #include "llvm/CodeGen/TargetRegisterInfo.h"
25 #include "llvm/Config/llvm-config.h"
26 #include "llvm/IR/Constants.h"
27 #include "llvm/IR/IRPrintingPasses.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/ModuleSlotTracker.h"
30 #include "llvm/MC/MCDwarf.h"
31 #include "llvm/Target/TargetIntrinsicInfo.h"
32 #include "llvm/Target/TargetMachine.h"
33
34 using namespace llvm;
35
36 static cl::opt<int>
37 PrintRegMaskNumRegs("print-regmask-num-regs",
38 cl::desc("Number of registers to limit to when "
39 "printing regmask operands in IR dumps. "
40 "unlimited = -1"),
41 cl::init(32), cl::Hidden);
42
getMFIfAvailable(const MachineOperand & MO)43 static const MachineFunction *getMFIfAvailable(const MachineOperand &MO) {
44 if (const MachineInstr *MI = MO.getParent())
45 if (const MachineBasicBlock *MBB = MI->getParent())
46 if (const MachineFunction *MF = MBB->getParent())
47 return MF;
48 return nullptr;
49 }
getMFIfAvailable(MachineOperand & MO)50 static MachineFunction *getMFIfAvailable(MachineOperand &MO) {
51 return const_cast<MachineFunction *>(
52 getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
53 }
54
setReg(Register Reg)55 void MachineOperand::setReg(Register Reg) {
56 if (getReg() == Reg)
57 return; // No change.
58
59 // Clear the IsRenamable bit to keep it conservatively correct.
60 IsRenamable = false;
61
62 // Otherwise, we have to change the register. If this operand is embedded
63 // into a machine function, we need to update the old and new register's
64 // use/def lists.
65 if (MachineFunction *MF = getMFIfAvailable(*this)) {
66 MachineRegisterInfo &MRI = MF->getRegInfo();
67 MRI.removeRegOperandFromUseList(this);
68 SmallContents.RegNo = Reg;
69 MRI.addRegOperandToUseList(this);
70 return;
71 }
72
73 // Otherwise, just change the register, no problem. :)
74 SmallContents.RegNo = Reg;
75 }
76
substVirtReg(Register Reg,unsigned SubIdx,const TargetRegisterInfo & TRI)77 void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx,
78 const TargetRegisterInfo &TRI) {
79 assert(Reg.isVirtual());
80 if (SubIdx && getSubReg())
81 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
82 setReg(Reg);
83 if (SubIdx)
84 setSubReg(SubIdx);
85 }
86
substPhysReg(MCRegister Reg,const TargetRegisterInfo & TRI)87 void MachineOperand::substPhysReg(MCRegister Reg, const TargetRegisterInfo &TRI) {
88 assert(Register::isPhysicalRegister(Reg));
89 if (getSubReg()) {
90 Reg = TRI.getSubReg(Reg, getSubReg());
91 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
92 // That won't happen in legal code.
93 setSubReg(0);
94 if (isDef())
95 setIsUndef(false);
96 }
97 setReg(Reg);
98 }
99
100 /// Change a def to a use, or a use to a def.
setIsDef(bool Val)101 void MachineOperand::setIsDef(bool Val) {
102 assert(isReg() && "Wrong MachineOperand accessor");
103 assert((!Val || !isDebug()) && "Marking a debug operation as def");
104 if (IsDef == Val)
105 return;
106 assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
107 // MRI may keep uses and defs in different list positions.
108 if (MachineFunction *MF = getMFIfAvailable(*this)) {
109 MachineRegisterInfo &MRI = MF->getRegInfo();
110 MRI.removeRegOperandFromUseList(this);
111 IsDef = Val;
112 MRI.addRegOperandToUseList(this);
113 return;
114 }
115 IsDef = Val;
116 }
117
isRenamable() const118 bool MachineOperand::isRenamable() const {
119 assert(isReg() && "Wrong MachineOperand accessor");
120 assert(Register::isPhysicalRegister(getReg()) &&
121 "isRenamable should only be checked on physical registers");
122 if (!IsRenamable)
123 return false;
124
125 const MachineInstr *MI = getParent();
126 if (!MI)
127 return true;
128
129 if (isDef())
130 return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
131
132 assert(isUse() && "Reg is not def or use");
133 return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
134 }
135
setIsRenamable(bool Val)136 void MachineOperand::setIsRenamable(bool Val) {
137 assert(isReg() && "Wrong MachineOperand accessor");
138 assert(Register::isPhysicalRegister(getReg()) &&
139 "setIsRenamable should only be called on physical registers");
140 IsRenamable = Val;
141 }
142
143 // If this operand is currently a register operand, and if this is in a
144 // function, deregister the operand from the register's use/def list.
removeRegFromUses()145 void MachineOperand::removeRegFromUses() {
146 if (!isReg() || !isOnRegUseList())
147 return;
148
149 if (MachineFunction *MF = getMFIfAvailable(*this))
150 MF->getRegInfo().removeRegOperandFromUseList(this);
151 }
152
153 /// ChangeToImmediate - Replace this operand with a new immediate operand of
154 /// the specified value. If an operand is known to be an immediate already,
155 /// the setImm method should be used.
ChangeToImmediate(int64_t ImmVal,unsigned TargetFlags)156 void MachineOperand::ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags) {
157 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
158
159 removeRegFromUses();
160
161 OpKind = MO_Immediate;
162 Contents.ImmVal = ImmVal;
163 setTargetFlags(TargetFlags);
164 }
165
ChangeToFPImmediate(const ConstantFP * FPImm,unsigned TargetFlags)166 void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm,
167 unsigned TargetFlags) {
168 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
169
170 removeRegFromUses();
171
172 OpKind = MO_FPImmediate;
173 Contents.CFP = FPImm;
174 setTargetFlags(TargetFlags);
175 }
176
ChangeToES(const char * SymName,unsigned TargetFlags)177 void MachineOperand::ChangeToES(const char *SymName,
178 unsigned TargetFlags) {
179 assert((!isReg() || !isTied()) &&
180 "Cannot change a tied operand into an external symbol");
181
182 removeRegFromUses();
183
184 OpKind = MO_ExternalSymbol;
185 Contents.OffsetedInfo.Val.SymbolName = SymName;
186 setOffset(0); // Offset is always 0.
187 setTargetFlags(TargetFlags);
188 }
189
ChangeToGA(const GlobalValue * GV,int64_t Offset,unsigned TargetFlags)190 void MachineOperand::ChangeToGA(const GlobalValue *GV, int64_t Offset,
191 unsigned TargetFlags) {
192 assert((!isReg() || !isTied()) &&
193 "Cannot change a tied operand into a global address");
194
195 removeRegFromUses();
196
197 OpKind = MO_GlobalAddress;
198 Contents.OffsetedInfo.Val.GV = GV;
199 setOffset(Offset);
200 setTargetFlags(TargetFlags);
201 }
202
ChangeToMCSymbol(MCSymbol * Sym,unsigned TargetFlags)203 void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags) {
204 assert((!isReg() || !isTied()) &&
205 "Cannot change a tied operand into an MCSymbol");
206
207 removeRegFromUses();
208
209 OpKind = MO_MCSymbol;
210 Contents.Sym = Sym;
211 setTargetFlags(TargetFlags);
212 }
213
ChangeToFrameIndex(int Idx,unsigned TargetFlags)214 void MachineOperand::ChangeToFrameIndex(int Idx, unsigned TargetFlags) {
215 assert((!isReg() || !isTied()) &&
216 "Cannot change a tied operand into a FrameIndex");
217
218 removeRegFromUses();
219
220 OpKind = MO_FrameIndex;
221 setIndex(Idx);
222 setTargetFlags(TargetFlags);
223 }
224
ChangeToTargetIndex(unsigned Idx,int64_t Offset,unsigned TargetFlags)225 void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
226 unsigned TargetFlags) {
227 assert((!isReg() || !isTied()) &&
228 "Cannot change a tied operand into a FrameIndex");
229
230 removeRegFromUses();
231
232 OpKind = MO_TargetIndex;
233 setIndex(Idx);
234 setOffset(Offset);
235 setTargetFlags(TargetFlags);
236 }
237
238 /// ChangeToRegister - Replace this operand with a new register operand of
239 /// the specified value. If an operand is known to be an register already,
240 /// the setReg method should be used.
ChangeToRegister(Register Reg,bool isDef,bool isImp,bool isKill,bool isDead,bool isUndef,bool isDebug)241 void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp,
242 bool isKill, bool isDead, bool isUndef,
243 bool isDebug) {
244 MachineRegisterInfo *RegInfo = nullptr;
245 if (MachineFunction *MF = getMFIfAvailable(*this))
246 RegInfo = &MF->getRegInfo();
247 // If this operand is already a register operand, remove it from the
248 // register's use/def lists.
249 bool WasReg = isReg();
250 if (RegInfo && WasReg)
251 RegInfo->removeRegOperandFromUseList(this);
252
253 // Change this to a register and set the reg#.
254 assert(!(isDead && !isDef) && "Dead flag on non-def");
255 assert(!(isKill && isDef) && "Kill flag on def");
256 OpKind = MO_Register;
257 SmallContents.RegNo = Reg;
258 SubReg_TargetFlags = 0;
259 IsDef = isDef;
260 IsImp = isImp;
261 IsDeadOrKill = isKill | isDead;
262 IsRenamable = false;
263 IsUndef = isUndef;
264 IsInternalRead = false;
265 IsEarlyClobber = false;
266 IsDebug = isDebug;
267 // Ensure isOnRegUseList() returns false.
268 Contents.Reg.Prev = nullptr;
269 // Preserve the tie when the operand was already a register.
270 if (!WasReg)
271 TiedTo = 0;
272
273 // If this operand is embedded in a function, add the operand to the
274 // register's use/def list.
275 if (RegInfo)
276 RegInfo->addRegOperandToUseList(this);
277 }
278
279 /// isIdenticalTo - Return true if this operand is identical to the specified
280 /// operand. Note that this should stay in sync with the hash_value overload
281 /// below.
isIdenticalTo(const MachineOperand & Other) const282 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
283 if (getType() != Other.getType() ||
284 getTargetFlags() != Other.getTargetFlags())
285 return false;
286
287 switch (getType()) {
288 case MachineOperand::MO_Register:
289 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
290 getSubReg() == Other.getSubReg();
291 case MachineOperand::MO_Immediate:
292 return getImm() == Other.getImm();
293 case MachineOperand::MO_CImmediate:
294 return getCImm() == Other.getCImm();
295 case MachineOperand::MO_FPImmediate:
296 return getFPImm() == Other.getFPImm();
297 case MachineOperand::MO_MachineBasicBlock:
298 return getMBB() == Other.getMBB();
299 case MachineOperand::MO_FrameIndex:
300 return getIndex() == Other.getIndex();
301 case MachineOperand::MO_ConstantPoolIndex:
302 case MachineOperand::MO_TargetIndex:
303 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
304 case MachineOperand::MO_JumpTableIndex:
305 return getIndex() == Other.getIndex();
306 case MachineOperand::MO_GlobalAddress:
307 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
308 case MachineOperand::MO_ExternalSymbol:
309 return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
310 getOffset() == Other.getOffset();
311 case MachineOperand::MO_BlockAddress:
312 return getBlockAddress() == Other.getBlockAddress() &&
313 getOffset() == Other.getOffset();
314 case MachineOperand::MO_RegisterMask:
315 case MachineOperand::MO_RegisterLiveOut: {
316 // Shallow compare of the two RegMasks
317 const uint32_t *RegMask = getRegMask();
318 const uint32_t *OtherRegMask = Other.getRegMask();
319 if (RegMask == OtherRegMask)
320 return true;
321
322 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
323 // Calculate the size of the RegMask
324 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
325 unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
326
327 // Deep compare of the two RegMasks
328 return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
329 }
330 // We don't know the size of the RegMask, so we can't deep compare the two
331 // reg masks.
332 return false;
333 }
334 case MachineOperand::MO_MCSymbol:
335 return getMCSymbol() == Other.getMCSymbol();
336 case MachineOperand::MO_CFIIndex:
337 return getCFIIndex() == Other.getCFIIndex();
338 case MachineOperand::MO_Metadata:
339 return getMetadata() == Other.getMetadata();
340 case MachineOperand::MO_IntrinsicID:
341 return getIntrinsicID() == Other.getIntrinsicID();
342 case MachineOperand::MO_Predicate:
343 return getPredicate() == Other.getPredicate();
344 case MachineOperand::MO_ShuffleMask:
345 return getShuffleMask() == Other.getShuffleMask();
346 }
347 llvm_unreachable("Invalid machine operand type");
348 }
349
350 // Note: this must stay exactly in sync with isIdenticalTo above.
hash_value(const MachineOperand & MO)351 hash_code llvm::hash_value(const MachineOperand &MO) {
352 switch (MO.getType()) {
353 case MachineOperand::MO_Register:
354 // Register operands don't have target flags.
355 return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef());
356 case MachineOperand::MO_Immediate:
357 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
358 case MachineOperand::MO_CImmediate:
359 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
360 case MachineOperand::MO_FPImmediate:
361 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
362 case MachineOperand::MO_MachineBasicBlock:
363 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
364 case MachineOperand::MO_FrameIndex:
365 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
366 case MachineOperand::MO_ConstantPoolIndex:
367 case MachineOperand::MO_TargetIndex:
368 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
369 MO.getOffset());
370 case MachineOperand::MO_JumpTableIndex:
371 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
372 case MachineOperand::MO_ExternalSymbol:
373 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
374 StringRef(MO.getSymbolName()));
375 case MachineOperand::MO_GlobalAddress:
376 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
377 MO.getOffset());
378 case MachineOperand::MO_BlockAddress:
379 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
380 MO.getOffset());
381 case MachineOperand::MO_RegisterMask:
382 case MachineOperand::MO_RegisterLiveOut:
383 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
384 case MachineOperand::MO_Metadata:
385 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
386 case MachineOperand::MO_MCSymbol:
387 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
388 case MachineOperand::MO_CFIIndex:
389 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
390 case MachineOperand::MO_IntrinsicID:
391 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
392 case MachineOperand::MO_Predicate:
393 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
394 case MachineOperand::MO_ShuffleMask:
395 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getShuffleMask());
396 }
397 llvm_unreachable("Invalid machine operand type");
398 }
399
400 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
401 // it.
tryToGetTargetInfo(const MachineOperand & MO,const TargetRegisterInfo * & TRI,const TargetIntrinsicInfo * & IntrinsicInfo)402 static void tryToGetTargetInfo(const MachineOperand &MO,
403 const TargetRegisterInfo *&TRI,
404 const TargetIntrinsicInfo *&IntrinsicInfo) {
405 if (const MachineFunction *MF = getMFIfAvailable(MO)) {
406 TRI = MF->getSubtarget().getRegisterInfo();
407 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
408 }
409 }
410
getTargetIndexName(const MachineFunction & MF,int Index)411 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
412 const auto *TII = MF.getSubtarget().getInstrInfo();
413 assert(TII && "expected instruction info");
414 auto Indices = TII->getSerializableTargetIndices();
415 auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
416 return I.first == Index;
417 });
418 if (Found != Indices.end())
419 return Found->second;
420 return nullptr;
421 }
422
getTargetIndexName() const423 const char *MachineOperand::getTargetIndexName() const {
424 const MachineFunction *MF = getMFIfAvailable(*this);
425 return MF ? ::getTargetIndexName(*MF, this->getIndex()) : nullptr;
426 }
427
getTargetFlagName(const TargetInstrInfo * TII,unsigned TF)428 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
429 auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
430 for (const auto &I : Flags) {
431 if (I.first == TF) {
432 return I.second;
433 }
434 }
435 return nullptr;
436 }
437
printCFIRegister(unsigned DwarfReg,raw_ostream & OS,const TargetRegisterInfo * TRI)438 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
439 const TargetRegisterInfo *TRI) {
440 if (!TRI) {
441 OS << "%dwarfreg." << DwarfReg;
442 return;
443 }
444
445 if (Optional<unsigned> Reg = TRI->getLLVMRegNum(DwarfReg, true))
446 OS << printReg(*Reg, TRI);
447 else
448 OS << "<badreg>";
449 }
450
printIRBlockReference(raw_ostream & OS,const BasicBlock & BB,ModuleSlotTracker & MST)451 static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB,
452 ModuleSlotTracker &MST) {
453 OS << "%ir-block.";
454 if (BB.hasName()) {
455 printLLVMNameWithoutPrefix(OS, BB.getName());
456 return;
457 }
458 Optional<int> Slot;
459 if (const Function *F = BB.getParent()) {
460 if (F == MST.getCurrentFunction()) {
461 Slot = MST.getLocalSlot(&BB);
462 } else if (const Module *M = F->getParent()) {
463 ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
464 CustomMST.incorporateFunction(*F);
465 Slot = CustomMST.getLocalSlot(&BB);
466 }
467 }
468 if (Slot)
469 MachineOperand::printIRSlotNumber(OS, *Slot);
470 else
471 OS << "<unknown>";
472 }
473
printSyncScope(raw_ostream & OS,const LLVMContext & Context,SyncScope::ID SSID,SmallVectorImpl<StringRef> & SSNs)474 static void printSyncScope(raw_ostream &OS, const LLVMContext &Context,
475 SyncScope::ID SSID,
476 SmallVectorImpl<StringRef> &SSNs) {
477 switch (SSID) {
478 case SyncScope::System:
479 break;
480 default:
481 if (SSNs.empty())
482 Context.getSyncScopeNames(SSNs);
483
484 OS << "syncscope(\"";
485 printEscapedString(SSNs[SSID], OS);
486 OS << "\") ";
487 break;
488 }
489 }
490
getTargetMMOFlagName(const TargetInstrInfo & TII,unsigned TMMOFlag)491 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
492 unsigned TMMOFlag) {
493 auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
494 for (const auto &I : Flags) {
495 if (I.first == TMMOFlag) {
496 return I.second;
497 }
498 }
499 return nullptr;
500 }
501
printFrameIndex(raw_ostream & OS,int FrameIndex,bool IsFixed,const MachineFrameInfo * MFI)502 static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
503 const MachineFrameInfo *MFI) {
504 StringRef Name;
505 if (MFI) {
506 IsFixed = MFI->isFixedObjectIndex(FrameIndex);
507 if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
508 if (Alloca->hasName())
509 Name = Alloca->getName();
510 if (IsFixed)
511 FrameIndex -= MFI->getObjectIndexBegin();
512 }
513 MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed, Name);
514 }
515
printSubRegIdx(raw_ostream & OS,uint64_t Index,const TargetRegisterInfo * TRI)516 void MachineOperand::printSubRegIdx(raw_ostream &OS, uint64_t Index,
517 const TargetRegisterInfo *TRI) {
518 OS << "%subreg.";
519 if (TRI)
520 OS << TRI->getSubRegIndexName(Index);
521 else
522 OS << Index;
523 }
524
printTargetFlags(raw_ostream & OS,const MachineOperand & Op)525 void MachineOperand::printTargetFlags(raw_ostream &OS,
526 const MachineOperand &Op) {
527 if (!Op.getTargetFlags())
528 return;
529 const MachineFunction *MF = getMFIfAvailable(Op);
530 if (!MF)
531 return;
532
533 const auto *TII = MF->getSubtarget().getInstrInfo();
534 assert(TII && "expected instruction info");
535 auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
536 OS << "target-flags(";
537 const bool HasDirectFlags = Flags.first;
538 const bool HasBitmaskFlags = Flags.second;
539 if (!HasDirectFlags && !HasBitmaskFlags) {
540 OS << "<unknown>) ";
541 return;
542 }
543 if (HasDirectFlags) {
544 if (const auto *Name = getTargetFlagName(TII, Flags.first))
545 OS << Name;
546 else
547 OS << "<unknown target flag>";
548 }
549 if (!HasBitmaskFlags) {
550 OS << ") ";
551 return;
552 }
553 bool IsCommaNeeded = HasDirectFlags;
554 unsigned BitMask = Flags.second;
555 auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
556 for (const auto &Mask : BitMasks) {
557 // Check if the flag's bitmask has the bits of the current mask set.
558 if ((BitMask & Mask.first) == Mask.first) {
559 if (IsCommaNeeded)
560 OS << ", ";
561 IsCommaNeeded = true;
562 OS << Mask.second;
563 // Clear the bits which were serialized from the flag's bitmask.
564 BitMask &= ~(Mask.first);
565 }
566 }
567 if (BitMask) {
568 // When the resulting flag's bitmask isn't zero, we know that we didn't
569 // serialize all of the bit flags.
570 if (IsCommaNeeded)
571 OS << ", ";
572 OS << "<unknown bitmask target flag>";
573 }
574 OS << ") ";
575 }
576
printSymbol(raw_ostream & OS,MCSymbol & Sym)577 void MachineOperand::printSymbol(raw_ostream &OS, MCSymbol &Sym) {
578 OS << "<mcsymbol " << Sym << ">";
579 }
580
printStackObjectReference(raw_ostream & OS,unsigned FrameIndex,bool IsFixed,StringRef Name)581 void MachineOperand::printStackObjectReference(raw_ostream &OS,
582 unsigned FrameIndex,
583 bool IsFixed, StringRef Name) {
584 if (IsFixed) {
585 OS << "%fixed-stack." << FrameIndex;
586 return;
587 }
588
589 OS << "%stack." << FrameIndex;
590 if (!Name.empty())
591 OS << '.' << Name;
592 }
593
printOperandOffset(raw_ostream & OS,int64_t Offset)594 void MachineOperand::printOperandOffset(raw_ostream &OS, int64_t Offset) {
595 if (Offset == 0)
596 return;
597 if (Offset < 0) {
598 OS << " - " << -Offset;
599 return;
600 }
601 OS << " + " << Offset;
602 }
603
printIRSlotNumber(raw_ostream & OS,int Slot)604 void MachineOperand::printIRSlotNumber(raw_ostream &OS, int Slot) {
605 if (Slot == -1)
606 OS << "<badref>";
607 else
608 OS << Slot;
609 }
610
printCFI(raw_ostream & OS,const MCCFIInstruction & CFI,const TargetRegisterInfo * TRI)611 static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
612 const TargetRegisterInfo *TRI) {
613 switch (CFI.getOperation()) {
614 case MCCFIInstruction::OpSameValue:
615 OS << "same_value ";
616 if (MCSymbol *Label = CFI.getLabel())
617 MachineOperand::printSymbol(OS, *Label);
618 printCFIRegister(CFI.getRegister(), OS, TRI);
619 break;
620 case MCCFIInstruction::OpRememberState:
621 OS << "remember_state ";
622 if (MCSymbol *Label = CFI.getLabel())
623 MachineOperand::printSymbol(OS, *Label);
624 break;
625 case MCCFIInstruction::OpRestoreState:
626 OS << "restore_state ";
627 if (MCSymbol *Label = CFI.getLabel())
628 MachineOperand::printSymbol(OS, *Label);
629 break;
630 case MCCFIInstruction::OpOffset:
631 OS << "offset ";
632 if (MCSymbol *Label = CFI.getLabel())
633 MachineOperand::printSymbol(OS, *Label);
634 printCFIRegister(CFI.getRegister(), OS, TRI);
635 OS << ", " << CFI.getOffset();
636 break;
637 case MCCFIInstruction::OpDefCfaRegister:
638 OS << "def_cfa_register ";
639 if (MCSymbol *Label = CFI.getLabel())
640 MachineOperand::printSymbol(OS, *Label);
641 printCFIRegister(CFI.getRegister(), OS, TRI);
642 break;
643 case MCCFIInstruction::OpDefCfaOffset:
644 OS << "def_cfa_offset ";
645 if (MCSymbol *Label = CFI.getLabel())
646 MachineOperand::printSymbol(OS, *Label);
647 OS << CFI.getOffset();
648 break;
649 case MCCFIInstruction::OpDefCfa:
650 OS << "def_cfa ";
651 if (MCSymbol *Label = CFI.getLabel())
652 MachineOperand::printSymbol(OS, *Label);
653 printCFIRegister(CFI.getRegister(), OS, TRI);
654 OS << ", " << CFI.getOffset();
655 break;
656 case MCCFIInstruction::OpRelOffset:
657 OS << "rel_offset ";
658 if (MCSymbol *Label = CFI.getLabel())
659 MachineOperand::printSymbol(OS, *Label);
660 printCFIRegister(CFI.getRegister(), OS, TRI);
661 OS << ", " << CFI.getOffset();
662 break;
663 case MCCFIInstruction::OpAdjustCfaOffset:
664 OS << "adjust_cfa_offset ";
665 if (MCSymbol *Label = CFI.getLabel())
666 MachineOperand::printSymbol(OS, *Label);
667 OS << CFI.getOffset();
668 break;
669 case MCCFIInstruction::OpRestore:
670 OS << "restore ";
671 if (MCSymbol *Label = CFI.getLabel())
672 MachineOperand::printSymbol(OS, *Label);
673 printCFIRegister(CFI.getRegister(), OS, TRI);
674 break;
675 case MCCFIInstruction::OpEscape: {
676 OS << "escape ";
677 if (MCSymbol *Label = CFI.getLabel())
678 MachineOperand::printSymbol(OS, *Label);
679 if (!CFI.getValues().empty()) {
680 size_t e = CFI.getValues().size() - 1;
681 for (size_t i = 0; i < e; ++i)
682 OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
683 OS << format("0x%02x", uint8_t(CFI.getValues()[e]));
684 }
685 break;
686 }
687 case MCCFIInstruction::OpUndefined:
688 OS << "undefined ";
689 if (MCSymbol *Label = CFI.getLabel())
690 MachineOperand::printSymbol(OS, *Label);
691 printCFIRegister(CFI.getRegister(), OS, TRI);
692 break;
693 case MCCFIInstruction::OpRegister:
694 OS << "register ";
695 if (MCSymbol *Label = CFI.getLabel())
696 MachineOperand::printSymbol(OS, *Label);
697 printCFIRegister(CFI.getRegister(), OS, TRI);
698 OS << ", ";
699 printCFIRegister(CFI.getRegister2(), OS, TRI);
700 break;
701 case MCCFIInstruction::OpWindowSave:
702 OS << "window_save ";
703 if (MCSymbol *Label = CFI.getLabel())
704 MachineOperand::printSymbol(OS, *Label);
705 break;
706 case MCCFIInstruction::OpNegateRAState:
707 OS << "negate_ra_sign_state ";
708 if (MCSymbol *Label = CFI.getLabel())
709 MachineOperand::printSymbol(OS, *Label);
710 break;
711 default:
712 // TODO: Print the other CFI Operations.
713 OS << "<unserializable cfi directive>";
714 break;
715 }
716 }
717
print(raw_ostream & OS,const TargetRegisterInfo * TRI,const TargetIntrinsicInfo * IntrinsicInfo) const718 void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
719 const TargetIntrinsicInfo *IntrinsicInfo) const {
720 print(OS, LLT{}, TRI, IntrinsicInfo);
721 }
722
print(raw_ostream & OS,LLT TypeToPrint,const TargetRegisterInfo * TRI,const TargetIntrinsicInfo * IntrinsicInfo) const723 void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
724 const TargetRegisterInfo *TRI,
725 const TargetIntrinsicInfo *IntrinsicInfo) const {
726 tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
727 ModuleSlotTracker DummyMST(nullptr);
728 print(OS, DummyMST, TypeToPrint, None, /*PrintDef=*/false,
729 /*IsStandalone=*/true,
730 /*ShouldPrintRegisterTies=*/true,
731 /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
732 }
733
print(raw_ostream & OS,ModuleSlotTracker & MST,LLT TypeToPrint,Optional<unsigned> OpIdx,bool PrintDef,bool IsStandalone,bool ShouldPrintRegisterTies,unsigned TiedOperandIdx,const TargetRegisterInfo * TRI,const TargetIntrinsicInfo * IntrinsicInfo) const734 void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
735 LLT TypeToPrint, Optional<unsigned> OpIdx, bool PrintDef,
736 bool IsStandalone, bool ShouldPrintRegisterTies,
737 unsigned TiedOperandIdx,
738 const TargetRegisterInfo *TRI,
739 const TargetIntrinsicInfo *IntrinsicInfo) const {
740 printTargetFlags(OS, *this);
741 switch (getType()) {
742 case MachineOperand::MO_Register: {
743 Register Reg = getReg();
744 if (isImplicit())
745 OS << (isDef() ? "implicit-def " : "implicit ");
746 else if (PrintDef && isDef())
747 // Print the 'def' flag only when the operand is defined after '='.
748 OS << "def ";
749 if (isInternalRead())
750 OS << "internal ";
751 if (isDead())
752 OS << "dead ";
753 if (isKill())
754 OS << "killed ";
755 if (isUndef())
756 OS << "undef ";
757 if (isEarlyClobber())
758 OS << "early-clobber ";
759 if (Register::isPhysicalRegister(getReg()) && isRenamable())
760 OS << "renamable ";
761 // isDebug() is exactly true for register operands of a DBG_VALUE. So we
762 // simply infer it when parsing and do not need to print it.
763
764 const MachineRegisterInfo *MRI = nullptr;
765 if (Register::isVirtualRegister(Reg)) {
766 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
767 MRI = &MF->getRegInfo();
768 }
769 }
770
771 OS << printReg(Reg, TRI, 0, MRI);
772 // Print the sub register.
773 if (unsigned SubReg = getSubReg()) {
774 if (TRI)
775 OS << '.' << TRI->getSubRegIndexName(SubReg);
776 else
777 OS << ".subreg" << SubReg;
778 }
779 // Print the register class / bank.
780 if (Register::isVirtualRegister(Reg)) {
781 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
782 const MachineRegisterInfo &MRI = MF->getRegInfo();
783 if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
784 OS << ':';
785 OS << printRegClassOrBank(Reg, MRI, TRI);
786 }
787 }
788 }
789 // Print ties.
790 if (ShouldPrintRegisterTies && isTied() && !isDef())
791 OS << "(tied-def " << TiedOperandIdx << ")";
792 // Print types.
793 if (TypeToPrint.isValid())
794 OS << '(' << TypeToPrint << ')';
795 break;
796 }
797 case MachineOperand::MO_Immediate: {
798 const MIRFormatter *Formatter = nullptr;
799 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
800 const auto *TII = MF->getSubtarget().getInstrInfo();
801 assert(TII && "expected instruction info");
802 Formatter = TII->getMIRFormatter();
803 }
804 if (Formatter)
805 Formatter->printImm(OS, *getParent(), OpIdx, getImm());
806 else
807 OS << getImm();
808 break;
809 }
810 case MachineOperand::MO_CImmediate:
811 getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
812 break;
813 case MachineOperand::MO_FPImmediate:
814 getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
815 break;
816 case MachineOperand::MO_MachineBasicBlock:
817 OS << printMBBReference(*getMBB());
818 break;
819 case MachineOperand::MO_FrameIndex: {
820 int FrameIndex = getIndex();
821 bool IsFixed = false;
822 const MachineFrameInfo *MFI = nullptr;
823 if (const MachineFunction *MF = getMFIfAvailable(*this))
824 MFI = &MF->getFrameInfo();
825 printFrameIndex(OS, FrameIndex, IsFixed, MFI);
826 break;
827 }
828 case MachineOperand::MO_ConstantPoolIndex:
829 OS << "%const." << getIndex();
830 printOperandOffset(OS, getOffset());
831 break;
832 case MachineOperand::MO_TargetIndex: {
833 OS << "target-index(";
834 const char *Name = "<unknown>";
835 if (const MachineFunction *MF = getMFIfAvailable(*this))
836 if (const auto *TargetIndexName = ::getTargetIndexName(*MF, getIndex()))
837 Name = TargetIndexName;
838 OS << Name << ')';
839 printOperandOffset(OS, getOffset());
840 break;
841 }
842 case MachineOperand::MO_JumpTableIndex:
843 OS << printJumpTableEntryReference(getIndex());
844 break;
845 case MachineOperand::MO_GlobalAddress:
846 getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
847 printOperandOffset(OS, getOffset());
848 break;
849 case MachineOperand::MO_ExternalSymbol: {
850 StringRef Name = getSymbolName();
851 OS << '&';
852 if (Name.empty()) {
853 OS << "\"\"";
854 } else {
855 printLLVMNameWithoutPrefix(OS, Name);
856 }
857 printOperandOffset(OS, getOffset());
858 break;
859 }
860 case MachineOperand::MO_BlockAddress: {
861 OS << "blockaddress(";
862 getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
863 MST);
864 OS << ", ";
865 printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
866 OS << ')';
867 MachineOperand::printOperandOffset(OS, getOffset());
868 break;
869 }
870 case MachineOperand::MO_RegisterMask: {
871 OS << "<regmask";
872 if (TRI) {
873 unsigned NumRegsInMask = 0;
874 unsigned NumRegsEmitted = 0;
875 for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
876 unsigned MaskWord = i / 32;
877 unsigned MaskBit = i % 32;
878 if (getRegMask()[MaskWord] & (1 << MaskBit)) {
879 if (PrintRegMaskNumRegs < 0 ||
880 NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
881 OS << " " << printReg(i, TRI);
882 NumRegsEmitted++;
883 }
884 NumRegsInMask++;
885 }
886 }
887 if (NumRegsEmitted != NumRegsInMask)
888 OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
889 } else {
890 OS << " ...";
891 }
892 OS << ">";
893 break;
894 }
895 case MachineOperand::MO_RegisterLiveOut: {
896 const uint32_t *RegMask = getRegLiveOut();
897 OS << "liveout(";
898 if (!TRI) {
899 OS << "<unknown>";
900 } else {
901 bool IsCommaNeeded = false;
902 for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
903 if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
904 if (IsCommaNeeded)
905 OS << ", ";
906 OS << printReg(Reg, TRI);
907 IsCommaNeeded = true;
908 }
909 }
910 }
911 OS << ")";
912 break;
913 }
914 case MachineOperand::MO_Metadata:
915 getMetadata()->printAsOperand(OS, MST);
916 break;
917 case MachineOperand::MO_MCSymbol:
918 printSymbol(OS, *getMCSymbol());
919 break;
920 case MachineOperand::MO_CFIIndex: {
921 if (const MachineFunction *MF = getMFIfAvailable(*this))
922 printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
923 else
924 OS << "<cfi directive>";
925 break;
926 }
927 case MachineOperand::MO_IntrinsicID: {
928 Intrinsic::ID ID = getIntrinsicID();
929 if (ID < Intrinsic::num_intrinsics)
930 OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
931 else if (IntrinsicInfo)
932 OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
933 else
934 OS << "intrinsic(" << ID << ')';
935 break;
936 }
937 case MachineOperand::MO_Predicate: {
938 auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
939 OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
940 << CmpInst::getPredicateName(Pred) << ')';
941 break;
942 }
943 case MachineOperand::MO_ShuffleMask:
944 OS << "shufflemask(";
945 ArrayRef<int> Mask = getShuffleMask();
946 StringRef Separator;
947 for (int Elt : Mask) {
948 if (Elt == -1)
949 OS << Separator << "undef";
950 else
951 OS << Separator << Elt;
952 Separator = ", ";
953 }
954
955 OS << ')';
956 break;
957 }
958 }
959
960 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
dump() const961 LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
962 #endif
963
964 //===----------------------------------------------------------------------===//
965 // MachineMemOperand Implementation
966 //===----------------------------------------------------------------------===//
967
968 /// getAddrSpace - Return the LLVM IR address space number that this pointer
969 /// points into.
getAddrSpace() const970 unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
971
972 /// isDereferenceable - Return true if V is always dereferenceable for
973 /// Offset + Size byte.
isDereferenceable(unsigned Size,LLVMContext & C,const DataLayout & DL) const974 bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C,
975 const DataLayout &DL) const {
976 if (!V.is<const Value *>())
977 return false;
978
979 const Value *BasePtr = V.get<const Value *>();
980 if (BasePtr == nullptr)
981 return false;
982
983 return isDereferenceableAndAlignedPointer(
984 BasePtr, Align(1), APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
985 }
986
987 /// getConstantPool - Return a MachinePointerInfo record that refers to the
988 /// constant pool.
getConstantPool(MachineFunction & MF)989 MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
990 return MachinePointerInfo(MF.getPSVManager().getConstantPool());
991 }
992
993 /// getFixedStack - Return a MachinePointerInfo record that refers to the
994 /// the specified FrameIndex.
getFixedStack(MachineFunction & MF,int FI,int64_t Offset)995 MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
996 int FI, int64_t Offset) {
997 return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
998 }
999
getJumpTable(MachineFunction & MF)1000 MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
1001 return MachinePointerInfo(MF.getPSVManager().getJumpTable());
1002 }
1003
getGOT(MachineFunction & MF)1004 MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
1005 return MachinePointerInfo(MF.getPSVManager().getGOT());
1006 }
1007
getStack(MachineFunction & MF,int64_t Offset,uint8_t ID)1008 MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
1009 int64_t Offset, uint8_t ID) {
1010 return MachinePointerInfo(MF.getPSVManager().getStack(), Offset, ID);
1011 }
1012
getUnknownStack(MachineFunction & MF)1013 MachinePointerInfo MachinePointerInfo::getUnknownStack(MachineFunction &MF) {
1014 return MachinePointerInfo(MF.getDataLayout().getAllocaAddrSpace());
1015 }
1016
MachineMemOperand(MachinePointerInfo ptrinfo,Flags f,uint64_t s,Align a,const AAMDNodes & AAInfo,const MDNode * Ranges,SyncScope::ID SSID,AtomicOrdering Ordering,AtomicOrdering FailureOrdering)1017 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
1018 uint64_t s, Align a,
1019 const AAMDNodes &AAInfo,
1020 const MDNode *Ranges, SyncScope::ID SSID,
1021 AtomicOrdering Ordering,
1022 AtomicOrdering FailureOrdering)
1023 : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlign(a), AAInfo(AAInfo),
1024 Ranges(Ranges) {
1025 assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
1026 isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
1027 "invalid pointer value");
1028 assert((isLoad() || isStore()) && "Not a load/store!");
1029
1030 AtomicInfo.SSID = static_cast<unsigned>(SSID);
1031 assert(getSyncScopeID() == SSID && "Value truncated");
1032 AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
1033 assert(getOrdering() == Ordering && "Value truncated");
1034 AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
1035 assert(getFailureOrdering() == FailureOrdering && "Value truncated");
1036 }
1037
1038 /// Profile - Gather unique data for the object.
1039 ///
Profile(FoldingSetNodeID & ID) const1040 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
1041 ID.AddInteger(getOffset());
1042 ID.AddInteger(Size);
1043 ID.AddPointer(getOpaqueValue());
1044 ID.AddInteger(getFlags());
1045 ID.AddInteger(getBaseAlign().value());
1046 }
1047
refineAlignment(const MachineMemOperand * MMO)1048 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
1049 // The Value and Offset may differ due to CSE. But the flags and size
1050 // should be the same.
1051 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1052 assert(MMO->getSize() == getSize() && "Size mismatch!");
1053
1054 if (MMO->getBaseAlign() >= getBaseAlign()) {
1055 // Update the alignment value.
1056 BaseAlign = MMO->getBaseAlign();
1057 // Also update the base and offset, because the new alignment may
1058 // not be applicable with the old ones.
1059 PtrInfo = MMO->PtrInfo;
1060 }
1061 }
1062
1063 /// getAlignment - Return the minimum known alignment in bytes of the
1064 /// actual memory reference.
getAlignment() const1065 uint64_t MachineMemOperand::getAlignment() const { return getAlign().value(); }
1066
1067 /// getAlign - Return the minimum known alignment in bytes of the
1068 /// actual memory reference.
getAlign() const1069 Align MachineMemOperand::getAlign() const {
1070 return commonAlignment(getBaseAlign(), getOffset());
1071 }
1072
print(raw_ostream & OS,ModuleSlotTracker & MST,SmallVectorImpl<StringRef> & SSNs,const LLVMContext & Context,const MachineFrameInfo * MFI,const TargetInstrInfo * TII) const1073 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
1074 SmallVectorImpl<StringRef> &SSNs,
1075 const LLVMContext &Context,
1076 const MachineFrameInfo *MFI,
1077 const TargetInstrInfo *TII) const {
1078 OS << '(';
1079 if (isVolatile())
1080 OS << "volatile ";
1081 if (isNonTemporal())
1082 OS << "non-temporal ";
1083 if (isDereferenceable())
1084 OS << "dereferenceable ";
1085 if (isInvariant())
1086 OS << "invariant ";
1087 if (getFlags() & MachineMemOperand::MOTargetFlag1)
1088 OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag1)
1089 << "\" ";
1090 if (getFlags() & MachineMemOperand::MOTargetFlag2)
1091 OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag2)
1092 << "\" ";
1093 if (getFlags() & MachineMemOperand::MOTargetFlag3)
1094 OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag3)
1095 << "\" ";
1096
1097 assert((isLoad() || isStore()) &&
1098 "machine memory operand must be a load or store (or both)");
1099 if (isLoad())
1100 OS << "load ";
1101 if (isStore())
1102 OS << "store ";
1103
1104 printSyncScope(OS, Context, getSyncScopeID(), SSNs);
1105
1106 if (getOrdering() != AtomicOrdering::NotAtomic)
1107 OS << toIRString(getOrdering()) << ' ';
1108 if (getFailureOrdering() != AtomicOrdering::NotAtomic)
1109 OS << toIRString(getFailureOrdering()) << ' ';
1110
1111 if (getSize() == MemoryLocation::UnknownSize)
1112 OS << "unknown-size";
1113 else
1114 OS << getSize();
1115
1116 if (const Value *Val = getValue()) {
1117 OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1118 MIRFormatter::printIRValue(OS, *Val, MST);
1119 } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1120 OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1121 assert(PVal && "Expected a pseudo source value");
1122 switch (PVal->kind()) {
1123 case PseudoSourceValue::Stack:
1124 OS << "stack";
1125 break;
1126 case PseudoSourceValue::GOT:
1127 OS << "got";
1128 break;
1129 case PseudoSourceValue::JumpTable:
1130 OS << "jump-table";
1131 break;
1132 case PseudoSourceValue::ConstantPool:
1133 OS << "constant-pool";
1134 break;
1135 case PseudoSourceValue::FixedStack: {
1136 int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1137 bool IsFixed = true;
1138 printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1139 break;
1140 }
1141 case PseudoSourceValue::GlobalValueCallEntry:
1142 OS << "call-entry ";
1143 cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1144 OS, /*PrintType=*/false, MST);
1145 break;
1146 case PseudoSourceValue::ExternalSymbolCallEntry:
1147 OS << "call-entry &";
1148 printLLVMNameWithoutPrefix(
1149 OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1150 break;
1151 default: {
1152 const MIRFormatter *Formatter = TII->getMIRFormatter();
1153 // FIXME: This is not necessarily the correct MIR serialization format for
1154 // a custom pseudo source value, but at least it allows
1155 // MIR printing to work on a target with custom pseudo source
1156 // values.
1157 OS << "custom \"";
1158 Formatter->printCustomPseudoSourceValue(OS, MST, *PVal);
1159 OS << '\"';
1160 break;
1161 }
1162 }
1163 }
1164 MachineOperand::printOperandOffset(OS, getOffset());
1165 if (getBaseAlign() != getSize())
1166 OS << ", align " << getBaseAlign().value();
1167 auto AAInfo = getAAInfo();
1168 if (AAInfo.TBAA) {
1169 OS << ", !tbaa ";
1170 AAInfo.TBAA->printAsOperand(OS, MST);
1171 }
1172 if (AAInfo.Scope) {
1173 OS << ", !alias.scope ";
1174 AAInfo.Scope->printAsOperand(OS, MST);
1175 }
1176 if (AAInfo.NoAlias) {
1177 OS << ", !noalias ";
1178 AAInfo.NoAlias->printAsOperand(OS, MST);
1179 }
1180 if (getRanges()) {
1181 OS << ", !range ";
1182 getRanges()->printAsOperand(OS, MST);
1183 }
1184 // FIXME: Implement addrspace printing/parsing in MIR.
1185 // For now, print this even though parsing it is not available in MIR.
1186 if (unsigned AS = getAddrSpace())
1187 OS << ", addrspace " << AS;
1188
1189 OS << ')';
1190 }
1191