1//===-- RISCVInstrInfo.td - Target Description for RISCV ---*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the RISC-V instructions in TableGen format. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// RISC-V specific DAG Nodes. 15//===----------------------------------------------------------------------===// 16 17// Target-independent type requirements, but with target-specific formats. 18def SDT_CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>, 19 SDTCisVT<1, i32>]>; 20def SDT_CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, 21 SDTCisVT<1, i32>]>; 22 23// Target-dependent type requirements. 24def SDT_RISCVCall : SDTypeProfile<0, -1, [SDTCisVT<0, XLenVT>]>; 25def SDT_RISCVSelectCC : SDTypeProfile<1, 5, [SDTCisSameAs<1, 2>, 26 SDTCisSameAs<0, 4>, 27 SDTCisSameAs<4, 5>]>; 28 29// Target-independent nodes, but with target-specific formats. 30def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart, 31 [SDNPHasChain, SDNPOutGlue]>; 32def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_CallSeqEnd, 33 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 34 35// Target-dependent nodes. 36def riscv_call : SDNode<"RISCVISD::CALL", SDT_RISCVCall, 37 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 38 SDNPVariadic]>; 39def riscv_ret_flag : SDNode<"RISCVISD::RET_FLAG", SDTNone, 40 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 41def riscv_uret_flag : SDNode<"RISCVISD::URET_FLAG", SDTNone, 42 [SDNPHasChain, SDNPOptInGlue]>; 43def riscv_sret_flag : SDNode<"RISCVISD::SRET_FLAG", SDTNone, 44 [SDNPHasChain, SDNPOptInGlue]>; 45def riscv_mret_flag : SDNode<"RISCVISD::MRET_FLAG", SDTNone, 46 [SDNPHasChain, SDNPOptInGlue]>; 47def riscv_selectcc : SDNode<"RISCVISD::SELECT_CC", SDT_RISCVSelectCC, 48 [SDNPInGlue]>; 49def riscv_tail : SDNode<"RISCVISD::TAIL", SDT_RISCVCall, 50 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 51 SDNPVariadic]>; 52def riscv_sllw : SDNode<"RISCVISD::SLLW", SDTIntShiftOp>; 53def riscv_sraw : SDNode<"RISCVISD::SRAW", SDTIntShiftOp>; 54def riscv_srlw : SDNode<"RISCVISD::SRLW", SDTIntShiftOp>; 55 56//===----------------------------------------------------------------------===// 57// Operand and SDNode transformation definitions. 58//===----------------------------------------------------------------------===// 59 60class ImmXLenAsmOperand<string prefix, string suffix = ""> : AsmOperandClass { 61 let Name = prefix # "ImmXLen" # suffix; 62 let RenderMethod = "addImmOperands"; 63 let DiagnosticType = !strconcat("Invalid", Name); 64} 65 66class ImmAsmOperand<string prefix, int width, string suffix> : AsmOperandClass { 67 let Name = prefix # "Imm" # width # suffix; 68 let RenderMethod = "addImmOperands"; 69 let DiagnosticType = !strconcat("Invalid", Name); 70} 71 72def ImmZeroAsmOperand : AsmOperandClass { 73 let Name = "ImmZero"; 74 let RenderMethod = "addImmOperands"; 75 let DiagnosticType = !strconcat("Invalid", Name); 76} 77 78class SImmAsmOperand<int width, string suffix = ""> 79 : ImmAsmOperand<"S", width, suffix> { 80} 81 82class UImmAsmOperand<int width, string suffix = ""> 83 : ImmAsmOperand<"U", width, suffix> { 84} 85 86def FenceArg : AsmOperandClass { 87 let Name = "FenceArg"; 88 let RenderMethod = "addFenceArgOperands"; 89 let DiagnosticType = "InvalidFenceArg"; 90} 91 92def fencearg : Operand<XLenVT> { 93 let ParserMatchClass = FenceArg; 94 let PrintMethod = "printFenceArg"; 95 let DecoderMethod = "decodeUImmOperand<4>"; 96 let OperandType = "OPERAND_UIMM4"; 97 let OperandNamespace = "RISCVOp"; 98} 99 100def UImmLog2XLenAsmOperand : AsmOperandClass { 101 let Name = "UImmLog2XLen"; 102 let RenderMethod = "addImmOperands"; 103 let DiagnosticType = "InvalidUImmLog2XLen"; 104} 105 106def uimmlog2xlen : Operand<XLenVT>, ImmLeaf<XLenVT, [{ 107 if (Subtarget->is64Bit()) 108 return isUInt<6>(Imm); 109 return isUInt<5>(Imm); 110}]> { 111 let ParserMatchClass = UImmLog2XLenAsmOperand; 112 // TODO: should ensure invalid shamt is rejected when decoding. 113 let DecoderMethod = "decodeUImmOperand<6>"; 114 let MCOperandPredicate = [{ 115 int64_t Imm; 116 if (!MCOp.evaluateAsConstantImm(Imm)) 117 return false; 118 if (STI.getTargetTriple().isArch64Bit()) 119 return isUInt<6>(Imm); 120 return isUInt<5>(Imm); 121 }]; 122 let OperandType = "OPERAND_UIMMLOG2XLEN"; 123 let OperandNamespace = "RISCVOp"; 124} 125 126def uimm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]> { 127 let ParserMatchClass = UImmAsmOperand<5>; 128 let DecoderMethod = "decodeUImmOperand<5>"; 129 let OperandType = "OPERAND_UIMM5"; 130 let OperandNamespace = "RISCVOp"; 131} 132 133def simm12 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<12>(Imm);}]> { 134 let ParserMatchClass = SImmAsmOperand<12>; 135 let EncoderMethod = "getImmOpValue"; 136 let DecoderMethod = "decodeSImmOperand<12>"; 137 let MCOperandPredicate = [{ 138 int64_t Imm; 139 if (MCOp.evaluateAsConstantImm(Imm)) 140 return isInt<12>(Imm); 141 return MCOp.isBareSymbolRef(); 142 }]; 143 let OperandType = "OPERAND_SIMM12"; 144 let OperandNamespace = "RISCVOp"; 145} 146 147// A 12-bit signed immediate plus one where the imm range will be -2047~2048. 148def simm12_plus1 : Operand<XLenVT>, ImmLeaf<XLenVT, 149 [{return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048;}]> { 150 let ParserMatchClass = SImmAsmOperand<12>; 151 let EncoderMethod = "getImmOpValue"; 152 let DecoderMethod = "decodeSImmOperand<12>"; 153 let MCOperandPredicate = [{ 154 int64_t Imm; 155 if (MCOp.evaluateAsConstantImm(Imm)) 156 return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048; 157 return MCOp.isBareSymbolRef(); 158 }]; 159} 160 161// A 13-bit signed immediate where the least significant bit is zero. 162def simm13_lsb0 : Operand<OtherVT> { 163 let ParserMatchClass = SImmAsmOperand<13, "Lsb0">; 164 let EncoderMethod = "getImmOpValueAsr1"; 165 let DecoderMethod = "decodeSImmOperandAndLsl1<13>"; 166 let MCOperandPredicate = [{ 167 int64_t Imm; 168 if (MCOp.evaluateAsConstantImm(Imm)) 169 return isShiftedInt<12, 1>(Imm); 170 return MCOp.isBareSymbolRef(); 171 }]; 172 let OperandType = "OPERAND_SIMM13_LSB0"; 173 let OperandNamespace = "RISCVOp"; 174} 175 176class UImm20Operand : Operand<XLenVT> { 177 let EncoderMethod = "getImmOpValue"; 178 let DecoderMethod = "decodeUImmOperand<20>"; 179 let MCOperandPredicate = [{ 180 int64_t Imm; 181 if (MCOp.evaluateAsConstantImm(Imm)) 182 return isUInt<20>(Imm); 183 return MCOp.isBareSymbolRef(); 184 }]; 185 let OperandType = "OPERAND_UIMM20"; 186 let OperandNamespace = "RISCVOp"; 187} 188 189def uimm20_lui : UImm20Operand { 190 let ParserMatchClass = UImmAsmOperand<20, "LUI">; 191} 192def uimm20_auipc : UImm20Operand { 193 let ParserMatchClass = UImmAsmOperand<20, "AUIPC">; 194} 195 196def Simm21Lsb0JALAsmOperand : SImmAsmOperand<21, "Lsb0JAL"> { 197 let ParserMethod = "parseJALOffset"; 198} 199 200// A 21-bit signed immediate where the least significant bit is zero. 201def simm21_lsb0_jal : Operand<OtherVT> { 202 let ParserMatchClass = Simm21Lsb0JALAsmOperand; 203 let EncoderMethod = "getImmOpValueAsr1"; 204 let DecoderMethod = "decodeSImmOperandAndLsl1<21>"; 205 let MCOperandPredicate = [{ 206 int64_t Imm; 207 if (MCOp.evaluateAsConstantImm(Imm)) 208 return isShiftedInt<20, 1>(Imm); 209 return MCOp.isBareSymbolRef(); 210 }]; 211 let OperandType = "OPERAND_SIMM21_LSB0"; 212 let OperandNamespace = "RISCVOp"; 213} 214 215def BareSymbol : AsmOperandClass { 216 let Name = "BareSymbol"; 217 let RenderMethod = "addImmOperands"; 218 let DiagnosticType = "InvalidBareSymbol"; 219 let ParserMethod = "parseBareSymbol"; 220} 221 222// A bare symbol. 223def bare_symbol : Operand<XLenVT> { 224 let ParserMatchClass = BareSymbol; 225} 226 227def CallSymbol : AsmOperandClass { 228 let Name = "CallSymbol"; 229 let RenderMethod = "addImmOperands"; 230 let DiagnosticType = "InvalidCallSymbol"; 231 let ParserMethod = "parseCallSymbol"; 232} 233 234// A bare symbol used in call/tail only. 235def call_symbol : Operand<XLenVT> { 236 let ParserMatchClass = CallSymbol; 237} 238 239def PseudoJumpSymbol : AsmOperandClass { 240 let Name = "PseudoJumpSymbol"; 241 let RenderMethod = "addImmOperands"; 242 let DiagnosticType = "InvalidPseudoJumpSymbol"; 243 let ParserMethod = "parsePseudoJumpSymbol"; 244} 245 246// A bare symbol used for pseudo jumps only. 247def pseudo_jump_symbol : Operand<XLenVT> { 248 let ParserMatchClass = PseudoJumpSymbol; 249} 250 251def TPRelAddSymbol : AsmOperandClass { 252 let Name = "TPRelAddSymbol"; 253 let RenderMethod = "addImmOperands"; 254 let DiagnosticType = "InvalidTPRelAddSymbol"; 255 let ParserMethod = "parseOperandWithModifier"; 256} 257 258// A bare symbol with the %tprel_add variant. 259def tprel_add_symbol : Operand<XLenVT> { 260 let ParserMatchClass = TPRelAddSymbol; 261} 262 263def CSRSystemRegister : AsmOperandClass { 264 let Name = "CSRSystemRegister"; 265 let ParserMethod = "parseCSRSystemRegister"; 266 let DiagnosticType = "InvalidCSRSystemRegister"; 267} 268 269def csr_sysreg : Operand<XLenVT> { 270 let ParserMatchClass = CSRSystemRegister; 271 let PrintMethod = "printCSRSystemRegister"; 272 let DecoderMethod = "decodeUImmOperand<12>"; 273 let OperandType = "OPERAND_UIMM12"; 274 let OperandNamespace = "RISCVOp"; 275} 276 277// A parameterized register class alternative to i32imm/i64imm from Target.td. 278def ixlenimm : Operand<XLenVT>; 279 280def ixlenimm_li : Operand<XLenVT> { 281 let ParserMatchClass = ImmXLenAsmOperand<"", "LI">; 282} 283 284// Standalone (codegen-only) immleaf patterns. 285def simm32 : ImmLeaf<XLenVT, [{return isInt<32>(Imm);}]>; 286def simm32hi20 : ImmLeaf<XLenVT, [{return isShiftedInt<20, 12>(Imm);}]>; 287// A mask value that won't affect significant shift bits. 288def immbottomxlenset : ImmLeaf<XLenVT, [{ 289 if (Subtarget->is64Bit()) 290 return countTrailingOnes<uint64_t>(Imm) >= 6; 291 return countTrailingOnes<uint64_t>(Imm) >= 5; 292}]>; 293 294// A 6-bit constant greater than 32. 295def uimm6gt32 : ImmLeaf<XLenVT, [{ 296 return isUInt<6>(Imm) && Imm > 32; 297}]>; 298 299// Addressing modes. 300// Necessary because a frameindex can't be matched directly in a pattern. 301def AddrFI : ComplexPattern<iPTR, 1, "SelectAddrFI", [frameindex], []>; 302 303// Extract least significant 12 bits from an immediate value and sign extend 304// them. 305def LO12Sext : SDNodeXForm<imm, [{ 306 return CurDAG->getTargetConstant(SignExtend64<12>(N->getZExtValue()), 307 SDLoc(N), N->getValueType(0)); 308}]>; 309 310// Extract the most significant 20 bits from an immediate value. Add 1 if bit 311// 11 is 1, to compensate for the low 12 bits in the matching immediate addi 312// or ld/st being negative. 313def HI20 : SDNodeXForm<imm, [{ 314 return CurDAG->getTargetConstant(((N->getZExtValue()+0x800) >> 12) & 0xfffff, 315 SDLoc(N), N->getValueType(0)); 316}]>; 317 318// Return the negation of an immediate value. 319def NegImm : SDNodeXForm<imm, [{ 320 return CurDAG->getTargetConstant(-N->getSExtValue(), SDLoc(N), 321 N->getValueType(0)); 322}]>; 323 324// Return an immediate value minus 32. 325def ImmSub32 : SDNodeXForm<imm, [{ 326 return CurDAG->getTargetConstant(N->getSExtValue() - 32, SDLoc(N), 327 N->getValueType(0)); 328}]>; 329 330//===----------------------------------------------------------------------===// 331// Instruction Formats 332//===----------------------------------------------------------------------===// 333 334include "RISCVInstrFormats.td" 335 336//===----------------------------------------------------------------------===// 337// Instruction Class Templates 338//===----------------------------------------------------------------------===// 339 340let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 341class BranchCC_rri<bits<3> funct3, string opcodestr> 342 : RVInstB<funct3, OPC_BRANCH, (outs), 343 (ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12), 344 opcodestr, "$rs1, $rs2, $imm12">, 345 Sched<[WriteJmp, ReadJmp, ReadJmp]> { 346 let isBranch = 1; 347 let isTerminator = 1; 348} 349 350let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 351class Load_ri<bits<3> funct3, string opcodestr> 352 : RVInstI<funct3, OPC_LOAD, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12), 353 opcodestr, "$rd, ${imm12}(${rs1})">; 354 355// Operands for stores are in the order srcreg, base, offset rather than 356// reflecting the order these fields are specified in the instruction 357// encoding. 358let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 359class Store_rri<bits<3> funct3, string opcodestr> 360 : RVInstS<funct3, OPC_STORE, (outs), 361 (ins GPR:$rs2, GPR:$rs1, simm12:$imm12), 362 opcodestr, "$rs2, ${imm12}(${rs1})">; 363 364let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 365class ALU_ri<bits<3> funct3, string opcodestr> 366 : RVInstI<funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12), 367 opcodestr, "$rd, $rs1, $imm12">, 368 Sched<[WriteIALU, ReadIALU]>; 369 370let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 371class Shift_ri<bit arithshift, bits<3> funct3, string opcodestr> 372 : RVInstIShift<arithshift, funct3, OPC_OP_IMM, (outs GPR:$rd), 373 (ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr, 374 "$rd, $rs1, $shamt">, 375 Sched<[WriteShift, ReadShift]>; 376 377let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 378class ALU_rr<bits<7> funct7, bits<3> funct3, string opcodestr> 379 : RVInstR<funct7, funct3, OPC_OP, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2), 380 opcodestr, "$rd, $rs1, $rs2">; 381 382let hasNoSchedulingInfo = 1, 383 hasSideEffects = 1, mayLoad = 0, mayStore = 0 in 384class CSR_ir<bits<3> funct3, string opcodestr> 385 : RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd), (ins csr_sysreg:$imm12, GPR:$rs1), 386 opcodestr, "$rd, $imm12, $rs1">, Sched<[WriteCSR, ReadCSR]>; 387 388let hasNoSchedulingInfo = 1, 389 hasSideEffects = 1, mayLoad = 0, mayStore = 0 in 390class CSR_ii<bits<3> funct3, string opcodestr> 391 : RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd), 392 (ins csr_sysreg:$imm12, uimm5:$rs1), 393 opcodestr, "$rd, $imm12, $rs1">, Sched<[WriteCSR]>; 394 395let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 396class ShiftW_ri<bit arithshift, bits<3> funct3, string opcodestr> 397 : RVInstIShiftW<arithshift, funct3, OPC_OP_IMM_32, (outs GPR:$rd), 398 (ins GPR:$rs1, uimm5:$shamt), opcodestr, 399 "$rd, $rs1, $shamt">, 400 Sched<[WriteShift32, ReadShift32]>; 401 402let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 403class ALUW_rr<bits<7> funct7, bits<3> funct3, string opcodestr> 404 : RVInstR<funct7, funct3, OPC_OP_32, (outs GPR:$rd), 405 (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">; 406 407let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in 408class Priv<string opcodestr, bits<7> funct7> 409 : RVInstR<funct7, 0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1, GPR:$rs2), 410 opcodestr, "">; 411 412//===----------------------------------------------------------------------===// 413// Instructions 414//===----------------------------------------------------------------------===// 415 416let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { 417let isReMaterializable = 1, isAsCheapAsAMove = 1 in 418def LUI : RVInstU<OPC_LUI, (outs GPR:$rd), (ins uimm20_lui:$imm20), 419 "lui", "$rd, $imm20">, Sched<[WriteIALU]>; 420 421def AUIPC : RVInstU<OPC_AUIPC, (outs GPR:$rd), (ins uimm20_auipc:$imm20), 422 "auipc", "$rd, $imm20">, Sched<[WriteIALU]>; 423 424let isCall = 1 in 425def JAL : RVInstJ<OPC_JAL, (outs GPR:$rd), (ins simm21_lsb0_jal:$imm20), 426 "jal", "$rd, $imm20">, Sched<[WriteJal]>; 427 428let isCall = 1 in 429def JALR : RVInstI<0b000, OPC_JALR, (outs GPR:$rd), 430 (ins GPR:$rs1, simm12:$imm12), 431 "jalr", "$rd, ${imm12}(${rs1})">, 432 Sched<[WriteJalr, ReadJalr]>; 433} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 434 435def BEQ : BranchCC_rri<0b000, "beq">; 436def BNE : BranchCC_rri<0b001, "bne">; 437def BLT : BranchCC_rri<0b100, "blt">; 438def BGE : BranchCC_rri<0b101, "bge">; 439def BLTU : BranchCC_rri<0b110, "bltu">; 440def BGEU : BranchCC_rri<0b111, "bgeu">; 441 442def LB : Load_ri<0b000, "lb">, Sched<[WriteLDB, ReadMemBase]>; 443def LH : Load_ri<0b001, "lh">, Sched<[WriteLDH, ReadMemBase]>; 444def LW : Load_ri<0b010, "lw">, Sched<[WriteLDW, ReadMemBase]>; 445def LBU : Load_ri<0b100, "lbu">, Sched<[WriteLDB, ReadMemBase]>; 446def LHU : Load_ri<0b101, "lhu">, Sched<[WriteLDH, ReadMemBase]>; 447 448def SB : Store_rri<0b000, "sb">, Sched<[WriteSTB, ReadStoreData, ReadMemBase]>; 449def SH : Store_rri<0b001, "sh">, Sched<[WriteSTH, ReadStoreData, ReadMemBase]>; 450def SW : Store_rri<0b010, "sw">, Sched<[WriteSTW, ReadStoreData, ReadMemBase]>; 451 452// ADDI isn't always rematerializable, but isReMaterializable will be used as 453// a hint which is verified in isReallyTriviallyReMaterializable. 454let isReMaterializable = 1, isAsCheapAsAMove = 1 in 455def ADDI : ALU_ri<0b000, "addi">; 456 457def SLTI : ALU_ri<0b010, "slti">; 458def SLTIU : ALU_ri<0b011, "sltiu">; 459 460let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 461def XORI : ALU_ri<0b100, "xori">; 462def ORI : ALU_ri<0b110, "ori">; 463} 464 465def ANDI : ALU_ri<0b111, "andi">; 466 467def SLLI : Shift_ri<0, 0b001, "slli">; 468def SRLI : Shift_ri<0, 0b101, "srli">; 469def SRAI : Shift_ri<1, 0b101, "srai">; 470 471def ADD : ALU_rr<0b0000000, 0b000, "add">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; 472def SUB : ALU_rr<0b0100000, 0b000, "sub">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; 473def SLL : ALU_rr<0b0000000, 0b001, "sll">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; 474def SLT : ALU_rr<0b0000000, 0b010, "slt">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; 475def SLTU : ALU_rr<0b0000000, 0b011, "sltu">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; 476def XOR : ALU_rr<0b0000000, 0b100, "xor">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; 477def SRL : ALU_rr<0b0000000, 0b101, "srl">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; 478def SRA : ALU_rr<0b0100000, 0b101, "sra">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; 479def OR : ALU_rr<0b0000000, 0b110, "or">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; 480def AND : ALU_rr<0b0000000, 0b111, "and">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; 481 482let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in { 483def FENCE : RVInstI<0b000, OPC_MISC_MEM, (outs), 484 (ins fencearg:$pred, fencearg:$succ), 485 "fence", "$pred, $succ">, Sched<[]> { 486 bits<4> pred; 487 bits<4> succ; 488 489 let rs1 = 0; 490 let rd = 0; 491 let imm12 = {0b0000,pred,succ}; 492} 493 494def FENCE_TSO : RVInstI<0b000, OPC_MISC_MEM, (outs), (ins), "fence.tso", "">, Sched<[]> { 495 let rs1 = 0; 496 let rd = 0; 497 let imm12 = {0b1000,0b0011,0b0011}; 498} 499 500def FENCE_I : RVInstI<0b001, OPC_MISC_MEM, (outs), (ins), "fence.i", "">, Sched<[]> { 501 let rs1 = 0; 502 let rd = 0; 503 let imm12 = 0; 504} 505 506def ECALL : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "ecall", "">, Sched<[WriteJmp]> { 507 let rs1 = 0; 508 let rd = 0; 509 let imm12 = 0; 510} 511 512def EBREAK : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "ebreak", "">, 513 Sched<[]> { 514 let rs1 = 0; 515 let rd = 0; 516 let imm12 = 1; 517} 518 519// This is a de facto standard (as set by GNU binutils) 32-bit unimplemented 520// instruction (i.e., it should always trap, if your implementation has invalid 521// instruction traps). 522def UNIMP : RVInstI<0b001, OPC_SYSTEM, (outs), (ins), "unimp", "">, 523 Sched<[]> { 524 let rs1 = 0; 525 let rd = 0; 526 let imm12 = 0b110000000000; 527} 528} // hasSideEffects = 1, mayLoad = 0, mayStore = 0 529 530def CSRRW : CSR_ir<0b001, "csrrw">; 531def CSRRS : CSR_ir<0b010, "csrrs">; 532def CSRRC : CSR_ir<0b011, "csrrc">; 533 534def CSRRWI : CSR_ii<0b101, "csrrwi">; 535def CSRRSI : CSR_ii<0b110, "csrrsi">; 536def CSRRCI : CSR_ii<0b111, "csrrci">; 537 538/// RV64I instructions 539 540let Predicates = [IsRV64] in { 541def LWU : Load_ri<0b110, "lwu">, Sched<[WriteLDWU, ReadMemBase]>; 542def LD : Load_ri<0b011, "ld">, Sched<[WriteLDD, ReadMemBase]>; 543def SD : Store_rri<0b011, "sd">, Sched<[WriteSTD, ReadStoreData, ReadMemBase]>; 544 545let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 546def ADDIW : RVInstI<0b000, OPC_OP_IMM_32, (outs GPR:$rd), 547 (ins GPR:$rs1, simm12:$imm12), 548 "addiw", "$rd, $rs1, $imm12">, 549 Sched<[WriteIALU32, ReadIALU32]>; 550 551def SLLIW : ShiftW_ri<0, 0b001, "slliw">; 552def SRLIW : ShiftW_ri<0, 0b101, "srliw">; 553def SRAIW : ShiftW_ri<1, 0b101, "sraiw">; 554 555def ADDW : ALUW_rr<0b0000000, 0b000, "addw">, 556 Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>; 557def SUBW : ALUW_rr<0b0100000, 0b000, "subw">, 558 Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>; 559def SLLW : ALUW_rr<0b0000000, 0b001, "sllw">, 560 Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>; 561def SRLW : ALUW_rr<0b0000000, 0b101, "srlw">, 562 Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>; 563def SRAW : ALUW_rr<0b0100000, 0b101, "sraw">, 564 Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>; 565} // Predicates = [IsRV64] 566 567//===----------------------------------------------------------------------===// 568// Privileged instructions 569//===----------------------------------------------------------------------===// 570 571let isBarrier = 1, isReturn = 1, isTerminator = 1 in { 572def URET : Priv<"uret", 0b0000000>, Sched<[]> { 573 let rd = 0; 574 let rs1 = 0; 575 let rs2 = 0b00010; 576} 577 578def SRET : Priv<"sret", 0b0001000>, Sched<[]> { 579 let rd = 0; 580 let rs1 = 0; 581 let rs2 = 0b00010; 582} 583 584def MRET : Priv<"mret", 0b0011000>, Sched<[]> { 585 let rd = 0; 586 let rs1 = 0; 587 let rs2 = 0b00010; 588} 589} // isBarrier = 1, isReturn = 1, isTerminator = 1 590 591def WFI : Priv<"wfi", 0b0001000>, Sched<[]> { 592 let rd = 0; 593 let rs1 = 0; 594 let rs2 = 0b00101; 595} 596 597let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in 598def SFENCE_VMA : RVInstR<0b0001001, 0b000, OPC_SYSTEM, (outs), 599 (ins GPR:$rs1, GPR:$rs2), 600 "sfence.vma", "$rs1, $rs2">, Sched<[]> { 601 let rd = 0; 602} 603 604//===----------------------------------------------------------------------===// 605// Debug instructions 606//===----------------------------------------------------------------------===// 607 608let isBarrier = 1, isReturn = 1, isTerminator = 1 in { 609def DRET : Priv<"dret", 0b0111101>, Sched<[]> { 610 let rd = 0; 611 let rs1 = 0; 612 let rs2 = 0b10010; 613} 614} // isBarrier = 1, isReturn = 1, isTerminator = 1 615 616//===----------------------------------------------------------------------===// 617// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20) 618//===----------------------------------------------------------------------===// 619 620def : InstAlias<"nop", (ADDI X0, X0, 0)>; 621 622// Note that the size is 32 because up to 8 32-bit instructions are needed to 623// generate an arbitrary 64-bit immediate. However, the size does not really 624// matter since PseudoLI is currently only used in the AsmParser where it gets 625// expanded to real instructions immediately. 626let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 32, 627 isCodeGenOnly = 0, isAsmParserOnly = 1 in 628def PseudoLI : Pseudo<(outs GPR:$rd), (ins ixlenimm_li:$imm), [], 629 "li", "$rd, $imm">; 630 631def PseudoLB : PseudoLoad<"lb">; 632def PseudoLBU : PseudoLoad<"lbu">; 633def PseudoLH : PseudoLoad<"lh">; 634def PseudoLHU : PseudoLoad<"lhu">; 635def PseudoLW : PseudoLoad<"lw">; 636 637def PseudoSB : PseudoStore<"sb">; 638def PseudoSH : PseudoStore<"sh">; 639def PseudoSW : PseudoStore<"sw">; 640 641let Predicates = [IsRV64] in { 642def PseudoLWU : PseudoLoad<"lwu">; 643def PseudoLD : PseudoLoad<"ld">; 644def PseudoSD : PseudoStore<"sd">; 645} // Predicates = [IsRV64] 646 647def : InstAlias<"mv $rd, $rs", (ADDI GPR:$rd, GPR:$rs, 0)>; 648def : InstAlias<"not $rd, $rs", (XORI GPR:$rd, GPR:$rs, -1)>; 649def : InstAlias<"neg $rd, $rs", (SUB GPR:$rd, X0, GPR:$rs)>; 650 651let Predicates = [IsRV64] in { 652def : InstAlias<"negw $rd, $rs", (SUBW GPR:$rd, X0, GPR:$rs)>; 653def : InstAlias<"sext.w $rd, $rs", (ADDIW GPR:$rd, GPR:$rs, 0)>; 654} // Predicates = [IsRV64] 655 656def : InstAlias<"seqz $rd, $rs", (SLTIU GPR:$rd, GPR:$rs, 1)>; 657def : InstAlias<"snez $rd, $rs", (SLTU GPR:$rd, X0, GPR:$rs)>; 658def : InstAlias<"sltz $rd, $rs", (SLT GPR:$rd, GPR:$rs, X0)>; 659def : InstAlias<"sgtz $rd, $rs", (SLT GPR:$rd, X0, GPR:$rs)>; 660 661// sgt/sgtu are recognised by the GNU assembler but the canonical slt/sltu 662// form will always be printed. Therefore, set a zero weight. 663def : InstAlias<"sgt $rd, $rs, $rt", (SLT GPR:$rd, GPR:$rt, GPR:$rs), 0>; 664def : InstAlias<"sgtu $rd, $rs, $rt", (SLTU GPR:$rd, GPR:$rt, GPR:$rs), 0>; 665 666def : InstAlias<"beqz $rs, $offset", 667 (BEQ GPR:$rs, X0, simm13_lsb0:$offset)>; 668def : InstAlias<"bnez $rs, $offset", 669 (BNE GPR:$rs, X0, simm13_lsb0:$offset)>; 670def : InstAlias<"blez $rs, $offset", 671 (BGE X0, GPR:$rs, simm13_lsb0:$offset)>; 672def : InstAlias<"bgez $rs, $offset", 673 (BGE GPR:$rs, X0, simm13_lsb0:$offset)>; 674def : InstAlias<"bltz $rs, $offset", 675 (BLT GPR:$rs, X0, simm13_lsb0:$offset)>; 676def : InstAlias<"bgtz $rs, $offset", 677 (BLT X0, GPR:$rs, simm13_lsb0:$offset)>; 678 679// Always output the canonical mnemonic for the pseudo branch instructions. 680// The GNU tools emit the canonical mnemonic for the branch pseudo instructions 681// as well (e.g. "bgt" will be recognised by the assembler but never printed by 682// objdump). Match this behaviour by setting a zero weight. 683def : InstAlias<"bgt $rs, $rt, $offset", 684 (BLT GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>; 685def : InstAlias<"ble $rs, $rt, $offset", 686 (BGE GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>; 687def : InstAlias<"bgtu $rs, $rt, $offset", 688 (BLTU GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>; 689def : InstAlias<"bleu $rs, $rt, $offset", 690 (BGEU GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>; 691 692def : InstAlias<"j $offset", (JAL X0, simm21_lsb0_jal:$offset)>; 693def : InstAlias<"jal $offset", (JAL X1, simm21_lsb0_jal:$offset)>; 694 695// Non-zero offset aliases of "jalr" are the lowest weight, followed by the 696// two-register form, then the one-register forms and finally "ret". 697def : InstAlias<"jr $rs", (JALR X0, GPR:$rs, 0), 3>; 698def : InstAlias<"jr ${offset}(${rs})", (JALR X0, GPR:$rs, simm12:$offset)>; 699def : InstAlias<"jalr $rs", (JALR X1, GPR:$rs, 0), 3>; 700def : InstAlias<"jalr ${offset}(${rs})", (JALR X1, GPR:$rs, simm12:$offset)>; 701def : InstAlias<"jalr $rd, $rs", (JALR GPR:$rd, GPR:$rs, 0), 2>; 702def : InstAlias<"ret", (JALR X0, X1, 0), 4>; 703 704// Non-canonical forms for jump targets also accepted by the assembler. 705def : InstAlias<"jr $rs, $offset", (JALR X0, GPR:$rs, simm12:$offset), 0>; 706def : InstAlias<"jalr $rs, $offset", (JALR X1, GPR:$rs, simm12:$offset), 0>; 707def : InstAlias<"jalr $rd, $rs, $offset", (JALR GPR:$rd, GPR:$rs, simm12:$offset), 0>; 708 709def : InstAlias<"fence", (FENCE 0xF, 0xF)>; // 0xF == iorw 710 711def : InstAlias<"rdinstret $rd", (CSRRS GPR:$rd, INSTRET.Encoding, X0)>; 712def : InstAlias<"rdcycle $rd", (CSRRS GPR:$rd, CYCLE.Encoding, X0)>; 713def : InstAlias<"rdtime $rd", (CSRRS GPR:$rd, TIME.Encoding, X0)>; 714 715let Predicates = [IsRV32] in { 716def : InstAlias<"rdinstreth $rd", (CSRRS GPR:$rd, INSTRETH.Encoding, X0)>; 717def : InstAlias<"rdcycleh $rd", (CSRRS GPR:$rd, CYCLEH.Encoding, X0)>; 718def : InstAlias<"rdtimeh $rd", (CSRRS GPR:$rd, TIMEH.Encoding, X0)>; 719} // Predicates = [IsRV32] 720 721def : InstAlias<"csrr $rd, $csr", (CSRRS GPR:$rd, csr_sysreg:$csr, X0)>; 722def : InstAlias<"csrw $csr, $rs", (CSRRW X0, csr_sysreg:$csr, GPR:$rs)>; 723def : InstAlias<"csrs $csr, $rs", (CSRRS X0, csr_sysreg:$csr, GPR:$rs)>; 724def : InstAlias<"csrc $csr, $rs", (CSRRC X0, csr_sysreg:$csr, GPR:$rs)>; 725 726def : InstAlias<"csrwi $csr, $imm", (CSRRWI X0, csr_sysreg:$csr, uimm5:$imm)>; 727def : InstAlias<"csrsi $csr, $imm", (CSRRSI X0, csr_sysreg:$csr, uimm5:$imm)>; 728def : InstAlias<"csrci $csr, $imm", (CSRRCI X0, csr_sysreg:$csr, uimm5:$imm)>; 729 730let EmitPriority = 0 in { 731def : InstAlias<"csrw $csr, $imm", (CSRRWI X0, csr_sysreg:$csr, uimm5:$imm)>; 732def : InstAlias<"csrs $csr, $imm", (CSRRSI X0, csr_sysreg:$csr, uimm5:$imm)>; 733def : InstAlias<"csrc $csr, $imm", (CSRRCI X0, csr_sysreg:$csr, uimm5:$imm)>; 734 735def : InstAlias<"csrrw $rd, $csr, $imm", (CSRRWI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>; 736def : InstAlias<"csrrs $rd, $csr, $imm", (CSRRSI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>; 737def : InstAlias<"csrrc $rd, $csr, $imm", (CSRRCI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>; 738} 739 740def : InstAlias<"sfence.vma", (SFENCE_VMA X0, X0)>; 741def : InstAlias<"sfence.vma $rs", (SFENCE_VMA GPR:$rs, X0)>; 742 743let EmitPriority = 0 in { 744def : InstAlias<"lb $rd, (${rs1})", 745 (LB GPR:$rd, GPR:$rs1, 0)>; 746def : InstAlias<"lh $rd, (${rs1})", 747 (LH GPR:$rd, GPR:$rs1, 0)>; 748def : InstAlias<"lw $rd, (${rs1})", 749 (LW GPR:$rd, GPR:$rs1, 0)>; 750def : InstAlias<"lbu $rd, (${rs1})", 751 (LBU GPR:$rd, GPR:$rs1, 0)>; 752def : InstAlias<"lhu $rd, (${rs1})", 753 (LHU GPR:$rd, GPR:$rs1, 0)>; 754 755def : InstAlias<"sb $rs2, (${rs1})", 756 (SB GPR:$rs2, GPR:$rs1, 0)>; 757def : InstAlias<"sh $rs2, (${rs1})", 758 (SH GPR:$rs2, GPR:$rs1, 0)>; 759def : InstAlias<"sw $rs2, (${rs1})", 760 (SW GPR:$rs2, GPR:$rs1, 0)>; 761 762def : InstAlias<"add $rd, $rs1, $imm12", 763 (ADDI GPR:$rd, GPR:$rs1, simm12:$imm12)>; 764def : InstAlias<"and $rd, $rs1, $imm12", 765 (ANDI GPR:$rd, GPR:$rs1, simm12:$imm12)>; 766def : InstAlias<"xor $rd, $rs1, $imm12", 767 (XORI GPR:$rd, GPR:$rs1, simm12:$imm12)>; 768def : InstAlias<"or $rd, $rs1, $imm12", 769 (ORI GPR:$rd, GPR:$rs1, simm12:$imm12)>; 770def : InstAlias<"sll $rd, $rs1, $shamt", 771 (SLLI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>; 772def : InstAlias<"srl $rd, $rs1, $shamt", 773 (SRLI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>; 774def : InstAlias<"sra $rd, $rs1, $shamt", 775 (SRAI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>; 776let Predicates = [IsRV64] in { 777def : InstAlias<"lwu $rd, (${rs1})", 778 (LWU GPR:$rd, GPR:$rs1, 0)>; 779def : InstAlias<"ld $rd, (${rs1})", 780 (LD GPR:$rd, GPR:$rs1, 0)>; 781def : InstAlias<"sd $rs2, (${rs1})", 782 (SD GPR:$rs2, GPR:$rs1, 0)>; 783 784def : InstAlias<"addw $rd, $rs1, $imm12", 785 (ADDIW GPR:$rd, GPR:$rs1, simm12:$imm12)>; 786def : InstAlias<"sllw $rd, $rs1, $shamt", 787 (SLLIW GPR:$rd, GPR:$rs1, uimm5:$shamt)>; 788def : InstAlias<"srlw $rd, $rs1, $shamt", 789 (SRLIW GPR:$rd, GPR:$rs1, uimm5:$shamt)>; 790def : InstAlias<"sraw $rd, $rs1, $shamt", 791 (SRAIW GPR:$rd, GPR:$rs1, uimm5:$shamt)>; 792} // Predicates = [IsRV64] 793def : InstAlias<"slt $rd, $rs1, $imm12", 794 (SLTI GPR:$rd, GPR:$rs1, simm12:$imm12)>; 795def : InstAlias<"sltu $rd, $rs1, $imm12", 796 (SLTIU GPR:$rd, GPR:$rs1, simm12:$imm12)>; 797} 798 799def : MnemonicAlias<"move", "mv">; 800 801// The SCALL and SBREAK instructions wererenamed to ECALL and EBREAK in 802// version 2.1 of the user-level ISA. Like the GNU toolchain, we still accept 803// the old name for backwards compatibility. 804def : MnemonicAlias<"scall", "ecall">; 805def : MnemonicAlias<"sbreak", "ebreak">; 806 807//===----------------------------------------------------------------------===// 808// Pseudo-instructions and codegen patterns 809// 810// Naming convention: For 'generic' pattern classes, we use the naming 811// convention PatTy1Ty2. For pattern classes which offer a more complex 812// expansion, prefix the class name, e.g. BccPat. 813//===----------------------------------------------------------------------===// 814 815/// Generic pattern classes 816 817class PatGprGpr<SDPatternOperator OpNode, RVInst Inst> 818 : Pat<(OpNode GPR:$rs1, GPR:$rs2), (Inst GPR:$rs1, GPR:$rs2)>; 819class PatGprSimm12<SDPatternOperator OpNode, RVInstI Inst> 820 : Pat<(OpNode GPR:$rs1, simm12:$imm12), (Inst GPR:$rs1, simm12:$imm12)>; 821class PatGprUimmLog2XLen<SDPatternOperator OpNode, RVInstIShift Inst> 822 : Pat<(OpNode GPR:$rs1, uimmlog2xlen:$shamt), 823 (Inst GPR:$rs1, uimmlog2xlen:$shamt)>; 824 825/// Predicates 826 827def IsOrAdd: PatFrag<(ops node:$A, node:$B), (or node:$A, node:$B), [{ 828 return isOrEquivalentToAdd(N); 829}]>; 830def assertsexti32 : PatFrag<(ops node:$src), (assertsext node:$src), [{ 831 return cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i32; 832}]>; 833def sexti32 : PatFrags<(ops node:$src), 834 [(sext_inreg node:$src, i32), 835 (assertsexti32 node:$src)]>; 836def assertzexti32 : PatFrag<(ops node:$src), (assertzext node:$src), [{ 837 return cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i32; 838}]>; 839def zexti32 : PatFrags<(ops node:$src), 840 [(and node:$src, 0xffffffff), 841 (assertzexti32 node:$src)]>; 842 843/// Immediates 844 845def : Pat<(simm12:$imm), (ADDI X0, simm12:$imm)>; 846def : Pat<(simm32hi20:$imm), (LUI (HI20 imm:$imm))>; 847def : Pat<(simm32:$imm), (ADDI (LUI (HI20 imm:$imm)), (LO12Sext imm:$imm))>, 848 Requires<[IsRV32]>; 849 850/// Simple arithmetic operations 851 852def : PatGprGpr<add, ADD>; 853def : PatGprSimm12<add, ADDI>; 854def : PatGprGpr<sub, SUB>; 855def : PatGprGpr<or, OR>; 856def : PatGprSimm12<or, ORI>; 857def : PatGprGpr<and, AND>; 858def : PatGprSimm12<and, ANDI>; 859def : PatGprGpr<xor, XOR>; 860def : PatGprSimm12<xor, XORI>; 861def : PatGprUimmLog2XLen<shl, SLLI>; 862def : PatGprUimmLog2XLen<srl, SRLI>; 863def : PatGprUimmLog2XLen<sra, SRAI>; 864 865// Match both a plain shift and one where the shift amount is masked (this is 866// typically introduced when the legalizer promotes the shift amount and 867// zero-extends it). For RISC-V, the mask is unnecessary as shifts in the base 868// ISA only read the least significant 5 bits (RV32I) or 6 bits (RV64I). 869class shiftop<SDPatternOperator operator> 870 : PatFrags<(ops node:$val, node:$count), 871 [(operator node:$val, node:$count), 872 (operator node:$val, (and node:$count, immbottomxlenset))]>; 873 874def : PatGprGpr<shiftop<shl>, SLL>; 875def : PatGprGpr<shiftop<srl>, SRL>; 876def : PatGprGpr<shiftop<sra>, SRA>; 877 878// This is a special case of the ADD instruction used to facilitate the use of a 879// fourth operand to emit a relocation on a symbol relating to this instruction. 880// The relocation does not affect any bits of the instruction itself but is used 881// as a hint to the linker. 882let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 0 in 883def PseudoAddTPRel : Pseudo<(outs GPR:$rd), 884 (ins GPR:$rs1, GPR:$rs2, tprel_add_symbol:$src), [], 885 "add", "$rd, $rs1, $rs2, $src">; 886 887/// FrameIndex calculations 888 889def : Pat<(add (i32 AddrFI:$Rs), simm12:$imm12), 890 (ADDI (i32 AddrFI:$Rs), simm12:$imm12)>; 891def : Pat<(IsOrAdd (i32 AddrFI:$Rs), simm12:$imm12), 892 (ADDI (i32 AddrFI:$Rs), simm12:$imm12)>; 893 894/// Setcc 895 896def : PatGprGpr<setlt, SLT>; 897def : PatGprSimm12<setlt, SLTI>; 898def : PatGprGpr<setult, SLTU>; 899def : PatGprSimm12<setult, SLTIU>; 900 901// Define pattern expansions for setcc operations that aren't directly 902// handled by a RISC-V instruction. 903def : Pat<(seteq GPR:$rs1, 0), (SLTIU GPR:$rs1, 1)>; 904def : Pat<(seteq GPR:$rs1, GPR:$rs2), (SLTIU (XOR GPR:$rs1, GPR:$rs2), 1)>; 905def : Pat<(seteq GPR:$rs1, simm12_plus1:$imm12), 906 (SLTIU (ADDI GPR:$rs1, (NegImm simm12_plus1:$imm12)), 1)>; 907def : Pat<(setne GPR:$rs1, 0), (SLTU X0, GPR:$rs1)>; 908def : Pat<(setne GPR:$rs1, GPR:$rs2), (SLTU X0, (XOR GPR:$rs1, GPR:$rs2))>; 909def : Pat<(setne GPR:$rs1, simm12_plus1:$imm12), 910 (SLTU X0, (ADDI GPR:$rs1, (NegImm simm12_plus1:$imm12)))>; 911def : Pat<(setugt GPR:$rs1, GPR:$rs2), (SLTU GPR:$rs2, GPR:$rs1)>; 912def : Pat<(setuge GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs1, GPR:$rs2), 1)>; 913def : Pat<(setule GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs2, GPR:$rs1), 1)>; 914def : Pat<(setgt GPR:$rs1, GPR:$rs2), (SLT GPR:$rs2, GPR:$rs1)>; 915def : Pat<(setge GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs1, GPR:$rs2), 1)>; 916def : Pat<(setle GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs2, GPR:$rs1), 1)>; 917 918let usesCustomInserter = 1 in 919class SelectCC_rrirr<RegisterClass valty, RegisterClass cmpty> 920 : Pseudo<(outs valty:$dst), 921 (ins cmpty:$lhs, cmpty:$rhs, ixlenimm:$imm, 922 valty:$truev, valty:$falsev), 923 [(set valty:$dst, (riscv_selectcc cmpty:$lhs, cmpty:$rhs, 924 (XLenVT imm:$imm), valty:$truev, valty:$falsev))]>; 925 926def Select_GPR_Using_CC_GPR : SelectCC_rrirr<GPR, GPR>; 927 928/// Branches and jumps 929 930// Match `(brcond (CondOp ..), ..)` and lower to the appropriate RISC-V branch 931// instruction. 932class BccPat<PatFrag CondOp, RVInstB Inst> 933 : Pat<(brcond (XLenVT (CondOp GPR:$rs1, GPR:$rs2)), bb:$imm12), 934 (Inst GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12)>; 935 936def : BccPat<seteq, BEQ>; 937def : BccPat<setne, BNE>; 938def : BccPat<setlt, BLT>; 939def : BccPat<setge, BGE>; 940def : BccPat<setult, BLTU>; 941def : BccPat<setuge, BGEU>; 942 943class BccSwapPat<PatFrag CondOp, RVInst InstBcc> 944 : Pat<(brcond (XLenVT (CondOp GPR:$rs1, GPR:$rs2)), bb:$imm12), 945 (InstBcc GPR:$rs2, GPR:$rs1, bb:$imm12)>; 946 947// Condition codes that don't have matching RISC-V branch instructions, but 948// are trivially supported by swapping the two input operands 949def : BccSwapPat<setgt, BLT>; 950def : BccSwapPat<setle, BGE>; 951def : BccSwapPat<setugt, BLTU>; 952def : BccSwapPat<setule, BGEU>; 953 954// An extra pattern is needed for a brcond without a setcc (i.e. where the 955// condition was calculated elsewhere). 956def : Pat<(brcond GPR:$cond, bb:$imm12), (BNE GPR:$cond, X0, bb:$imm12)>; 957 958let isBarrier = 1, isBranch = 1, isTerminator = 1 in 959def PseudoBR : Pseudo<(outs), (ins simm21_lsb0_jal:$imm20), [(br bb:$imm20)]>, 960 PseudoInstExpansion<(JAL X0, simm21_lsb0_jal:$imm20)>; 961 962let isBarrier = 1, isBranch = 1, isIndirectBranch = 1, isTerminator = 1 in 963def PseudoBRIND : Pseudo<(outs), (ins GPR:$rs1, simm12:$imm12), []>, 964 PseudoInstExpansion<(JALR X0, GPR:$rs1, simm12:$imm12)>; 965 966def : Pat<(brind GPR:$rs1), (PseudoBRIND GPR:$rs1, 0)>; 967def : Pat<(brind (add GPR:$rs1, simm12:$imm12)), 968 (PseudoBRIND GPR:$rs1, simm12:$imm12)>; 969 970// PseudoCALLReg is a generic pseudo instruction for calls which will eventually 971// expand to auipc and jalr while encoding, with any given register used as the 972// destination. 973// Define AsmString to print "call" when compile with -S flag. 974// Define isCodeGenOnly = 0 to support parsing assembly "call" instruction. 975let isCall = 1, isBarrier = 1, isCodeGenOnly = 0, hasSideEffects = 0, 976 mayStore = 0, mayLoad = 0 in 977def PseudoCALLReg : Pseudo<(outs GPR:$rd), (ins call_symbol:$func), []> { 978 let AsmString = "call\t$rd, $func"; 979} 980 981// PseudoCALL is a pseudo instruction which will eventually expand to auipc 982// and jalr while encoding. This is desirable, as an auipc+jalr pair with 983// R_RISCV_CALL and R_RISCV_RELAX relocations can be be relaxed by the linker 984// if the offset fits in a signed 21-bit immediate. 985// Define AsmString to print "call" when compile with -S flag. 986// Define isCodeGenOnly = 0 to support parsing assembly "call" instruction. 987let isCall = 1, Defs = [X1], isCodeGenOnly = 0 in 988def PseudoCALL : Pseudo<(outs), (ins call_symbol:$func), []> { 989 let AsmString = "call\t$func"; 990} 991 992def : Pat<(riscv_call tglobaladdr:$func), (PseudoCALL tglobaladdr:$func)>; 993def : Pat<(riscv_call texternalsym:$func), (PseudoCALL texternalsym:$func)>; 994 995def : Pat<(riscv_uret_flag), (URET X0, X0)>; 996def : Pat<(riscv_sret_flag), (SRET X0, X0)>; 997def : Pat<(riscv_mret_flag), (MRET X0, X0)>; 998 999let isCall = 1, Defs = [X1] in 1000def PseudoCALLIndirect : Pseudo<(outs), (ins GPR:$rs1), 1001 [(riscv_call GPR:$rs1)]>, 1002 PseudoInstExpansion<(JALR X1, GPR:$rs1, 0)>; 1003 1004let isBarrier = 1, isReturn = 1, isTerminator = 1 in 1005def PseudoRET : Pseudo<(outs), (ins), [(riscv_ret_flag)]>, 1006 PseudoInstExpansion<(JALR X0, X1, 0)>; 1007 1008// PseudoTAIL is a pseudo instruction similar to PseudoCALL and will eventually 1009// expand to auipc and jalr while encoding. 1010// Define AsmString to print "tail" when compile with -S flag. 1011let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [X2], 1012 isCodeGenOnly = 0 in 1013def PseudoTAIL : Pseudo<(outs), (ins call_symbol:$dst), []> { 1014 let AsmString = "tail\t$dst"; 1015} 1016 1017let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [X2] in 1018def PseudoTAILIndirect : Pseudo<(outs), (ins GPRTC:$rs1), 1019 [(riscv_tail GPRTC:$rs1)]>, 1020 PseudoInstExpansion<(JALR X0, GPR:$rs1, 0)>; 1021 1022def : Pat<(riscv_tail (iPTR tglobaladdr:$dst)), 1023 (PseudoTAIL texternalsym:$dst)>; 1024def : Pat<(riscv_tail (iPTR texternalsym:$dst)), 1025 (PseudoTAIL texternalsym:$dst)>; 1026 1027let isCall = 0, isBarrier = 1, isBranch = 1, isTerminator = 1, 1028 isCodeGenOnly = 0, hasSideEffects = 0, mayStore = 0, mayLoad = 0 in 1029def PseudoJump : Pseudo<(outs GPR:$rd), (ins pseudo_jump_symbol:$target), []> { 1030 let AsmString = "jump\t$target, $rd"; 1031} 1032 1033let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 0, 1034 isAsmParserOnly = 1 in 1035def PseudoLLA : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [], 1036 "lla", "$dst, $src">; 1037 1038let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isCodeGenOnly = 0, 1039 isAsmParserOnly = 1 in 1040def PseudoLA : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [], 1041 "la", "$dst, $src">; 1042 1043let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isCodeGenOnly = 0, 1044 isAsmParserOnly = 1 in 1045def PseudoLA_TLS_IE : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [], 1046 "la.tls.ie", "$dst, $src">; 1047 1048let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isCodeGenOnly = 0, 1049 isAsmParserOnly = 1 in 1050def PseudoLA_TLS_GD : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [], 1051 "la.tls.gd", "$dst, $src">; 1052 1053/// Loads 1054 1055multiclass LdPat<PatFrag LoadOp, RVInst Inst> { 1056 def : Pat<(LoadOp GPR:$rs1), (Inst GPR:$rs1, 0)>; 1057 def : Pat<(LoadOp AddrFI:$rs1), (Inst AddrFI:$rs1, 0)>; 1058 def : Pat<(LoadOp (add GPR:$rs1, simm12:$imm12)), 1059 (Inst GPR:$rs1, simm12:$imm12)>; 1060 def : Pat<(LoadOp (add AddrFI:$rs1, simm12:$imm12)), 1061 (Inst AddrFI:$rs1, simm12:$imm12)>; 1062 def : Pat<(LoadOp (IsOrAdd AddrFI:$rs1, simm12:$imm12)), 1063 (Inst AddrFI:$rs1, simm12:$imm12)>; 1064} 1065 1066defm : LdPat<sextloadi8, LB>; 1067defm : LdPat<extloadi8, LB>; 1068defm : LdPat<sextloadi16, LH>; 1069defm : LdPat<extloadi16, LH>; 1070defm : LdPat<load, LW>, Requires<[IsRV32]>; 1071defm : LdPat<zextloadi8, LBU>; 1072defm : LdPat<zextloadi16, LHU>; 1073 1074/// Stores 1075 1076multiclass StPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy> { 1077 def : Pat<(StoreOp StTy:$rs2, GPR:$rs1), (Inst StTy:$rs2, GPR:$rs1, 0)>; 1078 def : Pat<(StoreOp StTy:$rs2, AddrFI:$rs1), (Inst StTy:$rs2, AddrFI:$rs1, 0)>; 1079 def : Pat<(StoreOp StTy:$rs2, (add GPR:$rs1, simm12:$imm12)), 1080 (Inst StTy:$rs2, GPR:$rs1, simm12:$imm12)>; 1081 def : Pat<(StoreOp StTy:$rs2, (add AddrFI:$rs1, simm12:$imm12)), 1082 (Inst StTy:$rs2, AddrFI:$rs1, simm12:$imm12)>; 1083 def : Pat<(StoreOp StTy:$rs2, (IsOrAdd AddrFI:$rs1, simm12:$imm12)), 1084 (Inst StTy:$rs2, AddrFI:$rs1, simm12:$imm12)>; 1085} 1086 1087defm : StPat<truncstorei8, SB, GPR>; 1088defm : StPat<truncstorei16, SH, GPR>; 1089defm : StPat<store, SW, GPR>, Requires<[IsRV32]>; 1090 1091/// Fences 1092 1093// Refer to Table A.6 in the version 2.3 draft of the RISC-V Instruction Set 1094// Manual: Volume I. 1095 1096// fence acquire -> fence r, rw 1097def : Pat<(atomic_fence (XLenVT 4), (timm)), (FENCE 0b10, 0b11)>; 1098// fence release -> fence rw, w 1099def : Pat<(atomic_fence (XLenVT 5), (timm)), (FENCE 0b11, 0b1)>; 1100// fence acq_rel -> fence.tso 1101def : Pat<(atomic_fence (XLenVT 6), (timm)), (FENCE_TSO)>; 1102// fence seq_cst -> fence rw, rw 1103def : Pat<(atomic_fence (XLenVT 7), (timm)), (FENCE 0b11, 0b11)>; 1104 1105// Lowering for atomic load and store is defined in RISCVInstrInfoA.td. 1106// Although these are lowered to fence+load/store instructions defined in the 1107// base RV32I/RV64I ISA, this lowering is only used when the A extension is 1108// present. This is necessary as it isn't valid to mix __atomic_* libcalls 1109// with inline atomic operations for the same object. 1110 1111/// Other pseudo-instructions 1112 1113// Pessimistically assume the stack pointer will be clobbered 1114let Defs = [X2], Uses = [X2] in { 1115def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 1116 [(callseq_start timm:$amt1, timm:$amt2)]>; 1117def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 1118 [(callseq_end timm:$amt1, timm:$amt2)]>; 1119} // Defs = [X2], Uses = [X2] 1120 1121/// RV64 patterns 1122 1123let Predicates = [IsRV64, NotHasStdExtZbbOrZbp] in 1124def : Pat<(and GPR:$rs1, 0xffffffff), (SRLI (SLLI GPR:$rs1, 32), 32)>; 1125 1126let Predicates = [IsRV64] in { 1127 1128/// sext and zext 1129 1130def : Pat<(sext_inreg GPR:$rs1, i32), (ADDIW GPR:$rs1, 0)>; 1131 1132/// ALU operations 1133 1134def : Pat<(sext_inreg (add GPR:$rs1, GPR:$rs2), i32), 1135 (ADDW GPR:$rs1, GPR:$rs2)>; 1136def : Pat<(sext_inreg (add GPR:$rs1, simm12:$imm12), i32), 1137 (ADDIW GPR:$rs1, simm12:$imm12)>; 1138def : Pat<(sext_inreg (sub GPR:$rs1, GPR:$rs2), i32), 1139 (SUBW GPR:$rs1, GPR:$rs2)>; 1140def : Pat<(sext_inreg (shl GPR:$rs1, uimm5:$shamt), i32), 1141 (SLLIW GPR:$rs1, uimm5:$shamt)>; 1142// (srl (zexti32 ...), uimm5:$shamt) is matched with custom code due to the 1143// need to undo manipulation of the mask value performed by DAGCombine. 1144def : Pat<(srl (shl GPR:$rs1, (i64 32)), uimm6gt32:$shamt), 1145 (SRLIW GPR:$rs1, (ImmSub32 uimm6gt32:$shamt))>; 1146def : Pat<(sra (sext_inreg GPR:$rs1, i32), uimm5:$shamt), 1147 (SRAIW GPR:$rs1, uimm5:$shamt)>; 1148 1149def : PatGprGpr<riscv_sllw, SLLW>; 1150def : PatGprGpr<riscv_srlw, SRLW>; 1151def : PatGprGpr<riscv_sraw, SRAW>; 1152 1153/// Loads 1154 1155defm : LdPat<sextloadi32, LW>; 1156defm : LdPat<extloadi32, LW>; 1157defm : LdPat<zextloadi32, LWU>; 1158defm : LdPat<load, LD>; 1159 1160/// Stores 1161 1162defm : StPat<truncstorei32, SW, GPR>; 1163defm : StPat<store, SD, GPR>; 1164} // Predicates = [IsRV64] 1165 1166/// readcyclecounter 1167// On RV64, we can directly read the 64-bit "cycle" CSR. 1168let Predicates = [IsRV64] in 1169def : Pat<(readcyclecounter), (CSRRS CYCLE.Encoding, X0)>; 1170// On RV32, ReadCycleWide will be expanded to the suggested loop reading both 1171// halves of the 64-bit "cycle" CSR. 1172let Predicates = [IsRV32], usesCustomInserter = 1, hasSideEffects = 0, 1173mayLoad = 0, mayStore = 0, hasNoSchedulingInfo = 1 in 1174def ReadCycleWide : Pseudo<(outs GPR:$lo, GPR:$hi), (ins), [], "", "">; 1175 1176/// traps 1177 1178// We lower `trap` to `unimp`, as this causes a hard exception on nearly all 1179// systems. 1180def : Pat<(trap), (UNIMP)>; 1181 1182// We lower `debugtrap` to `ebreak`, as this will get the attention of the 1183// debugger if possible. 1184def : Pat<(debugtrap), (EBREAK)>; 1185 1186//===----------------------------------------------------------------------===// 1187// Standard extensions 1188//===----------------------------------------------------------------------===// 1189 1190include "RISCVInstrInfoM.td" 1191include "RISCVInstrInfoA.td" 1192include "RISCVInstrInfoF.td" 1193include "RISCVInstrInfoD.td" 1194include "RISCVInstrInfoC.td" 1195include "RISCVInstrInfoB.td" 1196include "RISCVInstrInfoV.td" 1197