1//==- SystemZInstrFP.td - Floating-point SystemZ instructions --*- tblgen-*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9// TODO: Most floating-point instructions (except for simple moves and the
10// like) can raise exceptions -- should they have hasSideEffects=1 ?
11
12//===----------------------------------------------------------------------===//
13// Select instructions
14//===----------------------------------------------------------------------===//
15
16// C's ?: operator for floating-point operands.
17let Predicates = [FeatureVector] in {
18  def SelectVR32 : SelectWrapper<f32, VR32>;
19  def SelectVR64 : SelectWrapper<f64, VR64>;
20}
21def SelectF32  : SelectWrapper<f32, FP32>;
22def SelectF64  : SelectWrapper<f64, FP64>;
23let Predicates = [FeatureNoVectorEnhancements1] in
24  def SelectF128 : SelectWrapper<f128, FP128>;
25let Predicates = [FeatureVectorEnhancements1] in
26  def SelectVR128 : SelectWrapper<f128, VR128>;
27
28defm CondStoreF32 : CondStores<FP32, simple_store,
29                               simple_load, bdxaddr20only>;
30defm CondStoreF64 : CondStores<FP64, simple_store,
31                               simple_load, bdxaddr20only>;
32
33//===----------------------------------------------------------------------===//
34// Move instructions
35//===----------------------------------------------------------------------===//
36
37// Load zero.
38let isAsCheapAsAMove = 1, isMoveImm = 1 in {
39  def LZER : InherentRRE<"lzer", 0xB374, FP32,  fpimm0>;
40  def LZDR : InherentRRE<"lzdr", 0xB375, FP64,  fpimm0>;
41  def LZXR : InherentRRE<"lzxr", 0xB376, FP128, fpimm0>;
42}
43
44// Moves between two floating-point registers.
45def LER : UnaryRR <"ler", 0x38,   null_frag, FP32,  FP32>;
46def LDR : UnaryRR <"ldr", 0x28,   null_frag, FP64,  FP64>;
47def LXR : UnaryRRE<"lxr", 0xB365, null_frag, FP128, FP128>;
48
49// For z13 we prefer LDR over LER to avoid partial register dependencies.
50let isCodeGenOnly = 1 in
51  def LDR32 : UnaryRR<"ldr", 0x28, null_frag, FP32, FP32>;
52
53// Moves between two floating-point registers that also set the condition
54// codes.
55let Uses = [FPC], mayRaiseFPException = 1,
56    Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
57  defm LTEBR : LoadAndTestRRE<"ltebr", 0xB302, FP32>;
58  defm LTDBR : LoadAndTestRRE<"ltdbr", 0xB312, FP64>;
59  defm LTXBR : LoadAndTestRRE<"ltxbr", 0xB342, FP128>;
60}
61// Note that LTxBRCompare is not available if we have vector support,
62// since load-and-test instructions will partially clobber the target
63// (vector) register.
64let Predicates = [FeatureNoVector] in {
65  defm : CompareZeroFP<LTEBRCompare, FP32>;
66  defm : CompareZeroFP<LTDBRCompare, FP64>;
67  defm : CompareZeroFP<LTXBRCompare, FP128>;
68}
69
70// Use a normal load-and-test for compare against zero in case of
71// vector support (via a pseudo to simplify instruction selection).
72let Uses = [FPC], mayRaiseFPException = 1,
73    Defs = [CC], usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
74  def LTEBRCompare_VecPseudo : Pseudo<(outs), (ins FP32:$R1, FP32:$R2), []>;
75  def LTDBRCompare_VecPseudo : Pseudo<(outs), (ins FP64:$R1, FP64:$R2), []>;
76  def LTXBRCompare_VecPseudo : Pseudo<(outs), (ins FP128:$R1, FP128:$R2), []>;
77}
78let Predicates = [FeatureVector] in {
79  defm : CompareZeroFP<LTEBRCompare_VecPseudo, FP32>;
80  defm : CompareZeroFP<LTDBRCompare_VecPseudo, FP64>;
81}
82let Predicates = [FeatureVector, FeatureNoVectorEnhancements1] in
83  defm : CompareZeroFP<LTXBRCompare_VecPseudo, FP128>;
84
85// Moves between 64-bit integer and floating-point registers.
86def LGDR : UnaryRRE<"lgdr", 0xB3CD, bitconvert, GR64, FP64>;
87def LDGR : UnaryRRE<"ldgr", 0xB3C1, bitconvert, FP64, GR64>;
88
89// fcopysign with an FP32 result.
90let isCodeGenOnly = 1 in {
91  def CPSDRss : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP32, FP32, FP32>;
92  def CPSDRsd : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP32, FP32, FP64>;
93}
94
95// The sign of an FP128 is in the high register.
96let Predicates = [FeatureNoVectorEnhancements1] in
97  def : Pat<(fcopysign FP32:$src1, (f32 (fpround (f128 FP128:$src2)))),
98            (CPSDRsd FP32:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>;
99let Predicates = [FeatureVectorEnhancements1] in
100  def : Pat<(fcopysign FP32:$src1, (f32 (fpround (f128 VR128:$src2)))),
101            (CPSDRsd FP32:$src1, (EXTRACT_SUBREG VR128:$src2, subreg_h64))>;
102
103// fcopysign with an FP64 result.
104let isCodeGenOnly = 1 in
105  def CPSDRds : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP64, FP64, FP32>;
106def CPSDRdd : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP64, FP64, FP64>;
107
108// The sign of an FP128 is in the high register.
109let Predicates = [FeatureNoVectorEnhancements1] in
110  def : Pat<(fcopysign FP64:$src1, (f64 (fpround (f128 FP128:$src2)))),
111            (CPSDRdd FP64:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>;
112let Predicates = [FeatureVectorEnhancements1] in
113  def : Pat<(fcopysign FP64:$src1, (f64 (fpround (f128 VR128:$src2)))),
114            (CPSDRdd FP64:$src1, (EXTRACT_SUBREG VR128:$src2, subreg_h64))>;
115
116// fcopysign with an FP128 result.  Use "upper" as the high half and leave
117// the low half as-is.
118class CopySign128<RegisterOperand cls, dag upper>
119  : Pat<(fcopysign FP128:$src1, cls:$src2),
120        (INSERT_SUBREG FP128:$src1, upper, subreg_h64)>;
121
122let Predicates = [FeatureNoVectorEnhancements1] in {
123  def : CopySign128<FP32,  (CPSDRds (EXTRACT_SUBREG FP128:$src1, subreg_h64),
124                                    FP32:$src2)>;
125  def : CopySign128<FP64,  (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64),
126                                    FP64:$src2)>;
127  def : CopySign128<FP128, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64),
128                                    (EXTRACT_SUBREG FP128:$src2, subreg_h64))>;
129}
130
131defm LoadStoreF32  : MVCLoadStore<load, f32,  MVCSequence, 4>;
132defm LoadStoreF64  : MVCLoadStore<load, f64,  MVCSequence, 8>;
133defm LoadStoreF128 : MVCLoadStore<load, f128, MVCSequence, 16>;
134
135//===----------------------------------------------------------------------===//
136// Load instructions
137//===----------------------------------------------------------------------===//
138
139let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in {
140  defm LE : UnaryRXPair<"le", 0x78, 0xED64, load, FP32, 4>;
141  defm LD : UnaryRXPair<"ld", 0x68, 0xED65, load, FP64, 8>;
142
143  // For z13 we prefer LDE over LE to avoid partial register dependencies.
144  let isCodeGenOnly = 1 in
145    def LDE32 : UnaryRXE<"lde", 0xED24, null_frag, FP32, 4>;
146
147  // These instructions are split after register allocation, so we don't
148  // want a custom inserter.
149  let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
150    def LX : Pseudo<(outs FP128:$dst), (ins bdxaddr20only128:$src),
151                     [(set FP128:$dst, (load bdxaddr20only128:$src))]>;
152  }
153}
154
155//===----------------------------------------------------------------------===//
156// Store instructions
157//===----------------------------------------------------------------------===//
158
159let SimpleBDXStore = 1, mayStore = 1 in {
160  defm STE : StoreRXPair<"ste", 0x70, 0xED66, store, FP32, 4>;
161  defm STD : StoreRXPair<"std", 0x60, 0xED67, store, FP64, 8>;
162
163  // These instructions are split after register allocation, so we don't
164  // want a custom inserter.
165  let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
166    def STX : Pseudo<(outs), (ins FP128:$src, bdxaddr20only128:$dst),
167                     [(store FP128:$src, bdxaddr20only128:$dst)]>;
168  }
169}
170
171//===----------------------------------------------------------------------===//
172// Conversion instructions
173//===----------------------------------------------------------------------===//
174
175// Convert floating-point values to narrower representations, rounding
176// according to the current mode.  The destination of LEXBR and LDXBR
177// is a 128-bit value, but only the first register of the pair is used.
178let Uses = [FPC], mayRaiseFPException = 1 in {
179  def LEDBR : UnaryRRE<"ledbr", 0xB344, any_fpround, FP32, FP64>;
180  def LEXBR : UnaryRRE<"lexbr", 0xB346, null_frag, FP128, FP128>;
181  def LDXBR : UnaryRRE<"ldxbr", 0xB345, null_frag, FP128, FP128>;
182
183  def LEDBRA : TernaryRRFe<"ledbra", 0xB344, FP32,  FP64>,
184               Requires<[FeatureFPExtension]>;
185  def LEXBRA : TernaryRRFe<"lexbra", 0xB346, FP128, FP128>,
186               Requires<[FeatureFPExtension]>;
187  def LDXBRA : TernaryRRFe<"ldxbra", 0xB345, FP128, FP128>,
188               Requires<[FeatureFPExtension]>;
189}
190
191let Predicates = [FeatureNoVectorEnhancements1] in {
192  def : Pat<(f32 (any_fpround FP128:$src)),
193            (EXTRACT_SUBREG (LEXBR FP128:$src), subreg_hh32)>;
194  def : Pat<(f64 (any_fpround FP128:$src)),
195            (EXTRACT_SUBREG (LDXBR FP128:$src), subreg_h64)>;
196}
197
198// Extend register floating-point values to wider representations.
199let Uses = [FPC], mayRaiseFPException = 1 in {
200  def LDEBR : UnaryRRE<"ldebr", 0xB304, any_fpextend, FP64, FP32>;
201  def LXEBR : UnaryRRE<"lxebr", 0xB306, null_frag, FP128, FP32>;
202  def LXDBR : UnaryRRE<"lxdbr", 0xB305, null_frag, FP128, FP64>;
203}
204let Predicates = [FeatureNoVectorEnhancements1] in {
205  def : Pat<(f128 (any_fpextend (f32 FP32:$src))), (LXEBR FP32:$src)>;
206  def : Pat<(f128 (any_fpextend (f64 FP64:$src))), (LXDBR FP64:$src)>;
207}
208
209// Extend memory floating-point values to wider representations.
210let Uses = [FPC], mayRaiseFPException = 1 in {
211  def LDEB : UnaryRXE<"ldeb", 0xED04, any_extloadf32, FP64, 4>;
212  def LXEB : UnaryRXE<"lxeb", 0xED06, null_frag, FP128, 4>;
213  def LXDB : UnaryRXE<"lxdb", 0xED05, null_frag, FP128, 8>;
214}
215let Predicates = [FeatureNoVectorEnhancements1] in {
216  def : Pat<(f128 (any_extloadf32 bdxaddr12only:$src)),
217            (LXEB bdxaddr12only:$src)>;
218  def : Pat<(f128 (any_extloadf64 bdxaddr12only:$src)),
219            (LXDB bdxaddr12only:$src)>;
220}
221
222// Convert a signed integer register value to a floating-point one.
223let Uses = [FPC], mayRaiseFPException = 1 in {
224  def CEFBR : UnaryRRE<"cefbr", 0xB394, any_sint_to_fp, FP32,  GR32>;
225  def CDFBR : UnaryRRE<"cdfbr", 0xB395, any_sint_to_fp, FP64,  GR32>;
226  def CXFBR : UnaryRRE<"cxfbr", 0xB396, any_sint_to_fp, FP128, GR32>;
227
228  def CEGBR : UnaryRRE<"cegbr", 0xB3A4, any_sint_to_fp, FP32,  GR64>;
229  def CDGBR : UnaryRRE<"cdgbr", 0xB3A5, any_sint_to_fp, FP64,  GR64>;
230  def CXGBR : UnaryRRE<"cxgbr", 0xB3A6, any_sint_to_fp, FP128, GR64>;
231}
232
233// The FP extension feature provides versions of the above that allow
234// specifying rounding mode and inexact-exception suppression flags.
235let Uses = [FPC], mayRaiseFPException = 1, Predicates = [FeatureFPExtension] in {
236  def CEFBRA : TernaryRRFe<"cefbra", 0xB394, FP32,  GR32>;
237  def CDFBRA : TernaryRRFe<"cdfbra", 0xB395, FP64,  GR32>;
238  def CXFBRA : TernaryRRFe<"cxfbra", 0xB396, FP128, GR32>;
239
240  def CEGBRA : TernaryRRFe<"cegbra", 0xB3A4, FP32,  GR64>;
241  def CDGBRA : TernaryRRFe<"cdgbra", 0xB3A5, FP64,  GR64>;
242  def CXGBRA : TernaryRRFe<"cxgbra", 0xB3A6, FP128, GR64>;
243}
244
245// Convert am unsigned integer register value to a floating-point one.
246let Predicates = [FeatureFPExtension] in {
247  let Uses = [FPC], mayRaiseFPException = 1 in {
248    def CELFBR : TernaryRRFe<"celfbr", 0xB390, FP32,  GR32>;
249    def CDLFBR : TernaryRRFe<"cdlfbr", 0xB391, FP64,  GR32>;
250    def CXLFBR : TernaryRRFe<"cxlfbr", 0xB392, FP128, GR32>;
251
252    def CELGBR : TernaryRRFe<"celgbr", 0xB3A0, FP32,  GR64>;
253    def CDLGBR : TernaryRRFe<"cdlgbr", 0xB3A1, FP64,  GR64>;
254    def CXLGBR : TernaryRRFe<"cxlgbr", 0xB3A2, FP128, GR64>;
255  }
256
257  def : Pat<(f32  (any_uint_to_fp GR32:$src)), (CELFBR 0, GR32:$src, 0)>;
258  def : Pat<(f64  (any_uint_to_fp GR32:$src)), (CDLFBR 0, GR32:$src, 0)>;
259  def : Pat<(f128 (any_uint_to_fp GR32:$src)), (CXLFBR 0, GR32:$src, 0)>;
260
261  def : Pat<(f32  (any_uint_to_fp GR64:$src)), (CELGBR 0, GR64:$src, 0)>;
262  def : Pat<(f64  (any_uint_to_fp GR64:$src)), (CDLGBR 0, GR64:$src, 0)>;
263  def : Pat<(f128 (any_uint_to_fp GR64:$src)), (CXLGBR 0, GR64:$src, 0)>;
264}
265
266// Convert a floating-point register value to a signed integer value,
267// with the second operand (modifier M3) specifying the rounding mode.
268let Uses = [FPC], mayRaiseFPException = 1, Defs = [CC] in {
269  def CFEBR : BinaryRRFe<"cfebr", 0xB398, GR32, FP32>;
270  def CFDBR : BinaryRRFe<"cfdbr", 0xB399, GR32, FP64>;
271  def CFXBR : BinaryRRFe<"cfxbr", 0xB39A, GR32, FP128>;
272
273  def CGEBR : BinaryRRFe<"cgebr", 0xB3A8, GR64, FP32>;
274  def CGDBR : BinaryRRFe<"cgdbr", 0xB3A9, GR64, FP64>;
275  def CGXBR : BinaryRRFe<"cgxbr", 0xB3AA, GR64, FP128>;
276}
277
278// fp_to_sint always rounds towards zero, which is modifier value 5.
279def : Pat<(i32 (any_fp_to_sint FP32:$src)),  (CFEBR 5, FP32:$src)>;
280def : Pat<(i32 (any_fp_to_sint FP64:$src)),  (CFDBR 5, FP64:$src)>;
281def : Pat<(i32 (any_fp_to_sint FP128:$src)), (CFXBR 5, FP128:$src)>;
282
283def : Pat<(i64 (any_fp_to_sint FP32:$src)),  (CGEBR 5, FP32:$src)>;
284def : Pat<(i64 (any_fp_to_sint FP64:$src)),  (CGDBR 5, FP64:$src)>;
285def : Pat<(i64 (any_fp_to_sint FP128:$src)), (CGXBR 5, FP128:$src)>;
286
287// The FP extension feature provides versions of the above that allow
288// also specifying the inexact-exception suppression flag.
289let Uses = [FPC], mayRaiseFPException = 1,
290    Predicates = [FeatureFPExtension], Defs = [CC] in {
291  def CFEBRA : TernaryRRFe<"cfebra", 0xB398, GR32, FP32>;
292  def CFDBRA : TernaryRRFe<"cfdbra", 0xB399, GR32, FP64>;
293  def CFXBRA : TernaryRRFe<"cfxbra", 0xB39A, GR32, FP128>;
294
295  def CGEBRA : TernaryRRFe<"cgebra", 0xB3A8, GR64, FP32>;
296  def CGDBRA : TernaryRRFe<"cgdbra", 0xB3A9, GR64, FP64>;
297  def CGXBRA : TernaryRRFe<"cgxbra", 0xB3AA, GR64, FP128>;
298}
299
300// Convert a floating-point register value to an unsigned integer value.
301let Predicates = [FeatureFPExtension] in {
302  let Uses = [FPC], mayRaiseFPException = 1, Defs = [CC] in {
303    def CLFEBR : TernaryRRFe<"clfebr", 0xB39C, GR32, FP32>;
304    def CLFDBR : TernaryRRFe<"clfdbr", 0xB39D, GR32, FP64>;
305    def CLFXBR : TernaryRRFe<"clfxbr", 0xB39E, GR32, FP128>;
306
307    def CLGEBR : TernaryRRFe<"clgebr", 0xB3AC, GR64, FP32>;
308    def CLGDBR : TernaryRRFe<"clgdbr", 0xB3AD, GR64, FP64>;
309    def CLGXBR : TernaryRRFe<"clgxbr", 0xB3AE, GR64, FP128>;
310  }
311
312  def : Pat<(i32 (any_fp_to_uint FP32:$src)),  (CLFEBR 5, FP32:$src,  0)>;
313  def : Pat<(i32 (any_fp_to_uint FP64:$src)),  (CLFDBR 5, FP64:$src,  0)>;
314  def : Pat<(i32 (any_fp_to_uint FP128:$src)), (CLFXBR 5, FP128:$src, 0)>;
315
316  def : Pat<(i64 (any_fp_to_uint FP32:$src)),  (CLGEBR 5, FP32:$src,  0)>;
317  def : Pat<(i64 (any_fp_to_uint FP64:$src)),  (CLGDBR 5, FP64:$src,  0)>;
318  def : Pat<(i64 (any_fp_to_uint FP128:$src)), (CLGXBR 5, FP128:$src, 0)>;
319}
320
321
322//===----------------------------------------------------------------------===//
323// Unary arithmetic
324//===----------------------------------------------------------------------===//
325
326// We prefer generic instructions during isel, because they do not
327// clobber CC and therefore give the scheduler more freedom. In cases
328// the CC is actually useful, the SystemZElimCompare pass will try to
329// convert generic instructions into opcodes that also set CC. Note
330// that lcdf / lpdf / lndf only affect the sign bit, and can therefore
331// be used with fp32 as well. This could be done for fp128, in which
332// case the operands would have to be tied.
333
334// Negation (Load Complement).
335let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
336  def LCEBR : UnaryRRE<"lcebr", 0xB303, null_frag, FP32,  FP32>;
337  def LCDBR : UnaryRRE<"lcdbr", 0xB313, null_frag, FP64,  FP64>;
338  def LCXBR : UnaryRRE<"lcxbr", 0xB343, fneg, FP128, FP128>;
339}
340// Generic form, which does not set CC.
341def LCDFR : UnaryRRE<"lcdfr", 0xB373, fneg, FP64,  FP64>;
342let isCodeGenOnly = 1 in
343  def LCDFR_32 : UnaryRRE<"lcdfr", 0xB373, fneg, FP32,  FP32>;
344
345// Absolute value (Load Positive).
346let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
347  def LPEBR : UnaryRRE<"lpebr", 0xB300, null_frag, FP32,  FP32>;
348  def LPDBR : UnaryRRE<"lpdbr", 0xB310, null_frag, FP64,  FP64>;
349  def LPXBR : UnaryRRE<"lpxbr", 0xB340, fabs, FP128, FP128>;
350}
351// Generic form, which does not set CC.
352def LPDFR : UnaryRRE<"lpdfr", 0xB370, fabs, FP64,  FP64>;
353let isCodeGenOnly = 1 in
354  def LPDFR_32 : UnaryRRE<"lpdfr", 0xB370, fabs, FP32,  FP32>;
355
356// Negative absolute value (Load Negative).
357let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
358  def LNEBR : UnaryRRE<"lnebr", 0xB301, null_frag, FP32,  FP32>;
359  def LNDBR : UnaryRRE<"lndbr", 0xB311, null_frag, FP64,  FP64>;
360  def LNXBR : UnaryRRE<"lnxbr", 0xB341, fnabs, FP128, FP128>;
361}
362// Generic form, which does not set CC.
363def LNDFR : UnaryRRE<"lndfr", 0xB371, fnabs, FP64,  FP64>;
364let isCodeGenOnly = 1 in
365  def LNDFR_32 : UnaryRRE<"lndfr", 0xB371, fnabs, FP32,  FP32>;
366
367// Square root.
368let Uses = [FPC], mayRaiseFPException = 1 in {
369  def SQEBR : UnaryRRE<"sqebr", 0xB314, any_fsqrt, FP32,  FP32>;
370  def SQDBR : UnaryRRE<"sqdbr", 0xB315, any_fsqrt, FP64,  FP64>;
371  def SQXBR : UnaryRRE<"sqxbr", 0xB316, any_fsqrt, FP128, FP128>;
372
373  def SQEB : UnaryRXE<"sqeb", 0xED14, loadu<any_fsqrt>, FP32, 4>;
374  def SQDB : UnaryRXE<"sqdb", 0xED15, loadu<any_fsqrt>, FP64, 8>;
375}
376
377// Round to an integer, with the second operand (modifier M3) specifying
378// the rounding mode.  These forms always check for inexact conditions.
379let Uses = [FPC], mayRaiseFPException = 1 in {
380  def FIEBR : BinaryRRFe<"fiebr", 0xB357, FP32,  FP32>;
381  def FIDBR : BinaryRRFe<"fidbr", 0xB35F, FP64,  FP64>;
382  def FIXBR : BinaryRRFe<"fixbr", 0xB347, FP128, FP128>;
383}
384
385// frint rounds according to the current mode (modifier 0) and detects
386// inexact conditions.
387def : Pat<(any_frint FP32:$src),  (FIEBR 0, FP32:$src)>;
388def : Pat<(any_frint FP64:$src),  (FIDBR 0, FP64:$src)>;
389def : Pat<(any_frint FP128:$src), (FIXBR 0, FP128:$src)>;
390
391let Predicates = [FeatureFPExtension] in {
392  // Extended forms of the FIxBR instructions.  M4 can be set to 4
393  // to suppress detection of inexact conditions.
394  let Uses = [FPC], mayRaiseFPException = 1 in {
395    def FIEBRA : TernaryRRFe<"fiebra", 0xB357, FP32,  FP32>;
396    def FIDBRA : TernaryRRFe<"fidbra", 0xB35F, FP64,  FP64>;
397    def FIXBRA : TernaryRRFe<"fixbra", 0xB347, FP128, FP128>;
398  }
399
400  // fnearbyint is like frint but does not detect inexact conditions.
401  def : Pat<(any_fnearbyint FP32:$src),  (FIEBRA 0, FP32:$src,  4)>;
402  def : Pat<(any_fnearbyint FP64:$src),  (FIDBRA 0, FP64:$src,  4)>;
403  def : Pat<(any_fnearbyint FP128:$src), (FIXBRA 0, FP128:$src, 4)>;
404
405  // floor is no longer allowed to raise an inexact condition,
406  // so restrict it to the cases where the condition can be suppressed.
407  // Mode 7 is round towards -inf.
408  def : Pat<(any_ffloor FP32:$src),  (FIEBRA 7, FP32:$src,  4)>;
409  def : Pat<(any_ffloor FP64:$src),  (FIDBRA 7, FP64:$src,  4)>;
410  def : Pat<(any_ffloor FP128:$src), (FIXBRA 7, FP128:$src, 4)>;
411
412  // Same idea for ceil, where mode 6 is round towards +inf.
413  def : Pat<(any_fceil FP32:$src),  (FIEBRA 6, FP32:$src,  4)>;
414  def : Pat<(any_fceil FP64:$src),  (FIDBRA 6, FP64:$src,  4)>;
415  def : Pat<(any_fceil FP128:$src), (FIXBRA 6, FP128:$src, 4)>;
416
417  // Same idea for trunc, where mode 5 is round towards zero.
418  def : Pat<(any_ftrunc FP32:$src),  (FIEBRA 5, FP32:$src,  4)>;
419  def : Pat<(any_ftrunc FP64:$src),  (FIDBRA 5, FP64:$src,  4)>;
420  def : Pat<(any_ftrunc FP128:$src), (FIXBRA 5, FP128:$src, 4)>;
421
422  // Same idea for round, where mode 1 is round towards nearest with
423  // ties away from zero.
424  def : Pat<(any_fround FP32:$src),  (FIEBRA 1, FP32:$src,  4)>;
425  def : Pat<(any_fround FP64:$src),  (FIDBRA 1, FP64:$src,  4)>;
426  def : Pat<(any_fround FP128:$src), (FIXBRA 1, FP128:$src, 4)>;
427}
428
429//===----------------------------------------------------------------------===//
430// Binary arithmetic
431//===----------------------------------------------------------------------===//
432
433// Addition.
434let Uses = [FPC], mayRaiseFPException = 1,
435    Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
436  let isCommutable = 1 in {
437    def AEBR : BinaryRRE<"aebr", 0xB30A, any_fadd, FP32,  FP32>;
438    def ADBR : BinaryRRE<"adbr", 0xB31A, any_fadd, FP64,  FP64>;
439    def AXBR : BinaryRRE<"axbr", 0xB34A, any_fadd, FP128, FP128>;
440  }
441  defm AEB : BinaryRXEAndPseudo<"aeb", 0xED0A, any_fadd, FP32, load, 4>;
442  defm ADB : BinaryRXEAndPseudo<"adb", 0xED1A, any_fadd, FP64, load, 8>;
443}
444
445// Subtraction.
446let Uses = [FPC], mayRaiseFPException = 1,
447    Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
448  def SEBR : BinaryRRE<"sebr", 0xB30B, any_fsub, FP32,  FP32>;
449  def SDBR : BinaryRRE<"sdbr", 0xB31B, any_fsub, FP64,  FP64>;
450  def SXBR : BinaryRRE<"sxbr", 0xB34B, any_fsub, FP128, FP128>;
451
452  defm SEB : BinaryRXEAndPseudo<"seb",  0xED0B, any_fsub, FP32, load, 4>;
453  defm SDB : BinaryRXEAndPseudo<"sdb",  0xED1B, any_fsub, FP64, load, 8>;
454}
455
456// Multiplication.
457let Uses = [FPC], mayRaiseFPException = 1 in {
458  let isCommutable = 1 in {
459    def MEEBR : BinaryRRE<"meebr", 0xB317, any_fmul, FP32,  FP32>;
460    def MDBR  : BinaryRRE<"mdbr",  0xB31C, any_fmul, FP64,  FP64>;
461    def MXBR  : BinaryRRE<"mxbr",  0xB34C, any_fmul, FP128, FP128>;
462  }
463  defm MEEB : BinaryRXEAndPseudo<"meeb", 0xED17, any_fmul, FP32, load, 4>;
464  defm MDB  : BinaryRXEAndPseudo<"mdb",  0xED1C, any_fmul, FP64, load, 8>;
465}
466
467// f64 multiplication of two FP32 registers.
468let Uses = [FPC], mayRaiseFPException = 1 in
469  def MDEBR : BinaryRRE<"mdebr", 0xB30C, null_frag, FP64, FP32>;
470def : Pat<(any_fmul (f64 (any_fpextend FP32:$src1)),
471                    (f64 (any_fpextend FP32:$src2))),
472          (MDEBR (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
473                                FP32:$src1, subreg_h32), FP32:$src2)>;
474
475// f64 multiplication of an FP32 register and an f32 memory.
476let Uses = [FPC], mayRaiseFPException = 1 in
477  def MDEB : BinaryRXE<"mdeb", 0xED0C, null_frag, FP64, load, 4>;
478def : Pat<(any_fmul (f64 (any_fpextend FP32:$src1)),
479                    (f64 (any_extloadf32 bdxaddr12only:$addr))),
480          (MDEB (INSERT_SUBREG (f64 (IMPLICIT_DEF)), FP32:$src1, subreg_h32),
481                bdxaddr12only:$addr)>;
482
483// f128 multiplication of two FP64 registers.
484let Uses = [FPC], mayRaiseFPException = 1 in
485  def MXDBR : BinaryRRE<"mxdbr", 0xB307, null_frag, FP128, FP64>;
486let Predicates = [FeatureNoVectorEnhancements1] in
487  def : Pat<(any_fmul (f128 (any_fpextend FP64:$src1)),
488                      (f128 (any_fpextend FP64:$src2))),
489            (MXDBR (INSERT_SUBREG (f128 (IMPLICIT_DEF)),
490                                  FP64:$src1, subreg_h64), FP64:$src2)>;
491
492// f128 multiplication of an FP64 register and an f64 memory.
493let Uses = [FPC], mayRaiseFPException = 1 in
494  def MXDB : BinaryRXE<"mxdb", 0xED07, null_frag, FP128, load, 8>;
495let Predicates = [FeatureNoVectorEnhancements1] in
496  def : Pat<(any_fmul (f128 (any_fpextend FP64:$src1)),
497                      (f128 (any_extloadf64 bdxaddr12only:$addr))),
498            (MXDB (INSERT_SUBREG (f128 (IMPLICIT_DEF)), FP64:$src1, subreg_h64),
499                  bdxaddr12only:$addr)>;
500
501// Fused multiply-add.
502let Uses = [FPC], mayRaiseFPException = 1 in {
503  def MAEBR : TernaryRRD<"maebr", 0xB30E, z_any_fma, FP32, FP32>;
504  def MADBR : TernaryRRD<"madbr", 0xB31E, z_any_fma, FP64, FP64>;
505
506  defm MAEB : TernaryRXFAndPseudo<"maeb", 0xED0E, z_any_fma, FP32, FP32, load, 4>;
507  defm MADB : TernaryRXFAndPseudo<"madb", 0xED1E, z_any_fma, FP64, FP64, load, 8>;
508}
509
510// Fused multiply-subtract.
511let Uses = [FPC], mayRaiseFPException = 1 in {
512  def MSEBR : TernaryRRD<"msebr", 0xB30F, z_any_fms, FP32, FP32>;
513  def MSDBR : TernaryRRD<"msdbr", 0xB31F, z_any_fms, FP64, FP64>;
514
515  defm MSEB : TernaryRXFAndPseudo<"mseb", 0xED0F, z_any_fms, FP32, FP32, load, 4>;
516  defm MSDB : TernaryRXFAndPseudo<"msdb", 0xED1F, z_any_fms, FP64, FP64, load, 8>;
517}
518
519// Division.
520let Uses = [FPC], mayRaiseFPException = 1 in {
521  def DEBR : BinaryRRE<"debr", 0xB30D, any_fdiv, FP32,  FP32>;
522  def DDBR : BinaryRRE<"ddbr", 0xB31D, any_fdiv, FP64,  FP64>;
523  def DXBR : BinaryRRE<"dxbr", 0xB34D, any_fdiv, FP128, FP128>;
524
525  defm DEB : BinaryRXEAndPseudo<"deb", 0xED0D, any_fdiv, FP32, load, 4>;
526  defm DDB : BinaryRXEAndPseudo<"ddb", 0xED1D, any_fdiv, FP64, load, 8>;
527}
528
529// Divide to integer.
530let Uses = [FPC], mayRaiseFPException = 1, Defs = [CC] in {
531  def DIEBR : TernaryRRFb<"diebr", 0xB353, FP32, FP32, FP32>;
532  def DIDBR : TernaryRRFb<"didbr", 0xB35B, FP64, FP64, FP64>;
533}
534
535//===----------------------------------------------------------------------===//
536// Comparisons
537//===----------------------------------------------------------------------===//
538
539let Uses = [FPC], mayRaiseFPException = 1, Defs = [CC], CCValues = 0xF in {
540  def CEBR : CompareRRE<"cebr", 0xB309, z_any_fcmp, FP32,  FP32>;
541  def CDBR : CompareRRE<"cdbr", 0xB319, z_any_fcmp, FP64,  FP64>;
542  def CXBR : CompareRRE<"cxbr", 0xB349, z_any_fcmp, FP128, FP128>;
543
544  def CEB : CompareRXE<"ceb", 0xED09, z_any_fcmp, FP32, load, 4>;
545  def CDB : CompareRXE<"cdb", 0xED19, z_any_fcmp, FP64, load, 8>;
546
547  def KEBR : CompareRRE<"kebr", 0xB308, z_strict_fcmps, FP32,  FP32>;
548  def KDBR : CompareRRE<"kdbr", 0xB318, z_strict_fcmps, FP64,  FP64>;
549  def KXBR : CompareRRE<"kxbr", 0xB348, z_strict_fcmps, FP128, FP128>;
550
551  def KEB : CompareRXE<"keb", 0xED08, z_strict_fcmps, FP32, load, 4>;
552  def KDB : CompareRXE<"kdb", 0xED18, z_strict_fcmps, FP64, load, 8>;
553}
554
555// Test Data Class.
556let Defs = [CC], CCValues = 0xC in {
557  def TCEB : TestRXE<"tceb", 0xED10, z_tdc, FP32>;
558  def TCDB : TestRXE<"tcdb", 0xED11, z_tdc, FP64>;
559  def TCXB : TestRXE<"tcxb", 0xED12, z_tdc, FP128>;
560}
561
562//===----------------------------------------------------------------------===//
563// Floating-point control register instructions
564//===----------------------------------------------------------------------===//
565
566let hasSideEffects = 1 in {
567  let mayLoad = 1, mayStore = 1 in {
568    // TODO: EFPC and SFPC do not touch memory at all
569    let Uses = [FPC] in {
570      def EFPC  : InherentRRE<"efpc", 0xB38C, GR32, int_s390_efpc>;
571      def STFPC : StoreInherentS<"stfpc", 0xB29C, storei<int_s390_efpc>, 4>;
572    }
573
574    let Defs = [FPC] in {
575      def SFPC : SideEffectUnaryRRE<"sfpc", 0xB384, GR32, int_s390_sfpc>;
576      def LFPC : SideEffectUnaryS<"lfpc", 0xB29D, loadu<int_s390_sfpc>, 4>;
577    }
578  }
579
580  let Defs = [FPC], mayRaiseFPException = 1 in {
581    def SFASR : SideEffectUnaryRRE<"sfasr", 0xB385, GR32, null_frag>;
582    def LFAS  : SideEffectUnaryS<"lfas", 0xB2BD, null_frag, 4>;
583  }
584
585  let Uses = [FPC], Defs = [FPC] in {
586    def SRNMB : SideEffectAddressS<"srnmb", 0xB2B8, null_frag, shift12only>,
587                Requires<[FeatureFPExtension]>;
588    def SRNM  : SideEffectAddressS<"srnm", 0xB299, null_frag, shift12only>;
589    def SRNMT : SideEffectAddressS<"srnmt", 0xB2B9, null_frag, shift12only>;
590  }
591}
592
593//===----------------------------------------------------------------------===//
594// Peepholes
595//===----------------------------------------------------------------------===//
596
597def : Pat<(f32  fpimmneg0), (LCDFR_32 (LZER))>;
598def : Pat<(f64  fpimmneg0), (LCDFR (LZDR))>;
599def : Pat<(f128 fpimmneg0), (LCXBR (LZXR))>;
600