1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the X86 specific subclass of TargetMachine.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "X86TargetMachine.h"
14 #include "MCTargetDesc/X86MCTargetDesc.h"
15 #include "TargetInfo/X86TargetInfo.h"
16 #include "X86.h"
17 #include "X86CallLowering.h"
18 #include "X86LegalizerInfo.h"
19 #include "X86MacroFusion.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetObjectFile.h"
22 #include "X86TargetTransformInfo.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/Analysis/TargetTransformInfo.h"
29 #include "llvm/CodeGen/ExecutionDomainFix.h"
30 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
31 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
32 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
33 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
34 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
35 #include "llvm/CodeGen/MachineScheduler.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/TargetPassConfig.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/MC/MCAsmInfo.h"
42 #include "llvm/Pass.h"
43 #include "llvm/Support/CodeGen.h"
44 #include "llvm/Support/CommandLine.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/Support/TargetRegistry.h"
47 #include "llvm/Target/TargetLoweringObjectFile.h"
48 #include "llvm/Target/TargetOptions.h"
49 #include "llvm/Transforms/CFGuard.h"
50 #include <memory>
51 #include <string>
52
53 using namespace llvm;
54
55 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
56 cl::desc("Enable the machine combiner pass"),
57 cl::init(true), cl::Hidden);
58
LLVMInitializeX86Target()59 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Target() {
60 // Register the target.
61 RegisterTargetMachine<X86TargetMachine> X(getTheX86_32Target());
62 RegisterTargetMachine<X86TargetMachine> Y(getTheX86_64Target());
63
64 PassRegistry &PR = *PassRegistry::getPassRegistry();
65 initializeGlobalISel(PR);
66 initializeWinEHStatePassPass(PR);
67 initializeFixupBWInstPassPass(PR);
68 initializeEvexToVexInstPassPass(PR);
69 initializeFixupLEAPassPass(PR);
70 initializeFPSPass(PR);
71 initializeX86FixupSetCCPassPass(PR);
72 initializeX86CallFrameOptimizationPass(PR);
73 initializeX86CmovConverterPassPass(PR);
74 initializeX86ExpandPseudoPass(PR);
75 initializeX86ExecutionDomainFixPass(PR);
76 initializeX86DomainReassignmentPass(PR);
77 initializeX86AvoidSFBPassPass(PR);
78 initializeX86AvoidTrailingCallPassPass(PR);
79 initializeX86SpeculativeLoadHardeningPassPass(PR);
80 initializeX86SpeculativeExecutionSideEffectSuppressionPass(PR);
81 initializeX86FlagsCopyLoweringPassPass(PR);
82 initializeX86LoadValueInjectionLoadHardeningPassPass(PR);
83 initializeX86LoadValueInjectionRetHardeningPassPass(PR);
84 initializeX86OptimizeLEAPassPass(PR);
85 initializeX86PartialReductionPass(PR);
86 }
87
createTLOF(const Triple & TT)88 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
89 if (TT.isOSBinFormatMachO()) {
90 if (TT.getArch() == Triple::x86_64)
91 return std::make_unique<X86_64MachoTargetObjectFile>();
92 return std::make_unique<TargetLoweringObjectFileMachO>();
93 }
94
95 if (TT.isOSBinFormatCOFF())
96 return std::make_unique<TargetLoweringObjectFileCOFF>();
97 return std::make_unique<X86ELFTargetObjectFile>();
98 }
99
computeDataLayout(const Triple & TT)100 static std::string computeDataLayout(const Triple &TT) {
101 // X86 is little endian
102 std::string Ret = "e";
103
104 Ret += DataLayout::getManglingComponent(TT);
105 // X86 and x32 have 32 bit pointers.
106 if ((TT.isArch64Bit() &&
107 (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
108 !TT.isArch64Bit())
109 Ret += "-p:32:32";
110
111 // Address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers.
112 Ret += "-p270:32:32-p271:32:32-p272:64:64";
113
114 // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
115 if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
116 Ret += "-i64:64";
117 else if (TT.isOSIAMCU())
118 Ret += "-i64:32-f64:32";
119 else
120 Ret += "-f64:32:64";
121
122 // Some ABIs align long double to 128 bits, others to 32.
123 if (TT.isOSNaCl() || TT.isOSIAMCU())
124 ; // No f80
125 else if (TT.isArch64Bit() || TT.isOSDarwin())
126 Ret += "-f80:128";
127 else
128 Ret += "-f80:32";
129
130 if (TT.isOSIAMCU())
131 Ret += "-f128:32";
132
133 // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
134 if (TT.isArch64Bit())
135 Ret += "-n8:16:32:64";
136 else
137 Ret += "-n8:16:32";
138
139 // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
140 if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
141 Ret += "-a:0:32-S32";
142 else
143 Ret += "-S128";
144
145 return Ret;
146 }
147
getEffectiveRelocModel(const Triple & TT,bool JIT,Optional<Reloc::Model> RM)148 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
149 bool JIT,
150 Optional<Reloc::Model> RM) {
151 bool is64Bit = TT.getArch() == Triple::x86_64;
152 if (!RM.hasValue()) {
153 // JIT codegen should use static relocations by default, since it's
154 // typically executed in process and not relocatable.
155 if (JIT)
156 return Reloc::Static;
157
158 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
159 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
160 // use static relocation model by default.
161 if (TT.isOSDarwin()) {
162 if (is64Bit)
163 return Reloc::PIC_;
164 return Reloc::DynamicNoPIC;
165 }
166 if (TT.isOSWindows() && is64Bit)
167 return Reloc::PIC_;
168 return Reloc::Static;
169 }
170
171 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
172 // is defined as a model for code which may be used in static or dynamic
173 // executables but not necessarily a shared library. On X86-32 we just
174 // compile in -static mode, in x86-64 we use PIC.
175 if (*RM == Reloc::DynamicNoPIC) {
176 if (is64Bit)
177 return Reloc::PIC_;
178 if (!TT.isOSDarwin())
179 return Reloc::Static;
180 }
181
182 // If we are on Darwin, disallow static relocation model in X86-64 mode, since
183 // the Mach-O file format doesn't support it.
184 if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
185 return Reloc::PIC_;
186
187 return *RM;
188 }
189
getEffectiveX86CodeModel(Optional<CodeModel::Model> CM,bool JIT,bool Is64Bit)190 static CodeModel::Model getEffectiveX86CodeModel(Optional<CodeModel::Model> CM,
191 bool JIT, bool Is64Bit) {
192 if (CM) {
193 if (*CM == CodeModel::Tiny)
194 report_fatal_error("Target does not support the tiny CodeModel", false);
195 return *CM;
196 }
197 if (JIT)
198 return Is64Bit ? CodeModel::Large : CodeModel::Small;
199 return CodeModel::Small;
200 }
201
202 /// Create an X86 target.
203 ///
X86TargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Optional<Reloc::Model> RM,Optional<CodeModel::Model> CM,CodeGenOpt::Level OL,bool JIT)204 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
205 StringRef CPU, StringRef FS,
206 const TargetOptions &Options,
207 Optional<Reloc::Model> RM,
208 Optional<CodeModel::Model> CM,
209 CodeGenOpt::Level OL, bool JIT)
210 : LLVMTargetMachine(
211 T, computeDataLayout(TT), TT, CPU, FS, Options,
212 getEffectiveRelocModel(TT, JIT, RM),
213 getEffectiveX86CodeModel(CM, JIT, TT.getArch() == Triple::x86_64),
214 OL),
215 TLOF(createTLOF(getTargetTriple())), IsJIT(JIT) {
216 // On PS4, the "return address" of a 'noreturn' call must still be within
217 // the calling function, and TrapUnreachable is an easy way to get that.
218 if (TT.isPS4() || TT.isOSBinFormatMachO()) {
219 this->Options.TrapUnreachable = true;
220 this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
221 }
222
223 setMachineOutliner(true);
224
225 // x86 supports the debug entry values.
226 setSupportsDebugEntryValues(true);
227
228 initAsmInfo();
229 }
230
231 X86TargetMachine::~X86TargetMachine() = default;
232
233 const X86Subtarget *
getSubtargetImpl(const Function & F) const234 X86TargetMachine::getSubtargetImpl(const Function &F) const {
235 Attribute CPUAttr = F.getFnAttribute("target-cpu");
236 Attribute TuneAttr = F.getFnAttribute("tune-cpu");
237 Attribute FSAttr = F.getFnAttribute("target-features");
238
239 StringRef CPU =
240 CPUAttr.isValid() ? CPUAttr.getValueAsString() : (StringRef)TargetCPU;
241 StringRef TuneCPU =
242 TuneAttr.isValid() ? TuneAttr.getValueAsString() : (StringRef)CPU;
243 StringRef FS =
244 FSAttr.isValid() ? FSAttr.getValueAsString() : (StringRef)TargetFS;
245
246 SmallString<512> Key;
247 // The additions here are ordered so that the definitely short strings are
248 // added first so we won't exceed the small size. We append the
249 // much longer FS string at the end so that we only heap allocate at most
250 // one time.
251
252 // Extract prefer-vector-width attribute.
253 unsigned PreferVectorWidthOverride = 0;
254 Attribute PreferVecWidthAttr = F.getFnAttribute("prefer-vector-width");
255 if (PreferVecWidthAttr.isValid()) {
256 StringRef Val = PreferVecWidthAttr.getValueAsString();
257 unsigned Width;
258 if (!Val.getAsInteger(0, Width)) {
259 Key += "prefer-vector-width=";
260 Key += Val;
261 PreferVectorWidthOverride = Width;
262 }
263 }
264
265 // Extract min-legal-vector-width attribute.
266 unsigned RequiredVectorWidth = UINT32_MAX;
267 Attribute MinLegalVecWidthAttr = F.getFnAttribute("min-legal-vector-width");
268 if (MinLegalVecWidthAttr.isValid()) {
269 StringRef Val = MinLegalVecWidthAttr.getValueAsString();
270 unsigned Width;
271 if (!Val.getAsInteger(0, Width)) {
272 Key += "min-legal-vector-width=";
273 Key += Val;
274 RequiredVectorWidth = Width;
275 }
276 }
277
278 // Add CPU to the Key.
279 Key += CPU;
280
281 // Add tune CPU to the Key.
282 Key += "tune=";
283 Key += TuneCPU;
284
285 // Keep track of the start of the feature portion of the string.
286 unsigned FSStart = Key.size();
287
288 // FIXME: This is related to the code below to reset the target options,
289 // we need to know whether or not the soft float flag is set on the
290 // function before we can generate a subtarget. We also need to use
291 // it as a key for the subtarget since that can be the only difference
292 // between two functions.
293 bool SoftFloat =
294 F.getFnAttribute("use-soft-float").getValueAsString() == "true";
295 // If the soft float attribute is set on the function turn on the soft float
296 // subtarget feature.
297 if (SoftFloat)
298 Key += FS.empty() ? "+soft-float" : "+soft-float,";
299
300 Key += FS;
301
302 // We may have added +soft-float to the features so move the StringRef to
303 // point to the full string in the Key.
304 FS = Key.substr(FSStart);
305
306 auto &I = SubtargetMap[Key];
307 if (!I) {
308 // This needs to be done before we create a new subtarget since any
309 // creation will depend on the TM and the code generation flags on the
310 // function that reside in TargetOptions.
311 resetTargetOptions(F);
312 I = std::make_unique<X86Subtarget>(
313 TargetTriple, CPU, TuneCPU, FS, *this,
314 MaybeAlign(Options.StackAlignmentOverride), PreferVectorWidthOverride,
315 RequiredVectorWidth);
316 }
317 return I.get();
318 }
319
isNoopAddrSpaceCast(unsigned SrcAS,unsigned DestAS) const320 bool X86TargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
321 unsigned DestAS) const {
322 assert(SrcAS != DestAS && "Expected different address spaces!");
323 if (getPointerSize(SrcAS) != getPointerSize(DestAS))
324 return false;
325 return SrcAS < 256 && DestAS < 256;
326 }
327
328 //===----------------------------------------------------------------------===//
329 // X86 TTI query.
330 //===----------------------------------------------------------------------===//
331
332 TargetTransformInfo
getTargetTransformInfo(const Function & F)333 X86TargetMachine::getTargetTransformInfo(const Function &F) {
334 return TargetTransformInfo(X86TTIImpl(this, F));
335 }
336
337 //===----------------------------------------------------------------------===//
338 // Pass Pipeline Configuration
339 //===----------------------------------------------------------------------===//
340
341 namespace {
342
343 /// X86 Code Generator Pass Configuration Options.
344 class X86PassConfig : public TargetPassConfig {
345 public:
X86PassConfig(X86TargetMachine & TM,PassManagerBase & PM)346 X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
347 : TargetPassConfig(TM, PM) {}
348
getX86TargetMachine() const349 X86TargetMachine &getX86TargetMachine() const {
350 return getTM<X86TargetMachine>();
351 }
352
353 ScheduleDAGInstrs *
createMachineScheduler(MachineSchedContext * C) const354 createMachineScheduler(MachineSchedContext *C) const override {
355 ScheduleDAGMILive *DAG = createGenericSchedLive(C);
356 DAG->addMutation(createX86MacroFusionDAGMutation());
357 return DAG;
358 }
359
360 ScheduleDAGInstrs *
createPostMachineScheduler(MachineSchedContext * C) const361 createPostMachineScheduler(MachineSchedContext *C) const override {
362 ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
363 DAG->addMutation(createX86MacroFusionDAGMutation());
364 return DAG;
365 }
366
367 void addIRPasses() override;
368 bool addInstSelector() override;
369 bool addIRTranslator() override;
370 bool addLegalizeMachineIR() override;
371 bool addRegBankSelect() override;
372 bool addGlobalInstructionSelect() override;
373 bool addILPOpts() override;
374 bool addPreISel() override;
375 void addMachineSSAOptimization() override;
376 void addPreRegAlloc() override;
377 void addPostRegAlloc() override;
378 void addPreEmitPass() override;
379 void addPreEmitPass2() override;
380 void addPreSched2() override;
381
382 std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
383 };
384
385 class X86ExecutionDomainFix : public ExecutionDomainFix {
386 public:
387 static char ID;
X86ExecutionDomainFix()388 X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
getPassName() const389 StringRef getPassName() const override {
390 return "X86 Execution Dependency Fix";
391 }
392 };
393 char X86ExecutionDomainFix::ID;
394
395 } // end anonymous namespace
396
397 INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
398 "X86 Execution Domain Fix", false, false)
INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)399 INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
400 INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
401 "X86 Execution Domain Fix", false, false)
402
403 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
404 return new X86PassConfig(*this, PM);
405 }
406
addIRPasses()407 void X86PassConfig::addIRPasses() {
408 addPass(createAtomicExpandPass());
409
410 TargetPassConfig::addIRPasses();
411
412 if (TM->getOptLevel() != CodeGenOpt::None) {
413 addPass(createInterleavedAccessPass());
414 addPass(createX86PartialReductionPass());
415 }
416
417 // Add passes that handle indirect branch removal and insertion of a retpoline
418 // thunk. These will be a no-op unless a function subtarget has the retpoline
419 // feature enabled.
420 addPass(createIndirectBrExpandPass());
421
422 // Add Control Flow Guard checks.
423 const Triple &TT = TM->getTargetTriple();
424 if (TT.isOSWindows()) {
425 if (TT.getArch() == Triple::x86_64) {
426 addPass(createCFGuardDispatchPass());
427 } else {
428 addPass(createCFGuardCheckPass());
429 }
430 }
431 }
432
addInstSelector()433 bool X86PassConfig::addInstSelector() {
434 // Install an instruction selector.
435 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
436
437 // For ELF, cleanup any local-dynamic TLS accesses.
438 if (TM->getTargetTriple().isOSBinFormatELF() &&
439 getOptLevel() != CodeGenOpt::None)
440 addPass(createCleanupLocalDynamicTLSPass());
441
442 addPass(createX86GlobalBaseRegPass());
443 return false;
444 }
445
addIRTranslator()446 bool X86PassConfig::addIRTranslator() {
447 addPass(new IRTranslator(getOptLevel()));
448 return false;
449 }
450
addLegalizeMachineIR()451 bool X86PassConfig::addLegalizeMachineIR() {
452 addPass(new Legalizer());
453 return false;
454 }
455
addRegBankSelect()456 bool X86PassConfig::addRegBankSelect() {
457 addPass(new RegBankSelect());
458 return false;
459 }
460
addGlobalInstructionSelect()461 bool X86PassConfig::addGlobalInstructionSelect() {
462 addPass(new InstructionSelect());
463 return false;
464 }
465
addILPOpts()466 bool X86PassConfig::addILPOpts() {
467 addPass(&EarlyIfConverterID);
468 if (EnableMachineCombinerPass)
469 addPass(&MachineCombinerID);
470 addPass(createX86CmovConverterPass());
471 return true;
472 }
473
addPreISel()474 bool X86PassConfig::addPreISel() {
475 // Only add this pass for 32-bit x86 Windows.
476 const Triple &TT = TM->getTargetTriple();
477 if (TT.isOSWindows() && TT.getArch() == Triple::x86)
478 addPass(createX86WinEHStatePass());
479 return true;
480 }
481
addPreRegAlloc()482 void X86PassConfig::addPreRegAlloc() {
483 if (getOptLevel() != CodeGenOpt::None) {
484 addPass(&LiveRangeShrinkID);
485 addPass(createX86FixupSetCC());
486 addPass(createX86OptimizeLEAs());
487 addPass(createX86CallFrameOptimization());
488 addPass(createX86AvoidStoreForwardingBlocks());
489 }
490
491 addPass(createX86SpeculativeLoadHardeningPass());
492 addPass(createX86FlagsCopyLoweringPass());
493 addPass(createX86WinAllocaExpander());
494 }
addMachineSSAOptimization()495 void X86PassConfig::addMachineSSAOptimization() {
496 addPass(createX86DomainReassignmentPass());
497 TargetPassConfig::addMachineSSAOptimization();
498 }
499
addPostRegAlloc()500 void X86PassConfig::addPostRegAlloc() {
501 addPass(createX86FloatingPointStackifierPass());
502 // When -O0 is enabled, the Load Value Injection Hardening pass will fall back
503 // to using the Speculative Execution Side Effect Suppression pass for
504 // mitigation. This is to prevent slow downs due to
505 // analyses needed by the LVIHardening pass when compiling at -O0.
506 if (getOptLevel() != CodeGenOpt::None)
507 addPass(createX86LoadValueInjectionLoadHardeningPass());
508 }
509
addPreSched2()510 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
511
addPreEmitPass()512 void X86PassConfig::addPreEmitPass() {
513 if (getOptLevel() != CodeGenOpt::None) {
514 addPass(new X86ExecutionDomainFix());
515 addPass(createBreakFalseDeps());
516 }
517
518 addPass(createX86IndirectBranchTrackingPass());
519
520 addPass(createX86IssueVZeroUpperPass());
521
522 if (getOptLevel() != CodeGenOpt::None) {
523 addPass(createX86FixupBWInsts());
524 addPass(createX86PadShortFunctions());
525 addPass(createX86FixupLEAs());
526 }
527 addPass(createX86EvexToVexInsts());
528 addPass(createX86DiscriminateMemOpsPass());
529 addPass(createX86InsertPrefetchPass());
530 addPass(createX86InsertX87waitPass());
531 }
532
addPreEmitPass2()533 void X86PassConfig::addPreEmitPass2() {
534 const Triple &TT = TM->getTargetTriple();
535 const MCAsmInfo *MAI = TM->getMCAsmInfo();
536
537 // The X86 Speculative Execution Pass must run after all control
538 // flow graph modifying passes. As a result it was listed to run right before
539 // the X86 Retpoline Thunks pass. The reason it must run after control flow
540 // graph modifications is that the model of LFENCE in LLVM has to be updated
541 // (FIXME: https://bugs.llvm.org/show_bug.cgi?id=45167). Currently the
542 // placement of this pass was hand checked to ensure that the subsequent
543 // passes don't move the code around the LFENCEs in a way that will hurt the
544 // correctness of this pass. This placement has been shown to work based on
545 // hand inspection of the codegen output.
546 addPass(createX86SpeculativeExecutionSideEffectSuppression());
547 addPass(createX86IndirectThunksPass());
548
549 // Insert extra int3 instructions after trailing call instructions to avoid
550 // issues in the unwinder.
551 if (TT.isOSWindows() && TT.getArch() == Triple::x86_64)
552 addPass(createX86AvoidTrailingCallPass());
553
554 // Verify basic block incoming and outgoing cfa offset and register values and
555 // correct CFA calculation rule where needed by inserting appropriate CFI
556 // instructions.
557 if (!TT.isOSDarwin() &&
558 (!TT.isOSWindows() ||
559 MAI->getExceptionHandlingType() == ExceptionHandling::DwarfCFI))
560 addPass(createCFIInstrInserter());
561 // Identify valid longjmp targets for Windows Control Flow Guard.
562 if (TT.isOSWindows())
563 addPass(createCFGuardLongjmpPass());
564 addPass(createX86LoadValueInjectionRetHardeningPass());
565 }
566
getCSEConfig() const567 std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig() const {
568 return getStandardCSEConfigForOpt(TM->getOptLevel());
569 }
570