1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck %s
3
4---
5name: test_sext_trunc_v2s32_to_v2s16_to_v2s32
6body: |
7  bb.0:
8    liveins: $vgpr0_vgpr1
9
10    ; CHECK-LABEL: name: test_sext_trunc_v2s32_to_v2s16_to_v2s32
11    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
12    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY [[COPY]](<2 x s32>)
13    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
14    ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 16
15    ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 16
16    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
17    ; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
18    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
19    %1:_(<2 x s16>) = G_TRUNC %0
20    %2:_(<2 x s32>) = G_SEXT %1
21    $vgpr0_vgpr1 = COPY %2
22...
23
24---
25name: test_sext_trunc_v2s32_to_v2s16_to_v2s64
26body: |
27  bb.0:
28    liveins: $vgpr0_vgpr1
29
30    ; CHECK-LABEL: name: test_sext_trunc_v2s32_to_v2s16_to_v2s64
31    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
32    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
33    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UV]](s32)
34    ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[UV1]](s32)
35    ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ANYEXT]], 16
36    ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ANYEXT1]], 16
37    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SEXT_INREG]](s64), [[SEXT_INREG1]](s64)
38    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
39    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
40    %1:_(<2 x s16>) = G_TRUNC %0
41    %2:_(<2 x s64>) = G_SEXT %1
42    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
43...
44
45---
46name: test_sext_trunc_v2s32_to_v2s8_to_v2s16
47body: |
48  bb.0:
49    liveins: $vgpr0_vgpr1
50
51    ; The G_SEXT_INREG doesn't lower here because G_TRUNC is both illegal and
52    ; unable to legalize. This prevents further legalization.
53    ; CHECK-LABEL: name: test_sext_trunc_v2s32_to_v2s8_to_v2s16
54    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
55    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
56    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
57    ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
58    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
59    ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
60    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
61    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG]](s32)
62    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
63    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG1]](s32)
64    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
65    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
66    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
67    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
68    ; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
69    ; CHECK: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
70    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
71    %1:_(<2 x s8>) = G_TRUNC %0
72    %2:_(<2 x s16>) = G_SEXT %1
73    $vgpr0 = COPY %2
74...
75
76---
77name: test_sext_trunc_v3s32_to_v3s16_to_v3s32
78body: |
79  bb.0:
80    liveins: $vgpr0_vgpr1_vgpr2
81
82    ; CHECK-LABEL: name: test_sext_trunc_v3s32_to_v3s16_to_v3s32
83    ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
84    ; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
85    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
86    ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 16
87    ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 16
88    ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 16
89    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
90    ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
91    %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
92    %1:_(<3 x s16>) = G_TRUNC %0
93    %2:_(<3 x s32>) = G_SEXT %1
94    $vgpr0_vgpr1_vgpr2 = COPY %2
95...
96