1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -march=amdgcn -mcpu=tahiti -denormal-fp-math-f32=ieee -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s 3# RUN: llc -march=amdgcn -mcpu=tahiti -denormal-fp-math-f32=preserve-sign -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s 4# RUN: llc -march=amdgcn -mcpu=gfx900 -denormal-fp-math-f32=ieee -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s 5# RUN: llc -march=amdgcn -mcpu=gfx900 -denormal-fp-math-f32=preserve-sign -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s 6 7--- 8name: fmad_ftz_s32_vvvv 9legalized: true 10regBankSelected: true 11tracksRegLiveness: true 12 13body: | 14 bb.0: 15 liveins: $vgpr0, $vgpr1, $vgpr2 16 17 ; GCN-LABEL: name: fmad_ftz_s32_vvvv 18 ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2 19 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 20 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 21 ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 22 ; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec 23 ; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]] 24 %0:vgpr(s32) = COPY $vgpr0 25 %1:vgpr(s32) = COPY $vgpr1 26 %2:vgpr(s32) = COPY $vgpr2 27 %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %1, %2 28 S_ENDPGM 0, implicit %3 29... 30 31--- 32name: fmad_ftz_s32_vsvv 33legalized: true 34regBankSelected: true 35tracksRegLiveness: true 36 37body: | 38 bb.0: 39 liveins: $sgpr0, $vgpr0, $vgpr1 40 41 ; GCN-LABEL: name: fmad_ftz_s32_vsvv 42 ; GCN: liveins: $sgpr0, $vgpr0, $vgpr1 43 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 44 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 45 ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 46 ; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec 47 ; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]] 48 %0:sgpr(s32) = COPY $sgpr0 49 %1:vgpr(s32) = COPY $vgpr0 50 %2:vgpr(s32) = COPY $vgpr1 51 %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %1, %2 52 S_ENDPGM 0, implicit %3 53... 54 55--- 56name: fmad_ftz_s32_vvsv 57legalized: true 58regBankSelected: true 59tracksRegLiveness: true 60 61body: | 62 bb.0: 63 liveins: $sgpr0, $vgpr0, $vgpr1 64 65 ; GCN-LABEL: name: fmad_ftz_s32_vvsv 66 ; GCN: liveins: $sgpr0, $vgpr0, $vgpr1 67 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 68 ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 69 ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 70 ; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec 71 ; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]] 72 %0:vgpr(s32) = COPY $vgpr0 73 %1:sgpr(s32) = COPY $sgpr0 74 %2:vgpr(s32) = COPY $vgpr1 75 %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %1, %2 76 S_ENDPGM 0, implicit %3 77... 78 79--- 80name: fmad_ftz_s32_vvvs 81legalized: true 82regBankSelected: true 83tracksRegLiveness: true 84 85body: | 86 bb.0: 87 liveins: $sgpr0, $vgpr0, $vgpr1 88 89 ; GCN-LABEL: name: fmad_ftz_s32_vvvs 90 ; GCN: liveins: $sgpr0, $vgpr0, $vgpr1 91 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 92 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 93 ; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 94 ; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY2]] 95 ; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY3]], 0, 0, implicit $mode, implicit $exec 96 ; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]] 97 %0:vgpr(s32) = COPY $vgpr0 98 %1:vgpr(s32) = COPY $vgpr0 99 %2:sgpr(s32) = COPY $sgpr0 100 %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %1, %2 101 S_ENDPGM 0, implicit %3 102... 103 104 105# Same SGPR used, so doesn't violate the constant bus restriction. 106--- 107name: fmad_ftz_s32_vssv 108legalized: true 109regBankSelected: true 110tracksRegLiveness: true 111 112body: | 113 bb.0: 114 liveins: $sgpr0, $vgpr0 115 116 ; GCN-LABEL: name: fmad_ftz_s32_vssv 117 ; GCN: liveins: $sgpr0, $vgpr0 118 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 119 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 120 ; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec 121 ; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]] 122 %0:sgpr(s32) = COPY $sgpr0 123 %1:vgpr(s32) = COPY $vgpr0 124 %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %0, %1 125 S_ENDPGM 0, implicit %2 126... 127 128--- 129name: fmad_ftz_s32_vsvs 130legalized: true 131regBankSelected: true 132tracksRegLiveness: true 133 134body: | 135 bb.0: 136 liveins: $sgpr0, $vgpr0 137 138 ; GCN-LABEL: name: fmad_ftz_s32_vsvs 139 ; GCN: liveins: $sgpr0, $vgpr0 140 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 141 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 142 ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]] 143 ; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec 144 ; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]] 145 %0:sgpr(s32) = COPY $sgpr0 146 %1:vgpr(s32) = COPY $vgpr0 147 %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %1, %0 148 S_ENDPGM 0, implicit %2 149... 150 151--- 152name: fmad_ftz_s32_vvss 153legalized: true 154regBankSelected: true 155tracksRegLiveness: true 156 157body: | 158 bb.0: 159 liveins: $sgpr0, $vgpr0 160 161 ; GCN-LABEL: name: fmad_ftz_s32_vvss 162 ; GCN: liveins: $sgpr0, $vgpr0 163 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 164 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 165 ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]] 166 ; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec 167 ; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]] 168 %0:sgpr(s32) = COPY $sgpr0 169 %1:vgpr(s32) = COPY $vgpr0 170 %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %1, %0, %0 171 S_ENDPGM 0, implicit %2 172... 173 174--- 175name: fmad_ftz_s32_vsss 176legalized: true 177regBankSelected: true 178tracksRegLiveness: true 179 180body: | 181 bb.0: 182 liveins: $sgpr0, $vgpr0 183 184 ; GCN-LABEL: name: fmad_ftz_s32_vsss 185 ; GCN: liveins: $sgpr0, $vgpr0 186 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 187 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]] 188 ; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec 189 ; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]] 190 %0:sgpr(s32) = COPY $sgpr0 191 %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %0, %0 192 S_ENDPGM 0, implicit %1 193... 194 195 196# FIXME: This should probably have been fixed by RegBankSelect, but we should fail to select it. 197# --- 198# name: fmad_ftz_s32_vssv_constant_bus_violation 199# legalized: true 200# regBankSelected: true 201# tracksRegLiveness: true 202 203# body: | 204# bb.0: 205# liveins: $sgpr0, $sgpr1, $vgpr0 206 207# %0:sgpr(s32) = COPY $sgpr0 208# %1:sgpr(s32) = COPY $sgpr1 209# %2:vgpr(s32) = COPY $vgpr0 210# %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %1, %2 211# S_ENDPGM 0, implicit %3 212# ... 213 214--- 215name: fmad_ftz_s32_vvv_fneg_v 216legalized: true 217regBankSelected: true 218tracksRegLiveness: true 219 220body: | 221 bb.0: 222 liveins: $vgpr0, $vgpr1, $vgpr2 223 224 ; GCN-LABEL: name: fmad_ftz_s32_vvv_fneg_v 225 ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2 226 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 227 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 228 ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 229 ; GCN: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec 230 ; GCN: S_ENDPGM 0, implicit [[V_MAD_F32_]] 231 %0:vgpr(s32) = COPY $vgpr0 232 %1:vgpr(s32) = COPY $vgpr1 233 %2:vgpr(s32) = COPY $vgpr2 234 %3:vgpr(s32) = G_FNEG %2 235 %4:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %1, %3 236 S_ENDPGM 0, implicit %4 237... 238