1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o -  | FileCheck -check-prefix=GCN %s
3
4---
5name: mul_u24_vsv
6legalized: true
7regBankSelected: true
8tracksRegLiveness: true
9
10body: |
11  bb.0:
12    liveins: $sgpr0, $vgpr0
13    ; GCN-LABEL: name: mul_u24_vsv
14    ; GCN: liveins: $sgpr0, $vgpr0
15    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
16    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
17    ; GCN: [[V_MUL_U32_U24_e64_:%[0-9]+]]:vgpr_32 = V_MUL_U32_U24_e64 [[COPY]], [[COPY1]], 0, implicit $exec
18    ; GCN: S_ENDPGM 0, implicit [[V_MUL_U32_U24_e64_]]
19    %0:sgpr(s32) = COPY $sgpr0
20    %1:vgpr(s32) = COPY $vgpr0
21    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mul.u24), %0, %1
22    S_ENDPGM 0, implicit %2
23...
24
25---
26name: mul_u24_vvs
27legalized: true
28regBankSelected: true
29tracksRegLiveness: true
30
31body: |
32  bb.0:
33    liveins: $sgpr0, $vgpr0
34    ; GCN-LABEL: name: mul_u24_vvs
35    ; GCN: liveins: $sgpr0, $vgpr0
36    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
37    ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
38    ; GCN: [[V_MUL_U32_U24_e64_:%[0-9]+]]:vgpr_32 = V_MUL_U32_U24_e64 [[COPY]], [[COPY1]], 0, implicit $exec
39    ; GCN: S_ENDPGM 0, implicit [[V_MUL_U32_U24_e64_]]
40    %0:vgpr(s32) = COPY $vgpr0
41    %1:sgpr(s32) = COPY $sgpr0
42    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mul.u24), %0, %1
43    S_ENDPGM 0, implicit %2
44...
45
46---
47name: mul_u24_vvv
48legalized: true
49regBankSelected: true
50tracksRegLiveness: true
51
52body: |
53  bb.0:
54    liveins: $vgpr0, $vgpr1
55    ; GCN-LABEL: name: mul_u24_vvv
56    ; GCN: liveins: $vgpr0, $vgpr1
57    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
58    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
59    ; GCN: [[V_MUL_U32_U24_e64_:%[0-9]+]]:vgpr_32 = V_MUL_U32_U24_e64 [[COPY]], [[COPY1]], 0, implicit $exec
60    ; GCN: S_ENDPGM 0, implicit [[V_MUL_U32_U24_e64_]]
61    %0:vgpr(s32) = COPY $vgpr0
62    %1:vgpr(s32) = COPY $vgpr1
63    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mul.u24), %0, %1
64    S_ENDPGM 0, implicit %2
65...
66