1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN
3# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN
4
5---
6
7name: anyext_sgpr_s16_to_sgpr_s32
8legalized:       true
9regBankSelected: true
10body: |
11  bb.0:
12    liveins: $sgpr0
13
14    ; GCN-LABEL: name: anyext_sgpr_s16_to_sgpr_s32
15    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
16    ; GCN: $sgpr0 = COPY [[COPY]]
17    %0:sgpr(s32) = COPY $sgpr0
18    %1:sgpr(s16) = G_TRUNC %0
19    %2:sgpr(s32) = G_ANYEXT %1
20    $sgpr0 = COPY %2
21
22...
23
24---
25name:  anyext_sgpr_s32_to_sgpr_s64
26legalized:       true
27regBankSelected: true
28tracksRegLiveness: true
29body:             |
30  bb.0:
31    liveins: $sgpr0
32
33    ; GCN-LABEL: name: anyext_sgpr_s32_to_sgpr_s64
34    ; GCN: liveins: $sgpr0
35    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
36    ; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
37    ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
38    ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
39    %0:sgpr(s32) = COPY $sgpr0
40    %1:sgpr(s64) = G_ANYEXT %0
41    S_ENDPGM 0, implicit %1
42
43...
44
45---
46name:  anyext_sgpr_s16_to_sgpr_s64
47legalized:       true
48regBankSelected: true
49tracksRegLiveness: true
50body:             |
51  bb.0:
52    liveins: $sgpr0
53
54    ; GCN-LABEL: name: anyext_sgpr_s16_to_sgpr_s64
55    ; GCN: liveins: $sgpr0
56    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
57    ; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
58    ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
59    ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
60    %0:sgpr(s32) = COPY $sgpr0
61    %1:sgpr(s16) = G_TRUNC %0
62    %2:sgpr(s64) = G_ANYEXT %1
63    S_ENDPGM 0, implicit %2
64
65...
66
67---
68name:  anyext_vgpr_s32_to_vgpr_s64
69legalized:       true
70regBankSelected: true
71tracksRegLiveness: true
72body:             |
73  bb.0:
74    liveins: $vgpr0
75
76    ; GCN-LABEL: name: anyext_vgpr_s32_to_vgpr_s64
77    ; GCN: liveins: $vgpr0
78    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
79    ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
80    ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
81    ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
82    %0:vgpr(s32) = COPY $vgpr0
83    %1:vgpr(s64) = G_ANYEXT %0
84    S_ENDPGM 0, implicit %1
85
86...
87
88---
89name:  anyext_vgpr_s16_to_vgpr_s64
90legalized:       true
91regBankSelected: true
92tracksRegLiveness: true
93body:             |
94  bb.0:
95    liveins: $vgpr0
96
97    ; GCN-LABEL: name: anyext_vgpr_s16_to_vgpr_s64
98    ; GCN: liveins: $vgpr0
99    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
100    ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
101    ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
102    ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
103    %0:vgpr(s32) = COPY $vgpr0
104    %1:vgpr(s16) = G_TRUNC %0
105    %2:vgpr(s64) = G_ANYEXT %1
106    S_ENDPGM 0, implicit %2
107
108...
109
110# vcc is an invalid extension source
111# ---
112
113# name: anyext_vcc_s1_to_vgpr_s32
114# legalized:       true
115# regBankSelected: true
116# body: |
117#   bb.0:
118#     liveins: $vgpr0
119
120#     %0:vgpr(s32) = COPY $vgpr0
121#     %1:vcc(s1) = G_ICMP intpred(eq), %0, %0
122#     %2:vgpr(s32) = G_ANYEXT %1
123#     $vgpr0 = COPY %2
124# ...
125
126---
127
128name: anyext_sgpr_s1_to_sgpr_s32
129legalized:       true
130regBankSelected: true
131body: |
132  bb.0:
133    liveins: $sgpr0
134
135    ; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s32
136    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
137    ; GCN: $sgpr0 = COPY [[COPY]]
138    %0:sgpr(s32) = COPY $sgpr0
139    %1:sgpr(s1) = G_TRUNC %0
140    %2:sgpr(s32) = G_ANYEXT %1
141    $sgpr0 = COPY %2
142...
143
144---
145
146name: anyext_vgpr_s1_to_vgpr_s32
147legalized:       true
148regBankSelected: true
149body: |
150  bb.0:
151    liveins: $vgpr0
152
153    ; GCN-LABEL: name: anyext_vgpr_s1_to_vgpr_s32
154    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
155    ; GCN: $vgpr0 = COPY [[COPY]]
156    %0:vgpr(s32) = COPY $vgpr0
157    %1:vgpr(s1) = G_TRUNC %0
158    %2:vgpr(s32) = G_ANYEXT %1
159    $vgpr0 = COPY %2
160...
161
162---
163
164name: anyext_sgpr_s1_to_vgpr_s32
165legalized:       true
166regBankSelected: true
167body: |
168  bb.0:
169    liveins: $sgpr0
170
171    ; GCN-LABEL: name: anyext_sgpr_s1_to_vgpr_s32
172    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
173    ; GCN: $sgpr0 = COPY [[COPY]]
174    %0:sgpr(s32) = COPY $sgpr0
175    %1:sgpr(s1) = G_TRUNC %0
176    %2:sgpr(s32) = G_ANYEXT %1
177    $sgpr0 = COPY %2
178...
179
180---
181
182name: anyext_vgpr_s16_to_vgpr_s32
183legalized:       true
184regBankSelected: true
185body: |
186  bb.0:
187    liveins: $vgpr0
188
189    ; GCN-LABEL: name: anyext_vgpr_s16_to_vgpr_s32
190    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
191    ; GCN: $vgpr0 = COPY [[COPY]]
192    %0:vgpr(s32) = COPY $vgpr0
193    %1:vgpr(s16) = G_TRUNC %0
194    %2:vgpr(s32) = G_ANYEXT %1
195    $vgpr0 = COPY %2
196
197...
198
199# The source register already has an assigned register class that
200# should not be interpreted as vcc.
201---
202
203name: anyext_regclass_sgpr_s1_to_sgpr_s32
204legalized:       true
205regBankSelected: true
206body: |
207  bb.0:
208    liveins: $sgpr0
209
210    ; GCN-LABEL: name: anyext_regclass_sgpr_s1_to_sgpr_s32
211    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
212    ; GCN: $sgpr0 = COPY [[COPY]]
213    %0:sgpr(s32) = COPY $sgpr0
214    %1:sreg_32(s1) = G_TRUNC %0
215    %2:sgpr(s32) = G_ANYEXT %1
216    $sgpr0 = COPY %2
217...
218