1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=WAVE64 %s 3# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=WAVE32 %s 4 5--- 6 7name: icmp_eq_s16_sv 8legalized: true 9regBankSelected: true 10 11body: | 12 bb.0: 13 liveins: $sgpr0, $vgpr0 14 15 ; WAVE64-LABEL: name: icmp_eq_s16_sv 16 ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 17 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 18 ; WAVE64: [[V_CMP_EQ_U16_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U16_e64 [[COPY]], [[COPY1]], implicit $exec 19 ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_EQ_U16_e64_]] 20 ; WAVE32-LABEL: name: icmp_eq_s16_sv 21 ; WAVE32: $vcc_hi = IMPLICIT_DEF 22 ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 23 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 24 ; WAVE32: [[V_CMP_EQ_U16_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U16_e64 [[COPY]], [[COPY1]], implicit $exec 25 ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_EQ_U16_e64_]] 26 %0:sgpr(s32) = COPY $sgpr0 27 %1:vgpr(s32) = COPY $vgpr0 28 %2:sgpr(s16) = G_TRUNC %0 29 %3:vgpr(s16) = G_TRUNC %1 30 %4:vcc(s1) = G_ICMP intpred(eq), %2, %3 31 S_ENDPGM 0, implicit %4 32... 33 34--- 35 36name: icmp_eq_s16_vs 37legalized: true 38regBankSelected: true 39 40body: | 41 bb.0: 42 liveins: $sgpr0, $vgpr0 43 44 ; WAVE64-LABEL: name: icmp_eq_s16_vs 45 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 46 ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 47 ; WAVE64: [[V_CMP_EQ_U16_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U16_e64 [[COPY]], [[COPY1]], implicit $exec 48 ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_EQ_U16_e64_]] 49 ; WAVE32-LABEL: name: icmp_eq_s16_vs 50 ; WAVE32: $vcc_hi = IMPLICIT_DEF 51 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 52 ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 53 ; WAVE32: [[V_CMP_EQ_U16_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U16_e64 [[COPY]], [[COPY1]], implicit $exec 54 ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_EQ_U16_e64_]] 55 %0:vgpr(s32) = COPY $vgpr0 56 %1:sgpr(s32) = COPY $sgpr0 57 %2:vgpr(s16) = G_TRUNC %0 58 %3:sgpr(s16) = G_TRUNC %1 59 %4:vcc(s1) = G_ICMP intpred(eq), %2, %3 60 S_ENDPGM 0, implicit %4 61... 62 63--- 64 65name: icmp_eq_s16_vv 66legalized: true 67regBankSelected: true 68 69body: | 70 bb.0: 71 liveins: $vgpr0, $vgpr1 72 73 ; WAVE64-LABEL: name: icmp_eq_s16_vv 74 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 75 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 76 ; WAVE64: [[V_CMP_EQ_U16_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U16_e64 [[COPY]], [[COPY1]], implicit $exec 77 ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_EQ_U16_e64_]] 78 ; WAVE32-LABEL: name: icmp_eq_s16_vv 79 ; WAVE32: $vcc_hi = IMPLICIT_DEF 80 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 81 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 82 ; WAVE32: [[V_CMP_EQ_U16_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U16_e64 [[COPY]], [[COPY1]], implicit $exec 83 ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_EQ_U16_e64_]] 84 %0:vgpr(s32) = COPY $vgpr0 85 %1:vgpr(s32) = COPY $vgpr1 86 %2:vgpr(s16) = G_TRUNC %0 87 %3:vgpr(s16) = G_TRUNC %1 88 %4:vcc(s1) = G_ICMP intpred(eq), %2, %3 89 S_ENDPGM 0, implicit %4 90... 91 92--- 93 94name: icmp_ne_s16_vv 95legalized: true 96regBankSelected: true 97 98body: | 99 bb.0: 100 liveins: $vgpr0, $vgpr1 101 102 ; WAVE64-LABEL: name: icmp_ne_s16_vv 103 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 104 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 105 ; WAVE64: [[V_CMP_NE_U16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U16_e64 [[COPY]], [[COPY1]], implicit $exec 106 ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NE_U16_e64_]] 107 ; WAVE32-LABEL: name: icmp_ne_s16_vv 108 ; WAVE32: $vcc_hi = IMPLICIT_DEF 109 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 110 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 111 ; WAVE32: [[V_CMP_NE_U16_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U16_e64 [[COPY]], [[COPY1]], implicit $exec 112 ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NE_U16_e64_]] 113 %0:vgpr(s32) = COPY $vgpr0 114 %1:vgpr(s32) = COPY $vgpr1 115 %2:vgpr(s16) = G_TRUNC %0 116 %3:vgpr(s16) = G_TRUNC %1 117 %4:vcc(s1) = G_ICMP intpred(ne), %2, %3 118 S_ENDPGM 0, implicit %4 119... 120 121--- 122 123name: icmp_slt_s16_vv 124legalized: true 125regBankSelected: true 126 127body: | 128 bb.0: 129 liveins: $vgpr0, $vgpr1 130 131 ; WAVE64-LABEL: name: icmp_slt_s16_vv 132 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 133 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 134 ; WAVE64: [[V_CMP_LT_I16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_I16_e64 [[COPY]], [[COPY1]], implicit $exec 135 ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LT_I16_e64_]] 136 ; WAVE32-LABEL: name: icmp_slt_s16_vv 137 ; WAVE32: $vcc_hi = IMPLICIT_DEF 138 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 139 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 140 ; WAVE32: [[V_CMP_LT_I16_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_I16_e64 [[COPY]], [[COPY1]], implicit $exec 141 ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LT_I16_e64_]] 142 %0:vgpr(s32) = COPY $vgpr0 143 %1:vgpr(s32) = COPY $vgpr1 144 %2:vgpr(s16) = G_TRUNC %0 145 %3:vgpr(s16) = G_TRUNC %1 146 %4:vcc(s1) = G_ICMP intpred(slt), %2, %3 147 S_ENDPGM 0, implicit %4 148... 149 150--- 151 152name: icmp_sle_s16_vv 153legalized: true 154regBankSelected: true 155 156body: | 157 bb.0: 158 liveins: $vgpr0, $vgpr1 159 160 ; WAVE64-LABEL: name: icmp_sle_s16_vv 161 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 162 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 163 ; WAVE64: [[V_CMP_LE_I16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LE_I16_e64 [[COPY]], [[COPY1]], implicit $exec 164 ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LE_I16_e64_]] 165 ; WAVE32-LABEL: name: icmp_sle_s16_vv 166 ; WAVE32: $vcc_hi = IMPLICIT_DEF 167 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 168 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 169 ; WAVE32: [[V_CMP_LE_I16_e64_:%[0-9]+]]:sreg_32 = V_CMP_LE_I16_e64 [[COPY]], [[COPY1]], implicit $exec 170 ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LE_I16_e64_]] 171 %0:vgpr(s32) = COPY $vgpr0 172 %1:vgpr(s32) = COPY $vgpr1 173 %2:vgpr(s16) = G_TRUNC %0 174 %3:vgpr(s16) = G_TRUNC %1 175 %4:vcc(s1) = G_ICMP intpred(sle), %2, %3 176 S_ENDPGM 0, implicit %4 177... 178 179--- 180 181name: icmp_ult_s16_vv 182legalized: true 183regBankSelected: true 184 185body: | 186 bb.0: 187 liveins: $vgpr0, $vgpr1 188 189 ; WAVE64-LABEL: name: icmp_ult_s16_vv 190 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 191 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 192 ; WAVE64: [[V_CMP_LT_U16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_U16_e64 [[COPY]], [[COPY1]], implicit $exec 193 ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LT_U16_e64_]] 194 ; WAVE32-LABEL: name: icmp_ult_s16_vv 195 ; WAVE32: $vcc_hi = IMPLICIT_DEF 196 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 197 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 198 ; WAVE32: [[V_CMP_LT_U16_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_U16_e64 [[COPY]], [[COPY1]], implicit $exec 199 ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LT_U16_e64_]] 200 %0:vgpr(s32) = COPY $vgpr0 201 %1:vgpr(s32) = COPY $vgpr1 202 %2:vgpr(s16) = G_TRUNC %0 203 %3:vgpr(s16) = G_TRUNC %1 204 %4:vcc(s1) = G_ICMP intpred(ult), %2, %3 205 S_ENDPGM 0, implicit %4 206... 207 208--- 209 210name: icmp_ule_s16_vv 211legalized: true 212regBankSelected: true 213 214body: | 215 bb.0: 216 liveins: $vgpr0, $vgpr1 217 218 ; WAVE64-LABEL: name: icmp_ule_s16_vv 219 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 220 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 221 ; WAVE64: [[V_CMP_LE_U16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LE_U16_e64 [[COPY]], [[COPY1]], implicit $exec 222 ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LE_U16_e64_]] 223 ; WAVE32-LABEL: name: icmp_ule_s16_vv 224 ; WAVE32: $vcc_hi = IMPLICIT_DEF 225 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 226 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 227 ; WAVE32: [[V_CMP_LE_U16_e64_:%[0-9]+]]:sreg_32 = V_CMP_LE_U16_e64 [[COPY]], [[COPY1]], implicit $exec 228 ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LE_U16_e64_]] 229 %0:vgpr(s32) = COPY $vgpr0 230 %1:vgpr(s32) = COPY $vgpr1 231 %2:vgpr(s16) = G_TRUNC %0 232 %3:vgpr(s16) = G_TRUNC %1 233 %4:vcc(s1) = G_ICMP intpred(ule), %2, %3 234 S_ENDPGM 0, implicit %4 235... 236 237