1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2; RUN: llc -march=amdgcn -global-isel -stop-after=irtranslator %s -o - | FileCheck %s 3 4define i16 @uaddsat_i16(i16 %lhs, i16 %rhs) { 5 ; CHECK-LABEL: name: uaddsat_i16 6 ; CHECK: bb.1 (%ir-block.0): 7 ; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31 8 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 9 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 10 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 11 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) 12 ; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 13 ; CHECK: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[TRUNC]], [[TRUNC1]] 14 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UADDSAT]](s16) 15 ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32) 16 ; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]] 17 ; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0 18 %res = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs) 19 ret i16 %res 20} 21declare i16 @llvm.uadd.sat.i16(i16, i16) 22 23define i32 @uaddsat_i32(i32 %lhs, i32 %rhs) { 24 ; CHECK-LABEL: name: uaddsat_i32 25 ; CHECK: bb.1 (%ir-block.0): 26 ; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31 27 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 28 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 29 ; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 30 ; CHECK: [[UADDSAT:%[0-9]+]]:_(s32) = G_UADDSAT [[COPY]], [[COPY1]] 31 ; CHECK: $vgpr0 = COPY [[UADDSAT]](s32) 32 ; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]] 33 ; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0 34 %res = call i32 @llvm.uadd.sat.i32(i32 %lhs, i32 %rhs) 35 ret i32 %res 36} 37declare i32 @llvm.uadd.sat.i32(i32, i32) 38 39define i64 @uaddsat_i64(i64 %lhs, i64 %rhs) { 40 ; CHECK-LABEL: name: uaddsat_i64 41 ; CHECK: bb.1 (%ir-block.0): 42 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31 43 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 44 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 45 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 46 ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 47 ; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 48 ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) 49 ; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32) 50 ; CHECK: [[UADDSAT:%[0-9]+]]:_(s64) = G_UADDSAT [[MV]], [[MV1]] 51 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UADDSAT]](s64) 52 ; CHECK: $vgpr0 = COPY [[UV]](s32) 53 ; CHECK: $vgpr1 = COPY [[UV1]](s32) 54 ; CHECK: [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]] 55 ; CHECK: S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1 56 %res = call i64 @llvm.uadd.sat.i64(i64 %lhs, i64 %rhs) 57 ret i64 %res 58} 59declare i64 @llvm.uadd.sat.i64(i64, i64) 60 61define <2 x i32> @uaddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { 62 ; CHECK-LABEL: name: uaddsat_v2i32 63 ; CHECK: bb.1 (%ir-block.0): 64 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31 65 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 66 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 67 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 68 ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 69 ; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 70 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 71 ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32) 72 ; CHECK: [[UADDSAT:%[0-9]+]]:_(<2 x s32>) = G_UADDSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]] 73 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UADDSAT]](<2 x s32>) 74 ; CHECK: $vgpr0 = COPY [[UV]](s32) 75 ; CHECK: $vgpr1 = COPY [[UV1]](s32) 76 ; CHECK: [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]] 77 ; CHECK: S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1 78 %res = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) 79 ret <2 x i32> %res 80} 81declare <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32>, <2 x i32>) 82 83define i16 @saddsat_i16(i16 %lhs, i16 %rhs) { 84 ; CHECK-LABEL: name: saddsat_i16 85 ; CHECK: bb.1 (%ir-block.0): 86 ; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31 87 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 88 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 89 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 90 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) 91 ; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 92 ; CHECK: [[SADDSAT:%[0-9]+]]:_(s16) = G_SADDSAT [[TRUNC]], [[TRUNC1]] 93 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SADDSAT]](s16) 94 ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32) 95 ; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]] 96 ; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0 97 %res = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs) 98 ret i16 %res 99} 100declare i16 @llvm.sadd.sat.i16(i16, i16) 101 102define i32 @saddsat_i32(i32 %lhs, i32 %rhs) { 103 ; CHECK-LABEL: name: saddsat_i32 104 ; CHECK: bb.1 (%ir-block.0): 105 ; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31 106 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 107 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 108 ; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 109 ; CHECK: [[SADDSAT:%[0-9]+]]:_(s32) = G_SADDSAT [[COPY]], [[COPY1]] 110 ; CHECK: $vgpr0 = COPY [[SADDSAT]](s32) 111 ; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]] 112 ; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0 113 %res = call i32 @llvm.sadd.sat.i32(i32 %lhs, i32 %rhs) 114 ret i32 %res 115} 116declare i32 @llvm.sadd.sat.i32(i32, i32) 117 118define i64 @saddsat_i64(i64 %lhs, i64 %rhs) { 119 ; CHECK-LABEL: name: saddsat_i64 120 ; CHECK: bb.1 (%ir-block.0): 121 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31 122 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 123 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 124 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 125 ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 126 ; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 127 ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) 128 ; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32) 129 ; CHECK: [[SADDSAT:%[0-9]+]]:_(s64) = G_SADDSAT [[MV]], [[MV1]] 130 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SADDSAT]](s64) 131 ; CHECK: $vgpr0 = COPY [[UV]](s32) 132 ; CHECK: $vgpr1 = COPY [[UV1]](s32) 133 ; CHECK: [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]] 134 ; CHECK: S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1 135 %res = call i64 @llvm.sadd.sat.i64(i64 %lhs, i64 %rhs) 136 ret i64 %res 137} 138declare i64 @llvm.sadd.sat.i64(i64, i64) 139 140define <2 x i32> @saddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { 141 ; CHECK-LABEL: name: saddsat_v2i32 142 ; CHECK: bb.1 (%ir-block.0): 143 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31 144 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 145 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 146 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 147 ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 148 ; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 149 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 150 ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32) 151 ; CHECK: [[SADDSAT:%[0-9]+]]:_(<2 x s32>) = G_SADDSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]] 152 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SADDSAT]](<2 x s32>) 153 ; CHECK: $vgpr0 = COPY [[UV]](s32) 154 ; CHECK: $vgpr1 = COPY [[UV1]](s32) 155 ; CHECK: [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]] 156 ; CHECK: S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1 157 %res = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) 158 ret <2 x i32> %res 159} 160declare <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32>, <2 x i32>) 161 162define i16 @usubsat_i16(i16 %lhs, i16 %rhs) { 163 ; CHECK-LABEL: name: usubsat_i16 164 ; CHECK: bb.1 (%ir-block.0): 165 ; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31 166 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 167 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 168 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 169 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) 170 ; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 171 ; CHECK: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[TRUNC]], [[TRUNC1]] 172 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[USUBSAT]](s16) 173 ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32) 174 ; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]] 175 ; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0 176 %res = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs) 177 ret i16 %res 178} 179declare i16 @llvm.usub.sat.i16(i16, i16) 180 181define i32 @usubsat_i32(i32 %lhs, i32 %rhs) { 182 ; CHECK-LABEL: name: usubsat_i32 183 ; CHECK: bb.1 (%ir-block.0): 184 ; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31 185 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 186 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 187 ; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 188 ; CHECK: [[USUBSAT:%[0-9]+]]:_(s32) = G_USUBSAT [[COPY]], [[COPY1]] 189 ; CHECK: $vgpr0 = COPY [[USUBSAT]](s32) 190 ; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]] 191 ; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0 192 %res = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs) 193 ret i32 %res 194} 195declare i32 @llvm.usub.sat.i32(i32, i32) 196 197define i64 @usubsat_i64(i64 %lhs, i64 %rhs) { 198 ; CHECK-LABEL: name: usubsat_i64 199 ; CHECK: bb.1 (%ir-block.0): 200 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31 201 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 202 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 203 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 204 ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 205 ; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 206 ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) 207 ; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32) 208 ; CHECK: [[USUBSAT:%[0-9]+]]:_(s64) = G_USUBSAT [[MV]], [[MV1]] 209 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[USUBSAT]](s64) 210 ; CHECK: $vgpr0 = COPY [[UV]](s32) 211 ; CHECK: $vgpr1 = COPY [[UV1]](s32) 212 ; CHECK: [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]] 213 ; CHECK: S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1 214 %res = call i64 @llvm.usub.sat.i64(i64 %lhs, i64 %rhs) 215 ret i64 %res 216} 217declare i64 @llvm.usub.sat.i64(i64, i64) 218 219define <2 x i32> @usubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { 220 ; CHECK-LABEL: name: usubsat_v2i32 221 ; CHECK: bb.1 (%ir-block.0): 222 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31 223 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 224 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 225 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 226 ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 227 ; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 228 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 229 ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32) 230 ; CHECK: [[USUBSAT:%[0-9]+]]:_(<2 x s32>) = G_USUBSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]] 231 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[USUBSAT]](<2 x s32>) 232 ; CHECK: $vgpr0 = COPY [[UV]](s32) 233 ; CHECK: $vgpr1 = COPY [[UV1]](s32) 234 ; CHECK: [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]] 235 ; CHECK: S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1 236 %res = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) 237 ret <2 x i32> %res 238} 239declare <2 x i32> @llvm.usub.sat.v2i32(<2 x i32>, <2 x i32>) 240 241define i16 @ssubsat_i16(i16 %lhs, i16 %rhs) { 242 ; CHECK-LABEL: name: ssubsat_i16 243 ; CHECK: bb.1 (%ir-block.0): 244 ; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31 245 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 246 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 247 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 248 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) 249 ; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 250 ; CHECK: [[SSUBSAT:%[0-9]+]]:_(s16) = G_SSUBSAT [[TRUNC]], [[TRUNC1]] 251 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SSUBSAT]](s16) 252 ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32) 253 ; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]] 254 ; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0 255 %res = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs) 256 ret i16 %res 257} 258declare i16 @llvm.ssub.sat.i16(i16, i16) 259 260define i32 @ssubsat_i32(i32 %lhs, i32 %rhs) { 261 ; CHECK-LABEL: name: ssubsat_i32 262 ; CHECK: bb.1 (%ir-block.0): 263 ; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31 264 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 265 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 266 ; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 267 ; CHECK: [[SSUBSAT:%[0-9]+]]:_(s32) = G_SSUBSAT [[COPY]], [[COPY1]] 268 ; CHECK: $vgpr0 = COPY [[SSUBSAT]](s32) 269 ; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]] 270 ; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0 271 %res = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs) 272 ret i32 %res 273} 274declare i32 @llvm.ssub.sat.i32(i32, i32) 275 276define i64 @ssubsat_i64(i64 %lhs, i64 %rhs) { 277 ; CHECK-LABEL: name: ssubsat_i64 278 ; CHECK: bb.1 (%ir-block.0): 279 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31 280 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 281 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 282 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 283 ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 284 ; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 285 ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) 286 ; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32) 287 ; CHECK: [[SSUBSAT:%[0-9]+]]:_(s64) = G_SSUBSAT [[MV]], [[MV1]] 288 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SSUBSAT]](s64) 289 ; CHECK: $vgpr0 = COPY [[UV]](s32) 290 ; CHECK: $vgpr1 = COPY [[UV1]](s32) 291 ; CHECK: [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]] 292 ; CHECK: S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1 293 %res = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs) 294 ret i64 %res 295} 296declare i64 @llvm.ssub.sat.i64(i64, i64) 297 298define <2 x i32> @ssubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { 299 ; CHECK-LABEL: name: ssubsat_v2i32 300 ; CHECK: bb.1 (%ir-block.0): 301 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31 302 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 303 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 304 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 305 ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 306 ; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 307 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 308 ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32) 309 ; CHECK: [[SSUBSAT:%[0-9]+]]:_(<2 x s32>) = G_SSUBSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]] 310 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SSUBSAT]](<2 x s32>) 311 ; CHECK: $vgpr0 = COPY [[UV]](s32) 312 ; CHECK: $vgpr1 = COPY [[UV1]](s32) 313 ; CHECK: [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]] 314 ; CHECK: S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1 315 %res = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) 316 ret <2 x i32> %res 317} 318declare <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32>, <2 x i32>) 319 320define i16 @ushlsat_i16(i16 %lhs, i16 %rhs) { 321 ; CHECK-LABEL: name: ushlsat_i16 322 ; CHECK: bb.1 (%ir-block.0): 323 ; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31 324 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 325 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 326 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 327 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) 328 ; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 329 ; CHECK: [[USHLSAT:%[0-9]+]]:_(s16) = G_USHLSAT [[TRUNC]], [[TRUNC1]](s16) 330 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[USHLSAT]](s16) 331 ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32) 332 ; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]] 333 ; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0 334 %res = call i16 @llvm.ushl.sat.i16(i16 %lhs, i16 %rhs) 335 ret i16 %res 336} 337declare i16 @llvm.ushl.sat.i16(i16, i16) 338 339define i32 @ushlsat_i32(i32 %lhs, i32 %rhs) { 340 ; CHECK-LABEL: name: ushlsat_i32 341 ; CHECK: bb.1 (%ir-block.0): 342 ; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31 343 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 344 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 345 ; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 346 ; CHECK: [[USHLSAT:%[0-9]+]]:_(s32) = G_USHLSAT [[COPY]], [[COPY1]](s32) 347 ; CHECK: $vgpr0 = COPY [[USHLSAT]](s32) 348 ; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]] 349 ; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0 350 %res = call i32 @llvm.ushl.sat.i32(i32 %lhs, i32 %rhs) 351 ret i32 %res 352} 353declare i32 @llvm.ushl.sat.i32(i32, i32) 354 355define i64 @ushlsat_i64(i64 %lhs, i64 %rhs) { 356 ; CHECK-LABEL: name: ushlsat_i64 357 ; CHECK: bb.1 (%ir-block.0): 358 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31 359 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 360 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 361 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 362 ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 363 ; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 364 ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) 365 ; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32) 366 ; CHECK: [[USHLSAT:%[0-9]+]]:_(s64) = G_USHLSAT [[MV]], [[MV1]](s64) 367 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[USHLSAT]](s64) 368 ; CHECK: $vgpr0 = COPY [[UV]](s32) 369 ; CHECK: $vgpr1 = COPY [[UV1]](s32) 370 ; CHECK: [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]] 371 ; CHECK: S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1 372 %res = call i64 @llvm.ushl.sat.i64(i64 %lhs, i64 %rhs) 373 ret i64 %res 374} 375declare i64 @llvm.ushl.sat.i64(i64, i64) 376 377define <2 x i32> @ushlsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { 378 ; CHECK-LABEL: name: ushlsat_v2i32 379 ; CHECK: bb.1 (%ir-block.0): 380 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31 381 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 382 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 383 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 384 ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 385 ; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 386 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 387 ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32) 388 ; CHECK: [[USHLSAT:%[0-9]+]]:_(<2 x s32>) = G_USHLSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]](<2 x s32>) 389 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[USHLSAT]](<2 x s32>) 390 ; CHECK: $vgpr0 = COPY [[UV]](s32) 391 ; CHECK: $vgpr1 = COPY [[UV1]](s32) 392 ; CHECK: [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]] 393 ; CHECK: S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1 394 %res = call <2 x i32> @llvm.ushl.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) 395 ret <2 x i32> %res 396} 397declare <2 x i32> @llvm.ushl.sat.v2i32(<2 x i32>, <2 x i32>) 398 399define i16 @sshlsat_i16(i16 %lhs, i16 %rhs) { 400 ; CHECK-LABEL: name: sshlsat_i16 401 ; CHECK: bb.1 (%ir-block.0): 402 ; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31 403 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 404 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 405 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 406 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) 407 ; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 408 ; CHECK: [[SSHLSAT:%[0-9]+]]:_(s16) = G_SSHLSAT [[TRUNC]], [[TRUNC1]](s16) 409 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SSHLSAT]](s16) 410 ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32) 411 ; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]] 412 ; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0 413 %res = call i16 @llvm.sshl.sat.i16(i16 %lhs, i16 %rhs) 414 ret i16 %res 415} 416declare i16 @llvm.sshl.sat.i16(i16, i16) 417 418define i32 @sshlsat_i32(i32 %lhs, i32 %rhs) { 419 ; CHECK-LABEL: name: sshlsat_i32 420 ; CHECK: bb.1 (%ir-block.0): 421 ; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31 422 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 423 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 424 ; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 425 ; CHECK: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[COPY1]](s32) 426 ; CHECK: $vgpr0 = COPY [[SSHLSAT]](s32) 427 ; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]] 428 ; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0 429 %res = call i32 @llvm.sshl.sat.i32(i32 %lhs, i32 %rhs) 430 ret i32 %res 431} 432declare i32 @llvm.sshl.sat.i32(i32, i32) 433 434define i64 @sshlsat_i64(i64 %lhs, i64 %rhs) { 435 ; CHECK-LABEL: name: sshlsat_i64 436 ; CHECK: bb.1 (%ir-block.0): 437 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31 438 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 439 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 440 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 441 ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 442 ; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 443 ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) 444 ; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32) 445 ; CHECK: [[SSHLSAT:%[0-9]+]]:_(s64) = G_SSHLSAT [[MV]], [[MV1]](s64) 446 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SSHLSAT]](s64) 447 ; CHECK: $vgpr0 = COPY [[UV]](s32) 448 ; CHECK: $vgpr1 = COPY [[UV1]](s32) 449 ; CHECK: [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]] 450 ; CHECK: S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1 451 %res = call i64 @llvm.sshl.sat.i64(i64 %lhs, i64 %rhs) 452 ret i64 %res 453} 454declare i64 @llvm.sshl.sat.i64(i64, i64) 455 456define <2 x i32> @sshlsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { 457 ; CHECK-LABEL: name: sshlsat_v2i32 458 ; CHECK: bb.1 (%ir-block.0): 459 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31 460 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 461 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 462 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 463 ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 464 ; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 465 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 466 ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32) 467 ; CHECK: [[SSHLSAT:%[0-9]+]]:_(<2 x s32>) = G_SSHLSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]](<2 x s32>) 468 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SSHLSAT]](<2 x s32>) 469 ; CHECK: $vgpr0 = COPY [[UV]](s32) 470 ; CHECK: $vgpr1 = COPY [[UV1]](s32) 471 ; CHECK: [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]] 472 ; CHECK: S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1 473 %res = call <2 x i32> @llvm.sshl.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) 474 ret <2 x i32> %res 475} 476declare <2 x i32> @llvm.sshl.sat.v2i32(<2 x i32>, <2 x i32>) 477