1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI %s
3# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s
4
5---
6name: test_rsq_clamp_flags_ieee_on_f32
7tracksRegLiveness: true
8machineFunctionInfo:
9  mode:
10    ieee: true
11
12body: |
13  bb.0:
14    liveins: $vgpr0
15
16    ; SI-LABEL: name: test_rsq_clamp_flags_ieee_on_f32
17    ; SI: liveins: $vgpr0
18    ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
19    ; SI: [[INT:%[0-9]+]]:_(s32) = nnan ninf nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), [[COPY]](s32)
20    ; SI: $vgpr0 = COPY [[INT]](s32)
21    ; VI-LABEL: name: test_rsq_clamp_flags_ieee_on_f32
22    ; VI: liveins: $vgpr0
23    ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
24    ; VI: [[INT:%[0-9]+]]:_(s32) = nnan ninf nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), [[COPY]](s32)
25    ; VI: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x47EFFFFFE0000000
26    ; VI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMINNUM_IEEE [[INT]], [[C]]
27    ; VI: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC7EFFFFFE0000000
28    ; VI: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[C1]]
29    ; VI: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
30    %0:_(s32) = COPY $vgpr0
31    %1:_(s32) = nnan ninf nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), %0
32    $vgpr0 = COPY %1
33...
34
35---
36name: test_rsq_clamp_flags_ieee_off_f32
37tracksRegLiveness: true
38machineFunctionInfo:
39  mode:
40    ieee: false
41
42body: |
43  bb.0:
44    liveins: $vgpr0
45
46    ; SI-LABEL: name: test_rsq_clamp_flags_ieee_off_f32
47    ; SI: liveins: $vgpr0
48    ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
49    ; SI: [[INT:%[0-9]+]]:_(s32) = nnan ninf nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), [[COPY]](s32)
50    ; SI: $vgpr0 = COPY [[INT]](s32)
51    ; VI-LABEL: name: test_rsq_clamp_flags_ieee_off_f32
52    ; VI: liveins: $vgpr0
53    ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
54    ; VI: [[INT:%[0-9]+]]:_(s32) = nnan ninf nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), [[COPY]](s32)
55    ; VI: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x47EFFFFFE0000000
56    ; VI: [[FMINNUM:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMINNUM [[INT]], [[C]]
57    ; VI: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC7EFFFFFE0000000
58    ; VI: [[FMAXNUM:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMAXNUM [[FMINNUM]], [[C1]]
59    ; VI: $vgpr0 = COPY [[FMAXNUM]](s32)
60    %0:_(s32) = COPY $vgpr0
61    %1:_(s32) = nnan ninf nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), %0
62    $vgpr0 = COPY %1
63...
64