1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE64 %s 3# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -O0 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE32 %s 4 5--- 6name: legal_brcond_vcc 7body: | 8 ; WAVE64-LABEL: name: legal_brcond_vcc 9 ; WAVE64: bb.0: 10 ; WAVE64: successors: %bb.1(0x80000000) 11 ; WAVE64: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 12 ; WAVE64: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 13 ; WAVE64: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]] 14 ; WAVE64: G_BRCOND [[ICMP]](s1), %bb.1 15 ; WAVE64: bb.1: 16 ; WAVE32-LABEL: name: legal_brcond_vcc 17 ; WAVE32: bb.0: 18 ; WAVE32: successors: %bb.1(0x80000000) 19 ; WAVE32: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 20 ; WAVE32: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 21 ; WAVE32: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]] 22 ; WAVE32: G_BRCOND [[ICMP]](s1), %bb.1 23 ; WAVE32: bb.1: 24 bb.0: 25 successors: %bb.1 26 liveins: $vgpr0, $vgpr1 27 %0:_(s32) = COPY $vgpr0 28 %1:_(s32) = COPY $vgpr1 29 %2:_(s1) = G_ICMP intpred(ne), %0, %1 30 G_BRCOND %2, %bb.1 31 32 bb.1: 33... 34 35--- 36 37name: legal_brcond_sgpr_s1 38 39body: | 40 ; WAVE64-LABEL: name: legal_brcond_sgpr_s1 41 ; WAVE64: bb.0: 42 ; WAVE64: successors: %bb.1(0x80000000) 43 ; WAVE64: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0 44 ; WAVE64: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1 45 ; WAVE64: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]] 46 ; WAVE64: G_BRCOND [[ICMP]](s1), %bb.1 47 ; WAVE64: bb.1: 48 ; WAVE32-LABEL: name: legal_brcond_sgpr_s1 49 ; WAVE32: bb.0: 50 ; WAVE32: successors: %bb.1(0x80000000) 51 ; WAVE32: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0 52 ; WAVE32: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1 53 ; WAVE32: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]] 54 ; WAVE32: G_BRCOND [[ICMP]](s1), %bb.1 55 ; WAVE32: bb.1: 56 bb.0: 57 liveins: $sgpr0, $sgpr1 58 59 %0:_(s32) = COPY $sgpr0 60 %1:_(s32) = COPY $sgpr1 61 %2:_(s1) = G_ICMP intpred(eq), %0, %1 62 G_BRCOND %2, %bb.1 63 64 bb.1: 65 66... 67 68--- 69 70name: legal_brcond_sgpr_s32 71 72body: | 73 ; WAVE64-LABEL: name: legal_brcond_sgpr_s32 74 ; WAVE64: bb.0: 75 ; WAVE64: successors: %bb.1(0x80000000) 76 ; WAVE64: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0 77 ; WAVE64: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1 78 ; WAVE64: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]] 79 ; WAVE64: G_BRCOND [[ICMP]](s32), %bb.1 80 ; WAVE64: bb.1: 81 ; WAVE32-LABEL: name: legal_brcond_sgpr_s32 82 ; WAVE32: bb.0: 83 ; WAVE32: successors: %bb.1(0x80000000) 84 ; WAVE32: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0 85 ; WAVE32: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1 86 ; WAVE32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]] 87 ; WAVE32: G_BRCOND [[ICMP]](s32), %bb.1 88 ; WAVE32: bb.1: 89 bb.0: 90 liveins: $sgpr0, $sgpr1 91 92 %0:_(s32) = COPY $sgpr0 93 %1:_(s32) = COPY $sgpr1 94 %2:_(s32) = G_ICMP intpred(eq), %0, %1 95 G_BRCOND %2, %bb.1 96 97 bb.1: 98 99... 100 101--- 102name: brcond_si_if 103body: | 104 ; WAVE64-LABEL: name: brcond_si_if 105 ; WAVE64: bb.0: 106 ; WAVE64: successors: %bb.1(0x80000000) 107 ; WAVE64: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 108 ; WAVE64: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 109 ; WAVE64: [[ICMP:%[0-9]+]]:sreg_64_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]] 110 ; WAVE64: [[SI_IF:%[0-9]+]]:sreg_64_xexec(s64) = SI_IF [[ICMP]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec 111 ; WAVE64: G_BR %bb.1 112 ; WAVE64: bb.1: 113 ; WAVE32-LABEL: name: brcond_si_if 114 ; WAVE32: bb.0: 115 ; WAVE32: successors: %bb.1(0x80000000) 116 ; WAVE32: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 117 ; WAVE32: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 118 ; WAVE32: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]] 119 ; WAVE32: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_IF [[ICMP]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec 120 ; WAVE32: G_BR %bb.1 121 ; WAVE32: bb.1: 122 bb.0: 123 successors: %bb.1 124 liveins: $vgpr0, $vgpr1 125 %0:_(s32) = COPY $vgpr0 126 %1:_(s32) = COPY $vgpr1 127 %2:_(s1) = G_ICMP intpred(ne), %0, %1 128 %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2 129 G_BRCOND %3, %bb.1 130 131 bb.1: 132... 133 134--- 135name: brcond_si_else 136body: | 137 ; WAVE64-LABEL: name: brcond_si_else 138 ; WAVE64: bb.0: 139 ; WAVE64: successors: %bb.1(0x80000000) 140 ; WAVE64: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 141 ; WAVE64: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 142 ; WAVE64: [[ICMP:%[0-9]+]]:sreg_64_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]] 143 ; WAVE64: [[SI_ELSE:%[0-9]+]]:sreg_64_xexec(s64) = SI_ELSE [[ICMP]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec 144 ; WAVE64: G_BR %bb.1 145 ; WAVE64: bb.1: 146 ; WAVE32-LABEL: name: brcond_si_else 147 ; WAVE32: bb.0: 148 ; WAVE32: successors: %bb.1(0x80000000) 149 ; WAVE32: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 150 ; WAVE32: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 151 ; WAVE32: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]] 152 ; WAVE32: [[SI_ELSE:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_ELSE [[ICMP]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec 153 ; WAVE32: G_BR %bb.1 154 ; WAVE32: bb.1: 155 bb.0: 156 successors: %bb.1 157 liveins: $vgpr0, $vgpr1 158 %0:_(s32) = COPY $vgpr0 159 %1:_(s32) = COPY $vgpr1 160 %2:_(s1) = G_ICMP intpred(ne), %0, %1 161 %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.else), %2 162 G_BRCOND %3, %bb.1 163 164 bb.1: 165... 166 167--- 168name: brcond_si_loop_brcond 169tracksRegLiveness: true 170body: | 171 ; WAVE64-LABEL: name: brcond_si_loop_brcond 172 ; WAVE64: bb.0: 173 ; WAVE64: successors: %bb.1(0x80000000) 174 ; WAVE64: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1 175 ; WAVE64: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 176 ; WAVE64: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 177 ; WAVE64: [[COPY2:%[0-9]+]]:sreg_64_xexec(s64) = COPY $sgpr0_sgpr1 178 ; WAVE64: bb.1: 179 ; WAVE64: successors: %bb.1(0x40000000), %bb.2(0x40000000) 180 ; WAVE64: S_NOP 0 181 ; WAVE64: SI_LOOP [[COPY2]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec 182 ; WAVE64: G_BR %bb.2 183 ; WAVE64: bb.2: 184 ; WAVE64: S_NOP 0 185 ; WAVE32-LABEL: name: brcond_si_loop_brcond 186 ; WAVE32: bb.0: 187 ; WAVE32: successors: %bb.1(0x80000000) 188 ; WAVE32: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1 189 ; WAVE32: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 190 ; WAVE32: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 191 ; WAVE32: [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec(s64) = COPY $sgpr0_sgpr1 192 ; WAVE32: bb.1: 193 ; WAVE32: successors: %bb.1(0x40000000), %bb.2(0x40000000) 194 ; WAVE32: S_NOP 0 195 ; WAVE32: SI_LOOP [[COPY2]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec 196 ; WAVE32: G_BR %bb.2 197 ; WAVE32: bb.2: 198 ; WAVE32: S_NOP 0 199 bb.0: 200 liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1 201 %0:_(s32) = COPY $vgpr0 202 %1:_(s32) = COPY $vgpr1 203 %2:_(s64) = COPY $sgpr0_sgpr1 204 205 bb.1: 206 successors: %bb.1, %bb.2 207 S_NOP 0 208 %3:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), %2 209 G_BRCOND %3, %bb.2 210 G_BR %bb.1 211 212 bb.2: 213 S_NOP 0 214... 215 216# This usage is backwards from how the intrinsic is supposed to be 217# used. 218--- 219name: brcond_si_loop_brcond_back 220tracksRegLiveness: true 221body: | 222 ; WAVE64-LABEL: name: brcond_si_loop_brcond_back 223 ; WAVE64: bb.0: 224 ; WAVE64: successors: %bb.1(0x80000000) 225 ; WAVE64: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1 226 ; WAVE64: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 227 ; WAVE64: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 228 ; WAVE64: [[COPY2:%[0-9]+]]:sreg_64_xexec(s64) = COPY $sgpr0_sgpr1 229 ; WAVE64: bb.1: 230 ; WAVE64: successors: %bb.1(0x40000000), %bb.2(0x40000000) 231 ; WAVE64: S_NOP 0 232 ; WAVE64: SI_LOOP [[COPY2]](s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec 233 ; WAVE64: G_BR %bb.1 234 ; WAVE64: bb.2: 235 ; WAVE64: S_NOP 0 236 ; WAVE32-LABEL: name: brcond_si_loop_brcond_back 237 ; WAVE32: bb.0: 238 ; WAVE32: successors: %bb.1(0x80000000) 239 ; WAVE32: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1 240 ; WAVE32: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 241 ; WAVE32: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 242 ; WAVE32: [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec(s64) = COPY $sgpr0_sgpr1 243 ; WAVE32: bb.1: 244 ; WAVE32: successors: %bb.1(0x40000000), %bb.2(0x40000000) 245 ; WAVE32: S_NOP 0 246 ; WAVE32: SI_LOOP [[COPY2]](s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec 247 ; WAVE32: G_BR %bb.1 248 ; WAVE32: bb.2: 249 ; WAVE32: S_NOP 0 250 bb.0: 251 liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1 252 %0:_(s32) = COPY $vgpr0 253 %1:_(s32) = COPY $vgpr1 254 %2:_(s64) = COPY $sgpr0_sgpr1 255 256 bb.1: 257 successors: %bb.1, %bb.2 258 S_NOP 0 259 %3:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), %2 260 G_BRCOND %3, %bb.1 261 G_BR %bb.2 262 263 bb.2: 264 S_NOP 0 265... 266 267# This usage is backwards from how the intrinsic is supposed to be 268# used. 269--- 270name: brcond_si_loop_brcond_back_fallthrough 271tracksRegLiveness: true 272body: | 273 ; WAVE64-LABEL: name: brcond_si_loop_brcond_back_fallthrough 274 ; WAVE64: bb.0: 275 ; WAVE64: successors: %bb.1(0x80000000) 276 ; WAVE64: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1 277 ; WAVE64: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 278 ; WAVE64: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 279 ; WAVE64: [[COPY2:%[0-9]+]]:sreg_64_xexec(s64) = COPY $sgpr0_sgpr1 280 ; WAVE64: bb.1: 281 ; WAVE64: successors: %bb.1(0x40000000), %bb.2(0x40000000) 282 ; WAVE64: S_NOP 0 283 ; WAVE64: SI_LOOP [[COPY2]](s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec 284 ; WAVE64: G_BR %bb.1 285 ; WAVE64: bb.2: 286 ; WAVE32-LABEL: name: brcond_si_loop_brcond_back_fallthrough 287 ; WAVE32: bb.0: 288 ; WAVE32: successors: %bb.1(0x80000000) 289 ; WAVE32: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1 290 ; WAVE32: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 291 ; WAVE32: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 292 ; WAVE32: [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec(s64) = COPY $sgpr0_sgpr1 293 ; WAVE32: bb.1: 294 ; WAVE32: successors: %bb.1(0x40000000), %bb.2(0x40000000) 295 ; WAVE32: S_NOP 0 296 ; WAVE32: SI_LOOP [[COPY2]](s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec 297 ; WAVE32: G_BR %bb.1 298 ; WAVE32: bb.2: 299 bb.0: 300 liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1 301 %0:_(s32) = COPY $vgpr0 302 %1:_(s32) = COPY $vgpr1 303 %2:_(s64) = COPY $sgpr0_sgpr1 304 305 bb.1: 306 successors: %bb.1, %bb.2 307 S_NOP 0 308 %3:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), %2 309 G_BRCOND %3, %bb.1 310 311 bb.2: 312... 313 314# There's another instruction between the intrinsic and the 315# conditional branch, so we need to move the insert point. 316--- 317name: brcond_si_if_need_insert_terminator_point 318body: | 319 ; WAVE64-LABEL: name: brcond_si_if_need_insert_terminator_point 320 ; WAVE64: bb.0: 321 ; WAVE64: successors: %bb.1(0x80000000) 322 ; WAVE64: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 323 ; WAVE64: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 324 ; WAVE64: [[ICMP:%[0-9]+]]:sreg_64_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]] 325 ; WAVE64: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 326 ; WAVE64: [[SI_IF:%[0-9]+]]:sreg_64_xexec(s64) = SI_IF [[ICMP]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec 327 ; WAVE64: G_BR %bb.1 328 ; WAVE64: bb.1: 329 ; WAVE64: S_ENDPGM 0, implicit [[COPY2]](s32) 330 ; WAVE32-LABEL: name: brcond_si_if_need_insert_terminator_point 331 ; WAVE32: bb.0: 332 ; WAVE32: successors: %bb.1(0x80000000) 333 ; WAVE32: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 334 ; WAVE32: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 335 ; WAVE32: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]] 336 ; WAVE32: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 337 ; WAVE32: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_IF [[ICMP]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec 338 ; WAVE32: G_BR %bb.1 339 ; WAVE32: bb.1: 340 ; WAVE32: S_ENDPGM 0, implicit [[COPY2]](s32) 341 bb.0: 342 successors: %bb.1 343 liveins: $vgpr0, $vgpr1, $vgpr2 344 %0:_(s32) = COPY $vgpr0 345 %1:_(s32) = COPY $vgpr1 346 %2:_(s1) = G_ICMP intpred(ne), %0, %1 347 %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2 348 %5:_(s32) = COPY $vgpr2 349 G_BRCOND %3, %bb.1 350 351 bb.1: 352 S_ENDPGM 0, implicit %5 353... 354 355--- 356name: brcond_si_loop_need_terminator_insert_point 357tracksRegLiveness: true 358body: | 359 ; WAVE64-LABEL: name: brcond_si_loop_need_terminator_insert_point 360 ; WAVE64: bb.0: 361 ; WAVE64: successors: %bb.1(0x80000000) 362 ; WAVE64: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1 363 ; WAVE64: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 364 ; WAVE64: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 365 ; WAVE64: [[COPY2:%[0-9]+]]:sreg_64_xexec(s64) = COPY $sgpr0_sgpr1 366 ; WAVE64: bb.1: 367 ; WAVE64: successors: %bb.1(0x40000000), %bb.2(0x40000000) 368 ; WAVE64: S_NOP 0 369 ; WAVE64: S_NOP 0 370 ; WAVE64: S_NOP 0 371 ; WAVE64: SI_LOOP [[COPY2]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec 372 ; WAVE64: G_BR %bb.2 373 ; WAVE64: bb.2: 374 ; WAVE64: S_NOP 0 375 ; WAVE32-LABEL: name: brcond_si_loop_need_terminator_insert_point 376 ; WAVE32: bb.0: 377 ; WAVE32: successors: %bb.1(0x80000000) 378 ; WAVE32: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1 379 ; WAVE32: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 380 ; WAVE32: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 381 ; WAVE32: [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec(s64) = COPY $sgpr0_sgpr1 382 ; WAVE32: bb.1: 383 ; WAVE32: successors: %bb.1(0x40000000), %bb.2(0x40000000) 384 ; WAVE32: S_NOP 0 385 ; WAVE32: S_NOP 0 386 ; WAVE32: S_NOP 0 387 ; WAVE32: SI_LOOP [[COPY2]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec 388 ; WAVE32: G_BR %bb.2 389 ; WAVE32: bb.2: 390 ; WAVE32: S_NOP 0 391 bb.0: 392 liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1 393 %0:_(s32) = COPY $vgpr0 394 %1:_(s32) = COPY $vgpr1 395 %2:_(s64) = COPY $sgpr0_sgpr1 396 397 bb.1: 398 successors: %bb.1, %bb.2 399 S_NOP 0 400 %3:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), %2 401 S_NOP 0 402 S_NOP 0 403 G_BRCOND %3, %bb.2 404 G_BR %bb.1 405 406 bb.2: 407 S_NOP 0 408... 409 410--- 411name: brcond_si_if_negated 412body: | 413 ; WAVE64-LABEL: name: brcond_si_if_negated 414 ; WAVE64: bb.0: 415 ; WAVE64: successors: %bb.1(0x80000000) 416 ; WAVE64: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 417 ; WAVE64: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 418 ; WAVE64: [[ICMP:%[0-9]+]]:sreg_64_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]] 419 ; WAVE64: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true 420 ; WAVE64: [[SI_IF:%[0-9]+]]:sreg_64_xexec(s64) = SI_IF [[ICMP]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec 421 ; WAVE64: G_BR %bb.1 422 ; WAVE64: bb.1: 423 ; WAVE64: successors: %bb.2(0x80000000) 424 ; WAVE64: S_NOP 0 425 ; WAVE64: bb.2: 426 ; WAVE64: S_NOP 1 427 ; WAVE32-LABEL: name: brcond_si_if_negated 428 ; WAVE32: bb.0: 429 ; WAVE32: successors: %bb.1(0x80000000) 430 ; WAVE32: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 431 ; WAVE32: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 432 ; WAVE32: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]] 433 ; WAVE32: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true 434 ; WAVE32: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_IF [[ICMP]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec 435 ; WAVE32: G_BR %bb.1 436 ; WAVE32: bb.1: 437 ; WAVE32: successors: %bb.2(0x80000000) 438 ; WAVE32: S_NOP 0 439 ; WAVE32: bb.2: 440 ; WAVE32: S_NOP 1 441 bb.0: 442 successors: %bb.1 443 liveins: $vgpr0, $vgpr1 444 %0:_(s32) = COPY $vgpr0 445 %1:_(s32) = COPY $vgpr1 446 %2:_(s1) = G_ICMP intpred(ne), %0, %1 447 %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2 448 %5:_(s1) = G_CONSTANT i1 true 449 %6:_(s1) = G_XOR %3, %5 450 G_BRCOND %6, %bb.2 451 452 bb.1: 453 S_NOP 0 454 455 bb.2: 456 S_NOP 1 457... 458 459--- 460name: brcond_si_if_br_negated 461body: | 462 ; WAVE64-LABEL: name: brcond_si_if_br_negated 463 ; WAVE64: bb.0: 464 ; WAVE64: successors: %bb.1(0x80000000) 465 ; WAVE64: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 466 ; WAVE64: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 467 ; WAVE64: [[ICMP:%[0-9]+]]:sreg_64_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]] 468 ; WAVE64: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true 469 ; WAVE64: [[SI_IF:%[0-9]+]]:sreg_64_xexec(s64) = SI_IF [[ICMP]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec 470 ; WAVE64: G_BR %bb.3 471 ; WAVE64: bb.1: 472 ; WAVE64: successors: %bb.2(0x80000000) 473 ; WAVE64: S_NOP 0 474 ; WAVE64: bb.2: 475 ; WAVE64: successors: %bb.3(0x80000000) 476 ; WAVE64: S_NOP 1 477 ; WAVE64: bb.3: 478 ; WAVE64: S_NOP 2 479 ; WAVE32-LABEL: name: brcond_si_if_br_negated 480 ; WAVE32: bb.0: 481 ; WAVE32: successors: %bb.1(0x80000000) 482 ; WAVE32: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 483 ; WAVE32: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 484 ; WAVE32: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]] 485 ; WAVE32: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true 486 ; WAVE32: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_IF [[ICMP]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec 487 ; WAVE32: G_BR %bb.3 488 ; WAVE32: bb.1: 489 ; WAVE32: successors: %bb.2(0x80000000) 490 ; WAVE32: S_NOP 0 491 ; WAVE32: bb.2: 492 ; WAVE32: successors: %bb.3(0x80000000) 493 ; WAVE32: S_NOP 1 494 ; WAVE32: bb.3: 495 ; WAVE32: S_NOP 2 496 bb.0: 497 successors: %bb.1 498 liveins: $vgpr0, $vgpr1 499 %0:_(s32) = COPY $vgpr0 500 %1:_(s32) = COPY $vgpr1 501 %2:_(s1) = G_ICMP intpred(ne), %0, %1 502 %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2 503 %5:_(s1) = G_CONSTANT i1 true 504 %6:_(s1) = G_XOR %3, %5 505 G_BRCOND %6, %bb.2 506 G_BR %bb.3 507 508 bb.1: 509 S_NOP 0 510 511 bb.2: 512 S_NOP 1 513 514 bb.3: 515 S_NOP 2 516... 517 518--- 519name: brcond_si_loop_brcond_negated 520tracksRegLiveness: true 521body: | 522 ; WAVE64-LABEL: name: brcond_si_loop_brcond_negated 523 ; WAVE64: bb.0: 524 ; WAVE64: successors: %bb.1(0x80000000) 525 ; WAVE64: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1 526 ; WAVE64: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 527 ; WAVE64: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 528 ; WAVE64: [[COPY2:%[0-9]+]]:sreg_64_xexec(s64) = COPY $sgpr0_sgpr1 529 ; WAVE64: bb.1: 530 ; WAVE64: successors: %bb.1(0x40000000), %bb.2(0x40000000) 531 ; WAVE64: S_NOP 0 532 ; WAVE64: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true 533 ; WAVE64: SI_LOOP [[COPY2]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec 534 ; WAVE64: G_BR %bb.2 535 ; WAVE64: bb.2: 536 ; WAVE64: S_NOP 0 537 ; WAVE32-LABEL: name: brcond_si_loop_brcond_negated 538 ; WAVE32: bb.0: 539 ; WAVE32: successors: %bb.1(0x80000000) 540 ; WAVE32: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1 541 ; WAVE32: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 542 ; WAVE32: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 543 ; WAVE32: [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec(s64) = COPY $sgpr0_sgpr1 544 ; WAVE32: bb.1: 545 ; WAVE32: successors: %bb.1(0x40000000), %bb.2(0x40000000) 546 ; WAVE32: S_NOP 0 547 ; WAVE32: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true 548 ; WAVE32: SI_LOOP [[COPY2]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec 549 ; WAVE32: G_BR %bb.2 550 ; WAVE32: bb.2: 551 ; WAVE32: S_NOP 0 552 bb.0: 553 liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1 554 %0:_(s32) = COPY $vgpr0 555 %1:_(s32) = COPY $vgpr1 556 %2:_(s64) = COPY $sgpr0_sgpr1 557 558 bb.1: 559 successors: %bb.1, %bb.2 560 S_NOP 0 561 %3:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), %2 562 %4:_(s1) = G_CONSTANT i1 true 563 %5:_(s1) = G_XOR %3, %4 564 G_BRCOND %5, %bb.1 565 566 bb.2: 567 S_NOP 0 568... 569 570--- 571name: brcond_si_loop_brcond_br_negated 572tracksRegLiveness: true 573body: | 574 ; WAVE64-LABEL: name: brcond_si_loop_brcond_br_negated 575 ; WAVE64: bb.0: 576 ; WAVE64: successors: %bb.1(0x80000000) 577 ; WAVE64: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1 578 ; WAVE64: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 579 ; WAVE64: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 580 ; WAVE64: [[COPY2:%[0-9]+]]:sreg_64_xexec(s64) = COPY $sgpr0_sgpr1 581 ; WAVE64: bb.1: 582 ; WAVE64: successors: %bb.1(0x40000000), %bb.2(0x40000000) 583 ; WAVE64: S_NOP 0 584 ; WAVE64: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true 585 ; WAVE64: SI_LOOP [[COPY2]](s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec 586 ; WAVE64: G_BR %bb.1 587 ; WAVE64: bb.2: 588 ; WAVE64: S_NOP 0 589 ; WAVE32-LABEL: name: brcond_si_loop_brcond_br_negated 590 ; WAVE32: bb.0: 591 ; WAVE32: successors: %bb.1(0x80000000) 592 ; WAVE32: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1 593 ; WAVE32: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 594 ; WAVE32: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 595 ; WAVE32: [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec(s64) = COPY $sgpr0_sgpr1 596 ; WAVE32: bb.1: 597 ; WAVE32: successors: %bb.1(0x40000000), %bb.2(0x40000000) 598 ; WAVE32: S_NOP 0 599 ; WAVE32: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true 600 ; WAVE32: SI_LOOP [[COPY2]](s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec 601 ; WAVE32: G_BR %bb.1 602 ; WAVE32: bb.2: 603 ; WAVE32: S_NOP 0 604 bb.0: 605 liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1 606 %0:_(s32) = COPY $vgpr0 607 %1:_(s32) = COPY $vgpr1 608 %2:_(s64) = COPY $sgpr0_sgpr1 609 610 bb.1: 611 successors: %bb.1, %bb.2 612 S_NOP 0 613 %3:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), %2 614 %4:_(s1) = G_CONSTANT i1 true 615 %5:_(s1) = G_XOR %3, %4 616 G_BRCOND %5, %bb.2 617 G_BR %bb.1 618 619 bb.2: 620 S_NOP 0 621... 622