1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -global-isel -march=amdgcn -mcpu=verde -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=GFX6 %s 3; RUN: llc -global-isel -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=GFX789 %s 4; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=GFX789 %s 5; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=GFX10 %s 6 7; FIXME: This test has a DAG duplicate 8 9; Immediate values: 10; (mode register ID = 1) | (Offset << 6) | ((Width - 1) << 11) 11; Offset: fp_round = 0, fp_denorm = 4, dx10_clamp = 8, ieee_mode = 9 12 13 14; Set FP32 fp_round to round to zero 15define amdgpu_kernel void @test_setreg_f32_round_mode_rtz() { 16; GFX6-LABEL: test_setreg_f32_round_mode_rtz: 17; GFX6: ; %bb.0: 18; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3 ; encoding: [0x01,0x08,0x80,0xba,0x03,0x00,0x00,0x00] 19; GFX6-NEXT: ;;#ASMSTART 20; GFX6-NEXT: ;;#ASMEND 21; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 22; 23; GFX789-LABEL: test_setreg_f32_round_mode_rtz: 24; GFX789: ; %bb.0: 25; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3 ; encoding: [0x01,0x08,0x00,0xba,0x03,0x00,0x00,0x00] 26; GFX789-NEXT: ;;#ASMSTART 27; GFX789-NEXT: ;;#ASMEND 28; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 29; 30; GFX10-LABEL: test_setreg_f32_round_mode_rtz: 31; GFX10: ; %bb.0: 32; GFX10-NEXT: ; implicit-def: $vcc_hi 33; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3 ; encoding: [0x01,0x08,0x80,0xba,0x03,0x00,0x00,0x00] 34; GFX10-NEXT: ;;#ASMSTART 35; GFX10-NEXT: ;;#ASMEND 36; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 37 call void @llvm.amdgcn.s.setreg(i32 2049, i32 3) 38 call void asm sideeffect "", ""() 39 ret void 40} 41 42; Set FP64/FP16 fp_round to round to zero 43define amdgpu_kernel void @test_setreg_f64_round_mode_rtz() { 44; GFX6-LABEL: test_setreg_f64_round_mode_rtz: 45; GFX6: ; %bb.0: 46; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 ; encoding: [0x81,0x08,0x80,0xba,0x03,0x00,0x00,0x00] 47; GFX6-NEXT: ;;#ASMSTART 48; GFX6-NEXT: ;;#ASMEND 49; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 50; 51; GFX789-LABEL: test_setreg_f64_round_mode_rtz: 52; GFX789: ; %bb.0: 53; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 ; encoding: [0x81,0x08,0x00,0xba,0x03,0x00,0x00,0x00] 54; GFX789-NEXT: ;;#ASMSTART 55; GFX789-NEXT: ;;#ASMEND 56; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 57; 58; GFX10-LABEL: test_setreg_f64_round_mode_rtz: 59; GFX10: ; %bb.0: 60; GFX10-NEXT: ; implicit-def: $vcc_hi 61; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 ; encoding: [0x81,0x08,0x80,0xba,0x03,0x00,0x00,0x00] 62; GFX10-NEXT: ;;#ASMSTART 63; GFX10-NEXT: ;;#ASMEND 64; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 65 call void @llvm.amdgcn.s.setreg(i32 2177, i32 3) 66 call void asm sideeffect "", ""() 67 ret void 68} 69 70; Set all fp_round to round to zero 71define amdgpu_kernel void @test_setreg_all_round_mode_rtz() { 72; GFX6-LABEL: test_setreg_all_round_mode_rtz: 73; GFX6: ; %bb.0: 74; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 4), 7 ; encoding: [0x81,0x18,0x80,0xba,0x07,0x00,0x00,0x00] 75; GFX6-NEXT: ;;#ASMSTART 76; GFX6-NEXT: ;;#ASMEND 77; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 78; 79; GFX789-LABEL: test_setreg_all_round_mode_rtz: 80; GFX789: ; %bb.0: 81; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 4), 7 ; encoding: [0x81,0x18,0x00,0xba,0x07,0x00,0x00,0x00] 82; GFX789-NEXT: ;;#ASMSTART 83; GFX789-NEXT: ;;#ASMEND 84; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 85; 86; GFX10-LABEL: test_setreg_all_round_mode_rtz: 87; GFX10: ; %bb.0: 88; GFX10-NEXT: ; implicit-def: $vcc_hi 89; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 4), 7 ; encoding: [0x81,0x18,0x80,0xba,0x07,0x00,0x00,0x00] 90; GFX10-NEXT: ;;#ASMSTART 91; GFX10-NEXT: ;;#ASMEND 92; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 93 call void @llvm.amdgcn.s.setreg(i32 6273, i32 7) 94 call void asm sideeffect "", ""() 95 ret void 96} 97 98; Set FP32 fp_round to dynamic mode 99define amdgpu_cs void @test_setreg_roundingmode_var(i32 inreg %var.mode) { 100; GFX6-LABEL: test_setreg_roundingmode_var: 101; GFX6: ; %bb.0: 102; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 2), s0 ; encoding: [0x01,0x08,0x80,0xb9] 103; GFX6-NEXT: ;;#ASMSTART 104; GFX6-NEXT: ;;#ASMEND 105; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 106; 107; GFX789-LABEL: test_setreg_roundingmode_var: 108; GFX789: ; %bb.0: 109; GFX789-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 2), s0 ; encoding: [0x01,0x08,0x00,0xb9] 110; GFX789-NEXT: ;;#ASMSTART 111; GFX789-NEXT: ;;#ASMEND 112; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 113; 114; GFX10-LABEL: test_setreg_roundingmode_var: 115; GFX10: ; %bb.0: 116; GFX10-NEXT: ; implicit-def: $vcc_hi 117; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 2), s0 ; encoding: [0x01,0x08,0x80,0xb9] 118; GFX10-NEXT: ;;#ASMSTART 119; GFX10-NEXT: ;;#ASMEND 120; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 121 call void @llvm.amdgcn.s.setreg(i32 2049, i32 %var.mode) 122 call void asm sideeffect "", ""() 123 ret void 124} 125 126define amdgpu_kernel void @test_setreg_ieee_mode_off() { 127; GFX6-LABEL: test_setreg_ieee_mode_off: 128; GFX6: ; %bb.0: 129; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 9, 1), 0 ; encoding: [0x41,0x02,0x80,0xba,0x00,0x00,0x00,0x00] 130; GFX6-NEXT: ;;#ASMSTART 131; GFX6-NEXT: ;;#ASMEND 132; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 133; 134; GFX789-LABEL: test_setreg_ieee_mode_off: 135; GFX789: ; %bb.0: 136; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 9, 1), 0 ; encoding: [0x41,0x02,0x00,0xba,0x00,0x00,0x00,0x00] 137; GFX789-NEXT: ;;#ASMSTART 138; GFX789-NEXT: ;;#ASMEND 139; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 140; 141; GFX10-LABEL: test_setreg_ieee_mode_off: 142; GFX10: ; %bb.0: 143; GFX10-NEXT: ; implicit-def: $vcc_hi 144; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 9, 1), 0 ; encoding: [0x41,0x02,0x80,0xba,0x00,0x00,0x00,0x00] 145; GFX10-NEXT: ;;#ASMSTART 146; GFX10-NEXT: ;;#ASMEND 147; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 148 call void @llvm.amdgcn.s.setreg(i32 577, i32 0) 149 call void asm sideeffect "", ""() 150 ret void 151} 152 153define amdgpu_kernel void @test_setreg_ieee_mode_on() { 154; GFX6-LABEL: test_setreg_ieee_mode_on: 155; GFX6: ; %bb.0: 156; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 9, 1), 1 ; encoding: [0x41,0x02,0x80,0xba,0x01,0x00,0x00,0x00] 157; GFX6-NEXT: ;;#ASMSTART 158; GFX6-NEXT: ;;#ASMEND 159; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 160; 161; GFX789-LABEL: test_setreg_ieee_mode_on: 162; GFX789: ; %bb.0: 163; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 9, 1), 1 ; encoding: [0x41,0x02,0x00,0xba,0x01,0x00,0x00,0x00] 164; GFX789-NEXT: ;;#ASMSTART 165; GFX789-NEXT: ;;#ASMEND 166; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 167; 168; GFX10-LABEL: test_setreg_ieee_mode_on: 169; GFX10: ; %bb.0: 170; GFX10-NEXT: ; implicit-def: $vcc_hi 171; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 9, 1), 1 ; encoding: [0x41,0x02,0x80,0xba,0x01,0x00,0x00,0x00] 172; GFX10-NEXT: ;;#ASMSTART 173; GFX10-NEXT: ;;#ASMEND 174; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 175 call void @llvm.amdgcn.s.setreg(i32 577, i32 1) 176 call void asm sideeffect "", ""() 177 ret void 178} 179 180define amdgpu_kernel void @test_setreg_dx10_clamp_off() { 181; GFX6-LABEL: test_setreg_dx10_clamp_off: 182; GFX6: ; %bb.0: 183; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 8, 1), 0 ; encoding: [0x01,0x02,0x80,0xba,0x00,0x00,0x00,0x00] 184; GFX6-NEXT: ;;#ASMSTART 185; GFX6-NEXT: ;;#ASMEND 186; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 187; 188; GFX789-LABEL: test_setreg_dx10_clamp_off: 189; GFX789: ; %bb.0: 190; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 8, 1), 0 ; encoding: [0x01,0x02,0x00,0xba,0x00,0x00,0x00,0x00] 191; GFX789-NEXT: ;;#ASMSTART 192; GFX789-NEXT: ;;#ASMEND 193; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 194; 195; GFX10-LABEL: test_setreg_dx10_clamp_off: 196; GFX10: ; %bb.0: 197; GFX10-NEXT: ; implicit-def: $vcc_hi 198; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 8, 1), 0 ; encoding: [0x01,0x02,0x80,0xba,0x00,0x00,0x00,0x00] 199; GFX10-NEXT: ;;#ASMSTART 200; GFX10-NEXT: ;;#ASMEND 201; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 202 call void @llvm.amdgcn.s.setreg(i32 513, i32 0) 203 call void asm sideeffect "", ""() 204 ret void 205} 206 207define amdgpu_kernel void @test_setreg_dx10_clamp_on() { 208; GFX6-LABEL: test_setreg_dx10_clamp_on: 209; GFX6: ; %bb.0: 210; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 8, 1), 1 ; encoding: [0x01,0x02,0x80,0xba,0x01,0x00,0x00,0x00] 211; GFX6-NEXT: ;;#ASMSTART 212; GFX6-NEXT: ;;#ASMEND 213; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 214; 215; GFX789-LABEL: test_setreg_dx10_clamp_on: 216; GFX789: ; %bb.0: 217; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 8, 1), 1 ; encoding: [0x01,0x02,0x00,0xba,0x01,0x00,0x00,0x00] 218; GFX789-NEXT: ;;#ASMSTART 219; GFX789-NEXT: ;;#ASMEND 220; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 221; 222; GFX10-LABEL: test_setreg_dx10_clamp_on: 223; GFX10: ; %bb.0: 224; GFX10-NEXT: ; implicit-def: $vcc_hi 225; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 8, 1), 1 ; encoding: [0x01,0x02,0x80,0xba,0x01,0x00,0x00,0x00] 226; GFX10-NEXT: ;;#ASMSTART 227; GFX10-NEXT: ;;#ASMEND 228; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 229 call void @llvm.amdgcn.s.setreg(i32 513, i32 1) 230 call void asm sideeffect "", ""() 231 ret void 232} 233 234; Sets full width of fp round and fp denorm fields, to a variable 235define amdgpu_cs void @test_setreg_full_both_round_mode_and_denorm_mode(i32 inreg %mode) { 236; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode: 237; GFX6: ; %bb.0: 238; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 8), s0 ; encoding: [0x01,0x38,0x80,0xb9] 239; GFX6-NEXT: ;;#ASMSTART 240; GFX6-NEXT: ;;#ASMEND 241; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 242; 243; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode: 244; GFX789: ; %bb.0: 245; GFX789-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 8), s0 ; encoding: [0x01,0x38,0x00,0xb9] 246; GFX789-NEXT: ;;#ASMSTART 247; GFX789-NEXT: ;;#ASMEND 248; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 249; 250; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode: 251; GFX10: ; %bb.0: 252; GFX10-NEXT: ; implicit-def: $vcc_hi 253; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 8), s0 ; encoding: [0x01,0x38,0x80,0xb9] 254; GFX10-NEXT: ;;#ASMSTART 255; GFX10-NEXT: ;;#ASMEND 256; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 257 call void @llvm.amdgcn.s.setreg(i32 14337, i32 inreg %mode) 258 call void asm sideeffect "", ""() 259 ret void 260} 261 262; Does not cover last bit of denorm field 263define amdgpu_cs void @test_setreg_most_both_round_mode_and_denorm_mode() { 264; GFX6-LABEL: test_setreg_most_both_round_mode_and_denorm_mode: 265; GFX6: ; %bb.0: 266; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 7), 6 ; encoding: [0x01,0x30,0x80,0xba,0x06,0x00,0x00,0x00] 267; GFX6-NEXT: ;;#ASMSTART 268; GFX6-NEXT: ;;#ASMEND 269; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 270; 271; GFX789-LABEL: test_setreg_most_both_round_mode_and_denorm_mode: 272; GFX789: ; %bb.0: 273; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 7), 6 ; encoding: [0x01,0x30,0x00,0xba,0x06,0x00,0x00,0x00] 274; GFX789-NEXT: ;;#ASMSTART 275; GFX789-NEXT: ;;#ASMEND 276; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 277; 278; GFX10-LABEL: test_setreg_most_both_round_mode_and_denorm_mode: 279; GFX10: ; %bb.0: 280; GFX10-NEXT: ; implicit-def: $vcc_hi 281; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 7), 6 ; encoding: [0x01,0x30,0x80,0xba,0x06,0x00,0x00,0x00] 282; GFX10-NEXT: ;;#ASMSTART 283; GFX10-NEXT: ;;#ASMEND 284; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 285 call void @llvm.amdgcn.s.setreg(i32 12289, i32 6) 286 call void asm sideeffect "", ""() 287 ret void 288} 289 290; Does not cover first bit of denorm field 291define amdgpu_cs void @test_setreg_most_both_round_mode_and_denorm_mode_6() { 292; GFX6-LABEL: test_setreg_most_both_round_mode_and_denorm_mode_6: 293; GFX6: ; %bb.0: 294; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 1, 3), 6 ; encoding: [0x41,0x10,0x80,0xba,0x06,0x00,0x00,0x00] 295; GFX6-NEXT: ;;#ASMSTART 296; GFX6-NEXT: ;;#ASMEND 297; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 298; 299; GFX789-LABEL: test_setreg_most_both_round_mode_and_denorm_mode_6: 300; GFX789: ; %bb.0: 301; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 1, 3), 6 ; encoding: [0x41,0x10,0x00,0xba,0x06,0x00,0x00,0x00] 302; GFX789-NEXT: ;;#ASMSTART 303; GFX789-NEXT: ;;#ASMEND 304; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 305; 306; GFX10-LABEL: test_setreg_most_both_round_mode_and_denorm_mode_6: 307; GFX10: ; %bb.0: 308; GFX10-NEXT: ; implicit-def: $vcc_hi 309; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 1, 3), 6 ; encoding: [0x41,0x10,0x80,0xba,0x06,0x00,0x00,0x00] 310; GFX10-NEXT: ;;#ASMSTART 311; GFX10-NEXT: ;;#ASMEND 312; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 313 call void @llvm.amdgcn.s.setreg(i32 4161, i32 6) 314 call void asm sideeffect "", ""() 315 ret void 316} 317 318define amdgpu_cs void @test_setreg_f32_denorm_mode(i32 inreg %val) { 319; GFX6-LABEL: test_setreg_f32_denorm_mode: 320; GFX6: ; %bb.0: 321; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0 ; encoding: [0x01,0x09,0x80,0xb9] 322; GFX6-NEXT: ;;#ASMSTART 323; GFX6-NEXT: ;;#ASMEND 324; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 325; 326; GFX789-LABEL: test_setreg_f32_denorm_mode: 327; GFX789: ; %bb.0: 328; GFX789-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0 ; encoding: [0x01,0x09,0x00,0xb9] 329; GFX789-NEXT: ;;#ASMSTART 330; GFX789-NEXT: ;;#ASMEND 331; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 332; 333; GFX10-LABEL: test_setreg_f32_denorm_mode: 334; GFX10: ; %bb.0: 335; GFX10-NEXT: ; implicit-def: $vcc_hi 336; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0 ; encoding: [0x01,0x09,0x80,0xb9] 337; GFX10-NEXT: ;;#ASMSTART 338; GFX10-NEXT: ;;#ASMEND 339; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 340 call void @llvm.amdgcn.s.setreg(i32 2305, i32 %val) 341 call void asm sideeffect "", ""() 342 ret void 343} 344 345define amdgpu_cs void @test_setreg_f64_denorm_mode(i32 inreg %val) { 346; GFX6-LABEL: test_setreg_f64_denorm_mode: 347; GFX6: ; %bb.0: 348; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 6, 2), s0 ; encoding: [0x81,0x09,0x80,0xb9] 349; GFX6-NEXT: ;;#ASMSTART 350; GFX6-NEXT: ;;#ASMEND 351; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 352; 353; GFX789-LABEL: test_setreg_f64_denorm_mode: 354; GFX789: ; %bb.0: 355; GFX789-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 6, 2), s0 ; encoding: [0x81,0x09,0x00,0xb9] 356; GFX789-NEXT: ;;#ASMSTART 357; GFX789-NEXT: ;;#ASMEND 358; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 359; 360; GFX10-LABEL: test_setreg_f64_denorm_mode: 361; GFX10: ; %bb.0: 362; GFX10-NEXT: ; implicit-def: $vcc_hi 363; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 6, 2), s0 ; encoding: [0x81,0x09,0x80,0xb9] 364; GFX10-NEXT: ;;#ASMSTART 365; GFX10-NEXT: ;;#ASMEND 366; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 367 call void @llvm.amdgcn.s.setreg(i32 2433, i32 %val) 368 call void asm sideeffect "", ""() 369 ret void 370} 371 372define amdgpu_cs void @test_setreg_full_denorm_mode(i32 inreg %val) { 373; GFX6-LABEL: test_setreg_full_denorm_mode: 374; GFX6: ; %bb.0: 375; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s0 ; encoding: [0x01,0x18,0x80,0xb9] 376; GFX6-NEXT: ;;#ASMSTART 377; GFX6-NEXT: ;;#ASMEND 378; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 379; 380; GFX789-LABEL: test_setreg_full_denorm_mode: 381; GFX789: ; %bb.0: 382; GFX789-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s0 ; encoding: [0x01,0x18,0x00,0xb9] 383; GFX789-NEXT: ;;#ASMSTART 384; GFX789-NEXT: ;;#ASMEND 385; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 386; 387; GFX10-LABEL: test_setreg_full_denorm_mode: 388; GFX10: ; %bb.0: 389; GFX10-NEXT: ; implicit-def: $vcc_hi 390; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s0 ; encoding: [0x01,0x18,0x80,0xb9] 391; GFX10-NEXT: ;;#ASMSTART 392; GFX10-NEXT: ;;#ASMEND 393; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 394 call void @llvm.amdgcn.s.setreg(i32 6145, i32 %val) 395 call void asm sideeffect "", ""() 396 ret void 397} 398 399define amdgpu_kernel void @test_setreg_full_round_mode_0() { 400; GFX6-LABEL: test_setreg_full_round_mode_0: 401; GFX6: ; %bb.0: 402; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 0 ; encoding: [0x01,0x18,0x80,0xba,0x00,0x00,0x00,0x00] 403; GFX6-NEXT: ;;#ASMSTART 404; GFX6-NEXT: ;;#ASMEND 405; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 406; 407; GFX789-LABEL: test_setreg_full_round_mode_0: 408; GFX789: ; %bb.0: 409; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 0 ; encoding: [0x01,0x18,0x00,0xba,0x00,0x00,0x00,0x00] 410; GFX789-NEXT: ;;#ASMSTART 411; GFX789-NEXT: ;;#ASMEND 412; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 413; 414; GFX10-LABEL: test_setreg_full_round_mode_0: 415; GFX10: ; %bb.0: 416; GFX10-NEXT: ; implicit-def: $vcc_hi 417; GFX10-NEXT: s_round_mode 0x0 ; encoding: [0x00,0x00,0xa4,0xbf] 418; GFX10-NEXT: ;;#ASMSTART 419; GFX10-NEXT: ;;#ASMEND 420; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 421 call void @llvm.amdgcn.s.setreg(i32 6145, i32 0) 422 call void asm sideeffect "", ""() 423 ret void 424} 425 426define amdgpu_kernel void @test_setreg_full_round_mode_1() { 427; GFX6-LABEL: test_setreg_full_round_mode_1: 428; GFX6: ; %bb.0: 429; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 1 ; encoding: [0x01,0x18,0x80,0xba,0x01,0x00,0x00,0x00] 430; GFX6-NEXT: ;;#ASMSTART 431; GFX6-NEXT: ;;#ASMEND 432; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 433; 434; GFX789-LABEL: test_setreg_full_round_mode_1: 435; GFX789: ; %bb.0: 436; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 1 ; encoding: [0x01,0x18,0x00,0xba,0x01,0x00,0x00,0x00] 437; GFX789-NEXT: ;;#ASMSTART 438; GFX789-NEXT: ;;#ASMEND 439; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 440; 441; GFX10-LABEL: test_setreg_full_round_mode_1: 442; GFX10: ; %bb.0: 443; GFX10-NEXT: ; implicit-def: $vcc_hi 444; GFX10-NEXT: s_round_mode 0x1 ; encoding: [0x01,0x00,0xa4,0xbf] 445; GFX10-NEXT: ;;#ASMSTART 446; GFX10-NEXT: ;;#ASMEND 447; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 448 call void @llvm.amdgcn.s.setreg(i32 6145, i32 1) 449 call void asm sideeffect "", ""() 450 ret void 451} 452 453define amdgpu_kernel void @test_setreg_full_round_mode_2() { 454; GFX6-LABEL: test_setreg_full_round_mode_2: 455; GFX6: ; %bb.0: 456; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 2 ; encoding: [0x01,0x18,0x80,0xba,0x02,0x00,0x00,0x00] 457; GFX6-NEXT: ;;#ASMSTART 458; GFX6-NEXT: ;;#ASMEND 459; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 460; 461; GFX789-LABEL: test_setreg_full_round_mode_2: 462; GFX789: ; %bb.0: 463; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 2 ; encoding: [0x01,0x18,0x00,0xba,0x02,0x00,0x00,0x00] 464; GFX789-NEXT: ;;#ASMSTART 465; GFX789-NEXT: ;;#ASMEND 466; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 467; 468; GFX10-LABEL: test_setreg_full_round_mode_2: 469; GFX10: ; %bb.0: 470; GFX10-NEXT: ; implicit-def: $vcc_hi 471; GFX10-NEXT: s_round_mode 0x2 ; encoding: [0x02,0x00,0xa4,0xbf] 472; GFX10-NEXT: ;;#ASMSTART 473; GFX10-NEXT: ;;#ASMEND 474; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 475 call void @llvm.amdgcn.s.setreg(i32 6145, i32 2) 476 call void asm sideeffect "", ""() 477 ret void 478} 479 480define amdgpu_kernel void @test_setreg_full_round_mode_4() { 481; GFX6-LABEL: test_setreg_full_round_mode_4: 482; GFX6: ; %bb.0: 483; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 4 ; encoding: [0x01,0x18,0x80,0xba,0x04,0x00,0x00,0x00] 484; GFX6-NEXT: ;;#ASMSTART 485; GFX6-NEXT: ;;#ASMEND 486; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 487; 488; GFX789-LABEL: test_setreg_full_round_mode_4: 489; GFX789: ; %bb.0: 490; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 4 ; encoding: [0x01,0x18,0x00,0xba,0x04,0x00,0x00,0x00] 491; GFX789-NEXT: ;;#ASMSTART 492; GFX789-NEXT: ;;#ASMEND 493; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 494; 495; GFX10-LABEL: test_setreg_full_round_mode_4: 496; GFX10: ; %bb.0: 497; GFX10-NEXT: ; implicit-def: $vcc_hi 498; GFX10-NEXT: s_round_mode 0x4 ; encoding: [0x04,0x00,0xa4,0xbf] 499; GFX10-NEXT: ;;#ASMSTART 500; GFX10-NEXT: ;;#ASMEND 501; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 502 call void @llvm.amdgcn.s.setreg(i32 6145, i32 4) 503 call void asm sideeffect "", ""() 504 ret void 505} 506 507define amdgpu_kernel void @test_setreg_full_round_mode_8() { 508; GFX6-LABEL: test_setreg_full_round_mode_8: 509; GFX6: ; %bb.0: 510; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 8 ; encoding: [0x01,0x18,0x80,0xba,0x08,0x00,0x00,0x00] 511; GFX6-NEXT: ;;#ASMSTART 512; GFX6-NEXT: ;;#ASMEND 513; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 514; 515; GFX789-LABEL: test_setreg_full_round_mode_8: 516; GFX789: ; %bb.0: 517; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 8 ; encoding: [0x01,0x18,0x00,0xba,0x08,0x00,0x00,0x00] 518; GFX789-NEXT: ;;#ASMSTART 519; GFX789-NEXT: ;;#ASMEND 520; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 521; 522; GFX10-LABEL: test_setreg_full_round_mode_8: 523; GFX10: ; %bb.0: 524; GFX10-NEXT: ; implicit-def: $vcc_hi 525; GFX10-NEXT: s_round_mode 0x8 ; encoding: [0x08,0x00,0xa4,0xbf] 526; GFX10-NEXT: ;;#ASMSTART 527; GFX10-NEXT: ;;#ASMEND 528; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 529 call void @llvm.amdgcn.s.setreg(i32 6145, i32 8) 530 call void asm sideeffect "", ""() 531 ret void 532} 533 534define amdgpu_kernel void @test_setreg_full_round_mode_15() { 535; GFX6-LABEL: test_setreg_full_round_mode_15: 536; GFX6: ; %bb.0: 537; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 15 ; encoding: [0x01,0x18,0x80,0xba,0x0f,0x00,0x00,0x00] 538; GFX6-NEXT: ;;#ASMSTART 539; GFX6-NEXT: ;;#ASMEND 540; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 541; 542; GFX789-LABEL: test_setreg_full_round_mode_15: 543; GFX789: ; %bb.0: 544; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 15 ; encoding: [0x01,0x18,0x00,0xba,0x0f,0x00,0x00,0x00] 545; GFX789-NEXT: ;;#ASMSTART 546; GFX789-NEXT: ;;#ASMEND 547; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 548; 549; GFX10-LABEL: test_setreg_full_round_mode_15: 550; GFX10: ; %bb.0: 551; GFX10-NEXT: ; implicit-def: $vcc_hi 552; GFX10-NEXT: s_round_mode 0xf ; encoding: [0x0f,0x00,0xa4,0xbf] 553; GFX10-NEXT: ;;#ASMSTART 554; GFX10-NEXT: ;;#ASMEND 555; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 556 call void @llvm.amdgcn.s.setreg(i32 6145, i32 15) 557 call void asm sideeffect "", ""() 558 ret void 559} 560 561; Should truncate set immediate value 562define amdgpu_kernel void @test_setreg_full_round_mode_42() { 563; GFX6-LABEL: test_setreg_full_round_mode_42: 564; GFX6: ; %bb.0: 565; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 42 ; encoding: [0x01,0x18,0x80,0xba,0x2a,0x00,0x00,0x00] 566; GFX6-NEXT: ;;#ASMSTART 567; GFX6-NEXT: ;;#ASMEND 568; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 569; 570; GFX789-LABEL: test_setreg_full_round_mode_42: 571; GFX789: ; %bb.0: 572; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 42 ; encoding: [0x01,0x18,0x00,0xba,0x2a,0x00,0x00,0x00] 573; GFX789-NEXT: ;;#ASMSTART 574; GFX789-NEXT: ;;#ASMEND 575; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 576; 577; GFX10-LABEL: test_setreg_full_round_mode_42: 578; GFX10: ; %bb.0: 579; GFX10-NEXT: ; implicit-def: $vcc_hi 580; GFX10-NEXT: s_round_mode 0xa ; encoding: [0x0a,0x00,0xa4,0xbf] 581; GFX10-NEXT: ;;#ASMSTART 582; GFX10-NEXT: ;;#ASMEND 583; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 584 call void @llvm.amdgcn.s.setreg(i32 6145, i32 42) 585 call void asm sideeffect "", ""() 586 ret void 587} 588 589define amdgpu_kernel void @test_setreg_full_denorm_mode_0() { 590; GFX6-LABEL: test_setreg_full_denorm_mode_0: 591; GFX6: ; %bb.0: 592; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 0 ; encoding: [0x01,0x19,0x80,0xba,0x00,0x00,0x00,0x00] 593; GFX6-NEXT: ;;#ASMSTART 594; GFX6-NEXT: ;;#ASMEND 595; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 596; 597; GFX789-LABEL: test_setreg_full_denorm_mode_0: 598; GFX789: ; %bb.0: 599; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 0 ; encoding: [0x01,0x19,0x00,0xba,0x00,0x00,0x00,0x00] 600; GFX789-NEXT: ;;#ASMSTART 601; GFX789-NEXT: ;;#ASMEND 602; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 603; 604; GFX10-LABEL: test_setreg_full_denorm_mode_0: 605; GFX10: ; %bb.0: 606; GFX10-NEXT: ; implicit-def: $vcc_hi 607; GFX10-NEXT: s_denorm_mode 0 ; encoding: [0x00,0x00,0xa5,0xbf] 608; GFX10-NEXT: ;;#ASMSTART 609; GFX10-NEXT: ;;#ASMEND 610; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 611 call void @llvm.amdgcn.s.setreg(i32 6401, i32 0) 612 call void asm sideeffect "", ""() 613 ret void 614} 615 616define amdgpu_kernel void @test_setreg_full_denorm_mode_1() { 617; GFX6-LABEL: test_setreg_full_denorm_mode_1: 618; GFX6: ; %bb.0: 619; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 1 ; encoding: [0x01,0x19,0x80,0xba,0x01,0x00,0x00,0x00] 620; GFX6-NEXT: ;;#ASMSTART 621; GFX6-NEXT: ;;#ASMEND 622; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 623; 624; GFX789-LABEL: test_setreg_full_denorm_mode_1: 625; GFX789: ; %bb.0: 626; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 1 ; encoding: [0x01,0x19,0x00,0xba,0x01,0x00,0x00,0x00] 627; GFX789-NEXT: ;;#ASMSTART 628; GFX789-NEXT: ;;#ASMEND 629; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 630; 631; GFX10-LABEL: test_setreg_full_denorm_mode_1: 632; GFX10: ; %bb.0: 633; GFX10-NEXT: ; implicit-def: $vcc_hi 634; GFX10-NEXT: s_denorm_mode 1 ; encoding: [0x01,0x00,0xa5,0xbf] 635; GFX10-NEXT: ;;#ASMSTART 636; GFX10-NEXT: ;;#ASMEND 637; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 638 call void @llvm.amdgcn.s.setreg(i32 6401, i32 1) 639 call void asm sideeffect "", ""() 640 ret void 641} 642 643 644define amdgpu_kernel void @test_setreg_full_denorm_mode_2() { 645; GFX6-LABEL: test_setreg_full_denorm_mode_2: 646; GFX6: ; %bb.0: 647; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 2 ; encoding: [0x01,0x19,0x80,0xba,0x02,0x00,0x00,0x00] 648; GFX6-NEXT: ;;#ASMSTART 649; GFX6-NEXT: ;;#ASMEND 650; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 651; 652; GFX789-LABEL: test_setreg_full_denorm_mode_2: 653; GFX789: ; %bb.0: 654; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 2 ; encoding: [0x01,0x19,0x00,0xba,0x02,0x00,0x00,0x00] 655; GFX789-NEXT: ;;#ASMSTART 656; GFX789-NEXT: ;;#ASMEND 657; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 658; 659; GFX10-LABEL: test_setreg_full_denorm_mode_2: 660; GFX10: ; %bb.0: 661; GFX10-NEXT: ; implicit-def: $vcc_hi 662; GFX10-NEXT: s_denorm_mode 2 ; encoding: [0x02,0x00,0xa5,0xbf] 663; GFX10-NEXT: ;;#ASMSTART 664; GFX10-NEXT: ;;#ASMEND 665; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 666 call void @llvm.amdgcn.s.setreg(i32 6401, i32 2) 667 call void asm sideeffect "", ""() 668 ret void 669} 670 671define amdgpu_kernel void @test_setreg_full_denorm_mode_4() { 672; GFX6-LABEL: test_setreg_full_denorm_mode_4: 673; GFX6: ; %bb.0: 674; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 4 ; encoding: [0x01,0x19,0x80,0xba,0x04,0x00,0x00,0x00] 675; GFX6-NEXT: ;;#ASMSTART 676; GFX6-NEXT: ;;#ASMEND 677; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 678; 679; GFX789-LABEL: test_setreg_full_denorm_mode_4: 680; GFX789: ; %bb.0: 681; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 4 ; encoding: [0x01,0x19,0x00,0xba,0x04,0x00,0x00,0x00] 682; GFX789-NEXT: ;;#ASMSTART 683; GFX789-NEXT: ;;#ASMEND 684; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 685; 686; GFX10-LABEL: test_setreg_full_denorm_mode_4: 687; GFX10: ; %bb.0: 688; GFX10-NEXT: ; implicit-def: $vcc_hi 689; GFX10-NEXT: s_denorm_mode 4 ; encoding: [0x04,0x00,0xa5,0xbf] 690; GFX10-NEXT: ;;#ASMSTART 691; GFX10-NEXT: ;;#ASMEND 692; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 693 call void @llvm.amdgcn.s.setreg(i32 6401, i32 4) 694 call void asm sideeffect "", ""() 695 ret void 696} 697 698define amdgpu_kernel void @test_setreg_full_denorm_mode_8() { 699; GFX6-LABEL: test_setreg_full_denorm_mode_8: 700; GFX6: ; %bb.0: 701; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 8 ; encoding: [0x01,0x19,0x80,0xba,0x08,0x00,0x00,0x00] 702; GFX6-NEXT: ;;#ASMSTART 703; GFX6-NEXT: ;;#ASMEND 704; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 705; 706; GFX789-LABEL: test_setreg_full_denorm_mode_8: 707; GFX789: ; %bb.0: 708; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 8 ; encoding: [0x01,0x19,0x00,0xba,0x08,0x00,0x00,0x00] 709; GFX789-NEXT: ;;#ASMSTART 710; GFX789-NEXT: ;;#ASMEND 711; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 712; 713; GFX10-LABEL: test_setreg_full_denorm_mode_8: 714; GFX10: ; %bb.0: 715; GFX10-NEXT: ; implicit-def: $vcc_hi 716; GFX10-NEXT: s_denorm_mode 8 ; encoding: [0x08,0x00,0xa5,0xbf] 717; GFX10-NEXT: ;;#ASMSTART 718; GFX10-NEXT: ;;#ASMEND 719; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 720 call void @llvm.amdgcn.s.setreg(i32 6401, i32 8) 721 call void asm sideeffect "", ""() 722 ret void 723} 724 725define amdgpu_kernel void @test_setreg_full_denorm_mode_15() { 726; GFX6-LABEL: test_setreg_full_denorm_mode_15: 727; GFX6: ; %bb.0: 728; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 15 ; encoding: [0x01,0x19,0x80,0xba,0x0f,0x00,0x00,0x00] 729; GFX6-NEXT: ;;#ASMSTART 730; GFX6-NEXT: ;;#ASMEND 731; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 732; 733; GFX789-LABEL: test_setreg_full_denorm_mode_15: 734; GFX789: ; %bb.0: 735; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 15 ; encoding: [0x01,0x19,0x00,0xba,0x0f,0x00,0x00,0x00] 736; GFX789-NEXT: ;;#ASMSTART 737; GFX789-NEXT: ;;#ASMEND 738; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 739; 740; GFX10-LABEL: test_setreg_full_denorm_mode_15: 741; GFX10: ; %bb.0: 742; GFX10-NEXT: ; implicit-def: $vcc_hi 743; GFX10-NEXT: s_denorm_mode 15 ; encoding: [0x0f,0x00,0xa5,0xbf] 744; GFX10-NEXT: ;;#ASMSTART 745; GFX10-NEXT: ;;#ASMEND 746; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 747 call void @llvm.amdgcn.s.setreg(i32 6401, i32 15) 748 call void asm sideeffect "", ""() 749 ret void 750} 751 752define amdgpu_kernel void @test_setreg_full_denorm_mode_42() { 753; GFX6-LABEL: test_setreg_full_denorm_mode_42: 754; GFX6: ; %bb.0: 755; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 42 ; encoding: [0x01,0x19,0x80,0xba,0x2a,0x00,0x00,0x00] 756; GFX6-NEXT: ;;#ASMSTART 757; GFX6-NEXT: ;;#ASMEND 758; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 759; 760; GFX789-LABEL: test_setreg_full_denorm_mode_42: 761; GFX789: ; %bb.0: 762; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 42 ; encoding: [0x01,0x19,0x00,0xba,0x2a,0x00,0x00,0x00] 763; GFX789-NEXT: ;;#ASMSTART 764; GFX789-NEXT: ;;#ASMEND 765; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 766; 767; GFX10-LABEL: test_setreg_full_denorm_mode_42: 768; GFX10: ; %bb.0: 769; GFX10-NEXT: ; implicit-def: $vcc_hi 770; GFX10-NEXT: s_denorm_mode 10 ; encoding: [0x0a,0x00,0xa5,0xbf] 771; GFX10-NEXT: ;;#ASMSTART 772; GFX10-NEXT: ;;#ASMEND 773; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 774 call void @llvm.amdgcn.s.setreg(i32 6401, i32 42) 775 call void asm sideeffect "", ""() 776 ret void 777} 778 779; Sets all fp round and fp denorm bits. 780define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_0() { 781; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_0: 782; GFX6: ; %bb.0: 783; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0 ; encoding: [0x01,0x38,0x80,0xba,0x00,0x00,0x00,0x00] 784; GFX6-NEXT: ;;#ASMSTART 785; GFX6-NEXT: ;;#ASMEND 786; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 787; 788; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_0: 789; GFX789: ; %bb.0: 790; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0 ; encoding: [0x01,0x38,0x00,0xba,0x00,0x00,0x00,0x00] 791; GFX789-NEXT: ;;#ASMSTART 792; GFX789-NEXT: ;;#ASMEND 793; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 794; 795; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_0: 796; GFX10: ; %bb.0: 797; GFX10-NEXT: s_round_mode 0x0 ; encoding: [0x00,0x00,0xa4,0xbf] 798; GFX10-NEXT: ; implicit-def: $vcc_hi 799; GFX10-NEXT: s_denorm_mode 0 ; encoding: [0x00,0x00,0xa5,0xbf] 800; GFX10-NEXT: ;;#ASMSTART 801; GFX10-NEXT: ;;#ASMEND 802; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 803 call void @llvm.amdgcn.s.setreg(i32 14337, i32 0) 804 call void asm sideeffect "", ""() 805 ret void 806} 807 808define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_1() { 809; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_1: 810; GFX6: ; %bb.0: 811; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 1 ; encoding: [0x01,0x38,0x80,0xba,0x01,0x00,0x00,0x00] 812; GFX6-NEXT: ;;#ASMSTART 813; GFX6-NEXT: ;;#ASMEND 814; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 815; 816; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_1: 817; GFX789: ; %bb.0: 818; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 1 ; encoding: [0x01,0x38,0x00,0xba,0x01,0x00,0x00,0x00] 819; GFX789-NEXT: ;;#ASMSTART 820; GFX789-NEXT: ;;#ASMEND 821; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 822; 823; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_1: 824; GFX10: ; %bb.0: 825; GFX10-NEXT: s_round_mode 0x1 ; encoding: [0x01,0x00,0xa4,0xbf] 826; GFX10-NEXT: ; implicit-def: $vcc_hi 827; GFX10-NEXT: s_denorm_mode 0 ; encoding: [0x00,0x00,0xa5,0xbf] 828; GFX10-NEXT: ;;#ASMSTART 829; GFX10-NEXT: ;;#ASMEND 830; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 831 call void @llvm.amdgcn.s.setreg(i32 14337, i32 1) 832 call void asm sideeffect "", ""() 833 ret void 834} 835 836define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_2() { 837; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_2: 838; GFX6: ; %bb.0: 839; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 2 ; encoding: [0x01,0x38,0x80,0xba,0x02,0x00,0x00,0x00] 840; GFX6-NEXT: ;;#ASMSTART 841; GFX6-NEXT: ;;#ASMEND 842; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 843; 844; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_2: 845; GFX789: ; %bb.0: 846; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 2 ; encoding: [0x01,0x38,0x00,0xba,0x02,0x00,0x00,0x00] 847; GFX789-NEXT: ;;#ASMSTART 848; GFX789-NEXT: ;;#ASMEND 849; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 850; 851; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_2: 852; GFX10: ; %bb.0: 853; GFX10-NEXT: s_round_mode 0x2 ; encoding: [0x02,0x00,0xa4,0xbf] 854; GFX10-NEXT: ; implicit-def: $vcc_hi 855; GFX10-NEXT: s_denorm_mode 0 ; encoding: [0x00,0x00,0xa5,0xbf] 856; GFX10-NEXT: ;;#ASMSTART 857; GFX10-NEXT: ;;#ASMEND 858; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 859 call void @llvm.amdgcn.s.setreg(i32 14337, i32 2) 860 call void asm sideeffect "", ""() 861 ret void 862} 863 864define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_4() { 865; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_4: 866; GFX6: ; %bb.0: 867; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 4 ; encoding: [0x01,0x38,0x80,0xba,0x04,0x00,0x00,0x00] 868; GFX6-NEXT: ;;#ASMSTART 869; GFX6-NEXT: ;;#ASMEND 870; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 871; 872; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_4: 873; GFX789: ; %bb.0: 874; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 4 ; encoding: [0x01,0x38,0x00,0xba,0x04,0x00,0x00,0x00] 875; GFX789-NEXT: ;;#ASMSTART 876; GFX789-NEXT: ;;#ASMEND 877; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 878; 879; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_4: 880; GFX10: ; %bb.0: 881; GFX10-NEXT: s_round_mode 0x4 ; encoding: [0x04,0x00,0xa4,0xbf] 882; GFX10-NEXT: ; implicit-def: $vcc_hi 883; GFX10-NEXT: s_denorm_mode 0 ; encoding: [0x00,0x00,0xa5,0xbf] 884; GFX10-NEXT: ;;#ASMSTART 885; GFX10-NEXT: ;;#ASMEND 886; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 887 call void @llvm.amdgcn.s.setreg(i32 14337, i32 4) 888 call void asm sideeffect "", ""() 889 ret void 890} 891 892define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_8() { 893; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_8: 894; GFX6: ; %bb.0: 895; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 8 ; encoding: [0x01,0x38,0x80,0xba,0x08,0x00,0x00,0x00] 896; GFX6-NEXT: ;;#ASMSTART 897; GFX6-NEXT: ;;#ASMEND 898; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 899; 900; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_8: 901; GFX789: ; %bb.0: 902; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 8 ; encoding: [0x01,0x38,0x00,0xba,0x08,0x00,0x00,0x00] 903; GFX789-NEXT: ;;#ASMSTART 904; GFX789-NEXT: ;;#ASMEND 905; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 906; 907; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_8: 908; GFX10: ; %bb.0: 909; GFX10-NEXT: s_round_mode 0x8 ; encoding: [0x08,0x00,0xa4,0xbf] 910; GFX10-NEXT: ; implicit-def: $vcc_hi 911; GFX10-NEXT: s_denorm_mode 0 ; encoding: [0x00,0x00,0xa5,0xbf] 912; GFX10-NEXT: ;;#ASMSTART 913; GFX10-NEXT: ;;#ASMEND 914; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 915 call void @llvm.amdgcn.s.setreg(i32 14337, i32 8) 916 call void asm sideeffect "", ""() 917 ret void 918} 919 920define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_16() { 921; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_16: 922; GFX6: ; %bb.0: 923; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 16 ; encoding: [0x01,0x38,0x80,0xba,0x10,0x00,0x00,0x00] 924; GFX6-NEXT: ;;#ASMSTART 925; GFX6-NEXT: ;;#ASMEND 926; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 927; 928; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_16: 929; GFX789: ; %bb.0: 930; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 16 ; encoding: [0x01,0x38,0x00,0xba,0x10,0x00,0x00,0x00] 931; GFX789-NEXT: ;;#ASMSTART 932; GFX789-NEXT: ;;#ASMEND 933; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 934; 935; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_16: 936; GFX10: ; %bb.0: 937; GFX10-NEXT: s_round_mode 0x0 ; encoding: [0x00,0x00,0xa4,0xbf] 938; GFX10-NEXT: ; implicit-def: $vcc_hi 939; GFX10-NEXT: s_denorm_mode 1 ; encoding: [0x01,0x00,0xa5,0xbf] 940; GFX10-NEXT: ;;#ASMSTART 941; GFX10-NEXT: ;;#ASMEND 942; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 943 call void @llvm.amdgcn.s.setreg(i32 14337, i32 16) 944 call void asm sideeffect "", ""() 945 ret void 946} 947 948define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_32() { 949; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_32: 950; GFX6: ; %bb.0: 951; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 32 ; encoding: [0x01,0x38,0x80,0xba,0x20,0x00,0x00,0x00] 952; GFX6-NEXT: ;;#ASMSTART 953; GFX6-NEXT: ;;#ASMEND 954; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 955; 956; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_32: 957; GFX789: ; %bb.0: 958; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 32 ; encoding: [0x01,0x38,0x00,0xba,0x20,0x00,0x00,0x00] 959; GFX789-NEXT: ;;#ASMSTART 960; GFX789-NEXT: ;;#ASMEND 961; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 962; 963; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_32: 964; GFX10: ; %bb.0: 965; GFX10-NEXT: s_round_mode 0x0 ; encoding: [0x00,0x00,0xa4,0xbf] 966; GFX10-NEXT: ; implicit-def: $vcc_hi 967; GFX10-NEXT: s_denorm_mode 2 ; encoding: [0x02,0x00,0xa5,0xbf] 968; GFX10-NEXT: ;;#ASMSTART 969; GFX10-NEXT: ;;#ASMEND 970; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 971 call void @llvm.amdgcn.s.setreg(i32 14337, i32 32) 972 call void asm sideeffect "", ""() 973 ret void 974} 975 976define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_64() { 977; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_64: 978; GFX6: ; %bb.0: 979; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 64 ; encoding: [0x01,0x38,0x80,0xba,0x40,0x00,0x00,0x00] 980; GFX6-NEXT: ;;#ASMSTART 981; GFX6-NEXT: ;;#ASMEND 982; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 983; 984; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_64: 985; GFX789: ; %bb.0: 986; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 64 ; encoding: [0x01,0x38,0x00,0xba,0x40,0x00,0x00,0x00] 987; GFX789-NEXT: ;;#ASMSTART 988; GFX789-NEXT: ;;#ASMEND 989; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 990; 991; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_64: 992; GFX10: ; %bb.0: 993; GFX10-NEXT: s_round_mode 0x0 ; encoding: [0x00,0x00,0xa4,0xbf] 994; GFX10-NEXT: ; implicit-def: $vcc_hi 995; GFX10-NEXT: s_denorm_mode 4 ; encoding: [0x04,0x00,0xa5,0xbf] 996; GFX10-NEXT: ;;#ASMSTART 997; GFX10-NEXT: ;;#ASMEND 998; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 999 call void @llvm.amdgcn.s.setreg(i32 14337, i32 64) 1000 call void asm sideeffect "", ""() 1001 ret void 1002} 1003 1004define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_128() { 1005; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_128: 1006; GFX6: ; %bb.0: 1007; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0x80 ; encoding: [0x01,0x38,0x80,0xba,0x80,0x00,0x00,0x00] 1008; GFX6-NEXT: ;;#ASMSTART 1009; GFX6-NEXT: ;;#ASMEND 1010; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1011; 1012; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_128: 1013; GFX789: ; %bb.0: 1014; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0x80 ; encoding: [0x01,0x38,0x00,0xba,0x80,0x00,0x00,0x00] 1015; GFX789-NEXT: ;;#ASMSTART 1016; GFX789-NEXT: ;;#ASMEND 1017; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1018; 1019; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_128: 1020; GFX10: ; %bb.0: 1021; GFX10-NEXT: s_round_mode 0x0 ; encoding: [0x00,0x00,0xa4,0xbf] 1022; GFX10-NEXT: ; implicit-def: $vcc_hi 1023; GFX10-NEXT: s_denorm_mode 8 ; encoding: [0x08,0x00,0xa5,0xbf] 1024; GFX10-NEXT: ;;#ASMSTART 1025; GFX10-NEXT: ;;#ASMEND 1026; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1027 call void @llvm.amdgcn.s.setreg(i32 14337, i32 128) 1028 call void asm sideeffect "", ""() 1029 ret void 1030} 1031 1032define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_15() { 1033; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_15: 1034; GFX6: ; %bb.0: 1035; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 15 ; encoding: [0x01,0x38,0x80,0xba,0x0f,0x00,0x00,0x00] 1036; GFX6-NEXT: ;;#ASMSTART 1037; GFX6-NEXT: ;;#ASMEND 1038; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1039; 1040; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_15: 1041; GFX789: ; %bb.0: 1042; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 15 ; encoding: [0x01,0x38,0x00,0xba,0x0f,0x00,0x00,0x00] 1043; GFX789-NEXT: ;;#ASMSTART 1044; GFX789-NEXT: ;;#ASMEND 1045; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1046; 1047; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_15: 1048; GFX10: ; %bb.0: 1049; GFX10-NEXT: s_round_mode 0xf ; encoding: [0x0f,0x00,0xa4,0xbf] 1050; GFX10-NEXT: ; implicit-def: $vcc_hi 1051; GFX10-NEXT: s_denorm_mode 0 ; encoding: [0x00,0x00,0xa5,0xbf] 1052; GFX10-NEXT: ;;#ASMSTART 1053; GFX10-NEXT: ;;#ASMEND 1054; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1055 call void @llvm.amdgcn.s.setreg(i32 14337, i32 15) 1056 call void asm sideeffect "", ""() 1057 ret void 1058} 1059 1060define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_255() { 1061; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_255: 1062; GFX6: ; %bb.0: 1063; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0xff ; encoding: [0x01,0x38,0x80,0xba,0xff,0x00,0x00,0x00] 1064; GFX6-NEXT: ;;#ASMSTART 1065; GFX6-NEXT: ;;#ASMEND 1066; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1067; 1068; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_255: 1069; GFX789: ; %bb.0: 1070; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0xff ; encoding: [0x01,0x38,0x00,0xba,0xff,0x00,0x00,0x00] 1071; GFX789-NEXT: ;;#ASMSTART 1072; GFX789-NEXT: ;;#ASMEND 1073; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1074; 1075; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_255: 1076; GFX10: ; %bb.0: 1077; GFX10-NEXT: s_round_mode 0xf ; encoding: [0x0f,0x00,0xa4,0xbf] 1078; GFX10-NEXT: ; implicit-def: $vcc_hi 1079; GFX10-NEXT: s_denorm_mode 15 ; encoding: [0x0f,0x00,0xa5,0xbf] 1080; GFX10-NEXT: ;;#ASMSTART 1081; GFX10-NEXT: ;;#ASMEND 1082; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1083 call void @llvm.amdgcn.s.setreg(i32 14337, i32 255) 1084 call void asm sideeffect "", ""() 1085 ret void 1086} 1087 1088; Truncate extra high bit 1089define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_597() { 1090; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_597: 1091; GFX6: ; %bb.0: 1092; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0x255 ; encoding: [0x01,0x38,0x80,0xba,0x55,0x02,0x00,0x00] 1093; GFX6-NEXT: ;;#ASMSTART 1094; GFX6-NEXT: ;;#ASMEND 1095; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1096; 1097; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_597: 1098; GFX789: ; %bb.0: 1099; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0x255 ; encoding: [0x01,0x38,0x00,0xba,0x55,0x02,0x00,0x00] 1100; GFX789-NEXT: ;;#ASMSTART 1101; GFX789-NEXT: ;;#ASMEND 1102; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1103; 1104; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_597: 1105; GFX10: ; %bb.0: 1106; GFX10-NEXT: s_round_mode 0x5 ; encoding: [0x05,0x00,0xa4,0xbf] 1107; GFX10-NEXT: ; implicit-def: $vcc_hi 1108; GFX10-NEXT: s_denorm_mode 5 ; encoding: [0x05,0x00,0xa5,0xbf] 1109; GFX10-NEXT: ;;#ASMSTART 1110; GFX10-NEXT: ;;#ASMEND 1111; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1112 call void @llvm.amdgcn.s.setreg(i32 14337, i32 597) 1113 call void asm sideeffect "", ""() 1114 ret void 1115} 1116 1117define amdgpu_kernel void @test_setreg_set_8_bits_straddles_round_and_denorm() { 1118; GFX6-LABEL: test_setreg_set_8_bits_straddles_round_and_denorm: 1119; GFX6: ; %bb.0: 1120; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 8), 0xff ; encoding: [0x81,0x38,0x80,0xba,0xff,0x00,0x00,0x00] 1121; GFX6-NEXT: ;;#ASMSTART 1122; GFX6-NEXT: ;;#ASMEND 1123; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1124; 1125; GFX789-LABEL: test_setreg_set_8_bits_straddles_round_and_denorm: 1126; GFX789: ; %bb.0: 1127; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 8), 0xff ; encoding: [0x81,0x38,0x00,0xba,0xff,0x00,0x00,0x00] 1128; GFX789-NEXT: ;;#ASMSTART 1129; GFX789-NEXT: ;;#ASMEND 1130; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1131; 1132; GFX10-LABEL: test_setreg_set_8_bits_straddles_round_and_denorm: 1133; GFX10: ; %bb.0: 1134; GFX10-NEXT: ; implicit-def: $vcc_hi 1135; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 8), 0xff ; encoding: [0x81,0x38,0x80,0xba,0xff,0x00,0x00,0x00] 1136; GFX10-NEXT: ;;#ASMSTART 1137; GFX10-NEXT: ;;#ASMEND 1138; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1139 call void @llvm.amdgcn.s.setreg(i32 14465, i32 255) 1140 call void asm sideeffect "", ""() 1141 ret void 1142} 1143 1144define amdgpu_kernel void @test_setreg_set_4_bits_straddles_round_and_denorm() { 1145; GFX6-LABEL: test_setreg_set_4_bits_straddles_round_and_denorm: 1146; GFX6: ; %bb.0: 1147; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 4), 15 ; encoding: [0x81,0x18,0x80,0xba,0x0f,0x00,0x00,0x00] 1148; GFX6-NEXT: ;;#ASMSTART 1149; GFX6-NEXT: ;;#ASMEND 1150; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1151; 1152; GFX789-LABEL: test_setreg_set_4_bits_straddles_round_and_denorm: 1153; GFX789: ; %bb.0: 1154; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 4), 15 ; encoding: [0x81,0x18,0x00,0xba,0x0f,0x00,0x00,0x00] 1155; GFX789-NEXT: ;;#ASMSTART 1156; GFX789-NEXT: ;;#ASMEND 1157; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1158; 1159; GFX10-LABEL: test_setreg_set_4_bits_straddles_round_and_denorm: 1160; GFX10: ; %bb.0: 1161; GFX10-NEXT: ; implicit-def: $vcc_hi 1162; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 4), 15 ; encoding: [0x81,0x18,0x80,0xba,0x0f,0x00,0x00,0x00] 1163; GFX10-NEXT: ;;#ASMSTART 1164; GFX10-NEXT: ;;#ASMEND 1165; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1166 call void @llvm.amdgcn.s.setreg(i32 6273, i32 15) 1167 call void asm sideeffect "", ""() 1168 ret void 1169} 1170 1171; FIXME: Broken for DAG 1172define void @test_setreg_roundingmode_var_vgpr(i32 %var.mode) { 1173; GFX6-LABEL: test_setreg_roundingmode_var_vgpr: 1174; GFX6: ; %bb.0: 1175; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf] 1176; GFX6-NEXT: v_readfirstlane_b32 s4, v0 ; encoding: [0x00,0x05,0x08,0x7e] 1177; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 3), s4 ; encoding: [0x01,0x10,0x84,0xb9] 1178; GFX6-NEXT: ;;#ASMSTART 1179; GFX6-NEXT: ;;#ASMEND 1180; GFX6-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x20,0x80,0xbe] 1181; 1182; GFX789-LABEL: test_setreg_roundingmode_var_vgpr: 1183; GFX789: ; %bb.0: 1184; GFX789-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf] 1185; GFX789-NEXT: v_readfirstlane_b32 s4, v0 ; encoding: [0x00,0x05,0x08,0x7e] 1186; GFX789-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 3), s4 ; encoding: [0x01,0x10,0x04,0xb9] 1187; GFX789-NEXT: ;;#ASMSTART 1188; GFX789-NEXT: ;;#ASMEND 1189; GFX789-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x1d,0x80,0xbe] 1190; 1191; GFX10-LABEL: test_setreg_roundingmode_var_vgpr: 1192; GFX10: ; %bb.0: 1193; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf] 1194; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb] 1195; GFX10-NEXT: v_readfirstlane_b32 s4, v0 ; encoding: [0x00,0x05,0x08,0x7e] 1196; GFX10-NEXT: ; implicit-def: $vcc_hi 1197; GFX10-NEXT: ;;#ASMSTART 1198; GFX10-NEXT: ;;#ASMEND 1199; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 3), s4 ; encoding: [0x01,0x10,0x84,0xb9] 1200; GFX10-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x20,0x80,0xbe] 1201 call void @llvm.amdgcn.s.setreg(i32 4097, i32 %var.mode) 1202 call void asm sideeffect "", ""() 1203 ret void 1204} 1205 1206declare void @llvm.amdgcn.s.setreg(i32 immarg, i32) #0 1207 1208attributes #0 = { nounwind } 1209