1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -global-isel -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX906 %s 3; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1011 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10 %s 4; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10 %s 5 6define i32 @v_udot4(i32 %a, i32 %b, i32 %c) { 7; GFX906-LABEL: v_udot4: 8; GFX906: ; %bb.0: 9; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 10; GFX906-NEXT: v_dot4_u32_u8 v0, v0, v1, v2 11; GFX906-NEXT: s_setpc_b64 s[30:31] 12; 13; GFX10-LABEL: v_udot4: 14; GFX10: ; %bb.0: 15; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 16; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 17; GFX10-NEXT: v_dot4_u32_u8 v0, v0, v1, v2 18; GFX10-NEXT: ; implicit-def: $vcc_hi 19; GFX10-NEXT: s_setpc_b64 s[30:31] 20 %r = call i32 @llvm.amdgcn.udot4(i32 %a, i32 %b, i32 %c, i1 false) 21 ret i32 %r 22} 23 24define i32 @v_udot4_clamp(i32 %a, i32 %b, i32 %c) { 25; GFX906-LABEL: v_udot4_clamp: 26; GFX906: ; %bb.0: 27; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 28; GFX906-NEXT: v_dot4_u32_u8 v0, v0, v1, v2 clamp 29; GFX906-NEXT: s_setpc_b64 s[30:31] 30; 31; GFX10-LABEL: v_udot4_clamp: 32; GFX10: ; %bb.0: 33; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 34; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 35; GFX10-NEXT: v_dot4_u32_u8 v0, v0, v1, v2 clamp 36; GFX10-NEXT: ; implicit-def: $vcc_hi 37; GFX10-NEXT: s_setpc_b64 s[30:31] 38 %r = call i32 @llvm.amdgcn.udot4(i32 %a, i32 %b, i32 %c, i1 true) 39 ret i32 %r 40} 41 42; FIXME: bitcast should not expand 43define i32 @v_udot4_cast_v4i8(<4 x i8> %a, <4 x i8> %b, i32 %c) { 44; GFX906-LABEL: v_udot4_cast_v4i8: 45; GFX906: ; %bb.0: 46; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 47; GFX906-NEXT: s_mov_b32 s5, 8 48; GFX906-NEXT: s_movk_i32 s4, 0xff 49; GFX906-NEXT: v_lshlrev_b32_sdwa v1, s5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 50; GFX906-NEXT: v_and_or_b32 v0, v0, s4, v1 51; GFX906-NEXT: v_and_b32_e32 v1, s4, v2 52; GFX906-NEXT: v_and_b32_e32 v2, s4, v3 53; GFX906-NEXT: v_lshlrev_b32_e32 v1, 16, v1 54; GFX906-NEXT: v_lshlrev_b32_e32 v2, 24, v2 55; GFX906-NEXT: v_or3_b32 v0, v0, v1, v2 56; GFX906-NEXT: v_lshlrev_b32_sdwa v1, s5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 57; GFX906-NEXT: v_and_b32_e32 v2, s4, v6 58; GFX906-NEXT: v_and_b32_e32 v3, s4, v7 59; GFX906-NEXT: v_and_or_b32 v1, v4, s4, v1 60; GFX906-NEXT: v_lshlrev_b32_e32 v2, 16, v2 61; GFX906-NEXT: v_lshlrev_b32_e32 v3, 24, v3 62; GFX906-NEXT: v_or3_b32 v1, v1, v2, v3 63; GFX906-NEXT: v_dot4_u32_u8 v0, v0, v1, v8 64; GFX906-NEXT: s_setpc_b64 s[30:31] 65; 66; GFX10-LABEL: v_udot4_cast_v4i8: 67; GFX10: ; %bb.0: 68; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 69; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 70; GFX10-NEXT: s_mov_b32 s4, 8 71; GFX10-NEXT: s_movk_i32 s5, 0xff 72; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 73; GFX10-NEXT: ; implicit-def: $vcc_hi 74; GFX10-NEXT: v_and_or_b32 v0, v0, s5, v1 75; GFX10-NEXT: v_and_b32_e32 v1, s5, v2 76; GFX10-NEXT: v_and_b32_e32 v2, s5, v3 77; GFX10-NEXT: v_lshlrev_b32_sdwa v3, s4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 78; GFX10-NEXT: v_and_b32_e32 v5, s5, v6 79; GFX10-NEXT: v_and_b32_e32 v6, s5, v7 80; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1 81; GFX10-NEXT: v_lshlrev_b32_e32 v2, 24, v2 82; GFX10-NEXT: v_and_or_b32 v3, v4, s5, v3 83; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v5 84; GFX10-NEXT: v_lshlrev_b32_e32 v5, 24, v6 85; GFX10-NEXT: v_or3_b32 v7, v0, v1, v2 86; GFX10-NEXT: v_or3_b32 v1, v3, v4, v5 87; GFX10-NEXT: v_dot4_u32_u8 v0, v7, v1, v8 88; GFX10-NEXT: s_setpc_b64 s[30:31] 89 %a.cast = bitcast <4 x i8> %a to i32 90 %b.cast = bitcast <4 x i8> %b to i32 91 %r = call i32 @llvm.amdgcn.udot4(i32 %a.cast, i32 %b.cast, i32 %c, i1 false) 92 ret i32 %r 93} 94 95define i32 @v_udot4_fnegf32_a(float %a, i32 %b, i32 %c) { 96; GFX906-LABEL: v_udot4_fnegf32_a: 97; GFX906: ; %bb.0: 98; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 99; GFX906-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 100; GFX906-NEXT: v_dot4_u32_u8 v0, v0, v1, v2 101; GFX906-NEXT: s_setpc_b64 s[30:31] 102; 103; GFX10-LABEL: v_udot4_fnegf32_a: 104; GFX10: ; %bb.0: 105; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 106; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 107; GFX10-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 108; GFX10-NEXT: ; implicit-def: $vcc_hi 109; GFX10-NEXT: v_dot4_u32_u8 v0, v0, v1, v2 110; GFX10-NEXT: s_setpc_b64 s[30:31] 111 %neg.a = fneg float %a 112 %cast.neg.a = bitcast float %neg.a to i32 113 %r = call i32 @llvm.amdgcn.udot4(i32 %cast.neg.a, i32 %b, i32 %c, i1 false) 114 ret i32 %r 115} 116 117define i32 @v_udot4_fnegv2f16_a(<2 x half> %a, i32 %b, i32 %c) { 118; GFX906-LABEL: v_udot4_fnegv2f16_a: 119; GFX906: ; %bb.0: 120; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 121; GFX906-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 122; GFX906-NEXT: v_dot4_u32_u8 v0, v0, v1, v2 123; GFX906-NEXT: s_setpc_b64 s[30:31] 124; 125; GFX10-LABEL: v_udot4_fnegv2f16_a: 126; GFX10: ; %bb.0: 127; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 128; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 129; GFX10-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 130; GFX10-NEXT: ; implicit-def: $vcc_hi 131; GFX10-NEXT: v_dot4_u32_u8 v0, v0, v1, v2 132; GFX10-NEXT: s_setpc_b64 s[30:31] 133 %neg.a = fneg <2 x half> %a 134 %cast.neg.a = bitcast <2 x half> %neg.a to i32 135 %r = call i32 @llvm.amdgcn.udot4(i32 %cast.neg.a, i32 %b, i32 %c, i1 false) 136 ret i32 %r 137} 138 139declare i32 @llvm.amdgcn.udot4(i32, i32, i32, i1 immarg) #0 140 141attributes #0 = { nounwind readnone speculatable } 142