1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
3# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
4
5---
6name: writelane_sss
7legalized: true
8
9body: |
10  bb.0:
11    liveins: $sgpr0, $sgpr1, $sgpr2
12    ; CHECK-LABEL: name: writelane_sss
13    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
14    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
15    ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
16    ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
17    ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.writelane), [[COPY]](s32), [[COPY1]](s32), [[COPY3]](s32)
18    %0:_(s32) = COPY $sgpr0
19    %1:_(s32) = COPY $sgpr1
20    %2:_(s32) = COPY $sgpr2
21    %3:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.writelane), %0, %1, %2
22...
23
24---
25name: writelane_ssv
26legalized: true
27
28body: |
29  bb.0:
30    liveins: $sgpr0, $sgpr1, $vgpr0
31    ; CHECK-LABEL: name: writelane_ssv
32    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
33    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
34    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
35    ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.writelane), [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
36    %0:_(s32) = COPY $sgpr0
37    %1:_(s32) = COPY $sgpr1
38    %2:_(s32) = COPY $vgpr0
39    %3:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.writelane), %0, %1, %2
40...
41
42---
43name: writelane_vsv
44legalized: true
45
46body: |
47  bb.0:
48    liveins: $sgpr0, $vgpr0, $vgpr1
49    ; CHECK-LABEL: name: writelane_vsv
50    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
51    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
52    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
53    ; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY]](s32), implicit $exec
54    ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.writelane), [[V_READFIRSTLANE_B32_]](s32), [[COPY1]](s32), [[COPY2]](s32)
55    %0:_(s32) = COPY $vgpr0
56    %1:_(s32) = COPY $sgpr0
57    %2:_(s32) = COPY $vgpr1
58    %3:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.writelane), %0, %1, %2
59...
60
61---
62name: writelane_vvv
63legalized: true
64
65body: |
66  bb.0:
67    liveins: $vgpr0, $vgpr1
68    ; CHECK-LABEL: name: writelane_vvv
69    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
70    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
71    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
72    ; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY]](s32), implicit $exec
73    ; CHECK: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY1]](s32), implicit $exec
74    ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.writelane), [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[COPY2]](s32)
75    %0:_(s32) = COPY $vgpr0
76    %1:_(s32) = COPY $vgpr1
77    %2:_(s32) = COPY $vgpr2
78    %3:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.writelane), %0, %1, %2
79...
80
81---
82name: writelane_svv
83legalized: true
84
85body: |
86  bb.0:
87    liveins: $sgpr0, $vgpr0, $vgpr1
88    ; CHECK-LABEL: name: writelane_svv
89    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
90    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
91    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
92    ; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY1]](s32), implicit $exec
93    ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.writelane), [[COPY]](s32), [[V_READFIRSTLANE_B32_]](s32), [[COPY2]](s32)
94    %0:_(s32) = COPY $sgpr0
95    %1:_(s32) = COPY $vgpr0
96    %2:_(s32) = COPY $vgpr1
97    %3:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.writelane), %0, %1, %2
98...
99