1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s 3# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s 4 5--- 6name: reg_sequence_ss_vreg 7legalized: true 8tracksRegLiveness: true 9 10body: | 11 bb.0: 12 liveins: $sgpr0, $sgpr1 13 14 ; CHECK-LABEL: name: reg_sequence_ss_vreg 15 ; CHECK: liveins: $sgpr0, $sgpr1 16 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 17 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 18 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr(s64) = REG_SEQUENCE [[COPY]](s32), %subreg.sub0, [[COPY1]](s32), %subreg.sub1 19 %0:_(s32) = COPY $sgpr0 20 %1:_(s32) = COPY $sgpr1 21 %2:_(s64) = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1 22... 23 24--- 25name: reg_sequence_ss_physreg 26legalized: true 27tracksRegLiveness: true 28 29body: | 30 bb.0: 31 liveins: $sgpr0, $sgpr1 32 33 ; CHECK-LABEL: name: reg_sequence_ss_physreg 34 ; CHECK: liveins: $sgpr0, $sgpr1 35 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $sgpr1, %subreg.sub1 36 %0:_(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $sgpr1, %subreg.sub1 37... 38 39--- 40name: reg_sequence_sv_vreg 41legalized: true 42tracksRegLiveness: true 43 44body: | 45 bb.0: 46 liveins: $sgpr0, $vgpr0 47 48 ; CHECK-LABEL: name: reg_sequence_sv_vreg 49 ; CHECK: liveins: $sgpr0, $vgpr0 50 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 51 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 52 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE [[COPY]](s32), %subreg.sub0, [[COPY1]](s32), %subreg.sub1 53 %0:_(s32) = COPY $sgpr0 54 %1:_(s32) = COPY $vgpr0 55 %2:_(s64) = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1 56... 57 58--- 59name: reg_sequence_sv_physreg 60legalized: true 61tracksRegLiveness: true 62 63body: | 64 bb.0: 65 liveins: $sgpr0, $vgpr0 66 67 ; CHECK-LABEL: name: reg_sequence_sv_physreg 68 ; CHECK: liveins: $sgpr0, $vgpr0 69 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $vgpr0, %subreg.sub1 70 %0:_(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $vgpr0, %subreg.sub1 71... 72 73--- 74name: reg_sequence_vs_vreg 75legalized: true 76tracksRegLiveness: true 77 78body: | 79 bb.0: 80 liveins: $vgpr0, $sgpr0 81 82 ; CHECK-LABEL: name: reg_sequence_vs_vreg 83 ; CHECK: liveins: $vgpr0, $sgpr0 84 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 85 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 86 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE [[COPY]](s32), %subreg.sub0, [[COPY1]](s32), %subreg.sub1 87 %0:_(s32) = COPY $vgpr0 88 %1:_(s32) = COPY $sgpr0 89 %2:_(s64) = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1 90... 91 92--- 93name: reg_sequence_vs_physreg 94legalized: true 95tracksRegLiveness: true 96 97body: | 98 bb.0: 99 liveins: $vgpr0, $sgpr0 100 101 ; CHECK-LABEL: name: reg_sequence_vs_physreg 102 ; CHECK: liveins: $vgpr0, $sgpr0 103 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE $vgpr0, %subreg.sub0, $sgpr0, %subreg.sub1 104 %0:_(s64) = REG_SEQUENCE $vgpr0, %subreg.sub0, $sgpr0, %subreg.sub1 105... 106 107--- 108name: reg_sequence_vv_vreg 109legalized: true 110tracksRegLiveness: true 111 112body: | 113 bb.0: 114 liveins: $vgpr0, $vgpr1 115 116 ; CHECK-LABEL: name: reg_sequence_vv_vreg 117 ; CHECK: liveins: $vgpr0, $vgpr1 118 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 119 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 120 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE [[COPY]](s32), %subreg.sub0, [[COPY1]](s32), %subreg.sub1 121 %0:_(s32) = COPY $vgpr0 122 %1:_(s32) = COPY $vgpr1 123 %2:_(s64) = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1 124... 125 126--- 127name: reg_sequence_vv_physreg 128legalized: true 129tracksRegLiveness: true 130 131body: | 132 bb.0: 133 liveins: $vgpr0, $vgpr1 134 135 ; CHECK-LABEL: name: reg_sequence_vv_physreg 136 ; CHECK: liveins: $vgpr0, $vgpr1 137 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE $vgpr0, %subreg.sub0, $vgpr1, %subreg.sub1 138 %0:_(s64) = REG_SEQUENCE $vgpr0, %subreg.sub0, $vgpr1, %subreg.sub1 139... 140 141