1; Test v4f32 comparisons.
2;
3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
4
5; Test oeq.
6define <4 x i32> @f1(<4 x float> %val1, <4 x float> %val2) {
7; CHECK-LABEL: f1:
8; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24
9; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24
10; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26
11; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26
12; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]
13; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]
14; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]
15; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]
16; CHECK-DAG: vfcedb [[HIGHRES:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]]
17; CHECK-DAG: vfcedb [[LOWRES:%v[0-9]+]], [[LOW0D]], [[LOW1D]]
18; CHECK: vpkg %v24, [[HIGHRES]], [[LOWRES]]
19; CHECK-NEXT: br %r14
20  %cmp = fcmp oeq <4 x float> %val1, %val2
21  %ret = sext <4 x i1> %cmp to <4 x i32>
22  ret <4 x i32> %ret
23}
24
25; Test one.
26define <4 x i32> @f2(<4 x float> %val1, <4 x float> %val2) {
27; CHECK-LABEL: f2:
28; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24
29; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24
30; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26
31; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26
32; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]
33; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]
34; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]
35; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]
36; CHECK-DAG: vfchdb [[HIGHRES0:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]]
37; CHECK-DAG: vfchdb [[LOWRES0:%v[0-9]+]], [[LOW0D]], [[LOW1D]]
38; CHECK-DAG: vfchdb [[HIGHRES1:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]]
39; CHECK-DAG: vfchdb [[LOWRES1:%v[0-9]+]], [[LOW1D]], [[LOW0D]]
40; CHECK-DAG: vpkg [[RES0:%v[0-9]+]], [[HIGHRES0]], [[LOWRES0]]
41; CHECK-DAG: vpkg [[RES1:%v[0-9]+]], [[HIGHRES1]], [[LOWRES1]]
42; CHECK: vo %v24, [[RES1]], [[RES0]]
43; CHECK-NEXT: br %r14
44  %cmp = fcmp one <4 x float> %val1, %val2
45  %ret = sext <4 x i1> %cmp to <4 x i32>
46  ret <4 x i32> %ret
47}
48
49; Test ogt.
50define <4 x i32> @f3(<4 x float> %val1, <4 x float> %val2) {
51; CHECK-LABEL: f3:
52; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24
53; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24
54; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26
55; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26
56; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]
57; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]
58; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]
59; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]
60; CHECK-DAG: vfchdb [[HIGHRES:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]]
61; CHECK-DAG: vfchdb [[LOWRES:%v[0-9]+]], [[LOW0D]], [[LOW1D]]
62; CHECK: vpkg %v24, [[HIGHRES]], [[LOWRES]]
63; CHECK-NEXT: br %r14
64  %cmp = fcmp ogt <4 x float> %val1, %val2
65  %ret = sext <4 x i1> %cmp to <4 x i32>
66  ret <4 x i32> %ret
67}
68
69; Test oge.
70define <4 x i32> @f4(<4 x float> %val1, <4 x float> %val2) {
71; CHECK-LABEL: f4:
72; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24
73; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24
74; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26
75; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26
76; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]
77; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]
78; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]
79; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]
80; CHECK-DAG: vfchedb [[HIGHRES:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]]
81; CHECK-DAG: vfchedb [[LOWRES:%v[0-9]+]], [[LOW0D]], [[LOW1D]]
82; CHECK: vpkg %v24, [[HIGHRES]], [[LOWRES]]
83; CHECK-NEXT: br %r14
84  %cmp = fcmp oge <4 x float> %val1, %val2
85  %ret = sext <4 x i1> %cmp to <4 x i32>
86  ret <4 x i32> %ret
87}
88
89; Test ole.
90define <4 x i32> @f5(<4 x float> %val1, <4 x float> %val2) {
91; CHECK-LABEL: f5:
92; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24
93; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24
94; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26
95; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26
96; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]
97; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]
98; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]
99; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]
100; CHECK-DAG: vfchedb [[HIGHRES:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]]
101; CHECK-DAG: vfchedb [[LOWRES:%v[0-9]+]], [[LOW1D]], [[LOW0D]]
102; CHECK: vpkg %v24, [[HIGHRES]], [[LOWRES]]
103; CHECK-NEXT: br %r14
104  %cmp = fcmp ole <4 x float> %val1, %val2
105  %ret = sext <4 x i1> %cmp to <4 x i32>
106  ret <4 x i32> %ret
107}
108
109; Test olt.
110define <4 x i32> @f6(<4 x float> %val1, <4 x float> %val2) {
111; CHECK-LABEL: f6:
112; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24
113; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24
114; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26
115; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26
116; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]
117; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]
118; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]
119; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]
120; CHECK-DAG: vfchdb [[HIGHRES:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]]
121; CHECK-DAG: vfchdb [[LOWRES:%v[0-9]+]], [[LOW1D]], [[LOW0D]]
122; CHECK: vpkg %v24, [[HIGHRES]], [[LOWRES]]
123; CHECK-NEXT: br %r14
124  %cmp = fcmp olt <4 x float> %val1, %val2
125  %ret = sext <4 x i1> %cmp to <4 x i32>
126  ret <4 x i32> %ret
127}
128
129; Test ueq.
130define <4 x i32> @f7(<4 x float> %val1, <4 x float> %val2) {
131; CHECK-LABEL: f7:
132; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24
133; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24
134; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26
135; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26
136; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]
137; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]
138; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]
139; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]
140; CHECK-DAG: vfchdb [[HIGHRES0:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]]
141; CHECK-DAG: vfchdb [[LOWRES0:%v[0-9]+]], [[LOW0D]], [[LOW1D]]
142; CHECK-DAG: vfchdb [[HIGHRES1:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]]
143; CHECK-DAG: vfchdb [[LOWRES1:%v[0-9]+]], [[LOW1D]], [[LOW0D]]
144; CHECK-DAG: vpkg [[RES0:%v[0-9]+]], [[HIGHRES0]], [[LOWRES0]]
145; CHECK-DAG: vpkg [[RES1:%v[0-9]+]], [[HIGHRES1]], [[LOWRES1]]
146; CHECK: vno %v24, [[RES1]], [[RES0]]
147; CHECK-NEXT: br %r14
148  %cmp = fcmp ueq <4 x float> %val1, %val2
149  %ret = sext <4 x i1> %cmp to <4 x i32>
150  ret <4 x i32> %ret
151}
152
153; Test une.
154define <4 x i32> @f8(<4 x float> %val1, <4 x float> %val2) {
155; CHECK-LABEL: f8:
156; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24
157; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24
158; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26
159; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26
160; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]
161; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]
162; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]
163; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]
164; CHECK-DAG: vfcedb [[HIGHRES:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]]
165; CHECK-DAG: vfcedb [[LOWRES:%v[0-9]+]], [[LOW0D]], [[LOW1D]]
166; CHECK: vpkg [[RES:%v[0-9]+]], [[HIGHRES]], [[LOWRES]]
167; CHECK-NEXT: vno %v24, [[RES]], [[RES]]
168; CHECK-NEXT: br %r14
169  %cmp = fcmp une <4 x float> %val1, %val2
170  %ret = sext <4 x i1> %cmp to <4 x i32>
171  ret <4 x i32> %ret
172}
173
174; Test ugt.
175define <4 x i32> @f9(<4 x float> %val1, <4 x float> %val2) {
176; CHECK-LABEL: f9:
177; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24
178; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24
179; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26
180; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26
181; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]
182; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]
183; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]
184; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]
185; CHECK-DAG: vfchedb [[HIGHRES:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]]
186; CHECK-DAG: vfchedb [[LOWRES:%v[0-9]+]], [[LOW1D]], [[LOW0D]]
187; CHECK: vpkg [[RES:%v[0-9]+]], [[HIGHRES]], [[LOWRES]]
188; CHECK-NEXT: vno %v24, [[RES]], [[RES]]
189; CHECK-NEXT: br %r14
190  %cmp = fcmp ugt <4 x float> %val1, %val2
191  %ret = sext <4 x i1> %cmp to <4 x i32>
192  ret <4 x i32> %ret
193}
194
195; Test uge.
196define <4 x i32> @f10(<4 x float> %val1, <4 x float> %val2) {
197; CHECK-LABEL: f10:
198; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24
199; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24
200; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26
201; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26
202; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]
203; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]
204; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]
205; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]
206; CHECK-DAG: vfchdb [[HIGHRES:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]]
207; CHECK-DAG: vfchdb [[LOWRES:%v[0-9]+]], [[LOW1D]], [[LOW0D]]
208; CHECK: vpkg [[RES:%v[0-9]+]], [[HIGHRES]], [[LOWRES]]
209; CHECK-NEXT: vno %v24, [[RES]], [[RES]]
210; CHECK-NEXT: br %r14
211  %cmp = fcmp uge <4 x float> %val1, %val2
212  %ret = sext <4 x i1> %cmp to <4 x i32>
213  ret <4 x i32> %ret
214}
215
216; Test ule.
217define <4 x i32> @f11(<4 x float> %val1, <4 x float> %val2) {
218; CHECK-LABEL: f11:
219; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24
220; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24
221; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26
222; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26
223; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]
224; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]
225; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]
226; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]
227; CHECK-DAG: vfchdb [[HIGHRES:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]]
228; CHECK-DAG: vfchdb [[LOWRES:%v[0-9]+]], [[LOW0D]], [[LOW1D]]
229; CHECK: vpkg [[RES:%v[0-9]+]], [[HIGHRES]], [[LOWRES]]
230; CHECK-NEXT: vno %v24, [[RES]], [[RES]]
231; CHECK-NEXT: br %r14
232  %cmp = fcmp ule <4 x float> %val1, %val2
233  %ret = sext <4 x i1> %cmp to <4 x i32>
234  ret <4 x i32> %ret
235}
236
237; Test ult.
238define <4 x i32> @f12(<4 x float> %val1, <4 x float> %val2) {
239; CHECK-LABEL: f12:
240; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24
241; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24
242; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26
243; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26
244; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]
245; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]
246; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]
247; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]
248; CHECK-DAG: vfchedb [[HIGHRES:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]]
249; CHECK-DAG: vfchedb [[LOWRES:%v[0-9]+]], [[LOW0D]], [[LOW1D]]
250; CHECK: vpkg [[RES:%v[0-9]+]], [[HIGHRES]], [[LOWRES]]
251; CHECK-NEXT: vno %v24, [[RES]], [[RES]]
252; CHECK-NEXT: br %r14
253  %cmp = fcmp ult <4 x float> %val1, %val2
254  %ret = sext <4 x i1> %cmp to <4 x i32>
255  ret <4 x i32> %ret
256}
257
258; Test ord.
259define <4 x i32> @f13(<4 x float> %val1, <4 x float> %val2) {
260; CHECK-LABEL: f13:
261; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24
262; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24
263; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26
264; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26
265; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]
266; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]
267; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]
268; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]
269; CHECK-DAG: vfchedb [[HIGHRES0:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]]
270; CHECK-DAG: vfchedb [[LOWRES0:%v[0-9]+]], [[LOW0D]], [[LOW1D]]
271; CHECK-DAG: vfchdb [[HIGHRES1:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]]
272; CHECK-DAG: vfchdb [[LOWRES1:%v[0-9]+]], [[LOW1D]], [[LOW0D]]
273; CHECK-DAG: vpkg [[RES0:%v[0-9]+]], [[HIGHRES0]], [[LOWRES0]]
274; CHECK-DAG: vpkg [[RES1:%v[0-9]+]], [[HIGHRES1]], [[LOWRES1]]
275; CHECK: vo %v24, [[RES1]], [[RES0]]
276; CHECK-NEXT: br %r14
277  %cmp = fcmp ord <4 x float> %val1, %val2
278  %ret = sext <4 x i1> %cmp to <4 x i32>
279  ret <4 x i32> %ret
280}
281
282; Test uno.
283define <4 x i32> @f14(<4 x float> %val1, <4 x float> %val2) {
284; CHECK-LABEL: f14:
285; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24
286; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24
287; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26
288; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26
289; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]
290; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]
291; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]
292; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]
293; CHECK-DAG: vfchedb [[HIGHRES0:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]]
294; CHECK-DAG: vfchedb [[LOWRES0:%v[0-9]+]], [[LOW0D]], [[LOW1D]]
295; CHECK-DAG: vfchdb [[HIGHRES1:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]]
296; CHECK-DAG: vfchdb [[LOWRES1:%v[0-9]+]], [[LOW1D]], [[LOW0D]]
297; CHECK-DAG: vpkg [[RES0:%v[0-9]+]], [[HIGHRES0]], [[LOWRES0]]
298; CHECK-DAG: vpkg [[RES1:%v[0-9]+]], [[HIGHRES1]], [[LOWRES1]]
299; CHECK: vno %v24, [[RES1]], [[RES0]]
300; CHECK-NEXT: br %r14
301  %cmp = fcmp uno <4 x float> %val1, %val2
302  %ret = sext <4 x i1> %cmp to <4 x i32>
303  ret <4 x i32> %ret
304}
305
306; Test oeq selects.
307define <4 x float> @f15(<4 x float> %val1, <4 x float> %val2,
308                        <4 x float> %val3, <4 x float> %val4) {
309; CHECK-LABEL: f15:
310; CHECK: vpkg [[REG:%v[0-9]+]],
311; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
312; CHECK-NEXT: br %r14
313  %cmp = fcmp oeq <4 x float> %val1, %val2
314  %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
315  ret <4 x float> %ret
316}
317
318; Test one selects.
319define <4 x float> @f16(<4 x float> %val1, <4 x float> %val2,
320                        <4 x float> %val3, <4 x float> %val4) {
321; CHECK-LABEL: f16:
322; CHECK: vo [[REG:%v[0-9]+]],
323; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
324; CHECK-NEXT: br %r14
325  %cmp = fcmp one <4 x float> %val1, %val2
326  %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
327  ret <4 x float> %ret
328}
329
330; Test ogt selects.
331define <4 x float> @f17(<4 x float> %val1, <4 x float> %val2,
332                        <4 x float> %val3, <4 x float> %val4) {
333; CHECK-LABEL: f17:
334; CHECK: vpkg [[REG:%v[0-9]+]],
335; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
336; CHECK-NEXT: br %r14
337  %cmp = fcmp ogt <4 x float> %val1, %val2
338  %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
339  ret <4 x float> %ret
340}
341
342; Test oge selects.
343define <4 x float> @f18(<4 x float> %val1, <4 x float> %val2,
344                        <4 x float> %val3, <4 x float> %val4) {
345; CHECK-LABEL: f18:
346; CHECK: vpkg [[REG:%v[0-9]+]],
347; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
348; CHECK-NEXT: br %r14
349  %cmp = fcmp oge <4 x float> %val1, %val2
350  %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
351  ret <4 x float> %ret
352}
353
354; Test ole selects.
355define <4 x float> @f19(<4 x float> %val1, <4 x float> %val2,
356                        <4 x float> %val3, <4 x float> %val4) {
357; CHECK-LABEL: f19:
358; CHECK: vpkg [[REG:%v[0-9]+]],
359; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
360; CHECK-NEXT: br %r14
361  %cmp = fcmp ole <4 x float> %val1, %val2
362  %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
363  ret <4 x float> %ret
364}
365
366; Test olt selects.
367define <4 x float> @f20(<4 x float> %val1, <4 x float> %val2,
368                        <4 x float> %val3, <4 x float> %val4) {
369; CHECK-LABEL: f20:
370; CHECK: vpkg [[REG:%v[0-9]+]],
371; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
372; CHECK-NEXT: br %r14
373  %cmp = fcmp olt <4 x float> %val1, %val2
374  %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
375  ret <4 x float> %ret
376}
377
378; Test ueq selects.
379define <4 x float> @f21(<4 x float> %val1, <4 x float> %val2,
380                        <4 x float> %val3, <4 x float> %val4) {
381; CHECK-LABEL: f21:
382; CHECK: vo [[REG:%v[0-9]+]],
383; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
384; CHECK-NEXT: br %r14
385  %cmp = fcmp ueq <4 x float> %val1, %val2
386  %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
387  ret <4 x float> %ret
388}
389
390; Test une selects.
391define <4 x float> @f22(<4 x float> %val1, <4 x float> %val2,
392                        <4 x float> %val3, <4 x float> %val4) {
393; CHECK-LABEL: f22:
394; CHECK: vpkg [[REG:%v[0-9]+]],
395; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
396; CHECK-NEXT: br %r14
397  %cmp = fcmp une <4 x float> %val1, %val2
398  %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
399  ret <4 x float> %ret
400}
401
402; Test ugt selects.
403define <4 x float> @f23(<4 x float> %val1, <4 x float> %val2,
404                        <4 x float> %val3, <4 x float> %val4) {
405; CHECK-LABEL: f23:
406; CHECK: vpkg [[REG:%v[0-9]+]],
407; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
408; CHECK-NEXT: br %r14
409  %cmp = fcmp ugt <4 x float> %val1, %val2
410  %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
411  ret <4 x float> %ret
412}
413
414; Test uge selects.
415define <4 x float> @f24(<4 x float> %val1, <4 x float> %val2,
416                        <4 x float> %val3, <4 x float> %val4) {
417; CHECK-LABEL: f24:
418; CHECK: vpkg [[REG:%v[0-9]+]],
419; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
420; CHECK-NEXT: br %r14
421  %cmp = fcmp uge <4 x float> %val1, %val2
422  %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
423  ret <4 x float> %ret
424}
425
426; Test ule selects.
427define <4 x float> @f25(<4 x float> %val1, <4 x float> %val2,
428                        <4 x float> %val3, <4 x float> %val4) {
429; CHECK-LABEL: f25:
430; CHECK: vpkg [[REG:%v[0-9]+]],
431; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
432; CHECK-NEXT: br %r14
433  %cmp = fcmp ule <4 x float> %val1, %val2
434  %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
435  ret <4 x float> %ret
436}
437
438; Test ult selects.
439define <4 x float> @f26(<4 x float> %val1, <4 x float> %val2,
440                        <4 x float> %val3, <4 x float> %val4) {
441; CHECK-LABEL: f26:
442; CHECK: vpkg [[REG:%v[0-9]+]],
443; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
444; CHECK-NEXT: br %r14
445  %cmp = fcmp ult <4 x float> %val1, %val2
446  %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
447  ret <4 x float> %ret
448}
449
450; Test ord selects.
451define <4 x float> @f27(<4 x float> %val1, <4 x float> %val2,
452                        <4 x float> %val3, <4 x float> %val4) {
453; CHECK-LABEL: f27:
454; CHECK: vo [[REG:%v[0-9]+]],
455; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
456; CHECK-NEXT: br %r14
457  %cmp = fcmp ord <4 x float> %val1, %val2
458  %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
459  ret <4 x float> %ret
460}
461
462; Test uno selects.
463define <4 x float> @f28(<4 x float> %val1, <4 x float> %val2,
464                        <4 x float> %val3, <4 x float> %val4) {
465; CHECK-LABEL: f28:
466; CHECK: vo [[REG:%v[0-9]+]],
467; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
468; CHECK-NEXT: br %r14
469  %cmp = fcmp uno <4 x float> %val1, %val2
470  %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
471  ret <4 x float> %ret
472}
473