1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 3 4--- | 5 6 define i8 @zext_i1_to_i8(i1 %val) { 7 %res = zext i1 %val to i8 8 ret i8 %res 9 } 10 11 define i16 @zext_i1_to_i16(i1 %val) { 12 %res = zext i1 %val to i16 13 ret i16 %res 14 } 15 16 define i32 @zext_i1_to_i32(i1 %val) { 17 %res = zext i1 %val to i32 18 ret i32 %res 19 } 20 21 define i64 @zext_i1_to_i64(i1 %val) { 22 %res = zext i1 %val to i64 23 ret i64 %res 24 } 25 26 define i16 @zext_i8_to_i16(i8 %val) { 27 %res = zext i8 %val to i16 28 ret i16 %res 29 } 30 31 define i32 @zext_i8_to_i32(i8 %val) { 32 %res = zext i8 %val to i32 33 ret i32 %res 34 } 35 36 define i64 @zext_i8_to_i64(i8 %val) { 37 %res = zext i8 %val to i64 38 ret i64 %res 39 } 40 41 define i32 @zext_i16_to_i32(i16 %val) { 42 %res = zext i16 %val to i32 43 ret i32 %res 44 } 45 46 define i64 @zext_i16_to_i64(i16 %val) { 47 %res = zext i16 %val to i64 48 ret i64 %res 49 } 50 51 define i64 @zext_i32_to_i64(i32 %val) { 52 %res = zext i32 %val to i64 53 ret i64 %res 54 } 55 56... 57--- 58name: zext_i1_to_i8 59alignment: 16 60legalized: true 61regBankSelected: true 62tracksRegLiveness: true 63registers: 64 - { id: 0, class: _ } 65 - { id: 1, class: gpr } 66 - { id: 2, class: gpr } 67 - { id: 3, class: gpr } 68 - { id: 4, class: gpr } 69body: | 70 bb.1 (%ir-block.0): 71 liveins: $edi 72 73 ; CHECK-LABEL: name: zext_i1_to_i8 74 ; CHECK: liveins: $edi 75 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 76 ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit 77 ; CHECK: [[AND8ri:%[0-9]+]]:gr8 = AND8ri [[COPY1]], 1, implicit-def $eflags 78 ; CHECK: $al = COPY [[AND8ri]] 79 ; CHECK: RET 0, implicit $al 80 %1:gpr(s32) = COPY $edi 81 %3:gpr(s8) = G_CONSTANT i8 1 82 %4:gpr(s8) = G_TRUNC %1(s32) 83 %2:gpr(s8) = G_AND %4, %3 84 $al = COPY %2(s8) 85 RET 0, implicit $al 86 87... 88--- 89name: zext_i1_to_i16 90alignment: 16 91legalized: true 92regBankSelected: true 93tracksRegLiveness: true 94registers: 95 - { id: 0, class: _ } 96 - { id: 1, class: gpr } 97 - { id: 2, class: gpr } 98 - { id: 3, class: gpr } 99 - { id: 4, class: gpr } 100body: | 101 bb.1 (%ir-block.0): 102 liveins: $edi 103 104 ; CHECK-LABEL: name: zext_i1_to_i16 105 ; CHECK: liveins: $edi 106 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 107 ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit 108 ; CHECK: [[AND16ri8_:%[0-9]+]]:gr16 = AND16ri8 [[COPY1]], 1, implicit-def $eflags 109 ; CHECK: $ax = COPY [[AND16ri8_]] 110 ; CHECK: RET 0, implicit $ax 111 %1:gpr(s32) = COPY $edi 112 %3:gpr(s16) = G_CONSTANT i16 1 113 %4:gpr(s16) = G_TRUNC %1(s32) 114 %2:gpr(s16) = G_AND %4, %3 115 $ax = COPY %2(s16) 116 RET 0, implicit $ax 117 118... 119--- 120name: zext_i1_to_i32 121alignment: 16 122legalized: true 123regBankSelected: true 124tracksRegLiveness: true 125registers: 126 - { id: 0, class: _ } 127 - { id: 1, class: gpr } 128 - { id: 2, class: gpr } 129 - { id: 3, class: gpr } 130 - { id: 4, class: gpr } 131body: | 132 bb.1 (%ir-block.0): 133 liveins: $edi 134 135 ; CHECK-LABEL: name: zext_i1_to_i32 136 ; CHECK: liveins: $edi 137 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 138 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[COPY]], 1, implicit-def $eflags 139 ; CHECK: $eax = COPY [[AND32ri8_]] 140 ; CHECK: RET 0, implicit $eax 141 %1:gpr(s32) = COPY $edi 142 %3:gpr(s32) = G_CONSTANT i32 1 143 %4:gpr(s32) = COPY %1(s32) 144 %2:gpr(s32) = G_AND %4, %3 145 $eax = COPY %2(s32) 146 RET 0, implicit $eax 147 148... 149--- 150name: zext_i1_to_i64 151alignment: 16 152legalized: true 153regBankSelected: true 154tracksRegLiveness: true 155registers: 156 - { id: 0, class: _ } 157 - { id: 1, class: gpr } 158 - { id: 2, class: gpr } 159 - { id: 3, class: gpr } 160 - { id: 4, class: gpr } 161body: | 162 bb.1 (%ir-block.0): 163 liveins: $edi 164 165 ; CHECK-LABEL: name: zext_i1_to_i64 166 ; CHECK: liveins: $edi 167 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 168 ; CHECK: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF 169 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit 170 ; CHECK: [[AND64ri8_:%[0-9]+]]:gr64 = AND64ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags 171 ; CHECK: $rax = COPY [[AND64ri8_]] 172 ; CHECK: RET 0, implicit $rax 173 %1:gpr(s32) = COPY $edi 174 %3:gpr(s64) = G_CONSTANT i64 1 175 %4:gpr(s64) = G_ANYEXT %1(s32) 176 %2:gpr(s64) = G_AND %4, %3 177 $rax = COPY %2(s64) 178 RET 0, implicit $rax 179 180... 181--- 182name: zext_i8_to_i16 183alignment: 16 184legalized: true 185regBankSelected: true 186tracksRegLiveness: true 187registers: 188 - { id: 0, class: _ } 189 - { id: 1, class: gpr } 190 - { id: 2, class: gpr } 191 - { id: 3, class: gpr } 192 - { id: 4, class: gpr } 193body: | 194 bb.1 (%ir-block.0): 195 liveins: $edi 196 197 ; CHECK-LABEL: name: zext_i8_to_i16 198 ; CHECK: liveins: $edi 199 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 200 ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit 201 ; CHECK: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit 202 ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY2]] 203 ; CHECK: [[COPY3:%[0-9]+]]:gr16 = COPY [[MOVZX32rr8_]].sub_16bit 204 ; CHECK: $ax = COPY [[COPY3]] 205 ; CHECK: RET 0, implicit $ax 206 %1:gpr(s32) = COPY $edi 207 %3:gpr(s16) = G_CONSTANT i16 255 208 %4:gpr(s16) = G_TRUNC %1(s32) 209 %2:gpr(s16) = G_AND %4, %3 210 $ax = COPY %2(s16) 211 RET 0, implicit $ax 212 213... 214--- 215name: zext_i8_to_i32 216alignment: 16 217legalized: true 218regBankSelected: true 219tracksRegLiveness: true 220registers: 221 - { id: 0, class: _ } 222 - { id: 1, class: gpr } 223 - { id: 2, class: gpr } 224 - { id: 3, class: gpr } 225 - { id: 4, class: gpr } 226body: | 227 bb.1 (%ir-block.0): 228 liveins: $edi 229 230 ; CHECK-LABEL: name: zext_i8_to_i32 231 ; CHECK: liveins: $edi 232 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 233 ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit 234 ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]] 235 ; CHECK: $eax = COPY [[MOVZX32rr8_]] 236 ; CHECK: RET 0, implicit $eax 237 %1:gpr(s32) = COPY $edi 238 %3:gpr(s32) = G_CONSTANT i32 255 239 %4:gpr(s32) = COPY %1(s32) 240 %2:gpr(s32) = G_AND %4, %3 241 $eax = COPY %2(s32) 242 RET 0, implicit $eax 243 244... 245--- 246name: zext_i8_to_i64 247alignment: 16 248legalized: true 249regBankSelected: true 250tracksRegLiveness: true 251registers: 252 - { id: 0, class: _ } 253 - { id: 1, class: gpr } 254 - { id: 2, class: gpr } 255 - { id: 3, class: gpr } 256 - { id: 4, class: gpr } 257body: | 258 bb.1 (%ir-block.0): 259 liveins: $edi 260 261 ; CHECK-LABEL: name: zext_i8_to_i64 262 ; CHECK: liveins: $edi 263 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 264 ; CHECK: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF 265 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit 266 ; CHECK: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 255, implicit-def $eflags 267 ; CHECK: $rax = COPY [[AND64ri32_]] 268 ; CHECK: RET 0, implicit $rax 269 %1:gpr(s32) = COPY $edi 270 %3:gpr(s64) = G_CONSTANT i64 255 271 %4:gpr(s64) = G_ANYEXT %1(s32) 272 %2:gpr(s64) = G_AND %4, %3 273 $rax = COPY %2(s64) 274 RET 0, implicit $rax 275 276... 277--- 278name: zext_i16_to_i32 279alignment: 16 280legalized: true 281regBankSelected: true 282tracksRegLiveness: true 283registers: 284 - { id: 0, class: _ } 285 - { id: 1, class: gpr } 286 - { id: 2, class: gpr } 287 - { id: 3, class: gpr } 288 - { id: 4, class: gpr } 289body: | 290 bb.1 (%ir-block.0): 291 liveins: $edi 292 293 ; CHECK-LABEL: name: zext_i16_to_i32 294 ; CHECK: liveins: $edi 295 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 296 ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit 297 ; CHECK: [[MOVZX32rr16_:%[0-9]+]]:gr32 = MOVZX32rr16 [[COPY1]] 298 ; CHECK: $eax = COPY [[MOVZX32rr16_]] 299 ; CHECK: RET 0, implicit $eax 300 %1:gpr(s32) = COPY $edi 301 %3:gpr(s32) = G_CONSTANT i32 65535 302 %4:gpr(s32) = COPY %1(s32) 303 %2:gpr(s32) = G_AND %4, %3 304 $eax = COPY %2(s32) 305 RET 0, implicit $eax 306 307... 308--- 309name: zext_i16_to_i64 310alignment: 16 311legalized: true 312regBankSelected: true 313tracksRegLiveness: true 314registers: 315 - { id: 0, class: _ } 316 - { id: 1, class: gpr } 317 - { id: 2, class: gpr } 318 - { id: 3, class: gpr } 319 - { id: 4, class: gpr } 320body: | 321 bb.1 (%ir-block.0): 322 liveins: $edi 323 324 ; CHECK-LABEL: name: zext_i16_to_i64 325 ; CHECK: liveins: $edi 326 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 327 ; CHECK: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF 328 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit 329 ; CHECK: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 65535, implicit-def $eflags 330 ; CHECK: $rax = COPY [[AND64ri32_]] 331 ; CHECK: RET 0, implicit $rax 332 %1:gpr(s32) = COPY $edi 333 %3:gpr(s64) = G_CONSTANT i64 65535 334 %4:gpr(s64) = G_ANYEXT %1(s32) 335 %2:gpr(s64) = G_AND %4, %3 336 $rax = COPY %2(s64) 337 RET 0, implicit $rax 338 339... 340--- 341name: zext_i32_to_i64 342alignment: 16 343legalized: true 344regBankSelected: true 345tracksRegLiveness: true 346registers: 347 - { id: 0, class: gpr } 348 - { id: 1, class: gpr } 349body: | 350 bb.1 (%ir-block.0): 351 liveins: $edi 352 353 ; CHECK-LABEL: name: zext_i32_to_i64 354 ; CHECK: liveins: $edi 355 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 356 ; CHECK: [[MOV32rr:%[0-9]+]]:gr32 = MOV32rr [[COPY]] 357 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[MOV32rr]], %subreg.sub_32bit 358 ; CHECK: $rax = COPY [[SUBREG_TO_REG]] 359 ; CHECK: RET 0, implicit $rax 360 %0:gpr(s32) = COPY $edi 361 %1:gpr(s64) = G_ZEXT %0(s32) 362 $rax = COPY %1(s64) 363 RET 0, implicit $rax 364 365... 366