1// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+WavefrontSize32,-WavefrontSize64 %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace 2 3//============================================================================== 4// destination must be different than all sources 5 6v_mqsad_pk_u16_u8 v[0:1], v[1:2], v9, v[4:5] 7// CHECK: error: destination must be different than all sources 8// CHECK-NEXT:{{^}}v_mqsad_pk_u16_u8 v[0:1], v[1:2], v9, v[4:5] 9// CHECK-NEXT:{{^}}^ 10 11//============================================================================== 12// dim modifier is required on this GPU 13 14image_atomic_add v252, v2, s[8:15] 15// CHECK: error: dim modifier is required on this GPU 16// CHECK-NEXT:{{^}}image_atomic_add v252, v2, s[8:15] 17// CHECK-NEXT:{{^}}^ 18 19//============================================================================== 20// duplicate data format 21 22tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT_32,BUF_DATA_FORMAT_8] 23// CHECK: error: duplicate data format 24// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT_32,BUF_DATA_FORMAT_8] 25// CHECK-NEXT:{{^}} ^ 26 27//============================================================================== 28// duplicate numeric format 29 30tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_NUM_FORMAT_UINT,BUF_NUM_FORMAT_FLOAT] 31// CHECK: error: duplicate numeric format 32// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_NUM_FORMAT_UINT,BUF_NUM_FORMAT_FLOAT] 33// CHECK-NEXT:{{^}} ^ 34 35//============================================================================== 36// expected ')' in parentheses expression 37 38v_bfe_u32 v0, 1+(100, v1, v2 39// CHECK: error: expected ')' in parentheses expression 40// CHECK-NEXT:{{^}}v_bfe_u32 v0, 1+(100, v1, v2 41// CHECK-NEXT:{{^}} ^ 42 43//============================================================================== 44// expected a 12-bit signed offset 45 46global_load_dword v1, v[3:4] off, offset:-4097 47// CHECK: error: expected a 12-bit signed offset 48// CHECK-NEXT:{{^}}global_load_dword v1, v[3:4] off, offset:-4097 49// CHECK-NEXT:{{^}} ^ 50 51scratch_load_dword v0, v1, off offset:-2049 glc slc 52// CHECK: error: expected a 12-bit signed offset 53// CHECK-NEXT:{{^}}scratch_load_dword v0, v1, off offset:-2049 glc slc 54// CHECK-NEXT:{{^}} ^ 55 56//============================================================================== 57// expected a 16-bit signed jump offset 58 59s_branch 0x10000 60// CHECK: error: expected a 16-bit signed jump offset 61// CHECK-NEXT:{{^}}s_branch 0x10000 62// CHECK-NEXT:{{^}} ^ 63 64//============================================================================== 65// expected a 2-bit lane id 66 67ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 4, 1, 2, 3) 68// CHECK: error: expected a 2-bit lane id 69// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 4, 1, 2, 3) 70// CHECK-NEXT:{{^}} ^ 71 72//============================================================================== 73// expected a 20-bit unsigned offset 74 75s_atc_probe_buffer 0x1, s[8:11], -1 76// CHECK: error: expected a 20-bit unsigned offset 77// CHECK-NEXT:{{^}}s_atc_probe_buffer 0x1, s[8:11], -1 78// CHECK-NEXT:{{^}} ^ 79 80s_atc_probe_buffer 0x1, s[8:11], 0xFFFFFFFFFFF00000 81// CHECK: error: expected a 20-bit unsigned offset 82// CHECK-NEXT:{{^}}s_atc_probe_buffer 0x1, s[8:11], 0xFFFFFFFFFFF00000 83// CHECK-NEXT:{{^}} ^ 84 85s_buffer_atomic_swap s5, s[4:7], 0x1FFFFF 86// CHECK: error: expected a 20-bit unsigned offset 87// CHECK-NEXT:{{^}}s_buffer_atomic_swap s5, s[4:7], 0x1FFFFF 88// CHECK-NEXT:{{^}} ^ 89 90//============================================================================== 91// expected a 21-bit signed offset 92 93s_atc_probe 0x7, s[4:5], 0x1FFFFF 94// CHECK: error: expected a 21-bit signed offset 95// CHECK-NEXT:{{^}}s_atc_probe 0x7, s[4:5], 0x1FFFFF 96// CHECK-NEXT:{{^}} ^ 97 98s_atomic_swap s5, s[2:3], 0x1FFFFF 99// CHECK: error: expected a 21-bit signed offset 100// CHECK-NEXT:{{^}}s_atomic_swap s5, s[2:3], 0x1FFFFF 101// CHECK-NEXT:{{^}} ^ 102 103//============================================================================== 104// expected a 5-character mask 105 106ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "ppii") 107// CHECK: error: expected a 5-character mask 108// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "ppii") 109// CHECK-NEXT:{{^}} ^ 110 111//============================================================================== 112// expected a closing parentheses 113 114ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3 115// CHECK: error: expected a closing parentheses 116// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3 117// CHECK-NEXT:{{^}} ^ 118 119ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3, 4) 120// CHECK: error: expected a closing parentheses 121// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3, 4) 122// CHECK-NEXT:{{^}} ^ 123 124//============================================================================== 125// expected a closing parenthesis 126 127s_sendmsg sendmsg(2, 2, 0, 0) 128// CHECK: error: expected a closing parenthesis 129// CHECK-NEXT:{{^}}s_sendmsg sendmsg(2, 2, 0, 0) 130// CHECK-NEXT:{{^}} ^ 131 132s_waitcnt vmcnt(0 133// CHECK: error: expected a closing parenthesis 134// CHECK-NEXT:{{^}}s_waitcnt vmcnt(0 135// CHECK-NEXT:{{^}} ^ 136 137//============================================================================== 138// expected a closing square bracket 139 140s_mov_b32 s1, s[0 1 141// CHECK: error: expected a closing square bracket 142// CHECK-NEXT:{{^}}s_mov_b32 s1, s[0 1 143// CHECK-NEXT:{{^}} ^ 144 145s_mov_b32 s1, s[0 s0 146// CHECK: error: expected a closing square bracket 147// CHECK-NEXT:{{^}}s_mov_b32 s1, s[0 s0 148// CHECK-NEXT:{{^}} ^ 149 150tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT_32,BUF_NUM_FORMAT_FLOAT,BUF_DATA_FORMAT_8] 151// CHECK: error: expected a closing square bracket 152// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT_32,BUF_NUM_FORMAT_FLOAT,BUF_DATA_FORMAT_8] 153// CHECK-NEXT:{{^}} ^ 154 155tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_NUM_FORMAT_UINT 156// CHECK: error: expected a closing square bracket 157// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_NUM_FORMAT_UINT 158// CHECK-NEXT:{{^}} ^ 159 160v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1 1 161// CHECK: error: expected a closing square bracket 162// CHECK-NEXT:{{^}}v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1 1 163// CHECK-NEXT:{{^}} ^ 164 165v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1, 166// CHECK: error: expected a closing square bracket 167// CHECK-NEXT:{{^}}v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1, 168// CHECK-NEXT:{{^}} ^ 169 170v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1[ 171// CHECK: error: expected a closing square bracket 172// CHECK-NEXT:{{^}}v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1[ 173// CHECK-NEXT:{{^}} ^ 174 175v_pk_add_u16 v1, v2, v3 op_sel:[0,0,0,0,0] 176// CHECK: error: expected a closing square bracket 177// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[0,0,0,0,0] 178// CHECK-NEXT:{{^}} ^ 179 180//============================================================================== 181// expected a colon 182 183ds_swizzle_b32 v8, v2 offset 184// CHECK: error: expected a colon 185// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset 186// CHECK-NEXT:{{^}} ^ 187 188ds_swizzle_b32 v8, v2 offset- 189// CHECK: error: expected a colon 190// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset- 191// CHECK-NEXT:{{^}} ^ 192 193//============================================================================== 194// expected a comma 195 196ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM 197// CHECK: error: expected a comma 198// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM 199// CHECK-NEXT:{{^}} ^ 200 201ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2) 202// CHECK: error: expected a comma 203// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2) 204// CHECK-NEXT:{{^}} ^ 205 206s_setreg_b32 hwreg(1,2 3), s2 207// CHECK: error: expected a comma 208// CHECK-NEXT:{{^}}s_setreg_b32 hwreg(1,2 3), s2 209// CHECK-NEXT:{{^}} ^ 210 211v_pk_add_u16 v1, v2, v3 op_sel:[0 0] 212// CHECK: error: expected a comma 213// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[0 0] 214// CHECK-NEXT:{{^}} ^ 215 216//============================================================================== 217// expected a comma or a closing parenthesis 218 219s_setreg_b32 hwreg(1 2,3), s2 220// CHECK: error: expected a comma or a closing parenthesis 221// CHECK-NEXT:{{^}}s_setreg_b32 hwreg(1 2,3), s2 222// CHECK-NEXT:{{^}} ^ 223 224//============================================================================== 225// expected a comma or a closing square bracket 226 227s_mov_b64 s[10:11], [s0 228// CHECK: error: expected a comma or a closing square bracket 229// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s0 230// CHECK-NEXT:{{^}} ^ 231 232s_mov_b64 s[10:11], [s0,s1 233// CHECK: error: expected a comma or a closing square bracket 234// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s0,s1 235// CHECK-NEXT:{{^}} ^ 236 237//============================================================================== 238// expected a counter name 239 240s_waitcnt vmcnt(0) & expcnt(0) & 1 241// CHECK: error: expected a counter name 242// CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) & 1 243// CHECK-NEXT:{{^}} ^ 244 245s_waitcnt vmcnt(0) & expcnt(0) & lgkmcnt(0)& 246// CHECK: error: expected a counter name 247// CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) & lgkmcnt(0)& 248// CHECK-NEXT:{{^}} ^ 249 250s_waitcnt vmcnt(0) & expcnt(0) 1 251// CHECK: error: expected a counter name 252// CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) 1 253// CHECK-NEXT:{{^}} ^ 254 255s_waitcnt vmcnt(0), expcnt(0), lgkmcnt(0), 256// CHECK: error: expected a counter name 257// CHECK-NEXT:{{^}}s_waitcnt vmcnt(0), expcnt(0), lgkmcnt(0), 258// CHECK-NEXT:{{^}} ^ 259 260//============================================================================== 261// expected a format string 262 263tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[] 264// CHECK: error: expected a format string 265// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[] 266// CHECK-NEXT:{{^}} ^ 267 268//============================================================================== 269// expected a left parenthesis 270 271s_waitcnt vmcnt(0) & expcnt(0) & x 272// CHECK: error: expected a left parenthesis 273// CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) & x 274// CHECK-NEXT:{{^}} ^ 275 276//============================================================================== 277// expected a left square bracket 278 279v_pk_add_u16 v1, v2, v3 op_sel: 280// CHECK: error: expected a left square bracket 281// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel: 282// CHECK-NEXT:{{^}} ^ 283 284//============================================================================== 285// expected a register or a list of registers 286 287s_mov_b32 s1, [s0, 1 288// CHECK: error: expected a register or a list of registers 289// CHECK-NEXT:{{^}}s_mov_b32 s1, [s0, 1 290// CHECK-NEXT:{{^}} ^ 291 292//============================================================================== 293// expected a single 32-bit register 294 295s_mov_b64 s[10:11], [s0,s[2:3]] 296// CHECK: error: expected a single 32-bit register 297// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s0,s[2:3]] 298// CHECK-NEXT:{{^}} ^ 299 300//============================================================================== 301// expected a string 302 303ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, pppii) 304// CHECK: error: expected a string 305// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, pppii) 306// CHECK-NEXT:{{^}} ^ 307 308//============================================================================== 309// expected a swizzle mode 310 311ds_swizzle_b32 v8, v2 offset:swizzle(XXX,1) 312// CHECK: error: expected a swizzle mode 313// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(XXX,1) 314// CHECK-NEXT:{{^}} ^ 315 316//============================================================================== 317// expected absolute expression 318 319ds_swizzle_b32 v8, v2 offset:SWIZZLE(QUAD_PERM, 0, 1, 2, 3) 320// CHECK: error: expected absolute expression 321// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:SWIZZLE(QUAD_PERM, 0, 1, 2, 3) 322// CHECK-NEXT:{{^}} ^ 323 324s_sendmsg sendmsg(MSG_GS, GS_OP_CUTX, 0) 325// CHECK: error: expected absolute expression 326// CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GS, GS_OP_CUTX, 0) 327// CHECK-NEXT:{{^}} ^ 328 329s_sendmsg sendmsg(MSG_GSX, GS_OP_CUT, 0) 330// CHECK: error: expected absolute expression 331// CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GSX, GS_OP_CUT, 0) 332// CHECK-NEXT:{{^}} ^ 333 334s_setreg_b32 hwreg(HW_REG_WRONG), s2 335// CHECK: error: expected absolute expression 336// CHECK-NEXT:{{^}}s_setreg_b32 hwreg(HW_REG_WRONG), s2 337// CHECK-NEXT:{{^}} ^ 338 339s_waitcnt vmcnt(x) 340// CHECK: error: expected absolute expression 341// CHECK-NEXT:{{^}}s_waitcnt vmcnt(x) 342// CHECK-NEXT:{{^}} ^ 343 344tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], format:[BUF_DATA_FORMAT_32] 345// CHECK: error: expected absolute expression 346// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], format:[BUF_DATA_FORMAT_32] 347// CHECK-NEXT:{{^}} ^ 348 349tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format: offset:52 350// CHECK: error: expected absolute expression 351// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format: offset:52 352// CHECK-NEXT:{{^}} ^ 353 354tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:BUF_NUM_FORMAT_UINT] 355// CHECK: error: expected absolute expression 356// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:BUF_NUM_FORMAT_UINT] 357// CHECK-NEXT:{{^}} ^ 358 359//============================================================================== 360// expected an 11-bit unsigned offset 361 362flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc 363// CHECK: error: expected an 11-bit unsigned offset 364// CHECK-NEXT:{{^}}flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc 365// CHECK-NEXT:{{^}} ^ 366 367//============================================================================== 368// expected an absolute expression 369 370v_ceil_f32 v1, abs(u) 371// CHECK: error: expected an absolute expression 372// CHECK-NEXT:{{^}}v_ceil_f32 v1, abs(u) 373// CHECK-NEXT:{{^}} ^ 374 375v_ceil_f32 v1, neg(u) 376// CHECK: error: expected an absolute expression 377// CHECK-NEXT:{{^}}v_ceil_f32 v1, neg(u) 378// CHECK-NEXT:{{^}} ^ 379 380v_ceil_f32 v1, |u| 381// CHECK: error: expected an absolute expression 382// CHECK-NEXT:{{^}}v_ceil_f32 v1, |u| 383// CHECK-NEXT:{{^}} ^ 384 385v_mov_b32_sdwa v1, sext(u) 386// CHECK: error: expected an absolute expression 387// CHECK-NEXT:{{^}}v_mov_b32_sdwa v1, sext(u) 388// CHECK-NEXT:{{^}} ^ 389 390//============================================================================== 391// failed parsing operand. 392 393image_load v[0:1], v0, s[0:7] dmask:0x9 dim:1 D 394// CHECK: error: failed parsing operand. 395// CHECK-NEXT:{{^}}image_load v[0:1], v0, s[0:7] dmask:0x9 dim:1 D 396// CHECK-NEXT:{{^}} ^ 397 398v_ceil_f16 v0, abs(neg(1)) 399// CHECK: error: failed parsing operand. 400// CHECK-NEXT:{{^}}v_ceil_f16 v0, abs(neg(1)) 401// CHECK-NEXT:{{^}} ^ 402 403v_interp_mov_f32 v11, invalid_param_3, attr0.y 404// CHECK: error: failed parsing operand. 405// CHECK-NEXT:{{^}}v_interp_mov_f32 v11, invalid_param_3, attr0.y 406// CHECK-NEXT:{{^}} ^ 407 408v_interp_mov_f32 v8, foo, attr0.x 409// CHECK: error: failed parsing operand. 410// CHECK-NEXT:{{^}}v_interp_mov_f32 v8, foo, attr0.x 411// CHECK-NEXT:{{^}} ^ 412 413v_interp_p2_f32 v0, v1, attr 414// CHECK: error: failed parsing operand. 415// CHECK-NEXT:{{^}}v_interp_p2_f32 v0, v1, attr 416// CHECK-NEXT:{{^}} ^ 417 418//============================================================================== 419// first register index should not exceed second index 420 421s_mov_b64 s[10:11], s[1:0] 422// CHECK: error: first register index should not exceed second index 423// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], s[1:0] 424// CHECK-NEXT:{{^}} ^ 425 426//============================================================================== 427// group size must be a power of two 428 429ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,3,1) 430// CHECK: error: group size must be a power of two 431// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,3,1) 432// CHECK-NEXT:{{^}} ^ 433 434//============================================================================== 435// group size must be in the interval [1,16] 436 437ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,0) 438// CHECK: error: group size must be in the interval [1,16] 439// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,0) 440// CHECK-NEXT:{{^}} ^ 441 442//============================================================================== 443// group size must be in the interval [2,32] 444 445ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,1,0) 446// CHECK: error: group size must be in the interval [2,32] 447// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,1,0) 448// CHECK-NEXT:{{^}} ^ 449 450//============================================================================== 451// image address size does not match dim and a16 452 453image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D 454// CHECK: error: image address size does not match dim and a16 455// CHECK-NEXT:{{^}}image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D 456// CHECK-NEXT:{{^}}^ 457 458//============================================================================== 459// image data size does not match dmask and tfe 460 461image_load v[0:1], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D 462// CHECK: error: image data size does not match dmask and tfe 463// CHECK-NEXT:{{^}}image_load v[0:1], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D 464// CHECK-NEXT:{{^}}^ 465 466//============================================================================== 467// instruction must use glc 468 469flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:2047 470// CHECK: error: instruction must use glc 471// CHECK-NEXT:{{^}}flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:2047 472// CHECK-NEXT:{{^}}^ 473 474//============================================================================== 475// instruction not supported on this GPU 476 477s_cbranch_join 1 478// CHECK: error: instruction not supported on this GPU 479// CHECK-NEXT:{{^}}s_cbranch_join 1 480// CHECK-NEXT:{{^}}^ 481 482//============================================================================== 483// invalid bit offset: only 5-bit values are legal 484 485s_getreg_b32 s2, hwreg(3,32,32) 486// CHECK: error: invalid bit offset: only 5-bit values are legal 487// CHECK-NEXT:{{^}}s_getreg_b32 s2, hwreg(3,32,32) 488// CHECK-NEXT:{{^}} ^ 489 490//============================================================================== 491// invalid bitfield width: only values from 1 to 32 are legal 492 493s_setreg_b32 hwreg(3,0,33), s2 494// CHECK: error: invalid bitfield width: only values from 1 to 32 are legal 495// CHECK-NEXT:{{^}}s_setreg_b32 hwreg(3,0,33), s2 496// CHECK-NEXT:{{^}} ^ 497 498//============================================================================== 499// invalid code of hardware register: only 6-bit values are legal 500 501s_setreg_b32 hwreg(0x40), s2 502// CHECK: error: invalid code of hardware register: only 6-bit values are legal 503// CHECK-NEXT:{{^}}s_setreg_b32 hwreg(0x40), s2 504// CHECK-NEXT:{{^}} ^ 505 506//============================================================================== 507// invalid counter name x 508 509s_waitcnt vmcnt(0) & expcnt(0) x(0) 510// CHECK: error: invalid counter name x 511// CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) x(0) 512// CHECK-NEXT:{{^}} ^ 513 514//============================================================================== 515// invalid exp target 516 517exp invalid_target_10 v3, v2, v1, v0 518// CHECK: error: invalid exp target 519// CHECK-NEXT:{{^}}exp invalid_target_10 v3, v2, v1, v0 520// CHECK-NEXT:{{^}} ^ 521 522//============================================================================== 523// invalid immediate: only 16-bit values are legal 524 525s_setreg_b32 0x1f803, s2 526// CHECK: error: invalid immediate: only 16-bit values are legal 527// CHECK-NEXT:{{^}}s_setreg_b32 0x1f803, s2 528// CHECK-NEXT:{{^}} ^ 529 530//============================================================================== 531// invalid instruction 532 533v_dot_f32_f16 v0, v1, v2 534// CHECK: error: invalid instruction 535// CHECK-NEXT:{{^}}v_dot_f32_f16 v0, v1, v2 536// CHECK-NEXT:{{^}}^ 537 538//============================================================================== 539// invalid literal operand 540 541v_add_f64 v[0:1], 1.23456, -abs(1.2345) 542// CHECK: error: invalid literal operand 543// CHECK-NEXT:{{^}}v_add_f64 v[0:1], 1.23456, -abs(1.2345) 544// CHECK-NEXT:{{^}}^ 545 546v_min3_i16 v5, 0x5678, 0x5678, 0x5679 547// CHECK: error: invalid literal operand 548// CHECK-NEXT:{{^}}v_min3_i16 v5, 0x5678, 0x5678, 0x5679 549// CHECK-NEXT:{{^}}^ 550 551v_pk_add_f16 v1, 25.0, 25.1 552// CHECK: error: invalid literal operand 553// CHECK-NEXT:{{^}}v_pk_add_f16 v1, 25.0, 25.1 554// CHECK-NEXT:{{^}}^ 555 556//============================================================================== 557// invalid mask 558 559ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "pppi2") 560// CHECK: error: invalid mask 561// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "pppi2") 562// CHECK-NEXT:{{^}} ^ 563 564//============================================================================== 565// invalid message id 566 567s_sendmsg sendmsg(-1) 568// CHECK: error: invalid message id 569// CHECK-NEXT:{{^}}s_sendmsg sendmsg(-1) 570// CHECK-NEXT:{{^}} ^ 571 572//============================================================================== 573// invalid message stream id 574 575s_sendmsg sendmsg(2, 2, 4) 576// CHECK: error: invalid message stream id 577// CHECK-NEXT:{{^}}s_sendmsg sendmsg(2, 2, 4) 578// CHECK-NEXT:{{^}} ^ 579 580s_sendmsg sendmsg(MSG_GS, GS_OP_CUT, 4) 581// CHECK: error: invalid message stream id 582// CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GS, GS_OP_CUT, 4) 583// CHECK-NEXT:{{^}} ^ 584 585//============================================================================== 586// invalid mul value. 587 588v_cvt_f64_i32 v[5:6], s1 mul:3 589// CHECK: error: invalid mul value. 590// CHECK-NEXT:{{^}}v_cvt_f64_i32 v[5:6], s1 mul:3 591// CHECK-NEXT:{{^}} ^ 592 593//============================================================================== 594// invalid op_sel operand 595 596v_permlane16_b32 v5, v1, s2, s3 op_sel:[0, 0, 0, 1] 597// CHECK: error: invalid op_sel operand 598// CHECK-NEXT:{{^}}v_permlane16_b32 v5, v1, s2, s3 op_sel:[0, 0, 0, 1] 599// CHECK-NEXT:{{^}}^ 600 601//============================================================================== 602// invalid op_sel value. 603 604v_pk_add_u16 v1, v2, v3 op_sel:[-1,0] 605// CHECK: error: invalid op_sel value. 606// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[-1,0] 607// CHECK-NEXT:{{^}} ^ 608 609//============================================================================== 610// invalid operand (violates constant bus restrictions) 611 612v_ashrrev_i64 v[0:1], 0x100, s[0:1] 613// CHECK: error: invalid operand (violates constant bus restrictions) 614// CHECK-NEXT:{{^}}v_ashrrev_i64 v[0:1], 0x100, s[0:1] 615// CHECK-NEXT:{{^}}^ 616 617v_bfe_u32 v0, s1, 0x3039, s2 618// CHECK: error: invalid operand (violates constant bus restrictions) 619// CHECK-NEXT:{{^}}v_bfe_u32 v0, s1, 0x3039, s2 620// CHECK-NEXT:{{^}}^ 621 622v_div_fmas_f32 v5, s3, 0x123, v3 623// CHECK: error: invalid operand (violates constant bus restrictions) 624// CHECK-NEXT:{{^}}v_div_fmas_f32 v5, s3, 0x123, v3 625// CHECK-NEXT:{{^}}^ 626 627//============================================================================== 628// invalid operand for instruction 629 630buffer_load_dword v5, off, s[8:11], s3 tfe lds 631// CHECK: error: invalid operand for instruction 632// CHECK-NEXT:{{^}}buffer_load_dword v5, off, s[8:11], s3 tfe lds 633// CHECK-NEXT:{{^}} ^ 634 635exp mrt0 0x12345678, v0, v0, v0 636// CHECK: error: invalid operand for instruction 637// CHECK-NEXT:{{^}}exp mrt0 0x12345678, v0, v0, v0 638// CHECK-NEXT:{{^}} ^ 639 640v_cmp_eq_f32 s[0:1], private_base, s0 641// CHECK: error: invalid operand for instruction 642// CHECK-NEXT:{{^}}v_cmp_eq_f32 s[0:1], private_base, s0 643// CHECK-NEXT:{{^}} ^ 644 645//============================================================================== 646// invalid operation id 647 648s_sendmsg sendmsg(15, -1) 649// CHECK: error: invalid operation id 650// CHECK-NEXT:{{^}}s_sendmsg sendmsg(15, -1) 651// CHECK-NEXT:{{^}} ^ 652 653//============================================================================== 654// invalid or unsupported register size 655 656s_mov_b64 s[0:17], -1 657// CHECK: error: invalid or unsupported register size 658// CHECK-NEXT:{{^}}s_mov_b64 s[0:17], -1 659// CHECK-NEXT:{{^}} ^ 660 661//============================================================================== 662// invalid register alignment 663 664s_load_dwordx4 s[1:4], s[2:3], s4 665// CHECK: error: invalid register alignment 666// CHECK-NEXT:{{^}}s_load_dwordx4 s[1:4], s[2:3], s4 667// CHECK-NEXT:{{^}} ^ 668 669//============================================================================== 670// invalid register index 671 672s_mov_b32 s1, s[0:-1] 673// CHECK: error: invalid register index 674// CHECK-NEXT:{{^}}s_mov_b32 s1, s[0:-1] 675// CHECK-NEXT:{{^}} ^ 676 677v_add_f64 v[0:1], v[0:1], v[0xF00000001:0x2] 678// CHECK: error: invalid register index 679// CHECK-NEXT:{{^}}v_add_f64 v[0:1], v[0:1], v[0xF00000001:0x2] 680// CHECK-NEXT:{{^}} ^ 681 682//============================================================================== 683// invalid register name 684 685s_mov_b64 s[10:11], [x0,s1] 686// CHECK: error: invalid register name 687// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [x0,s1] 688// CHECK-NEXT:{{^}} ^ 689 690//============================================================================== 691// invalid syntax, expected 'neg' modifier 692 693v_ceil_f32 v0, --1 694// CHECK: error: invalid syntax, expected 'neg' modifier 695// CHECK-NEXT:{{^}}v_ceil_f32 v0, --1 696// CHECK-NEXT:{{^}} ^ 697 698//============================================================================== 699// invalid use of lds_direct 700 701v_ashrrev_i16 v0, lds_direct, v0 702// CHECK: error: invalid use of lds_direct 703// CHECK-NEXT:{{^}}v_ashrrev_i16 v0, lds_direct, v0 704// CHECK-NEXT:{{^}}^ 705 706//============================================================================== 707// lane id must be in the interval [0,group size - 1] 708 709ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,2,-1) 710// CHECK: error: lane id must be in the interval [0,group size - 1] 711// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,2,-1) 712// CHECK-NEXT:{{^}} ^ 713 714//============================================================================== 715// message does not support operations 716 717s_sendmsg sendmsg(MSG_GS_ALLOC_REQ, 0) 718// CHECK: error: message does not support operations 719// CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GS_ALLOC_REQ, 0) 720// CHECK-NEXT:{{^}} ^ 721 722//============================================================================== 723// message operation does not support streams 724 725s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP, 0) 726// CHECK: error: message operation does not support streams 727// CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP, 0) 728// CHECK-NEXT:{{^}} ^ 729 730//============================================================================== 731// missing message operation 732 733s_sendmsg sendmsg(MSG_SYSMSG) 734// CHECK: error: missing message operation 735// CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_SYSMSG) 736// CHECK-NEXT:{{^}} ^ 737 738//============================================================================== 739// missing register index 740 741s_mov_b64 s[10:11], [s 742// CHECK: error: missing register index 743// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s 744// CHECK-NEXT:{{^}} ^ 745 746s_mov_b64 s[10:11], [s,s1] 747// CHECK: error: missing register index 748// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s,s1] 749// CHECK-NEXT:{{^}} ^ 750 751//============================================================================== 752// not a valid operand. 753 754s_branch offset:1 755// CHECK: error: not a valid operand. 756// CHECK-NEXT:{{^}}s_branch offset:1 757// CHECK-NEXT:{{^}} ^ 758 759v_mov_b32 v0, v0 row_bcast:0 760// CHECK: error: not a valid operand. 761// CHECK-NEXT:{{^}}v_mov_b32 v0, v0 row_bcast:0 762// CHECK-NEXT:{{^}} ^ 763 764//============================================================================== 765// only one literal operand is allowed 766 767s_and_b32 s2, 0x12345678, 0x12345679 768// CHECK: error: only one literal operand is allowed 769// CHECK-NEXT:{{^}}s_and_b32 s2, 0x12345678, 0x12345679 770// CHECK-NEXT:{{^}}^ 771 772//============================================================================== 773// out of bounds attr 774 775v_interp_p1_f32 v0, v1, attr64.w 776// CHECK: error: out of bounds attr 777// CHECK-NEXT:{{^}}v_interp_p1_f32 v0, v1, attr64.w 778// CHECK-NEXT:{{^}} ^ 779 780//============================================================================== 781// out of range format 782 783tbuffer_load_format_d16_x v0, off, s[0:3], format:-1, 0 784// CHECK: error: out of range format 785// CHECK-NEXT:{{^}}tbuffer_load_format_d16_x v0, off, s[0:3], format:-1, 0 786// CHECK-NEXT:{{^}} ^ 787 788//============================================================================== 789// register does not fit in the list 790 791s_mov_b64 s[10:11], [exec,exec_lo] 792// CHECK: error: register does not fit in the list 793// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [exec,exec_lo] 794// CHECK-NEXT:{{^}} ^ 795 796s_mov_b64 s[10:11], [exec_lo,exec] 797// CHECK: error: register does not fit in the list 798// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [exec_lo,exec] 799// CHECK-NEXT:{{^}} ^ 800 801//============================================================================== 802// register index is out of range 803 804s_add_i32 s106, s0, s1 805// CHECK: error: register index is out of range 806// CHECK-NEXT:{{^}}s_add_i32 s106, s0, s1 807// CHECK-NEXT:{{^}} ^ 808 809s_load_dwordx16 s[100:115], s[2:3], s4 810// CHECK: error: register index is out of range 811// CHECK-NEXT:{{^}}s_load_dwordx16 s[100:115], s[2:3], s4 812// CHECK-NEXT:{{^}} ^ 813 814s_mov_b32 ttmp16, 0 815// CHECK: error: register index is out of range 816// CHECK-NEXT:{{^}}s_mov_b32 ttmp16, 0 817// CHECK-NEXT:{{^}} ^ 818 819v_add_nc_i32 v256, v0, v1 820// CHECK: error: register index is out of range 821// CHECK-NEXT:{{^}}v_add_nc_i32 v256, v0, v1 822// CHECK-NEXT:{{^}} ^ 823 824//============================================================================== 825// register not available on this GPU 826 827s_and_b32 ttmp9, tma_hi, 0x0000ffff 828// CHECK: error: register not available on this GPU 829// CHECK-NEXT:{{^}}s_and_b32 ttmp9, tma_hi, 0x0000ffff 830// CHECK-NEXT:{{^}} ^ 831 832s_mov_b32 flat_scratch, -1 833// CHECK: error: register not available on this GPU 834// CHECK-NEXT:{{^}}s_mov_b32 flat_scratch, -1 835// CHECK-NEXT:{{^}} ^ 836 837//============================================================================== 838// registers in a list must be of the same kind 839 840s_mov_b64 s[10:11], [a0,v1] 841// CHECK: error: registers in a list must be of the same kind 842// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [a0,v1] 843// CHECK-NEXT:{{^}} ^ 844 845//============================================================================== 846// registers in a list must have consecutive indices 847 848s_mov_b64 s[10:11], [a0,a2] 849// CHECK: error: registers in a list must have consecutive indices 850// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [a0,a2] 851// CHECK-NEXT:{{^}} ^ 852 853s_mov_b64 s[10:11], [s0,s0] 854// CHECK: error: registers in a list must have consecutive indices 855// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s0,s0] 856// CHECK-NEXT:{{^}} ^ 857 858s_mov_b64 s[10:11], [s2,s1] 859// CHECK: error: registers in a list must have consecutive indices 860// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s2,s1] 861// CHECK-NEXT:{{^}} ^ 862 863//============================================================================== 864// source operand must be a VGPR 865 866v_movrels_b32_sdwa v0, 1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD 867// CHECK: error: source operand must be a VGPR 868// CHECK-NEXT:{{^}}v_movrels_b32_sdwa v0, 1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD 869// CHECK-NEXT:{{^}}^ 870 871//============================================================================== 872// specified hardware register is not supported on this GPU 873 874s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES) 875// CHECK: error: specified hardware register is not supported on this GPU 876// CHECK-NEXT:{{^}}s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES) 877// CHECK-NEXT:{{^}} ^ 878 879//============================================================================== 880// too few operands for instruction 881 882tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7] 883// CHECK: error: too few operands for instruction 884// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7] 885// CHECK-NEXT:{{^}}^ 886 887v_add_f32_e64 v0, v1 888// CHECK: error: too few operands for instruction 889// CHECK-NEXT:{{^}}v_add_f32_e64 v0, v1 890// CHECK-NEXT:{{^}}^ 891 892//============================================================================== 893// too large value for expcnt 894 895s_waitcnt expcnt(8) 896// CHECK: error: too large value for expcnt 897// CHECK-NEXT:{{^}}s_waitcnt expcnt(8) 898// CHECK-NEXT:{{^}} ^ 899 900//============================================================================== 901// too large value for lgkmcnt 902 903s_waitcnt lgkmcnt(64) 904// CHECK: error: too large value for lgkmcnt 905// CHECK-NEXT:{{^}}s_waitcnt lgkmcnt(64) 906// CHECK-NEXT:{{^}} ^ 907 908//============================================================================== 909// too large value for vmcnt 910 911s_waitcnt vmcnt(64) 912// CHECK: error: too large value for vmcnt 913// CHECK-NEXT:{{^}}s_waitcnt vmcnt(64) 914// CHECK-NEXT:{{^}} ^ 915 916//============================================================================== 917// unknown token in expression 918 919ds_swizzle_b32 v8, v2 offset: 920// CHECK: error: unknown token in expression 921// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset: 922// CHECK-NEXT:{{^}} ^ 923 924s_sendmsg sendmsg(1 -) 925// CHECK: error: unknown token in expression 926// CHECK-NEXT:{{^}}s_sendmsg sendmsg(1 -) 927// CHECK-NEXT:{{^}} ^ 928 929tbuffer_load_format_d16_x v0, off, s[0:3], format:1,, s0 930// CHECK: error: unknown token in expression 931// CHECK-NEXT:{{^}}tbuffer_load_format_d16_x v0, off, s[0:3], format:1,, s0 932// CHECK-NEXT:{{^}} ^ 933 934tbuffer_load_format_d16_x v0, off, s[0:3], format:1:, s0 935// CHECK: error: unknown token in expression 936// CHECK-NEXT:{{^}}tbuffer_load_format_d16_x v0, off, s[0:3], format:1:, s0 937// CHECK-NEXT:{{^}} ^ 938 939v_pk_add_u16 v1, v2, v3 op_sel:[ 940// CHECK: error: unknown token in expression 941// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[ 942// CHECK-NEXT:{{^}} ^ 943 944v_pk_add_u16 v1, v2, v3 op_sel:[,0] 945// CHECK: error: unknown token in expression 946// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[,0] 947// CHECK-NEXT:{{^}} ^ 948 949v_pk_add_u16 v1, v2, v3 op_sel:[,] 950// CHECK: error: unknown token in expression 951// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[,] 952// CHECK-NEXT:{{^}} ^ 953 954v_pk_add_u16 v1, v2, v3 op_sel:[0,] 955// CHECK: error: unknown token in expression 956// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[0,] 957// CHECK-NEXT:{{^}} ^ 958 959v_pk_add_u16 v1, v2, v3 op_sel:[] 960// CHECK: error: unknown token in expression 961// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[] 962// CHECK-NEXT:{{^}} ^ 963 964//============================================================================== 965// unsupported format 966 967tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT] 968// CHECK: error: unsupported format 969// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT] 970// CHECK-NEXT:{{^}} ^ 971 972//============================================================================== 973// expected vertical bar 974 975v_ceil_f32 v1, |1+1| 976// CHECK: error: expected vertical bar 977// CHECK-NEXT:{{^}}v_ceil_f32 v1, |1+1| 978// CHECK-NEXT:{{^}} ^ 979 980//============================================================================== 981// expected left paren after neg 982 983v_ceil_f32 v1, neg-(v2) 984// CHECK: error: expected left paren after neg 985// CHECK-NEXT:{{^}}v_ceil_f32 v1, neg-(v2) 986// CHECK-NEXT:{{^}} ^ 987 988//============================================================================== 989// expected left paren after abs 990 991v_ceil_f32 v1, abs-(v2) 992// CHECK: error: expected left paren after abs 993// CHECK-NEXT:{{^}}v_ceil_f32 v1, abs-(v2) 994// CHECK-NEXT:{{^}} ^ 995 996//============================================================================== 997// expected left paren after sext 998 999v_cmpx_f_i32_sdwa sext[v1], v2 src0_sel:DWORD src1_sel:DWORD 1000// CHECK: error: expected left paren after sext 1001// CHECK-NEXT:{{^}}v_cmpx_f_i32_sdwa sext[v1], v2 src0_sel:DWORD src1_sel:DWORD 1002// CHECK-NEXT:{{^}} ^ 1003 1004//============================================================================== 1005// expected closing parentheses 1006 1007v_ceil_f32 v1, abs(v2] 1008// CHECK: error: expected closing parentheses 1009// CHECK-NEXT:{{^}}v_ceil_f32 v1, abs(v2] 1010// CHECK-NEXT:{{^}} ^ 1011 1012v_ceil_f32 v1, neg(v2] 1013// CHECK: error: expected closing parentheses 1014// CHECK-NEXT:{{^}}v_ceil_f32 v1, neg(v2] 1015// CHECK-NEXT:{{^}} ^ 1016 1017v_cmpx_f_i32_sdwa sext(v1], v2 src0_sel:DWORD src1_sel:DWORD 1018// CHECK: error: expected closing parentheses 1019// CHECK-NEXT:{{^}}v_cmpx_f_i32_sdwa sext(v1], v2 src0_sel:DWORD src1_sel:DWORD 1020// CHECK-NEXT:{{^}} ^ 1021 1022//============================================================================== 1023// expected a left parentheses 1024 1025ds_swizzle_b32 v8, v2 offset:swizzle[QUAD_PERM, 0, 1, 2, 3] 1026// CHECK: error: expected a left parentheses 1027// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle[QUAD_PERM, 0, 1, 2, 3] 1028// CHECK-NEXT:{{^}} ^ 1029 1030//============================================================================== 1031// expected an absolute expression or a label 1032 1033s_branch 1+x 1034// CHECK: error: expected an absolute expression or a label 1035// CHECK-NEXT:{{^}}s_branch 1+x 1036// CHECK-NEXT:{{^}} ^ 1037 1038//============================================================================== 1039// expected a 16-bit offset 1040 1041ds_swizzle_b32 v8, v2 offset:0x10000 1042// CHECK: error: expected a 16-bit offset 1043// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:0x10000 1044// CHECK-NEXT:{{^}} ^ 1045