1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Assembly Matcher Source Fragment *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9 10#ifdef GET_ASSEMBLER_HEADER 11#undef GET_ASSEMBLER_HEADER 12 // This should be included into the middle of the declaration of 13 // your subclasses implementation of MCTargetAsmParser. 14 FeatureBitset ComputeAvailableFeatures(const FeatureBitset& FB) const; 15 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode, 16 const OperandVector &Operands); 17 void convertToMapAndConstraints(unsigned Kind, 18 const OperandVector &Operands) override; 19 unsigned MatchInstructionImpl(const OperandVector &Operands, 20 MCInst &Inst, 21 uint64_t &ErrorInfo, 22 FeatureBitset &MissingFeatures, 23 bool matchingInlineAsm, 24 unsigned VariantID = 0); 25 unsigned MatchInstructionImpl(const OperandVector &Operands, 26 MCInst &Inst, 27 uint64_t &ErrorInfo, 28 bool matchingInlineAsm, 29 unsigned VariantID = 0) { 30 FeatureBitset MissingFeatures; 31 return MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures, 32 matchingInlineAsm, VariantID); 33 } 34 35 OperandMatchResultTy MatchOperandParserImpl( 36 OperandVector &Operands, 37 StringRef Mnemonic, 38 bool ParseForAllFeatures = false); 39 OperandMatchResultTy tryCustomParseOperand( 40 OperandVector &Operands, 41 unsigned MCK); 42 43#endif // GET_ASSEMBLER_HEADER_INFO 44 45 46#ifdef GET_OPERAND_DIAGNOSTIC_TYPES 47#undef GET_OPERAND_DIAGNOSTIC_TYPES 48 49 Match_Immz, 50 Match_MemSImm10, 51 Match_MemSImm10Lsl1, 52 Match_MemSImm10Lsl2, 53 Match_MemSImm10Lsl3, 54 Match_MemSImm11, 55 Match_MemSImm12, 56 Match_MemSImm16, 57 Match_MemSImm9, 58 Match_MemSImmPtr, 59 Match_SImm10_0, 60 Match_SImm10_Lsl1, 61 Match_SImm10_Lsl2, 62 Match_SImm10_Lsl3, 63 Match_SImm11_0, 64 Match_SImm16, 65 Match_SImm16_Relaxed, 66 Match_SImm19_Lsl2, 67 Match_SImm32, 68 Match_SImm32_Relaxed, 69 Match_SImm4_0, 70 Match_SImm5_0, 71 Match_SImm6_0, 72 Match_SImm7_Lsl2, 73 Match_SImm9_0, 74 Match_UImm10_0, 75 Match_UImm16, 76 Match_UImm16_AltRelaxed, 77 Match_UImm16_Relaxed, 78 Match_UImm1_0, 79 Match_UImm20_0, 80 Match_UImm26_0, 81 Match_UImm2_0, 82 Match_UImm2_1, 83 Match_UImm32_Coerced, 84 Match_UImm3_0, 85 Match_UImm4_0, 86 Match_UImm5_0, 87 Match_UImm5_0_Report_UImm6, 88 Match_UImm5_1, 89 Match_UImm5_32, 90 Match_UImm5_33, 91 Match_UImm5_Lsl2, 92 Match_UImm6_0, 93 Match_UImm6_Lsl2, 94 Match_UImm7_0, 95 Match_UImm7_N1, 96 Match_UImm8_0, 97 Match_UImmRange2_64, 98 END_OPERAND_DIAGNOSTIC_TYPES 99#endif // GET_OPERAND_DIAGNOSTIC_TYPES 100 101 102#ifdef GET_REGISTER_MATCHER 103#undef GET_REGISTER_MATCHER 104 105// Bits for subtarget features that participate in instruction matching. 106enum SubtargetFeatureBits : uint8_t { 107 Feature_HasMips2Bit = 11, 108 Feature_HasMips3_32Bit = 17, 109 Feature_HasMips3_32r2Bit = 18, 110 Feature_HasMips3Bit = 12, 111 Feature_NotMips3Bit = 46, 112 Feature_HasMips4_32Bit = 19, 113 Feature_NotMips4_32Bit = 48, 114 Feature_HasMips4_32r2Bit = 20, 115 Feature_HasMips5_32r2Bit = 21, 116 Feature_HasMips32Bit = 13, 117 Feature_HasMips32r2Bit = 14, 118 Feature_HasMips32r5Bit = 15, 119 Feature_HasMips32r6Bit = 16, 120 Feature_NotMips32r6Bit = 47, 121 Feature_IsGP64bitBit = 32, 122 Feature_IsGP32bitBit = 31, 123 Feature_IsPTR64bitBit = 36, 124 Feature_IsPTR32bitBit = 35, 125 Feature_HasMips64Bit = 22, 126 Feature_NotMips64Bit = 49, 127 Feature_HasMips64r2Bit = 23, 128 Feature_HasMips64r5Bit = 24, 129 Feature_HasMips64r6Bit = 25, 130 Feature_NotMips64r6Bit = 50, 131 Feature_InMips16ModeBit = 29, 132 Feature_NotInMips16ModeBit = 45, 133 Feature_HasCnMipsBit = 1, 134 Feature_NotCnMipsBit = 41, 135 Feature_HasCnMipsPBit = 2, 136 Feature_NotCnMipsPBit = 42, 137 Feature_IsSym32Bit = 38, 138 Feature_IsSym64Bit = 39, 139 Feature_HasStdEncBit = 26, 140 Feature_InMicroMipsBit = 28, 141 Feature_NotInMicroMipsBit = 44, 142 Feature_HasEVABit = 6, 143 Feature_HasMSABit = 8, 144 Feature_HasMadd4Bit = 10, 145 Feature_HasMTBit = 9, 146 Feature_UseIndirectJumpsHazardBit = 51, 147 Feature_NoIndirectJumpGuardsBit = 40, 148 Feature_HasCRCBit = 0, 149 Feature_HasVirtBit = 27, 150 Feature_HasGINVBit = 7, 151 Feature_IsFP64bitBit = 30, 152 Feature_NotFP64bitBit = 43, 153 Feature_IsSingleFloatBit = 37, 154 Feature_IsNotSingleFloatBit = 33, 155 Feature_IsNotSoftFloatBit = 34, 156 Feature_HasDSPBit = 3, 157 Feature_HasDSPR2Bit = 4, 158 Feature_HasDSPR3Bit = 5, 159}; 160 161#endif // GET_REGISTER_MATCHER 162 163 164#ifdef GET_SUBTARGET_FEATURE_NAME 165#undef GET_SUBTARGET_FEATURE_NAME 166 167// User-level names for subtarget features that participate in 168// instruction matching. 169static const char *getSubtargetFeatureName(uint64_t Val) { 170 switch(Val) { 171 case Feature_HasMips2Bit: return ""; 172 case Feature_HasMips3_32Bit: return ""; 173 case Feature_HasMips3_32r2Bit: return ""; 174 case Feature_HasMips3Bit: return ""; 175 case Feature_NotMips3Bit: return ""; 176 case Feature_HasMips4_32Bit: return ""; 177 case Feature_NotMips4_32Bit: return ""; 178 case Feature_HasMips4_32r2Bit: return ""; 179 case Feature_HasMips5_32r2Bit: return ""; 180 case Feature_HasMips32Bit: return ""; 181 case Feature_HasMips32r2Bit: return ""; 182 case Feature_HasMips32r5Bit: return ""; 183 case Feature_HasMips32r6Bit: return ""; 184 case Feature_NotMips32r6Bit: return ""; 185 case Feature_IsGP64bitBit: return ""; 186 case Feature_IsGP32bitBit: return ""; 187 case Feature_IsPTR64bitBit: return ""; 188 case Feature_IsPTR32bitBit: return ""; 189 case Feature_HasMips64Bit: return ""; 190 case Feature_NotMips64Bit: return ""; 191 case Feature_HasMips64r2Bit: return ""; 192 case Feature_HasMips64r5Bit: return ""; 193 case Feature_HasMips64r6Bit: return ""; 194 case Feature_NotMips64r6Bit: return ""; 195 case Feature_InMips16ModeBit: return ""; 196 case Feature_NotInMips16ModeBit: return ""; 197 case Feature_HasCnMipsBit: return ""; 198 case Feature_NotCnMipsBit: return ""; 199 case Feature_HasCnMipsPBit: return ""; 200 case Feature_NotCnMipsPBit: return ""; 201 case Feature_IsSym32Bit: return ""; 202 case Feature_IsSym64Bit: return ""; 203 case Feature_HasStdEncBit: return ""; 204 case Feature_InMicroMipsBit: return ""; 205 case Feature_NotInMicroMipsBit: return ""; 206 case Feature_HasEVABit: return ""; 207 case Feature_HasMSABit: return ""; 208 case Feature_HasMadd4Bit: return ""; 209 case Feature_HasMTBit: return ""; 210 case Feature_UseIndirectJumpsHazardBit: return ""; 211 case Feature_NoIndirectJumpGuardsBit: return ""; 212 case Feature_HasCRCBit: return ""; 213 case Feature_HasVirtBit: return ""; 214 case Feature_HasGINVBit: return ""; 215 case Feature_IsFP64bitBit: return ""; 216 case Feature_NotFP64bitBit: return ""; 217 case Feature_IsSingleFloatBit: return ""; 218 case Feature_IsNotSingleFloatBit: return ""; 219 case Feature_IsNotSoftFloatBit: return ""; 220 case Feature_HasDSPBit: return ""; 221 case Feature_HasDSPR2Bit: return ""; 222 case Feature_HasDSPR3Bit: return ""; 223 default: return "(unknown)"; 224 } 225} 226 227#endif // GET_SUBTARGET_FEATURE_NAME 228 229 230#ifdef GET_MATCHER_IMPLEMENTATION 231#undef GET_MATCHER_IMPLEMENTATION 232 233enum { 234 Tie0_1_1, 235 Tie0_1_2, 236}; 237 238static const uint8_t TiedAsmOperandTable[][3] = { 239 /* Tie0_1_1 */ { 0, 1, 1 }, 240 /* Tie0_1_2 */ { 0, 1, 2 }, 241}; 242 243namespace { 244enum OperatorConversionKind { 245 CVT_Done, 246 CVT_Reg, 247 CVT_Tied, 248 CVT_95_addGPR32AsmRegOperands, 249 CVT_95_addAFGR64AsmRegOperands, 250 CVT_95_addFGR64AsmRegOperands, 251 CVT_95_addFGR32AsmRegOperands, 252 CVT_95_addSImmOperands_LT_32_GT_, 253 CVT_95_addMSA128AsmRegOperands, 254 CVT_95_addSImmOperands_LT_16_GT_, 255 CVT_95_Reg, 256 CVT_95_addImmOperands, 257 CVT_95_addGPRMM16AsmRegOperands, 258 CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_, 259 CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 260 CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 261 CVT_95_addUImmOperands_LT_16_GT_, 262 CVT_95_addGPR64AsmRegOperands, 263 CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 264 CVT_regZERO, 265 CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 266 CVT_regFCC0, 267 CVT_95_addFCCAsmRegOperands, 268 CVT_95_addCOP2AsmRegOperands, 269 CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 270 CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 271 CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 272 CVT_imm_95_0, 273 CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 274 CVT_95_addMemOperands, 275 CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_, 276 CVT_95_addCCRAsmRegOperands, 277 CVT_95_addMSACtrlAsmRegOperands, 278 CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 279 CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_, 280 CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 281 CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 282 CVT_95_addGPR32NonZeroAsmRegOperands, 283 CVT_95_addGPR32ZeroAsmRegOperands, 284 CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 285 CVT_95_addCOP0AsmRegOperands, 286 CVT_regZERO_64, 287 CVT_95_addACC64DSPAsmRegOperands, 288 CVT_95_addConstantUImmOperands_LT_1_GT_, 289 CVT_regRA, 290 CVT_regRA_64, 291 CVT_95_addMicroMipsMemOperands, 292 CVT_95_addCOP3AsmRegOperands, 293 CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 294 CVT_95_addConstantUImmOperands_LT_32_GT_, 295 CVT_95_addStrictlyAFGR64AsmRegOperands, 296 CVT_95_addStrictlyFGR64AsmRegOperands, 297 CVT_95_addStrictlyFGR32AsmRegOperands, 298 CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_, 299 CVT_95_addRegListOperands, 300 CVT_ConvertXWPOperands, 301 CVT_regAC0, 302 CVT_95_addGPRMM16AsmRegMovePPairFirstOperands, 303 CVT_95_addGPRMM16AsmRegMovePPairSecondOperands, 304 CVT_95_addGPRMM16AsmRegMovePOperands, 305 CVT_95_addHI32DSPAsmRegOperands, 306 CVT_95_addLO32DSPAsmRegOperands, 307 CVT_regS0, 308 CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_, 309 CVT_95_addHWRegsAsmRegOperands, 310 CVT_95_addGPRMM16AsmRegZeroOperands, 311 CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_, 312 CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_, 313 CVT_imm_95_2, 314 CVT_imm_95_6, 315 CVT_imm_95_4, 316 CVT_imm_95_5, 317 CVT_imm_95_31, 318 CVT_NUM_CONVERTERS 319}; 320 321enum InstructionConversionKind { 322 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, 323 Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, 324 Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, 325 Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, 326 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, 327 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, 328 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, 329 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, 330 Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, 331 Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, 332 Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, 333 Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, 334 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, 335 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, 336 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1, 337 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, 338 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2, 339 Convert__SImm161_1, 340 Convert__Reg1_0__SImm161_1, 341 Convert__Reg1_0__SImm161_2, 342 Convert__Reg1_0__Reg1_1__SImm161_2, 343 Convert__Reg1_0__Tie0_1_1__SImm161_1, 344 Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, 345 Convert__GPRMM16AsmReg1_0__Imm1_1, 346 Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1, 347 Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, 348 Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1, 349 Convert__Imm1_0, 350 Convert__Reg1_0__Reg1_1__Reg1_2, 351 Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, 352 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, 353 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, 354 Convert__GPR32AsmReg1_0__SImm161_1, 355 Convert__Reg1_0__Tie0_1_1__Reg1_1, 356 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, 357 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, 358 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, 359 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, 360 Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, 361 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, 362 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, 363 Convert__regZERO__regZERO__JumpTarget1_0, 364 Convert__JumpTarget1_0, 365 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, 366 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, 367 Convert__regZERO__JumpTarget1_0, 368 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1, 369 Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2, 370 Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2, 371 Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2, 372 Convert__FGR64AsmReg1_0__JumpTarget1_1, 373 Convert__regFCC0__JumpTarget1_0, 374 Convert__FCCAsmReg1_0__JumpTarget1_1, 375 Convert__COP2AsmReg1_0__JumpTarget1_1, 376 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, 377 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, 378 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, 379 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 380 Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 381 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, 382 Convert__Reg1_0__JumpTarget1_1, 383 Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, 384 Convert__GPRMM16AsmReg1_0__JumpTarget1_1, 385 Convert__GPR32AsmReg1_0__JumpTarget1_1, 386 Convert__GPR64AsmReg1_0__JumpTarget1_1, 387 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, 388 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2, 389 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2, 390 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2, 391 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2, 392 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, 393 Convert__MSA128AsmReg1_0__JumpTarget1_1, 394 Convert__imm_95_0__imm_95_0, 395 Convert_NoOperands, 396 Convert__ConstantUImm10_01_0__imm_95_0, 397 Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, 398 Convert__ConstantUImm4_01_0, 399 Convert__SImm161_0, 400 Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, 401 Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, 402 Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, 403 Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, 404 Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, 405 Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, 406 Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0, 407 Convert__Mem2_1__ConstantUImm5_01_0, 408 Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, 409 Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, 410 Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, 411 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, 412 Convert__GPR32AsmReg1_0__CCRAsmReg1_1, 413 Convert__GPR32AsmReg1_0__COP2AsmReg1_1, 414 Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1, 415 Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, 416 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, 417 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2, 418 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, 419 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3, 420 Convert__Reg1_0__Reg1_1, 421 Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, 422 Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, 423 Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, 424 Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, 425 Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, 426 Convert__CCRAsmReg1_1__GPR32AsmReg1_0, 427 Convert__COP2AsmReg1_1__GPR32AsmReg1_0, 428 Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1, 429 Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, 430 Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, 431 Convert__FGR64AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, 432 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, 433 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, 434 Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2, 435 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3, 436 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2, 437 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, 438 Convert__GPR64AsmReg1_1__GPR64AsmReg1_2, 439 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3, 440 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3, 441 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3, 442 Convert__regZERO, 443 Convert__GPR32AsmReg1_0, 444 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1, 445 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1, 446 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1, 447 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, 448 Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1, 449 Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1, 450 Convert__Reg1_1__Reg1_2, 451 Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, 452 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, 453 Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, 454 Convert__GPR64AsmReg1_0__Imm1_1, 455 Convert__GPR64AsmReg1_0__Mem2_1, 456 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3, 457 Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0, 458 Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, 459 Convert__GPR64AsmReg1_0__FGR64AsmReg1_1, 460 Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0, 461 Convert__GPR64AsmReg1_0__UImm161_1, 462 Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, 463 Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0, 464 Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, 465 Convert__FGR64AsmReg1_1__GPR64AsmReg1_0, 466 Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0, 467 Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, 468 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, 469 Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0, 470 Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1, 471 Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, 472 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0, 473 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1, 474 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, 475 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, 476 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, 477 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, 478 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, 479 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, 480 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, 481 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, 482 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, 483 Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, 484 Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, 485 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, 486 Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, 487 Convert__MSA128AsmReg1_0__GPR64AsmReg1_1, 488 Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2, 489 Convert__GPR32AsmReg1_0__ConstantUImm2_01_1, 490 Convert__imm_95_0, 491 Convert__ConstantUImm10_01_0, 492 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, 493 Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2, 494 Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2, 495 Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2, 496 Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2, 497 Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1, 498 Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6, 499 Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6, 500 Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6, 501 Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6, 502 Convert__regRA__GPR32AsmReg1_0, 503 Convert__regRA_64__GPR64AsmReg1_0, 504 Convert__Reg1_0, 505 Convert__GPR32AsmReg1_0__imm_95_0, 506 Convert__GPR64AsmReg1_0__imm_95_0, 507 Convert__regZERO__GPR32AsmReg1_0, 508 Convert__GPR64AsmReg1_0, 509 Convert__regZERO_64__GPR64AsmReg1_0, 510 Convert__UImm5Lsl21_0, 511 Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, 512 Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, 513 Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1, 514 Convert__GPR32AsmReg1_0__Imm1_1, 515 Convert__GPR32AsmReg1_0__Mem2_1, 516 Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, 517 Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1, 518 Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, 519 Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, 520 Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, 521 Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, 522 Convert__MSA128AsmReg1_0__MemOffsetSimm10_02_1, 523 Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1, 524 Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1, 525 Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1, 526 Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, 527 Convert__COP2AsmReg1_0__MemOffsetSimm16_02_1, 528 Convert__COP3AsmReg1_0__Mem2_1, 529 Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, 530 Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1, 531 Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, 532 Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, 533 Convert__GPR32AsmReg1_0__UImm32_Coerced1_1, 534 Convert__StrictlyAFGR64AsmReg1_0__Imm1_1, 535 Convert__StrictlyFGR64AsmReg1_0__Imm1_1, 536 Convert__StrictlyFGR32AsmReg1_0__Imm1_1, 537 Convert__GPRMM16AsmReg1_0__UImm7_N11_1, 538 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3, 539 Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3, 540 Convert__GPR32AsmReg1_0__UImm161_1, 541 Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1, 542 Convert__Reg1_0__Imm1_1__imm_95_0, 543 Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, 544 Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1, 545 Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, 546 Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1__Tie0_1_1, 547 Convert__RegList1_0__Mem2_1, 548 Convert__RegList161_0__MemOffsetUimm42_1, 549 ConvertCustom_ConvertXWPOperands, 550 Convert__GPR32AsmReg1_0__MemOffsetSimm12_02_1, 551 Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, 552 Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, 553 Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, 554 Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, 555 Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, 556 Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, 557 Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, 558 Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, 559 Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, 560 Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0, 561 Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, 562 Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1, 563 Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, 564 Convert__GPR32AsmReg1_0__regAC0, 565 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, 566 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4, 567 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, 568 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64, 569 Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3, 570 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, 571 Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, 572 Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, 573 Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, 574 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, 575 Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, 576 Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, 577 Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, 578 Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, 579 Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, 580 Convert__FGR64AsmReg1_1__GPR32AsmReg1_0, 581 Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0, 582 Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, 583 Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, 584 Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, 585 Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, 586 Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1, 587 Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, 588 Convert__regAC0__GPR32AsmReg1_0, 589 Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, 590 Convert__GPR32AsmReg1_1__GPR32AsmReg1_0, 591 Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4, 592 Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, 593 Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, 594 Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, 595 Convert__regZERO__regZERO__imm_95_0, 596 Convert__regZERO__regS0, 597 Convert__regZERO__regZERO, 598 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, 599 Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1, 600 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, 601 Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0, 602 Convert__GPR32AsmReg1_0__ConstantUImm7_01_1, 603 Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, 604 Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, 605 Convert__GPR64AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, 606 Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2, 607 Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2, 608 Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, 609 Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, 610 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, 611 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, 612 Convert__GPR64AsmReg1_0__GPR64AsmReg1_2, 613 Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, 614 Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1, 615 Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm9_02_1, 616 Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, 617 Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1, 618 Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1, 619 Convert__ConstantUImm20_01_0, 620 Convert__Reg1_0__Tie0_1_1, 621 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1, 622 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2, 623 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm32_Coerced1_1, 624 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm32_Coerced1_2, 625 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, 626 Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, 627 Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1, 628 Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1, 629 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, 630 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, 631 Convert__UImm161_0, 632 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, 633 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3, 634 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3, 635 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3, 636 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3, 637 Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, 638 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, 639 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, 640 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, 641 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, 642 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, 643 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1, 644 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2, 645 Convert__ConstantUImm5_01_0, 646 Convert__MemOffsetSimm16_02_0, 647 Convert__imm_95_2, 648 Convert__imm_95_6, 649 Convert__imm_95_4, 650 Convert__imm_95_5, 651 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, 652 Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2, 653 Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2, 654 Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2, 655 Convert__GPR32AsmReg1_0__imm_95_31, 656 CVT_NUM_SIGNATURES 657}; 658 659} // end anonymous namespace 660 661static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][11] = { 662 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1 663 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, 664 // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1 665 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done }, 666 // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1 667 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done }, 668 // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1 669 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done }, 670 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1 671 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, 672 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1 673 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done }, 674 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2 675 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, 676 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2 677 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done }, 678 // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2 679 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done }, 680 // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2 681 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done }, 682 // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2 683 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done }, 684 // Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1 685 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done }, 686 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2 687 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done }, 688 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1 689 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, 690 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1 691 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, 692 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2 693 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done }, 694 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2 695 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done }, 696 // Convert__SImm161_1 697 { CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, 698 // Convert__Reg1_0__SImm161_1 699 { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, 700 // Convert__Reg1_0__SImm161_2 701 { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done }, 702 // Convert__Reg1_0__Reg1_1__SImm161_2 703 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done }, 704 // Convert__Reg1_0__Tie0_1_1__SImm161_1 705 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, 706 // Convert__GPR32AsmReg1_0__Simm19_Lsl21_1 707 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 708 // Convert__GPRMM16AsmReg1_0__Imm1_1 709 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 710 // Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1 711 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 712 // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2 713 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, 714 // Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1 715 { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_, 2, CVT_Done }, 716 // Convert__Imm1_0 717 { CVT_95_addImmOperands, 1, CVT_Done }, 718 // Convert__Reg1_0__Reg1_1__Reg1_2 719 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done }, 720 // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2 721 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addGPRMM16AsmRegOperands, 3, CVT_Done }, 722 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2 723 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, 724 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3 725 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done }, 726 // Convert__GPR32AsmReg1_0__SImm161_1 727 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, 728 // Convert__Reg1_0__Tie0_1_1__Reg1_1 729 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done }, 730 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1 731 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done }, 732 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1 733 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 734 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2 735 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done }, 736 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2 737 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, 738 // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1 739 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done }, 740 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2 741 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done }, 742 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1 743 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Tied, Tie0_1_1, CVT_Done }, 744 // Convert__regZERO__regZERO__JumpTarget1_0 745 { CVT_regZERO, 0, CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done }, 746 // Convert__JumpTarget1_0 747 { CVT_95_addImmOperands, 1, CVT_Done }, 748 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1 749 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done }, 750 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2 751 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done }, 752 // Convert__regZERO__JumpTarget1_0 753 { CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done }, 754 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1 755 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Tied, Tie0_1_1, CVT_Done }, 756 // Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2 757 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done }, 758 // Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2 759 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done }, 760 // Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2 761 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done }, 762 // Convert__FGR64AsmReg1_0__JumpTarget1_1 763 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 764 // Convert__regFCC0__JumpTarget1_0 765 { CVT_regFCC0, 0, CVT_95_addImmOperands, 1, CVT_Done }, 766 // Convert__FCCAsmReg1_0__JumpTarget1_1 767 { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 768 // Convert__COP2AsmReg1_0__JumpTarget1_1 769 { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 770 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2 771 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, 772 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2 773 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done }, 774 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2 775 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done }, 776 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2 777 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, 778 // Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2 779 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, 780 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2 781 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, 782 // Convert__Reg1_0__JumpTarget1_1 783 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, 784 // Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1 785 { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addImmOperands, 2, CVT_Done }, 786 // Convert__GPRMM16AsmReg1_0__JumpTarget1_1 787 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 788 // Convert__GPR32AsmReg1_0__JumpTarget1_1 789 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 790 // Convert__GPR64AsmReg1_0__JumpTarget1_1 791 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 792 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2 793 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done }, 794 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2 795 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, 796 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2 797 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done }, 798 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2 799 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done }, 800 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2 801 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, 802 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2 803 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done }, 804 // Convert__MSA128AsmReg1_0__JumpTarget1_1 805 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 806 // Convert__imm_95_0__imm_95_0 807 { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done }, 808 // Convert_NoOperands 809 { CVT_Done }, 810 // Convert__ConstantUImm10_01_0__imm_95_0 811 { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_imm_95_0, 0, CVT_Done }, 812 // Convert__ConstantUImm10_01_0__ConstantUImm10_01_1 813 { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done }, 814 // Convert__ConstantUImm4_01_0 815 { CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 1, CVT_Done }, 816 // Convert__SImm161_0 817 { CVT_95_addSImmOperands_LT_16_GT_, 1, CVT_Done }, 818 // Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1 819 { CVT_regFCC0, 0, CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done }, 820 // Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1 821 { CVT_regFCC0, 0, CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done }, 822 // Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2 823 { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done }, 824 // Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2 825 { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done }, 826 // Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1 827 { CVT_regFCC0, 0, CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done }, 828 // Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2 829 { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done }, 830 // Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0 831 { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done }, 832 // Convert__Mem2_1__ConstantUImm5_01_0 833 { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done }, 834 // Convert__FGR64AsmReg1_0__FGR32AsmReg1_1 835 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done }, 836 // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1 837 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done }, 838 // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1 839 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done }, 840 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2 841 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, 842 // Convert__GPR32AsmReg1_0__CCRAsmReg1_1 843 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCCRAsmRegOperands, 2, CVT_Done }, 844 // Convert__GPR32AsmReg1_0__COP2AsmReg1_1 845 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_Done }, 846 // Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1 847 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSACtrlAsmRegOperands, 2, CVT_Done }, 848 // Convert__GPR32AsmReg1_0__FGR32AsmReg1_1 849 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done }, 850 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2 851 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, 852 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2 853 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, 854 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3 855 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done }, 856 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3 857 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done }, 858 // Convert__Reg1_0__Reg1_1 859 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done }, 860 // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2 861 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done }, 862 // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3 863 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done }, 864 // Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3 865 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done }, 866 // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3 867 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done }, 868 // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3 869 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done }, 870 // Convert__CCRAsmReg1_1__GPR32AsmReg1_0 871 { CVT_95_addCCRAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 872 // Convert__COP2AsmReg1_1__GPR32AsmReg1_0 873 { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 874 // Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1 875 { CVT_95_addMSACtrlAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, 876 // Convert__FGR32AsmReg1_1__GPR32AsmReg1_0 877 { CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 878 // Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1 879 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done }, 880 // Convert__FGR64AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2 881 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done }, 882 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1 883 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, 884 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2 885 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done }, 886 // Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2 887 { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done }, 888 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3 889 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done }, 890 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2 891 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done }, 892 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1 893 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done }, 894 // Convert__GPR64AsmReg1_1__GPR64AsmReg1_2 895 { CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done }, 896 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3 897 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_, 4, CVT_Done }, 898 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3 899 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done }, 900 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3 901 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done }, 902 // Convert__regZERO 903 { CVT_regZERO, 0, CVT_Done }, 904 // Convert__GPR32AsmReg1_0 905 { CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 906 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1 907 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addImmOperands, 4, CVT_Tied, Tie0_1_1, CVT_Done }, 908 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1 909 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done }, 910 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1 911 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done }, 912 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1 913 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done }, 914 // Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1 915 { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, 916 // Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1 917 { CVT_95_addGPR32ZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, 918 // Convert__Reg1_1__Reg1_2 919 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done }, 920 // Convert__GPR32AsmReg1_1__GPR32AsmReg1_2 921 { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, 922 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2 923 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done }, 924 // Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2 925 { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, 926 // Convert__GPR64AsmReg1_0__Imm1_1 927 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 928 // Convert__GPR64AsmReg1_0__Mem2_1 929 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 930 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3 931 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done }, 932 // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0 933 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, 934 // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2 935 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, 936 // Convert__GPR64AsmReg1_0__FGR64AsmReg1_1 937 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done }, 938 // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0 939 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, 940 // Convert__GPR64AsmReg1_0__UImm161_1 941 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done }, 942 // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2 943 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, 944 // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0 945 { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done }, 946 // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2 947 { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, 948 // Convert__FGR64AsmReg1_1__GPR64AsmReg1_0 949 { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done }, 950 // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0 951 { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done }, 952 // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2 953 { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, 954 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2 955 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done }, 956 // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0 957 { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done }, 958 // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1 959 { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done }, 960 // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1 961 { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, 962 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0 963 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done }, 964 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1 965 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done }, 966 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1 967 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 2, CVT_Done }, 968 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2 969 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done }, 970 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1 971 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done }, 972 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2 973 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, 974 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2 975 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, 976 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1 977 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, 978 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1 979 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 980 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2 981 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, 982 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3 983 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done }, 984 // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2 985 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, 986 // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2 987 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, 988 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1 989 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_Done }, 990 // Convert__MSA128AsmReg1_0__GPR32AsmReg1_1 991 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, 992 // Convert__MSA128AsmReg1_0__GPR64AsmReg1_1 993 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done }, 994 // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2 995 { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, 996 // Convert__GPR32AsmReg1_0__ConstantUImm2_01_1 997 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 2, CVT_Done }, 998 // Convert__imm_95_0 999 { CVT_imm_95_0, 0, CVT_Done }, 1000 // Convert__ConstantUImm10_01_0 1001 { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_Done }, 1002 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1 1003 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done }, 1004 // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2 1005 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done }, 1006 // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2 1007 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR64AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_Done }, 1008 // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2 1009 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, 1010 // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2 1011 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Done }, 1012 // Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1 1013 { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, 1014 // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6 1015 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done }, 1016 // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6 1017 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done }, 1018 // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6 1019 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done }, 1020 // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6 1021 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done }, 1022 // Convert__regRA__GPR32AsmReg1_0 1023 { CVT_regRA, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 1024 // Convert__regRA_64__GPR64AsmReg1_0 1025 { CVT_regRA_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done }, 1026 // Convert__Reg1_0 1027 { CVT_95_Reg, 1, CVT_Done }, 1028 // Convert__GPR32AsmReg1_0__imm_95_0 1029 { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done }, 1030 // Convert__GPR64AsmReg1_0__imm_95_0 1031 { CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done }, 1032 // Convert__regZERO__GPR32AsmReg1_0 1033 { CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 1034 // Convert__GPR64AsmReg1_0 1035 { CVT_95_addGPR64AsmRegOperands, 1, CVT_Done }, 1036 // Convert__regZERO_64__GPR64AsmReg1_0 1037 { CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done }, 1038 // Convert__UImm5Lsl21_0 1039 { CVT_95_addImmOperands, 1, CVT_Done }, 1040 // Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1 1041 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1042 // Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1 1043 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1044 // Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1 1045 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1046 // Convert__GPR32AsmReg1_0__Imm1_1 1047 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 1048 // Convert__GPR32AsmReg1_0__Mem2_1 1049 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1050 // Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1 1051 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1052 // Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1 1053 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1054 // Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1 1055 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1056 // Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1 1057 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done }, 1058 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1 1059 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, 1060 // Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1 1061 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1062 // Convert__MSA128AsmReg1_0__MemOffsetSimm10_02_1 1063 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1064 // Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1 1065 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1066 // Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1 1067 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1068 // Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1 1069 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1070 // Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1 1071 { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1072 // Convert__COP2AsmReg1_0__MemOffsetSimm16_02_1 1073 { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1074 // Convert__COP3AsmReg1_0__Mem2_1 1075 { CVT_95_addCOP3AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1076 // Convert__MSA128AsmReg1_0__ConstantSImm10_01_1 1077 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done }, 1078 // Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1 1079 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done }, 1080 // Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1 1081 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, 1082 // Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1 1083 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, 1084 // Convert__GPR32AsmReg1_0__UImm32_Coerced1_1 1085 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_32_GT_, 2, CVT_Done }, 1086 // Convert__StrictlyAFGR64AsmReg1_0__Imm1_1 1087 { CVT_95_addStrictlyAFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 1088 // Convert__StrictlyFGR64AsmReg1_0__Imm1_1 1089 { CVT_95_addStrictlyFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 1090 // Convert__StrictlyFGR32AsmReg1_0__Imm1_1 1091 { CVT_95_addStrictlyFGR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 1092 // Convert__GPRMM16AsmReg1_0__UImm7_N11_1 1093 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_, 2, CVT_Done }, 1094 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3 1095 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done }, 1096 // Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3 1097 { CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done }, 1098 // Convert__GPR32AsmReg1_0__UImm161_1 1099 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done }, 1100 // Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1 1101 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done }, 1102 // Convert__Reg1_0__Imm1_1__imm_95_0 1103 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done }, 1104 // Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1 1105 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1106 // Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1 1107 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1108 // Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1 1109 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done }, 1110 // Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1__Tie0_1_1 1111 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done }, 1112 // Convert__RegList1_0__Mem2_1 1113 { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1114 // Convert__RegList161_0__MemOffsetUimm42_1 1115 { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1116 // ConvertCustom_ConvertXWPOperands 1117 { CVT_ConvertXWPOperands, 0, CVT_Done }, 1118 // Convert__GPR32AsmReg1_0__MemOffsetSimm12_02_1 1119 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1120 // Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1 1121 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, 1122 // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3 1123 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_95_addAFGR64AsmRegOperands, 4, CVT_Done }, 1124 // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3 1125 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_95_addFGR64AsmRegOperands, 4, CVT_Done }, 1126 // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3 1127 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 4, CVT_Done }, 1128 // Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2 1129 { CVT_95_addFGR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done }, 1130 // Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2 1131 { CVT_95_addFGR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done }, 1132 // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0 1133 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, 1134 // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2 1135 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, 1136 // Convert__GPR32AsmReg1_0__FGR64AsmReg1_1 1137 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done }, 1138 // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0 1139 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, 1140 // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2 1141 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, 1142 // Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1 1143 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done }, 1144 // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1 1145 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_Done }, 1146 // Convert__GPR32AsmReg1_0__regAC0 1147 { CVT_95_addGPR32AsmRegOperands, 1, CVT_regAC0, 0, CVT_Done }, 1148 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0 1149 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, 1150 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4 1151 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 5, CVT_Done }, 1152 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO 1153 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_regZERO, 0, CVT_Done }, 1154 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64 1155 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_regZERO_64, 0, CVT_Done }, 1156 // Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3 1157 { CVT_95_addGPRMM16AsmRegMovePPairFirstOperands, 1, CVT_95_addGPRMM16AsmRegMovePPairSecondOperands, 2, CVT_95_addGPRMM16AsmRegMovePOperands, 3, CVT_95_addGPRMM16AsmRegMovePOperands, 4, CVT_Done }, 1158 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1 1159 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, 1160 // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1 1161 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, 1162 // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1 1163 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, 1164 // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1 1165 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, 1166 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1 1167 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, 1168 // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1 1169 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, 1170 // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1 1171 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, 1172 // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1 1173 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, 1174 // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0 1175 { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done }, 1176 // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2 1177 { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, 1178 // Convert__FGR64AsmReg1_1__GPR32AsmReg1_0 1179 { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 1180 // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0 1181 { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done }, 1182 // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2 1183 { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, 1184 // Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0 1185 { CVT_95_addAFGR64AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 1186 // Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0 1187 { CVT_95_addFGR64AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 1188 // Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0 1189 { CVT_95_addHI32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 1190 // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1 1191 { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_Done }, 1192 // Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0 1193 { CVT_95_addLO32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 1194 // Convert__regAC0__GPR32AsmReg1_0 1195 { CVT_regAC0, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 1196 // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0 1197 { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 1198 // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0 1199 { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 1200 // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4 1201 { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 5, CVT_Done }, 1202 // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2 1203 { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, 1204 // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0 1205 { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 1206 // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1 1207 { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, 1208 // Convert__regZERO__regZERO__imm_95_0 1209 { CVT_regZERO, 0, CVT_regZERO, 0, CVT_imm_95_0, 0, CVT_Done }, 1210 // Convert__regZERO__regS0 1211 { CVT_regZERO, 0, CVT_regS0, 0, CVT_Done }, 1212 // Convert__regZERO__regZERO 1213 { CVT_regZERO, 0, CVT_regZERO, 0, CVT_Done }, 1214 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO 1215 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_Done }, 1216 // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1 1217 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Done }, 1218 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0 1219 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 1220 // Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0 1221 { CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done }, 1222 // Convert__GPR32AsmReg1_0__ConstantUImm7_01_1 1223 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_, 2, CVT_Done }, 1224 // Convert__GPR32AsmReg1_0__ConstantUImm10_01_1 1225 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done }, 1226 // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0 1227 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, 1228 // Convert__GPR64AsmReg1_0__HWRegsAsmReg1_1__imm_95_0 1229 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, 1230 // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2 1231 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, 1232 // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2 1233 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done }, 1234 // Convert__GPR32AsmReg1_0__ConstantSImm10_01_1 1235 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done }, 1236 // Convert__GPR32AsmReg1_0__ConstantUImm8_01_1 1237 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 2, CVT_Done }, 1238 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1 1239 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done }, 1240 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2 1241 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, 1242 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_2 1243 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done }, 1244 // Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1 1245 { CVT_95_addGPRMM16AsmRegZeroOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done }, 1246 // Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1 1247 { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done }, 1248 // Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm9_02_1 1249 { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done }, 1250 // Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1 1251 { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done }, 1252 // Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1 1253 { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done }, 1254 // Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1 1255 { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done }, 1256 // Convert__ConstantUImm20_01_0 1257 { CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_, 1, CVT_Done }, 1258 // Convert__Reg1_0__Tie0_1_1 1259 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done }, 1260 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1 1261 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done }, 1262 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2 1263 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done }, 1264 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm32_Coerced1_1 1265 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_32_GT_, 2, CVT_Done }, 1266 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm32_Coerced1_2 1267 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_32_GT_, 3, CVT_Done }, 1268 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0 1269 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 1270 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1 1271 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, 1272 // Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1 1273 { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_, 2, CVT_Tied, Tie0_1_1, CVT_Done }, 1274 // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1 1275 { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done }, 1276 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2 1277 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done }, 1278 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2 1279 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, 1280 // Convert__UImm161_0 1281 { CVT_95_addUImmOperands_LT_16_GT_, 1, CVT_Done }, 1282 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3 1283 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done }, 1284 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3 1285 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done }, 1286 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3 1287 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done }, 1288 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3 1289 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done }, 1290 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3 1291 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done }, 1292 // Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2 1293 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, 1294 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3 1295 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done }, 1296 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3 1297 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done }, 1298 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3 1299 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done }, 1300 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3 1301 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done }, 1302 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3 1303 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done }, 1304 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1 1305 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 1306 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2 1307 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, 1308 // Convert__ConstantUImm5_01_0 1309 { CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done }, 1310 // Convert__MemOffsetSimm16_02_0 1311 { CVT_95_addMemOperands, 1, CVT_Done }, 1312 // Convert__imm_95_2 1313 { CVT_imm_95_2, 0, CVT_Done }, 1314 // Convert__imm_95_6 1315 { CVT_imm_95_6, 0, CVT_Done }, 1316 // Convert__imm_95_4 1317 { CVT_imm_95_4, 0, CVT_Done }, 1318 // Convert__imm_95_5 1319 { CVT_imm_95_5, 0, CVT_Done }, 1320 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2 1321 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done }, 1322 // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2 1323 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, 1324 // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2 1325 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, 1326 // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2 1327 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, 1328 // Convert__GPR32AsmReg1_0__imm_95_31 1329 { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_31, 0, CVT_Done }, 1330}; 1331 1332void MipsAsmParser:: 1333convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode, 1334 const OperandVector &Operands) { 1335 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); 1336 const uint8_t *Converter = ConversionTable[Kind]; 1337 unsigned OpIdx; 1338 Inst.setOpcode(Opcode); 1339 for (const uint8_t *p = Converter; *p; p+= 2) { 1340 OpIdx = *(p + 1); 1341 switch (*p) { 1342 default: llvm_unreachable("invalid conversion entry!"); 1343 case CVT_Reg: 1344 static_cast<MipsOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1); 1345 break; 1346 case CVT_Tied: { 1347 assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) - 1348 std::begin(TiedAsmOperandTable)) && 1349 "Tied operand not found"); 1350 unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0]; 1351 if (TiedResOpnd != (uint8_t) -1) 1352 Inst.addOperand(Inst.getOperand(TiedResOpnd)); 1353 break; 1354 } 1355 case CVT_95_addGPR32AsmRegOperands: 1356 static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32AsmRegOperands(Inst, 1); 1357 break; 1358 case CVT_95_addAFGR64AsmRegOperands: 1359 static_cast<MipsOperand&>(*Operands[OpIdx]).addAFGR64AsmRegOperands(Inst, 1); 1360 break; 1361 case CVT_95_addFGR64AsmRegOperands: 1362 static_cast<MipsOperand&>(*Operands[OpIdx]).addFGR64AsmRegOperands(Inst, 1); 1363 break; 1364 case CVT_95_addFGR32AsmRegOperands: 1365 static_cast<MipsOperand&>(*Operands[OpIdx]).addFGR32AsmRegOperands(Inst, 1); 1366 break; 1367 case CVT_95_addSImmOperands_LT_32_GT_: 1368 static_cast<MipsOperand&>(*Operands[OpIdx]).addSImmOperands<32>(Inst, 1); 1369 break; 1370 case CVT_95_addMSA128AsmRegOperands: 1371 static_cast<MipsOperand&>(*Operands[OpIdx]).addMSA128AsmRegOperands(Inst, 1); 1372 break; 1373 case CVT_95_addSImmOperands_LT_16_GT_: 1374 static_cast<MipsOperand&>(*Operands[OpIdx]).addSImmOperands<16>(Inst, 1); 1375 break; 1376 case CVT_95_Reg: 1377 static_cast<MipsOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1); 1378 break; 1379 case CVT_95_addImmOperands: 1380 static_cast<MipsOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1); 1381 break; 1382 case CVT_95_addGPRMM16AsmRegOperands: 1383 static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegOperands(Inst, 1); 1384 break; 1385 case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_: 1386 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<4, 0>(Inst, 1); 1387 break; 1388 case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_: 1389 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 0>(Inst, 1); 1390 break; 1391 case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_: 1392 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<2, 0>(Inst, 1); 1393 break; 1394 case CVT_95_addUImmOperands_LT_16_GT_: 1395 static_cast<MipsOperand&>(*Operands[OpIdx]).addUImmOperands<16>(Inst, 1); 1396 break; 1397 case CVT_95_addGPR64AsmRegOperands: 1398 static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR64AsmRegOperands(Inst, 1); 1399 break; 1400 case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_: 1401 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<8, 0>(Inst, 1); 1402 break; 1403 case CVT_regZERO: 1404 Inst.addOperand(MCOperand::createReg(Mips::ZERO)); 1405 break; 1406 case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_: 1407 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 32, -32>(Inst, 1); 1408 break; 1409 case CVT_regFCC0: 1410 Inst.addOperand(MCOperand::createReg(Mips::FCC0)); 1411 break; 1412 case CVT_95_addFCCAsmRegOperands: 1413 static_cast<MipsOperand&>(*Operands[OpIdx]).addFCCAsmRegOperands(Inst, 1); 1414 break; 1415 case CVT_95_addCOP2AsmRegOperands: 1416 static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP2AsmRegOperands(Inst, 1); 1417 break; 1418 case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_: 1419 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<3, 0>(Inst, 1); 1420 break; 1421 case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_: 1422 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<6, 0>(Inst, 1); 1423 break; 1424 case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_: 1425 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<4, 0>(Inst, 1); 1426 break; 1427 case CVT_imm_95_0: 1428 Inst.addOperand(MCOperand::createImm(0)); 1429 break; 1430 case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_: 1431 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<10, 0>(Inst, 1); 1432 break; 1433 case CVT_95_addMemOperands: 1434 static_cast<MipsOperand&>(*Operands[OpIdx]).addMemOperands(Inst, 2); 1435 break; 1436 case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_: 1437 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<5, 0>(Inst, 1); 1438 break; 1439 case CVT_95_addCCRAsmRegOperands: 1440 static_cast<MipsOperand&>(*Operands[OpIdx]).addCCRAsmRegOperands(Inst, 1); 1441 break; 1442 case CVT_95_addMSACtrlAsmRegOperands: 1443 static_cast<MipsOperand&>(*Operands[OpIdx]).addMSACtrlAsmRegOperands(Inst, 1); 1444 break; 1445 case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_: 1446 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<1, 0>(Inst, 1); 1447 break; 1448 case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_: 1449 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 33>(Inst, 1); 1450 break; 1451 case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_: 1452 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 32>(Inst, 1); 1453 break; 1454 case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_: 1455 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 1>(Inst, 1); 1456 break; 1457 case CVT_95_addGPR32NonZeroAsmRegOperands: 1458 static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32NonZeroAsmRegOperands(Inst, 1); 1459 break; 1460 case CVT_95_addGPR32ZeroAsmRegOperands: 1461 static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32ZeroAsmRegOperands(Inst, 1); 1462 break; 1463 case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_: 1464 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<2, 1>(Inst, 1); 1465 break; 1466 case CVT_95_addCOP0AsmRegOperands: 1467 static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP0AsmRegOperands(Inst, 1); 1468 break; 1469 case CVT_regZERO_64: 1470 Inst.addOperand(MCOperand::createReg(Mips::ZERO_64)); 1471 break; 1472 case CVT_95_addACC64DSPAsmRegOperands: 1473 static_cast<MipsOperand&>(*Operands[OpIdx]).addACC64DSPAsmRegOperands(Inst, 1); 1474 break; 1475 case CVT_95_addConstantUImmOperands_LT_1_GT_: 1476 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<1>(Inst, 1); 1477 break; 1478 case CVT_regRA: 1479 Inst.addOperand(MCOperand::createReg(Mips::RA)); 1480 break; 1481 case CVT_regRA_64: 1482 Inst.addOperand(MCOperand::createReg(Mips::RA_64)); 1483 break; 1484 case CVT_95_addMicroMipsMemOperands: 1485 static_cast<MipsOperand&>(*Operands[OpIdx]).addMicroMipsMemOperands(Inst, 2); 1486 break; 1487 case CVT_95_addCOP3AsmRegOperands: 1488 static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP3AsmRegOperands(Inst, 1); 1489 break; 1490 case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_: 1491 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<10, 0>(Inst, 1); 1492 break; 1493 case CVT_95_addConstantUImmOperands_LT_32_GT_: 1494 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<32>(Inst, 1); 1495 break; 1496 case CVT_95_addStrictlyAFGR64AsmRegOperands: 1497 static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyAFGR64AsmRegOperands(Inst, 1); 1498 break; 1499 case CVT_95_addStrictlyFGR64AsmRegOperands: 1500 static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyFGR64AsmRegOperands(Inst, 1); 1501 break; 1502 case CVT_95_addStrictlyFGR32AsmRegOperands: 1503 static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyFGR32AsmRegOperands(Inst, 1); 1504 break; 1505 case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_: 1506 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<7, -1>(Inst, 1); 1507 break; 1508 case CVT_95_addRegListOperands: 1509 static_cast<MipsOperand&>(*Operands[OpIdx]).addRegListOperands(Inst, 1); 1510 break; 1511 case CVT_ConvertXWPOperands: 1512 ConvertXWPOperands(Inst, Operands); 1513 break; 1514 case CVT_regAC0: 1515 Inst.addOperand(MCOperand::createReg(Mips::AC0)); 1516 break; 1517 case CVT_95_addGPRMM16AsmRegMovePPairFirstOperands: 1518 static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegMovePPairFirstOperands(Inst, 1); 1519 break; 1520 case CVT_95_addGPRMM16AsmRegMovePPairSecondOperands: 1521 static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegMovePPairSecondOperands(Inst, 1); 1522 break; 1523 case CVT_95_addGPRMM16AsmRegMovePOperands: 1524 static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegMovePOperands(Inst, 1); 1525 break; 1526 case CVT_95_addHI32DSPAsmRegOperands: 1527 static_cast<MipsOperand&>(*Operands[OpIdx]).addHI32DSPAsmRegOperands(Inst, 1); 1528 break; 1529 case CVT_95_addLO32DSPAsmRegOperands: 1530 static_cast<MipsOperand&>(*Operands[OpIdx]).addLO32DSPAsmRegOperands(Inst, 1); 1531 break; 1532 case CVT_regS0: 1533 Inst.addOperand(MCOperand::createReg(Mips::S0)); 1534 break; 1535 case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_: 1536 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<7, 0>(Inst, 1); 1537 break; 1538 case CVT_95_addHWRegsAsmRegOperands: 1539 static_cast<MipsOperand&>(*Operands[OpIdx]).addHWRegsAsmRegOperands(Inst, 1); 1540 break; 1541 case CVT_95_addGPRMM16AsmRegZeroOperands: 1542 static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegZeroOperands(Inst, 1); 1543 break; 1544 case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_: 1545 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<20, 0>(Inst, 1); 1546 break; 1547 case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_: 1548 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<6, 0>(Inst, 1); 1549 break; 1550 case CVT_imm_95_2: 1551 Inst.addOperand(MCOperand::createImm(2)); 1552 break; 1553 case CVT_imm_95_6: 1554 Inst.addOperand(MCOperand::createImm(6)); 1555 break; 1556 case CVT_imm_95_4: 1557 Inst.addOperand(MCOperand::createImm(4)); 1558 break; 1559 case CVT_imm_95_5: 1560 Inst.addOperand(MCOperand::createImm(5)); 1561 break; 1562 case CVT_imm_95_31: 1563 Inst.addOperand(MCOperand::createImm(31)); 1564 break; 1565 } 1566 } 1567} 1568 1569void MipsAsmParser:: 1570convertToMapAndConstraints(unsigned Kind, 1571 const OperandVector &Operands) { 1572 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); 1573 unsigned NumMCOperands = 0; 1574 const uint8_t *Converter = ConversionTable[Kind]; 1575 for (const uint8_t *p = Converter; *p; p+= 2) { 1576 switch (*p) { 1577 default: llvm_unreachable("invalid conversion entry!"); 1578 case CVT_Reg: 1579 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1580 Operands[*(p + 1)]->setConstraint("r"); 1581 ++NumMCOperands; 1582 break; 1583 case CVT_Tied: 1584 ++NumMCOperands; 1585 break; 1586 case CVT_95_addGPR32AsmRegOperands: 1587 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1588 Operands[*(p + 1)]->setConstraint("m"); 1589 NumMCOperands += 1; 1590 break; 1591 case CVT_95_addAFGR64AsmRegOperands: 1592 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1593 Operands[*(p + 1)]->setConstraint("m"); 1594 NumMCOperands += 1; 1595 break; 1596 case CVT_95_addFGR64AsmRegOperands: 1597 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1598 Operands[*(p + 1)]->setConstraint("m"); 1599 NumMCOperands += 1; 1600 break; 1601 case CVT_95_addFGR32AsmRegOperands: 1602 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1603 Operands[*(p + 1)]->setConstraint("m"); 1604 NumMCOperands += 1; 1605 break; 1606 case CVT_95_addSImmOperands_LT_32_GT_: 1607 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1608 Operands[*(p + 1)]->setConstraint("m"); 1609 NumMCOperands += 1; 1610 break; 1611 case CVT_95_addMSA128AsmRegOperands: 1612 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1613 Operands[*(p + 1)]->setConstraint("m"); 1614 NumMCOperands += 1; 1615 break; 1616 case CVT_95_addSImmOperands_LT_16_GT_: 1617 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1618 Operands[*(p + 1)]->setConstraint("m"); 1619 NumMCOperands += 1; 1620 break; 1621 case CVT_95_Reg: 1622 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1623 Operands[*(p + 1)]->setConstraint("r"); 1624 NumMCOperands += 1; 1625 break; 1626 case CVT_95_addImmOperands: 1627 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1628 Operands[*(p + 1)]->setConstraint("m"); 1629 NumMCOperands += 1; 1630 break; 1631 case CVT_95_addGPRMM16AsmRegOperands: 1632 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1633 Operands[*(p + 1)]->setConstraint("m"); 1634 NumMCOperands += 1; 1635 break; 1636 case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_: 1637 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1638 Operands[*(p + 1)]->setConstraint("m"); 1639 NumMCOperands += 1; 1640 break; 1641 case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_: 1642 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1643 Operands[*(p + 1)]->setConstraint("m"); 1644 NumMCOperands += 1; 1645 break; 1646 case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_: 1647 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1648 Operands[*(p + 1)]->setConstraint("m"); 1649 NumMCOperands += 1; 1650 break; 1651 case CVT_95_addUImmOperands_LT_16_GT_: 1652 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1653 Operands[*(p + 1)]->setConstraint("m"); 1654 NumMCOperands += 1; 1655 break; 1656 case CVT_95_addGPR64AsmRegOperands: 1657 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1658 Operands[*(p + 1)]->setConstraint("m"); 1659 NumMCOperands += 1; 1660 break; 1661 case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_: 1662 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1663 Operands[*(p + 1)]->setConstraint("m"); 1664 NumMCOperands += 1; 1665 break; 1666 case CVT_regZERO: 1667 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1668 Operands[*(p + 1)]->setConstraint("m"); 1669 ++NumMCOperands; 1670 break; 1671 case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_: 1672 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1673 Operands[*(p + 1)]->setConstraint("m"); 1674 NumMCOperands += 1; 1675 break; 1676 case CVT_regFCC0: 1677 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1678 Operands[*(p + 1)]->setConstraint("m"); 1679 ++NumMCOperands; 1680 break; 1681 case CVT_95_addFCCAsmRegOperands: 1682 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1683 Operands[*(p + 1)]->setConstraint("m"); 1684 NumMCOperands += 1; 1685 break; 1686 case CVT_95_addCOP2AsmRegOperands: 1687 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1688 Operands[*(p + 1)]->setConstraint("m"); 1689 NumMCOperands += 1; 1690 break; 1691 case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_: 1692 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1693 Operands[*(p + 1)]->setConstraint("m"); 1694 NumMCOperands += 1; 1695 break; 1696 case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_: 1697 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1698 Operands[*(p + 1)]->setConstraint("m"); 1699 NumMCOperands += 1; 1700 break; 1701 case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_: 1702 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1703 Operands[*(p + 1)]->setConstraint("m"); 1704 NumMCOperands += 1; 1705 break; 1706 case CVT_imm_95_0: 1707 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1708 Operands[*(p + 1)]->setConstraint(""); 1709 ++NumMCOperands; 1710 break; 1711 case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_: 1712 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1713 Operands[*(p + 1)]->setConstraint("m"); 1714 NumMCOperands += 1; 1715 break; 1716 case CVT_95_addMemOperands: 1717 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1718 Operands[*(p + 1)]->setConstraint("m"); 1719 NumMCOperands += 2; 1720 break; 1721 case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_: 1722 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1723 Operands[*(p + 1)]->setConstraint("m"); 1724 NumMCOperands += 1; 1725 break; 1726 case CVT_95_addCCRAsmRegOperands: 1727 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1728 Operands[*(p + 1)]->setConstraint("m"); 1729 NumMCOperands += 1; 1730 break; 1731 case CVT_95_addMSACtrlAsmRegOperands: 1732 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1733 Operands[*(p + 1)]->setConstraint("m"); 1734 NumMCOperands += 1; 1735 break; 1736 case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_: 1737 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1738 Operands[*(p + 1)]->setConstraint("m"); 1739 NumMCOperands += 1; 1740 break; 1741 case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_: 1742 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1743 Operands[*(p + 1)]->setConstraint("m"); 1744 NumMCOperands += 1; 1745 break; 1746 case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_: 1747 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1748 Operands[*(p + 1)]->setConstraint("m"); 1749 NumMCOperands += 1; 1750 break; 1751 case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_: 1752 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1753 Operands[*(p + 1)]->setConstraint("m"); 1754 NumMCOperands += 1; 1755 break; 1756 case CVT_95_addGPR32NonZeroAsmRegOperands: 1757 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1758 Operands[*(p + 1)]->setConstraint("m"); 1759 NumMCOperands += 1; 1760 break; 1761 case CVT_95_addGPR32ZeroAsmRegOperands: 1762 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1763 Operands[*(p + 1)]->setConstraint("m"); 1764 NumMCOperands += 1; 1765 break; 1766 case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_: 1767 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1768 Operands[*(p + 1)]->setConstraint("m"); 1769 NumMCOperands += 1; 1770 break; 1771 case CVT_95_addCOP0AsmRegOperands: 1772 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1773 Operands[*(p + 1)]->setConstraint("m"); 1774 NumMCOperands += 1; 1775 break; 1776 case CVT_regZERO_64: 1777 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1778 Operands[*(p + 1)]->setConstraint("m"); 1779 ++NumMCOperands; 1780 break; 1781 case CVT_95_addACC64DSPAsmRegOperands: 1782 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1783 Operands[*(p + 1)]->setConstraint("m"); 1784 NumMCOperands += 1; 1785 break; 1786 case CVT_95_addConstantUImmOperands_LT_1_GT_: 1787 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1788 Operands[*(p + 1)]->setConstraint("m"); 1789 NumMCOperands += 1; 1790 break; 1791 case CVT_regRA: 1792 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1793 Operands[*(p + 1)]->setConstraint("m"); 1794 ++NumMCOperands; 1795 break; 1796 case CVT_regRA_64: 1797 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1798 Operands[*(p + 1)]->setConstraint("m"); 1799 ++NumMCOperands; 1800 break; 1801 case CVT_95_addMicroMipsMemOperands: 1802 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1803 Operands[*(p + 1)]->setConstraint("m"); 1804 NumMCOperands += 2; 1805 break; 1806 case CVT_95_addCOP3AsmRegOperands: 1807 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1808 Operands[*(p + 1)]->setConstraint("m"); 1809 NumMCOperands += 1; 1810 break; 1811 case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_: 1812 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1813 Operands[*(p + 1)]->setConstraint("m"); 1814 NumMCOperands += 1; 1815 break; 1816 case CVT_95_addConstantUImmOperands_LT_32_GT_: 1817 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1818 Operands[*(p + 1)]->setConstraint("m"); 1819 NumMCOperands += 1; 1820 break; 1821 case CVT_95_addStrictlyAFGR64AsmRegOperands: 1822 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1823 Operands[*(p + 1)]->setConstraint("m"); 1824 NumMCOperands += 1; 1825 break; 1826 case CVT_95_addStrictlyFGR64AsmRegOperands: 1827 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1828 Operands[*(p + 1)]->setConstraint("m"); 1829 NumMCOperands += 1; 1830 break; 1831 case CVT_95_addStrictlyFGR32AsmRegOperands: 1832 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1833 Operands[*(p + 1)]->setConstraint("m"); 1834 NumMCOperands += 1; 1835 break; 1836 case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_: 1837 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1838 Operands[*(p + 1)]->setConstraint("m"); 1839 NumMCOperands += 1; 1840 break; 1841 case CVT_95_addRegListOperands: 1842 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1843 Operands[*(p + 1)]->setConstraint("m"); 1844 NumMCOperands += 1; 1845 break; 1846 case CVT_regAC0: 1847 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1848 Operands[*(p + 1)]->setConstraint("m"); 1849 ++NumMCOperands; 1850 break; 1851 case CVT_95_addGPRMM16AsmRegMovePPairFirstOperands: 1852 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1853 Operands[*(p + 1)]->setConstraint("m"); 1854 NumMCOperands += 1; 1855 break; 1856 case CVT_95_addGPRMM16AsmRegMovePPairSecondOperands: 1857 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1858 Operands[*(p + 1)]->setConstraint("m"); 1859 NumMCOperands += 1; 1860 break; 1861 case CVT_95_addGPRMM16AsmRegMovePOperands: 1862 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1863 Operands[*(p + 1)]->setConstraint("m"); 1864 NumMCOperands += 1; 1865 break; 1866 case CVT_95_addHI32DSPAsmRegOperands: 1867 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1868 Operands[*(p + 1)]->setConstraint("m"); 1869 NumMCOperands += 1; 1870 break; 1871 case CVT_95_addLO32DSPAsmRegOperands: 1872 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1873 Operands[*(p + 1)]->setConstraint("m"); 1874 NumMCOperands += 1; 1875 break; 1876 case CVT_regS0: 1877 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1878 Operands[*(p + 1)]->setConstraint("m"); 1879 ++NumMCOperands; 1880 break; 1881 case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_: 1882 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1883 Operands[*(p + 1)]->setConstraint("m"); 1884 NumMCOperands += 1; 1885 break; 1886 case CVT_95_addHWRegsAsmRegOperands: 1887 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1888 Operands[*(p + 1)]->setConstraint("m"); 1889 NumMCOperands += 1; 1890 break; 1891 case CVT_95_addGPRMM16AsmRegZeroOperands: 1892 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1893 Operands[*(p + 1)]->setConstraint("m"); 1894 NumMCOperands += 1; 1895 break; 1896 case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_: 1897 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1898 Operands[*(p + 1)]->setConstraint("m"); 1899 NumMCOperands += 1; 1900 break; 1901 case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_: 1902 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1903 Operands[*(p + 1)]->setConstraint("m"); 1904 NumMCOperands += 1; 1905 break; 1906 case CVT_imm_95_2: 1907 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1908 Operands[*(p + 1)]->setConstraint(""); 1909 ++NumMCOperands; 1910 break; 1911 case CVT_imm_95_6: 1912 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1913 Operands[*(p + 1)]->setConstraint(""); 1914 ++NumMCOperands; 1915 break; 1916 case CVT_imm_95_4: 1917 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1918 Operands[*(p + 1)]->setConstraint(""); 1919 ++NumMCOperands; 1920 break; 1921 case CVT_imm_95_5: 1922 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1923 Operands[*(p + 1)]->setConstraint(""); 1924 ++NumMCOperands; 1925 break; 1926 case CVT_imm_95_31: 1927 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1928 Operands[*(p + 1)]->setConstraint(""); 1929 ++NumMCOperands; 1930 break; 1931 } 1932 } 1933} 1934 1935namespace { 1936 1937/// MatchClassKind - The kinds of classes which participate in 1938/// instruction matching. 1939enum MatchClassKind { 1940 InvalidMatchClass = 0, 1941 OptionalMatchClass = 1, 1942 MCK__HASH_, // '#' 1943 MCK__40_, // '(' 1944 MCK__41_, // ')' 1945 MCK_0, // '0' 1946 MCK_16, // '16' 1947 MCK__91_, // '[' 1948 MCK__93_, // ']' 1949 MCK_bit, // 'bit' 1950 MCK_inst, // 'inst' 1951 MCK_LAST_TOKEN = MCK_inst, 1952 MCK_Reg37, // derived register class 1953 MCK_Reg19, // derived register class 1954 MCK_ACC128, // register class 'ACC128' 1955 MCK_ACC64, // register class 'ACC64' 1956 MCK_CPURAReg, // register class 'CPURAReg,RA' 1957 MCK_CPUSPReg, // register class 'CPUSPReg,SP32,SP' 1958 MCK_DSPCC, // register class 'DSPCC' 1959 MCK_GP32, // register class 'GP32' 1960 MCK_GP64, // register class 'GP64' 1961 MCK_GPR32ZERO, // register class 'GPR32ZERO,ZERO' 1962 MCK_HI32, // register class 'HI32' 1963 MCK_HI64, // register class 'HI64' 1964 MCK_LO32, // register class 'LO32' 1965 MCK_LO64, // register class 'LO64' 1966 MCK_PC, // register class 'PC' 1967 MCK_SP64, // register class 'SP64' 1968 MCK_Reg32, // derived register class 1969 MCK_Reg13, // derived register class 1970 MCK_Reg33, // derived register class 1971 MCK_Reg31, // derived register class 1972 MCK_Reg30, // derived register class 1973 MCK_Reg14, // derived register class 1974 MCK_Reg11, // derived register class 1975 MCK_GPRMM16MovePPairFirst, // register class 'GPRMM16MovePPairFirst' 1976 MCK_OCTEON_MPL, // register class 'OCTEON_MPL' 1977 MCK_OCTEON_P, // register class 'OCTEON_P' 1978 MCK_Reg28, // derived register class 1979 MCK_Reg23, // derived register class 1980 MCK_Reg9, // derived register class 1981 MCK_Reg4, // derived register class 1982 MCK_ACC64DSP, // register class 'ACC64DSP' 1983 MCK_HI32DSP, // register class 'HI32DSP' 1984 MCK_LO32DSP, // register class 'LO32DSP' 1985 MCK_Reg34, // derived register class 1986 MCK_GPRMM16MovePPairSecond, // register class 'GPRMM16MovePPairSecond' 1987 MCK_Reg29, // derived register class 1988 MCK_Reg27, // derived register class 1989 MCK_Reg10, // derived register class 1990 MCK_Reg8, // derived register class 1991 MCK_Reg25, // derived register class 1992 MCK_Reg22, // derived register class 1993 MCK_Reg21, // derived register class 1994 MCK_CPU16Regs, // register class 'CPU16Regs,GPRMM16' 1995 MCK_FCC, // register class 'FCC' 1996 MCK_GPRMM16MoveP, // register class 'GPRMM16MoveP' 1997 MCK_GPRMM16Zero, // register class 'GPRMM16Zero' 1998 MCK_Reg26, // derived register class 1999 MCK_CPU16RegsPlusSP, // register class 'CPU16RegsPlusSP' 2000 MCK_AFGR64, // register class 'AFGR64' 2001 MCK_MSA128WEvens, // register class 'MSA128WEvens' 2002 MCK_Reg24, // derived register class 2003 MCK_GPR32NONZERO, // register class 'GPR32NONZERO' 2004 MCK_CCR, // register class 'CCR' 2005 MCK_COP0, // register class 'COP0' 2006 MCK_COP2, // register class 'COP2' 2007 MCK_COP3, // register class 'COP3' 2008 MCK_DSPR, // register class 'DSPR,GPR32' 2009 MCK_FGR32, // register class 'FGR32,FGRCC' 2010 MCK_FGR64, // register class 'FGR64' 2011 MCK_GPR64, // register class 'GPR64' 2012 MCK_HWRegs, // register class 'HWRegs' 2013 MCK_MSA128F16, // register class 'MSA128F16,MSA128B,MSA128D,MSA128H,MSA128W' 2014 MCK_MSACtrl, // register class 'MSACtrl' 2015 MCK_LAST_REGISTER = MCK_MSACtrl, 2016 MCK_ACC64DSPAsmReg, // user defined class 'ACC64DSPAsmOperand' 2017 MCK_AFGR64AsmReg, // user defined class 'AFGR64AsmOperand' 2018 MCK_CCRAsmReg, // user defined class 'CCRAsmOperand' 2019 MCK_COP0AsmReg, // user defined class 'COP0AsmOperand' 2020 MCK_COP2AsmReg, // user defined class 'COP2AsmOperand' 2021 MCK_COP3AsmReg, // user defined class 'COP3AsmOperand' 2022 MCK_FCCAsmReg, // user defined class 'FCCRegsAsmOperand' 2023 MCK_FGR32AsmReg, // user defined class 'FGR32AsmOperand' 2024 MCK_FGR64AsmReg, // user defined class 'FGR64AsmOperand' 2025 MCK_GPR32AsmReg, // user defined class 'GPR32AsmOperand' 2026 MCK_GPR32NonZeroAsmReg, // user defined class 'GPR32NonZeroAsmOperand' 2027 MCK_GPR32ZeroAsmReg, // user defined class 'GPR32ZeroAsmOperand' 2028 MCK_GPR64AsmReg, // user defined class 'GPR64AsmOperand' 2029 MCK_GPRMM16AsmReg, // user defined class 'GPRMM16AsmOperand' 2030 MCK_GPRMM16AsmRegMoveP, // user defined class 'GPRMM16AsmOperandMoveP' 2031 MCK_GPRMM16AsmRegMovePPairFirst, // user defined class 'GPRMM16AsmOperandMovePPairFirst' 2032 MCK_GPRMM16AsmRegMovePPairSecond, // user defined class 'GPRMM16AsmOperandMovePPairSecond' 2033 MCK_GPRMM16AsmRegZero, // user defined class 'GPRMM16AsmOperandZero' 2034 MCK_HI32DSPAsmReg, // user defined class 'HI32DSPAsmOperand' 2035 MCK_HWRegsAsmReg, // user defined class 'HWRegsAsmOperand' 2036 MCK_Imm, // user defined class 'ImmAsmOperand' 2037 MCK_LO32DSPAsmReg, // user defined class 'LO32DSPAsmOperand' 2038 MCK_MSA128AsmReg, // user defined class 'MSA128AsmOperand' 2039 MCK_MSACtrlAsmReg, // user defined class 'MSACtrlAsmOperand' 2040 MCK_MicroMipsMemGP, // user defined class 'MicroMipsMemGPAsmOperand' 2041 MCK_MicroMipsMem, // user defined class 'MicroMipsMemGPRMM16AsmOperand' 2042 MCK_MicroMipsMemSP, // user defined class 'MicroMipsMemSPAsmOperand' 2043 MCK_InvNum, // user defined class 'MipsInvertedImmoperand' 2044 MCK_JumpTarget, // user defined class 'MipsJumpTargetAsmOperand' 2045 MCK_MemOffsetSimmPtr, // user defined class 'MipsMemSimmPtrAsmOperand' 2046 MCK_MemOffsetUimm4, // user defined class 'MipsMemUimm4AsmOperand' 2047 MCK_MemOffsetSimm9_0, // user defined class 'anonymous_2605' 2048 MCK_MemOffsetSimm10_0, // user defined class 'anonymous_2606' 2049 MCK_MemOffsetSimm11_0, // user defined class 'anonymous_2607' 2050 MCK_MemOffsetSimm12_0, // user defined class 'anonymous_2608' 2051 MCK_MemOffsetSimm16_0, // user defined class 'anonymous_2609' 2052 MCK_MemOffsetSimm10_1, // user defined class 'anonymous_2610' 2053 MCK_MemOffsetSimm10_2, // user defined class 'anonymous_2611' 2054 MCK_MemOffsetSimm10_3, // user defined class 'anonymous_2612' 2055 MCK_Mem, // user defined class 'MipsMemAsmOperand' 2056 MCK_RegList16, // user defined class 'RegList16AsmOperand' 2057 MCK_RegList, // user defined class 'RegListAsmOperand' 2058 MCK_Simm19_Lsl2, // user defined class 'Simm19Lsl2AsmOperand' 2059 MCK_StrictlyAFGR64AsmReg, // user defined class 'StrictlyAFGR64AsmOperand' 2060 MCK_StrictlyFGR32AsmReg, // user defined class 'StrictlyFGR32AsmOperand' 2061 MCK_StrictlyFGR64AsmReg, // user defined class 'StrictlyFGR64AsmOperand' 2062 MCK_ConstantImmz, // user defined class 'ConstantImmzAsmOperandClass' 2063 MCK_ConstantUImm1_0, // user defined class 'ConstantUImm1AsmOperandClass' 2064 MCK_ConstantUImm2_0, // user defined class 'ConstantUImm2AsmOperandClass' 2065 MCK_ConstantUImm2_1, // user defined class 'ConstantUImm2Plus1AsmOperandClass' 2066 MCK_ConstantUImm3_0, // user defined class 'ConstantUImm3AsmOperandClass' 2067 MCK_ConstantSImm4_0, // user defined class 'ConstantSImm4AsmOperandClass' 2068 MCK_ConstantUImm4_0, // user defined class 'ConstantUImm4AsmOperandClass' 2069 MCK_ConstantSImm5_0, // user defined class 'ConstantSImm5AsmOperandClass' 2070 MCK_ConstantUImm5_0, // user defined class 'ConstantUImm5AsmOperandClass' 2071 MCK_ConstantUImm5_1, // user defined class 'ConstantUImm5Plus1AsmOperandClass' 2072 MCK_ConstantUImm5_Plus1_Report_UImm6, // user defined class 'ConstantUImm5Plus1ReportUImm6AsmOperandClass' 2073 MCK_ConstantUImm5_32_Norm, // user defined class 'ConstantUImm5Plus32NormalizeAsmOperandClass' 2074 MCK_ConstantUImm5_32, // user defined class 'ConstantUImm5Plus32AsmOperandClass' 2075 MCK_ConstantUImm5_0_Report_UImm6, // user defined class 'ConstantUImm5ReportUImm6AsmOperandClass' 2076 MCK_ConstantUImm5_33, // user defined class 'ConstantUImm5Plus33AsmOperandClass' 2077 MCK_ConstantUImmRange2_64, // user defined class 'ConstantUImm5_Range2_64AsmOperandClass' 2078 MCK_UImm5Lsl2, // user defined class 'ConstantUImm5Lsl2AsmOperandClass' 2079 MCK_ConstantSImm6_0, // user defined class 'ConstantSImm6AsmOperandClass' 2080 MCK_ConstantUImm6_0, // user defined class 'ConstantUImm6AsmOperandClass' 2081 MCK_UImm6Lsl2, // user defined class 'ConstantUImm6Lsl2AsmOperandClass' 2082 MCK_ConstantUImm7_0, // user defined class 'ConstantUImm7AsmOperandClass' 2083 MCK_UImm7_N1, // user defined class 'ConstantUImm7Sub1AsmOperandClass' 2084 MCK_ConstantUImm8_0, // user defined class 'ConstantUImm8AsmOperandClass' 2085 MCK_SImm7Lsl2, // user defined class 'ConstantSImm7Lsl2AsmOperandClass' 2086 MCK_ConstantSImm9_0, // user defined class 'ConstantSImm9AsmOperandClass' 2087 MCK_ConstantSImm10_0, // user defined class 'ConstantSImm10AsmOperandClass' 2088 MCK_ConstantUImm10_0, // user defined class 'ConstantUImm10AsmOperandClass' 2089 MCK_SImm10Lsl1, // user defined class 'ConstantSImm10Lsl1AsmOperandClass' 2090 MCK_ConstantSImm11_0, // user defined class 'ConstantSImm11AsmOperandClass' 2091 MCK_SImm10Lsl2, // user defined class 'ConstantSImm10Lsl2AsmOperandClass' 2092 MCK_SImm10Lsl3, // user defined class 'ConstantSImm10Lsl3AsmOperandClass' 2093 MCK_SImm16, // user defined class 'SImm16AsmOperandClass' 2094 MCK_SImm16_Relaxed, // user defined class 'SImm16RelaxedAsmOperandClass' 2095 MCK_UImm16_AltRelaxed, // user defined class 'UImm16AltRelaxedAsmOperandClass' 2096 MCK_UImm16, // user defined class 'UImm16AsmOperandClass' 2097 MCK_SImm19Lsl2, // user defined class 'ConstantSImm19Lsl2AsmOperandClass' 2098 MCK_UImm16_Relaxed, // user defined class 'UImm16RelaxedAsmOperandClass' 2099 MCK_ConstantUImm20_0, // user defined class 'ConstantUImm20AsmOperandClass' 2100 MCK_ConstantUImm26_0, // user defined class 'ConstantUImm26AsmOperandClass' 2101 MCK_SImm32, // user defined class 'SImm32AsmOperandClass' 2102 MCK_SImm32_Relaxed, // user defined class 'SImm32RelaxedAsmOperandClass' 2103 MCK_UImm32_Coerced, // user defined class 'UImm32CoercedAsmOperandClass' 2104 NumMatchClassKinds 2105}; 2106 2107} // end anonymous namespace 2108 2109static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) { 2110 return MCTargetAsmParser::Match_InvalidOperand; 2111} 2112 2113static MatchClassKind matchTokenString(StringRef Name) { 2114 switch (Name.size()) { 2115 default: break; 2116 case 1: // 6 strings to match. 2117 switch (Name[0]) { 2118 default: break; 2119 case '#': // 1 string to match. 2120 return MCK__HASH_; // "#" 2121 case '(': // 1 string to match. 2122 return MCK__40_; // "(" 2123 case ')': // 1 string to match. 2124 return MCK__41_; // ")" 2125 case '0': // 1 string to match. 2126 return MCK_0; // "0" 2127 case '[': // 1 string to match. 2128 return MCK__91_; // "[" 2129 case ']': // 1 string to match. 2130 return MCK__93_; // "]" 2131 } 2132 break; 2133 case 2: // 1 string to match. 2134 if (memcmp(Name.data()+0, "16", 2) != 0) 2135 break; 2136 return MCK_16; // "16" 2137 case 3: // 1 string to match. 2138 if (memcmp(Name.data()+0, "bit", 3) != 0) 2139 break; 2140 return MCK_bit; // "bit" 2141 case 4: // 1 string to match. 2142 if (memcmp(Name.data()+0, "inst", 4) != 0) 2143 break; 2144 return MCK_inst; // "inst" 2145 } 2146 return InvalidMatchClass; 2147} 2148 2149/// isSubclass - Compute whether \p A is a subclass of \p B. 2150static bool isSubclass(MatchClassKind A, MatchClassKind B) { 2151 if (A == B) 2152 return true; 2153 2154 switch (A) { 2155 default: 2156 return false; 2157 2158 case MCK_Reg37: 2159 switch (B) { 2160 default: return false; 2161 case MCK_Reg24: return true; 2162 case MCK_GPR64: return true; 2163 } 2164 2165 case MCK_Reg19: 2166 switch (B) { 2167 default: return false; 2168 case MCK_Reg23: return true; 2169 case MCK_Reg22: return true; 2170 case MCK_Reg21: return true; 2171 case MCK_GPR64: return true; 2172 } 2173 2174 case MCK_ACC64: 2175 return B == MCK_ACC64DSP; 2176 2177 case MCK_CPURAReg: 2178 switch (B) { 2179 default: return false; 2180 case MCK_GPR32NONZERO: return true; 2181 case MCK_DSPR: return true; 2182 } 2183 2184 case MCK_CPUSPReg: 2185 switch (B) { 2186 default: return false; 2187 case MCK_CPU16RegsPlusSP: return true; 2188 case MCK_GPR32NONZERO: return true; 2189 case MCK_DSPR: return true; 2190 } 2191 2192 case MCK_GP32: 2193 switch (B) { 2194 default: return false; 2195 case MCK_GPR32NONZERO: return true; 2196 case MCK_DSPR: return true; 2197 } 2198 2199 case MCK_GP64: 2200 switch (B) { 2201 default: return false; 2202 case MCK_Reg24: return true; 2203 case MCK_GPR64: return true; 2204 } 2205 2206 case MCK_GPR32ZERO: 2207 switch (B) { 2208 default: return false; 2209 case MCK_Reg4: return true; 2210 case MCK_GPRMM16MoveP: return true; 2211 case MCK_GPRMM16Zero: return true; 2212 case MCK_DSPR: return true; 2213 } 2214 2215 case MCK_HI32: 2216 return B == MCK_HI32DSP; 2217 2218 case MCK_LO32: 2219 return B == MCK_LO32DSP; 2220 2221 case MCK_SP64: 2222 switch (B) { 2223 default: return false; 2224 case MCK_Reg26: return true; 2225 case MCK_Reg24: return true; 2226 case MCK_GPR64: return true; 2227 } 2228 2229 case MCK_Reg32: 2230 switch (B) { 2231 default: return false; 2232 case MCK_Reg33: return true; 2233 case MCK_Reg31: return true; 2234 case MCK_Reg34: return true; 2235 case MCK_Reg27: return true; 2236 case MCK_Reg25: return true; 2237 case MCK_Reg21: return true; 2238 case MCK_Reg26: return true; 2239 case MCK_Reg24: return true; 2240 case MCK_GPR64: return true; 2241 } 2242 2243 case MCK_Reg13: 2244 switch (B) { 2245 default: return false; 2246 case MCK_Reg14: return true; 2247 case MCK_GPRMM16MovePPairFirst: return true; 2248 case MCK_GPRMM16MovePPairSecond: return true; 2249 case MCK_Reg8: return true; 2250 case MCK_CPU16Regs: return true; 2251 case MCK_GPRMM16Zero: return true; 2252 case MCK_CPU16RegsPlusSP: return true; 2253 case MCK_GPR32NONZERO: return true; 2254 case MCK_DSPR: return true; 2255 } 2256 2257 case MCK_Reg33: 2258 switch (B) { 2259 default: return false; 2260 case MCK_Reg34: return true; 2261 case MCK_Reg27: return true; 2262 case MCK_Reg25: return true; 2263 case MCK_Reg21: return true; 2264 case MCK_Reg26: return true; 2265 case MCK_Reg24: return true; 2266 case MCK_GPR64: return true; 2267 } 2268 2269 case MCK_Reg31: 2270 switch (B) { 2271 default: return false; 2272 case MCK_Reg27: return true; 2273 case MCK_Reg25: return true; 2274 case MCK_Reg21: return true; 2275 case MCK_Reg26: return true; 2276 case MCK_Reg24: return true; 2277 case MCK_GPR64: return true; 2278 } 2279 2280 case MCK_Reg30: 2281 switch (B) { 2282 default: return false; 2283 case MCK_Reg28: return true; 2284 case MCK_Reg23: return true; 2285 case MCK_Reg29: return true; 2286 case MCK_Reg27: return true; 2287 case MCK_Reg25: return true; 2288 case MCK_Reg22: return true; 2289 case MCK_Reg21: return true; 2290 case MCK_Reg26: return true; 2291 case MCK_Reg24: return true; 2292 case MCK_GPR64: return true; 2293 } 2294 2295 case MCK_Reg14: 2296 switch (B) { 2297 default: return false; 2298 case MCK_GPRMM16MovePPairSecond: return true; 2299 case MCK_Reg8: return true; 2300 case MCK_CPU16Regs: return true; 2301 case MCK_GPRMM16Zero: return true; 2302 case MCK_CPU16RegsPlusSP: return true; 2303 case MCK_GPR32NONZERO: return true; 2304 case MCK_DSPR: return true; 2305 } 2306 2307 case MCK_Reg11: 2308 switch (B) { 2309 default: return false; 2310 case MCK_Reg9: return true; 2311 case MCK_Reg4: return true; 2312 case MCK_Reg10: return true; 2313 case MCK_Reg8: return true; 2314 case MCK_CPU16Regs: return true; 2315 case MCK_GPRMM16MoveP: return true; 2316 case MCK_GPRMM16Zero: return true; 2317 case MCK_CPU16RegsPlusSP: return true; 2318 case MCK_GPR32NONZERO: return true; 2319 case MCK_DSPR: return true; 2320 } 2321 2322 case MCK_GPRMM16MovePPairFirst: 2323 switch (B) { 2324 default: return false; 2325 case MCK_Reg8: return true; 2326 case MCK_CPU16Regs: return true; 2327 case MCK_GPRMM16Zero: return true; 2328 case MCK_CPU16RegsPlusSP: return true; 2329 case MCK_GPR32NONZERO: return true; 2330 case MCK_DSPR: return true; 2331 } 2332 2333 case MCK_Reg28: 2334 switch (B) { 2335 default: return false; 2336 case MCK_Reg29: return true; 2337 case MCK_Reg25: return true; 2338 case MCK_Reg22: return true; 2339 case MCK_Reg26: return true; 2340 case MCK_Reg24: return true; 2341 case MCK_GPR64: return true; 2342 } 2343 2344 case MCK_Reg23: 2345 switch (B) { 2346 default: return false; 2347 case MCK_Reg22: return true; 2348 case MCK_Reg21: return true; 2349 case MCK_GPR64: return true; 2350 } 2351 2352 case MCK_Reg9: 2353 switch (B) { 2354 default: return false; 2355 case MCK_Reg10: return true; 2356 case MCK_CPU16Regs: return true; 2357 case MCK_GPRMM16MoveP: return true; 2358 case MCK_CPU16RegsPlusSP: return true; 2359 case MCK_GPR32NONZERO: return true; 2360 case MCK_DSPR: return true; 2361 } 2362 2363 case MCK_Reg4: 2364 switch (B) { 2365 default: return false; 2366 case MCK_GPRMM16MoveP: return true; 2367 case MCK_GPRMM16Zero: return true; 2368 case MCK_DSPR: return true; 2369 } 2370 2371 case MCK_Reg34: 2372 switch (B) { 2373 default: return false; 2374 case MCK_Reg24: return true; 2375 case MCK_GPR64: return true; 2376 } 2377 2378 case MCK_GPRMM16MovePPairSecond: 2379 switch (B) { 2380 default: return false; 2381 case MCK_GPR32NONZERO: return true; 2382 case MCK_DSPR: return true; 2383 } 2384 2385 case MCK_Reg29: 2386 switch (B) { 2387 default: return false; 2388 case MCK_Reg22: return true; 2389 case MCK_Reg24: return true; 2390 case MCK_GPR64: return true; 2391 } 2392 2393 case MCK_Reg27: 2394 switch (B) { 2395 default: return false; 2396 case MCK_Reg25: return true; 2397 case MCK_Reg21: return true; 2398 case MCK_Reg26: return true; 2399 case MCK_Reg24: return true; 2400 case MCK_GPR64: return true; 2401 } 2402 2403 case MCK_Reg10: 2404 switch (B) { 2405 default: return false; 2406 case MCK_GPRMM16MoveP: return true; 2407 case MCK_GPR32NONZERO: return true; 2408 case MCK_DSPR: return true; 2409 } 2410 2411 case MCK_Reg8: 2412 switch (B) { 2413 default: return false; 2414 case MCK_CPU16Regs: return true; 2415 case MCK_GPRMM16Zero: return true; 2416 case MCK_CPU16RegsPlusSP: return true; 2417 case MCK_GPR32NONZERO: return true; 2418 case MCK_DSPR: return true; 2419 } 2420 2421 case MCK_Reg25: 2422 switch (B) { 2423 default: return false; 2424 case MCK_Reg26: return true; 2425 case MCK_Reg24: return true; 2426 case MCK_GPR64: return true; 2427 } 2428 2429 case MCK_Reg22: 2430 return B == MCK_GPR64; 2431 2432 case MCK_Reg21: 2433 return B == MCK_GPR64; 2434 2435 case MCK_CPU16Regs: 2436 switch (B) { 2437 default: return false; 2438 case MCK_CPU16RegsPlusSP: return true; 2439 case MCK_GPR32NONZERO: return true; 2440 case MCK_DSPR: return true; 2441 } 2442 2443 case MCK_GPRMM16MoveP: 2444 return B == MCK_DSPR; 2445 2446 case MCK_GPRMM16Zero: 2447 return B == MCK_DSPR; 2448 2449 case MCK_Reg26: 2450 switch (B) { 2451 default: return false; 2452 case MCK_Reg24: return true; 2453 case MCK_GPR64: return true; 2454 } 2455 2456 case MCK_CPU16RegsPlusSP: 2457 switch (B) { 2458 default: return false; 2459 case MCK_GPR32NONZERO: return true; 2460 case MCK_DSPR: return true; 2461 } 2462 2463 case MCK_MSA128WEvens: 2464 return B == MCK_MSA128F16; 2465 2466 case MCK_Reg24: 2467 return B == MCK_GPR64; 2468 2469 case MCK_GPR32NONZERO: 2470 return B == MCK_DSPR; 2471 2472 case MCK_MemOffsetSimmPtr: 2473 return B == MCK_Mem; 2474 2475 case MCK_MemOffsetUimm4: 2476 return B == MCK_Mem; 2477 2478 case MCK_MemOffsetSimm9_0: 2479 return B == MCK_Mem; 2480 2481 case MCK_MemOffsetSimm10_0: 2482 return B == MCK_Mem; 2483 2484 case MCK_MemOffsetSimm11_0: 2485 return B == MCK_Mem; 2486 2487 case MCK_MemOffsetSimm12_0: 2488 return B == MCK_Mem; 2489 2490 case MCK_MemOffsetSimm16_0: 2491 return B == MCK_Mem; 2492 2493 case MCK_MemOffsetSimm10_1: 2494 return B == MCK_Mem; 2495 2496 case MCK_MemOffsetSimm10_2: 2497 return B == MCK_Mem; 2498 2499 case MCK_MemOffsetSimm10_3: 2500 return B == MCK_Mem; 2501 2502 case MCK_ConstantImmz: 2503 switch (B) { 2504 default: return false; 2505 case MCK_ConstantUImm1_0: return true; 2506 case MCK_ConstantUImm2_0: return true; 2507 case MCK_ConstantUImm3_0: return true; 2508 case MCK_ConstantSImm4_0: return true; 2509 case MCK_ConstantUImm4_0: return true; 2510 case MCK_ConstantSImm5_0: return true; 2511 case MCK_ConstantUImm5_0: return true; 2512 case MCK_ConstantUImm5_1: return true; 2513 case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; 2514 case MCK_ConstantUImm5_32_Norm: return true; 2515 case MCK_ConstantUImm5_32: return true; 2516 case MCK_ConstantUImm5_0_Report_UImm6: return true; 2517 case MCK_ConstantUImm5_33: return true; 2518 case MCK_ConstantUImmRange2_64: return true; 2519 case MCK_UImm5Lsl2: return true; 2520 case MCK_ConstantSImm6_0: return true; 2521 case MCK_ConstantUImm6_0: return true; 2522 case MCK_UImm6Lsl2: return true; 2523 case MCK_ConstantUImm7_0: return true; 2524 case MCK_UImm7_N1: return true; 2525 case MCK_ConstantUImm8_0: return true; 2526 case MCK_SImm7Lsl2: return true; 2527 case MCK_ConstantSImm9_0: return true; 2528 case MCK_ConstantSImm10_0: return true; 2529 case MCK_ConstantUImm10_0: return true; 2530 case MCK_SImm10Lsl1: return true; 2531 case MCK_ConstantSImm11_0: return true; 2532 case MCK_SImm10Lsl2: return true; 2533 case MCK_SImm10Lsl3: return true; 2534 case MCK_SImm16: return true; 2535 case MCK_SImm16_Relaxed: return true; 2536 case MCK_UImm16_Relaxed: return true; 2537 case MCK_ConstantUImm20_0: return true; 2538 case MCK_ConstantUImm26_0: return true; 2539 case MCK_SImm32: return true; 2540 case MCK_SImm32_Relaxed: return true; 2541 case MCK_UImm32_Coerced: return true; 2542 } 2543 2544 case MCK_ConstantUImm1_0: 2545 switch (B) { 2546 default: return false; 2547 case MCK_ConstantUImm2_0: return true; 2548 case MCK_ConstantUImm3_0: return true; 2549 case MCK_ConstantSImm4_0: return true; 2550 case MCK_ConstantUImm4_0: return true; 2551 case MCK_ConstantSImm5_0: return true; 2552 case MCK_ConstantUImm5_0: return true; 2553 case MCK_ConstantUImm5_1: return true; 2554 case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; 2555 case MCK_ConstantUImm5_32_Norm: return true; 2556 case MCK_ConstantUImm5_32: return true; 2557 case MCK_ConstantUImm5_0_Report_UImm6: return true; 2558 case MCK_ConstantUImm5_33: return true; 2559 case MCK_ConstantUImmRange2_64: return true; 2560 case MCK_UImm5Lsl2: return true; 2561 case MCK_ConstantSImm6_0: return true; 2562 case MCK_ConstantUImm6_0: return true; 2563 case MCK_UImm6Lsl2: return true; 2564 case MCK_ConstantUImm7_0: return true; 2565 case MCK_UImm7_N1: return true; 2566 case MCK_ConstantUImm8_0: return true; 2567 case MCK_SImm7Lsl2: return true; 2568 case MCK_ConstantSImm9_0: return true; 2569 case MCK_ConstantSImm10_0: return true; 2570 case MCK_ConstantUImm10_0: return true; 2571 case MCK_SImm10Lsl1: return true; 2572 case MCK_ConstantSImm11_0: return true; 2573 case MCK_SImm10Lsl2: return true; 2574 case MCK_SImm10Lsl3: return true; 2575 case MCK_SImm16: return true; 2576 case MCK_SImm16_Relaxed: return true; 2577 case MCK_UImm16_Relaxed: return true; 2578 case MCK_ConstantUImm20_0: return true; 2579 case MCK_ConstantUImm26_0: return true; 2580 case MCK_SImm32: return true; 2581 case MCK_SImm32_Relaxed: return true; 2582 case MCK_UImm32_Coerced: return true; 2583 } 2584 2585 case MCK_ConstantUImm2_0: 2586 switch (B) { 2587 default: return false; 2588 case MCK_ConstantUImm3_0: return true; 2589 case MCK_ConstantSImm4_0: return true; 2590 case MCK_ConstantUImm4_0: return true; 2591 case MCK_ConstantSImm5_0: return true; 2592 case MCK_ConstantUImm5_0: return true; 2593 case MCK_ConstantUImm5_1: return true; 2594 case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; 2595 case MCK_ConstantUImm5_32_Norm: return true; 2596 case MCK_ConstantUImm5_32: return true; 2597 case MCK_ConstantUImm5_0_Report_UImm6: return true; 2598 case MCK_ConstantUImm5_33: return true; 2599 case MCK_ConstantUImmRange2_64: return true; 2600 case MCK_UImm5Lsl2: return true; 2601 case MCK_ConstantSImm6_0: return true; 2602 case MCK_ConstantUImm6_0: return true; 2603 case MCK_UImm6Lsl2: return true; 2604 case MCK_ConstantUImm7_0: return true; 2605 case MCK_UImm7_N1: return true; 2606 case MCK_ConstantUImm8_0: return true; 2607 case MCK_SImm7Lsl2: return true; 2608 case MCK_ConstantSImm9_0: return true; 2609 case MCK_ConstantSImm10_0: return true; 2610 case MCK_ConstantUImm10_0: return true; 2611 case MCK_SImm10Lsl1: return true; 2612 case MCK_ConstantSImm11_0: return true; 2613 case MCK_SImm10Lsl2: return true; 2614 case MCK_SImm10Lsl3: return true; 2615 case MCK_SImm16: return true; 2616 case MCK_SImm16_Relaxed: return true; 2617 case MCK_UImm16_Relaxed: return true; 2618 case MCK_ConstantUImm20_0: return true; 2619 case MCK_ConstantUImm26_0: return true; 2620 case MCK_SImm32: return true; 2621 case MCK_SImm32_Relaxed: return true; 2622 case MCK_UImm32_Coerced: return true; 2623 } 2624 2625 case MCK_ConstantUImm2_1: 2626 switch (B) { 2627 default: return false; 2628 case MCK_ConstantUImm3_0: return true; 2629 case MCK_ConstantSImm4_0: return true; 2630 case MCK_ConstantUImm4_0: return true; 2631 case MCK_ConstantSImm5_0: return true; 2632 case MCK_ConstantUImm5_0: return true; 2633 case MCK_ConstantUImm5_1: return true; 2634 case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; 2635 case MCK_ConstantUImm5_32_Norm: return true; 2636 case MCK_ConstantUImm5_32: return true; 2637 case MCK_ConstantUImm5_0_Report_UImm6: return true; 2638 case MCK_ConstantUImm5_33: return true; 2639 case MCK_ConstantUImmRange2_64: return true; 2640 case MCK_UImm5Lsl2: return true; 2641 case MCK_ConstantSImm6_0: return true; 2642 case MCK_ConstantUImm6_0: return true; 2643 case MCK_UImm6Lsl2: return true; 2644 case MCK_ConstantUImm7_0: return true; 2645 case MCK_UImm7_N1: return true; 2646 case MCK_ConstantUImm8_0: return true; 2647 case MCK_SImm7Lsl2: return true; 2648 case MCK_ConstantSImm9_0: return true; 2649 case MCK_ConstantSImm10_0: return true; 2650 case MCK_ConstantUImm10_0: return true; 2651 case MCK_SImm10Lsl1: return true; 2652 case MCK_ConstantSImm11_0: return true; 2653 case MCK_SImm10Lsl2: return true; 2654 case MCK_SImm10Lsl3: return true; 2655 case MCK_SImm16: return true; 2656 case MCK_SImm16_Relaxed: return true; 2657 case MCK_UImm16_Relaxed: return true; 2658 case MCK_ConstantUImm20_0: return true; 2659 case MCK_ConstantUImm26_0: return true; 2660 case MCK_SImm32: return true; 2661 case MCK_SImm32_Relaxed: return true; 2662 case MCK_UImm32_Coerced: return true; 2663 } 2664 2665 case MCK_ConstantUImm3_0: 2666 switch (B) { 2667 default: return false; 2668 case MCK_ConstantSImm4_0: return true; 2669 case MCK_ConstantUImm4_0: return true; 2670 case MCK_ConstantSImm5_0: return true; 2671 case MCK_ConstantUImm5_0: return true; 2672 case MCK_ConstantUImm5_1: return true; 2673 case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; 2674 case MCK_ConstantUImm5_32_Norm: return true; 2675 case MCK_ConstantUImm5_32: return true; 2676 case MCK_ConstantUImm5_0_Report_UImm6: return true; 2677 case MCK_ConstantUImm5_33: return true; 2678 case MCK_ConstantUImmRange2_64: return true; 2679 case MCK_UImm5Lsl2: return true; 2680 case MCK_ConstantSImm6_0: return true; 2681 case MCK_ConstantUImm6_0: return true; 2682 case MCK_UImm6Lsl2: return true; 2683 case MCK_ConstantUImm7_0: return true; 2684 case MCK_UImm7_N1: return true; 2685 case MCK_ConstantUImm8_0: return true; 2686 case MCK_SImm7Lsl2: return true; 2687 case MCK_ConstantSImm9_0: return true; 2688 case MCK_ConstantSImm10_0: return true; 2689 case MCK_ConstantUImm10_0: return true; 2690 case MCK_SImm10Lsl1: return true; 2691 case MCK_ConstantSImm11_0: return true; 2692 case MCK_SImm10Lsl2: return true; 2693 case MCK_SImm10Lsl3: return true; 2694 case MCK_SImm16: return true; 2695 case MCK_SImm16_Relaxed: return true; 2696 case MCK_UImm16_Relaxed: return true; 2697 case MCK_ConstantUImm20_0: return true; 2698 case MCK_ConstantUImm26_0: return true; 2699 case MCK_SImm32: return true; 2700 case MCK_SImm32_Relaxed: return true; 2701 case MCK_UImm32_Coerced: return true; 2702 } 2703 2704 case MCK_ConstantSImm4_0: 2705 switch (B) { 2706 default: return false; 2707 case MCK_ConstantUImm4_0: return true; 2708 case MCK_ConstantSImm5_0: return true; 2709 case MCK_ConstantUImm5_0: return true; 2710 case MCK_ConstantUImm5_1: return true; 2711 case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; 2712 case MCK_ConstantUImm5_32_Norm: return true; 2713 case MCK_ConstantUImm5_32: return true; 2714 case MCK_ConstantUImm5_0_Report_UImm6: return true; 2715 case MCK_ConstantUImm5_33: return true; 2716 case MCK_ConstantUImmRange2_64: return true; 2717 case MCK_UImm5Lsl2: return true; 2718 case MCK_ConstantSImm6_0: return true; 2719 case MCK_ConstantUImm6_0: return true; 2720 case MCK_UImm6Lsl2: return true; 2721 case MCK_ConstantUImm7_0: return true; 2722 case MCK_UImm7_N1: return true; 2723 case MCK_ConstantUImm8_0: return true; 2724 case MCK_SImm7Lsl2: return true; 2725 case MCK_ConstantSImm9_0: return true; 2726 case MCK_ConstantSImm10_0: return true; 2727 case MCK_ConstantUImm10_0: return true; 2728 case MCK_SImm10Lsl1: return true; 2729 case MCK_ConstantSImm11_0: return true; 2730 case MCK_SImm10Lsl2: return true; 2731 case MCK_SImm10Lsl3: return true; 2732 case MCK_SImm16: return true; 2733 case MCK_SImm16_Relaxed: return true; 2734 case MCK_UImm16_Relaxed: return true; 2735 case MCK_ConstantUImm20_0: return true; 2736 case MCK_ConstantUImm26_0: return true; 2737 case MCK_SImm32: return true; 2738 case MCK_SImm32_Relaxed: return true; 2739 case MCK_UImm32_Coerced: return true; 2740 } 2741 2742 case MCK_ConstantUImm4_0: 2743 switch (B) { 2744 default: return false; 2745 case MCK_ConstantSImm5_0: return true; 2746 case MCK_ConstantUImm5_0: return true; 2747 case MCK_ConstantUImm5_1: return true; 2748 case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; 2749 case MCK_ConstantUImm5_32_Norm: return true; 2750 case MCK_ConstantUImm5_32: return true; 2751 case MCK_ConstantUImm5_0_Report_UImm6: return true; 2752 case MCK_ConstantUImm5_33: return true; 2753 case MCK_ConstantUImmRange2_64: return true; 2754 case MCK_UImm5Lsl2: return true; 2755 case MCK_ConstantSImm6_0: return true; 2756 case MCK_ConstantUImm6_0: return true; 2757 case MCK_UImm6Lsl2: return true; 2758 case MCK_ConstantUImm7_0: return true; 2759 case MCK_UImm7_N1: return true; 2760 case MCK_ConstantUImm8_0: return true; 2761 case MCK_SImm7Lsl2: return true; 2762 case MCK_ConstantSImm9_0: return true; 2763 case MCK_ConstantSImm10_0: return true; 2764 case MCK_ConstantUImm10_0: return true; 2765 case MCK_SImm10Lsl1: return true; 2766 case MCK_ConstantSImm11_0: return true; 2767 case MCK_SImm10Lsl2: return true; 2768 case MCK_SImm10Lsl3: return true; 2769 case MCK_SImm16: return true; 2770 case MCK_SImm16_Relaxed: return true; 2771 case MCK_UImm16_Relaxed: return true; 2772 case MCK_ConstantUImm20_0: return true; 2773 case MCK_ConstantUImm26_0: return true; 2774 case MCK_SImm32: return true; 2775 case MCK_SImm32_Relaxed: return true; 2776 case MCK_UImm32_Coerced: return true; 2777 } 2778 2779 case MCK_ConstantSImm5_0: 2780 switch (B) { 2781 default: return false; 2782 case MCK_ConstantUImm5_0: return true; 2783 case MCK_ConstantUImm5_1: return true; 2784 case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; 2785 case MCK_ConstantUImm5_32_Norm: return true; 2786 case MCK_ConstantUImm5_32: return true; 2787 case MCK_ConstantUImm5_0_Report_UImm6: return true; 2788 case MCK_ConstantUImm5_33: return true; 2789 case MCK_ConstantUImmRange2_64: return true; 2790 case MCK_UImm5Lsl2: return true; 2791 case MCK_ConstantSImm6_0: return true; 2792 case MCK_ConstantUImm6_0: return true; 2793 case MCK_UImm6Lsl2: return true; 2794 case MCK_ConstantUImm7_0: return true; 2795 case MCK_UImm7_N1: return true; 2796 case MCK_ConstantUImm8_0: return true; 2797 case MCK_SImm7Lsl2: return true; 2798 case MCK_ConstantSImm9_0: return true; 2799 case MCK_ConstantSImm10_0: return true; 2800 case MCK_ConstantUImm10_0: return true; 2801 case MCK_SImm10Lsl1: return true; 2802 case MCK_ConstantSImm11_0: return true; 2803 case MCK_SImm10Lsl2: return true; 2804 case MCK_SImm10Lsl3: return true; 2805 case MCK_SImm16: return true; 2806 case MCK_SImm16_Relaxed: return true; 2807 case MCK_UImm16_Relaxed: return true; 2808 case MCK_ConstantUImm20_0: return true; 2809 case MCK_ConstantUImm26_0: return true; 2810 case MCK_SImm32: return true; 2811 case MCK_SImm32_Relaxed: return true; 2812 case MCK_UImm32_Coerced: return true; 2813 } 2814 2815 case MCK_ConstantUImm5_0: 2816 switch (B) { 2817 default: return false; 2818 case MCK_ConstantUImm5_1: return true; 2819 case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; 2820 case MCK_ConstantUImm5_32_Norm: return true; 2821 case MCK_ConstantUImm5_32: return true; 2822 case MCK_ConstantUImm5_0_Report_UImm6: return true; 2823 case MCK_ConstantUImm5_33: return true; 2824 case MCK_ConstantUImmRange2_64: return true; 2825 case MCK_UImm5Lsl2: return true; 2826 case MCK_ConstantSImm6_0: return true; 2827 case MCK_ConstantUImm6_0: return true; 2828 case MCK_UImm6Lsl2: return true; 2829 case MCK_ConstantUImm7_0: return true; 2830 case MCK_UImm7_N1: return true; 2831 case MCK_ConstantUImm8_0: return true; 2832 case MCK_SImm7Lsl2: return true; 2833 case MCK_ConstantSImm9_0: return true; 2834 case MCK_ConstantSImm10_0: return true; 2835 case MCK_ConstantUImm10_0: return true; 2836 case MCK_SImm10Lsl1: return true; 2837 case MCK_ConstantSImm11_0: return true; 2838 case MCK_SImm10Lsl2: return true; 2839 case MCK_SImm10Lsl3: return true; 2840 case MCK_SImm16: return true; 2841 case MCK_SImm16_Relaxed: return true; 2842 case MCK_UImm16_Relaxed: return true; 2843 case MCK_ConstantUImm20_0: return true; 2844 case MCK_ConstantUImm26_0: return true; 2845 case MCK_SImm32: return true; 2846 case MCK_SImm32_Relaxed: return true; 2847 case MCK_UImm32_Coerced: return true; 2848 } 2849 2850 case MCK_ConstantUImm5_1: 2851 switch (B) { 2852 default: return false; 2853 case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; 2854 case MCK_ConstantUImm5_32_Norm: return true; 2855 case MCK_ConstantUImm5_32: return true; 2856 case MCK_ConstantUImm5_0_Report_UImm6: return true; 2857 case MCK_ConstantUImm5_33: return true; 2858 case MCK_ConstantUImmRange2_64: return true; 2859 case MCK_UImm5Lsl2: return true; 2860 case MCK_ConstantSImm6_0: return true; 2861 case MCK_ConstantUImm6_0: return true; 2862 case MCK_UImm6Lsl2: return true; 2863 case MCK_ConstantUImm7_0: return true; 2864 case MCK_UImm7_N1: return true; 2865 case MCK_ConstantUImm8_0: return true; 2866 case MCK_SImm7Lsl2: return true; 2867 case MCK_ConstantSImm9_0: return true; 2868 case MCK_ConstantSImm10_0: return true; 2869 case MCK_ConstantUImm10_0: return true; 2870 case MCK_SImm10Lsl1: return true; 2871 case MCK_ConstantSImm11_0: return true; 2872 case MCK_SImm10Lsl2: return true; 2873 case MCK_SImm10Lsl3: return true; 2874 case MCK_SImm16: return true; 2875 case MCK_SImm16_Relaxed: return true; 2876 case MCK_UImm16_Relaxed: return true; 2877 case MCK_ConstantUImm20_0: return true; 2878 case MCK_ConstantUImm26_0: return true; 2879 case MCK_SImm32: return true; 2880 case MCK_SImm32_Relaxed: return true; 2881 case MCK_UImm32_Coerced: return true; 2882 } 2883 2884 case MCK_ConstantUImm5_Plus1_Report_UImm6: 2885 switch (B) { 2886 default: return false; 2887 case MCK_ConstantUImm5_32_Norm: return true; 2888 case MCK_ConstantUImm5_32: return true; 2889 case MCK_ConstantUImm5_0_Report_UImm6: return true; 2890 case MCK_ConstantUImm5_33: return true; 2891 case MCK_ConstantUImmRange2_64: return true; 2892 case MCK_UImm5Lsl2: return true; 2893 case MCK_ConstantSImm6_0: return true; 2894 case MCK_ConstantUImm6_0: return true; 2895 case MCK_UImm6Lsl2: return true; 2896 case MCK_ConstantUImm7_0: return true; 2897 case MCK_UImm7_N1: return true; 2898 case MCK_ConstantUImm8_0: return true; 2899 case MCK_SImm7Lsl2: return true; 2900 case MCK_ConstantSImm9_0: return true; 2901 case MCK_ConstantSImm10_0: return true; 2902 case MCK_ConstantUImm10_0: return true; 2903 case MCK_SImm10Lsl1: return true; 2904 case MCK_ConstantSImm11_0: return true; 2905 case MCK_SImm10Lsl2: return true; 2906 case MCK_SImm10Lsl3: return true; 2907 case MCK_SImm16: return true; 2908 case MCK_SImm16_Relaxed: return true; 2909 case MCK_UImm16_Relaxed: return true; 2910 case MCK_ConstantUImm20_0: return true; 2911 case MCK_ConstantUImm26_0: return true; 2912 case MCK_SImm32: return true; 2913 case MCK_SImm32_Relaxed: return true; 2914 case MCK_UImm32_Coerced: return true; 2915 } 2916 2917 case MCK_ConstantUImm5_32_Norm: 2918 switch (B) { 2919 default: return false; 2920 case MCK_ConstantUImm5_32: return true; 2921 case MCK_ConstantUImm5_0_Report_UImm6: return true; 2922 case MCK_ConstantUImm5_33: return true; 2923 case MCK_ConstantUImmRange2_64: return true; 2924 case MCK_UImm5Lsl2: return true; 2925 case MCK_ConstantSImm6_0: return true; 2926 case MCK_ConstantUImm6_0: return true; 2927 case MCK_UImm6Lsl2: return true; 2928 case MCK_ConstantUImm7_0: return true; 2929 case MCK_UImm7_N1: return true; 2930 case MCK_ConstantUImm8_0: return true; 2931 case MCK_SImm7Lsl2: return true; 2932 case MCK_ConstantSImm9_0: return true; 2933 case MCK_ConstantSImm10_0: return true; 2934 case MCK_ConstantUImm10_0: return true; 2935 case MCK_SImm10Lsl1: return true; 2936 case MCK_ConstantSImm11_0: return true; 2937 case MCK_SImm10Lsl2: return true; 2938 case MCK_SImm10Lsl3: return true; 2939 case MCK_SImm16: return true; 2940 case MCK_SImm16_Relaxed: return true; 2941 case MCK_UImm16_Relaxed: return true; 2942 case MCK_ConstantUImm20_0: return true; 2943 case MCK_ConstantUImm26_0: return true; 2944 case MCK_SImm32: return true; 2945 case MCK_SImm32_Relaxed: return true; 2946 case MCK_UImm32_Coerced: return true; 2947 } 2948 2949 case MCK_ConstantUImm5_32: 2950 switch (B) { 2951 default: return false; 2952 case MCK_ConstantUImm5_0_Report_UImm6: return true; 2953 case MCK_ConstantUImm5_33: return true; 2954 case MCK_ConstantUImmRange2_64: return true; 2955 case MCK_UImm5Lsl2: return true; 2956 case MCK_ConstantSImm6_0: return true; 2957 case MCK_ConstantUImm6_0: return true; 2958 case MCK_UImm6Lsl2: return true; 2959 case MCK_ConstantUImm7_0: return true; 2960 case MCK_UImm7_N1: return true; 2961 case MCK_ConstantUImm8_0: return true; 2962 case MCK_SImm7Lsl2: return true; 2963 case MCK_ConstantSImm9_0: return true; 2964 case MCK_ConstantSImm10_0: return true; 2965 case MCK_ConstantUImm10_0: return true; 2966 case MCK_SImm10Lsl1: return true; 2967 case MCK_ConstantSImm11_0: return true; 2968 case MCK_SImm10Lsl2: return true; 2969 case MCK_SImm10Lsl3: return true; 2970 case MCK_SImm16: return true; 2971 case MCK_SImm16_Relaxed: return true; 2972 case MCK_UImm16_Relaxed: return true; 2973 case MCK_ConstantUImm20_0: return true; 2974 case MCK_ConstantUImm26_0: return true; 2975 case MCK_SImm32: return true; 2976 case MCK_SImm32_Relaxed: return true; 2977 case MCK_UImm32_Coerced: return true; 2978 } 2979 2980 case MCK_ConstantUImm5_0_Report_UImm6: 2981 switch (B) { 2982 default: return false; 2983 case MCK_ConstantUImm5_33: return true; 2984 case MCK_ConstantUImmRange2_64: return true; 2985 case MCK_UImm5Lsl2: return true; 2986 case MCK_ConstantSImm6_0: return true; 2987 case MCK_ConstantUImm6_0: return true; 2988 case MCK_UImm6Lsl2: return true; 2989 case MCK_ConstantUImm7_0: return true; 2990 case MCK_UImm7_N1: return true; 2991 case MCK_ConstantUImm8_0: return true; 2992 case MCK_SImm7Lsl2: return true; 2993 case MCK_ConstantSImm9_0: return true; 2994 case MCK_ConstantSImm10_0: return true; 2995 case MCK_ConstantUImm10_0: return true; 2996 case MCK_SImm10Lsl1: return true; 2997 case MCK_ConstantSImm11_0: return true; 2998 case MCK_SImm10Lsl2: return true; 2999 case MCK_SImm10Lsl3: return true; 3000 case MCK_SImm16: return true; 3001 case MCK_SImm16_Relaxed: return true; 3002 case MCK_UImm16_Relaxed: return true; 3003 case MCK_ConstantUImm20_0: return true; 3004 case MCK_ConstantUImm26_0: return true; 3005 case MCK_SImm32: return true; 3006 case MCK_SImm32_Relaxed: return true; 3007 case MCK_UImm32_Coerced: return true; 3008 } 3009 3010 case MCK_ConstantUImm5_33: 3011 switch (B) { 3012 default: return false; 3013 case MCK_ConstantUImmRange2_64: return true; 3014 case MCK_UImm5Lsl2: return true; 3015 case MCK_ConstantSImm6_0: return true; 3016 case MCK_ConstantUImm6_0: return true; 3017 case MCK_UImm6Lsl2: return true; 3018 case MCK_ConstantUImm7_0: return true; 3019 case MCK_UImm7_N1: return true; 3020 case MCK_ConstantUImm8_0: return true; 3021 case MCK_SImm7Lsl2: return true; 3022 case MCK_ConstantSImm9_0: return true; 3023 case MCK_ConstantSImm10_0: return true; 3024 case MCK_ConstantUImm10_0: return true; 3025 case MCK_SImm10Lsl1: return true; 3026 case MCK_ConstantSImm11_0: return true; 3027 case MCK_SImm10Lsl2: return true; 3028 case MCK_SImm10Lsl3: return true; 3029 case MCK_SImm16: return true; 3030 case MCK_SImm16_Relaxed: return true; 3031 case MCK_UImm16_Relaxed: return true; 3032 case MCK_ConstantUImm20_0: return true; 3033 case MCK_ConstantUImm26_0: return true; 3034 case MCK_SImm32: return true; 3035 case MCK_SImm32_Relaxed: return true; 3036 case MCK_UImm32_Coerced: return true; 3037 } 3038 3039 case MCK_ConstantUImmRange2_64: 3040 switch (B) { 3041 default: return false; 3042 case MCK_UImm5Lsl2: return true; 3043 case MCK_ConstantSImm6_0: return true; 3044 case MCK_ConstantUImm6_0: return true; 3045 case MCK_UImm6Lsl2: return true; 3046 case MCK_ConstantUImm7_0: return true; 3047 case MCK_UImm7_N1: return true; 3048 case MCK_ConstantUImm8_0: return true; 3049 case MCK_SImm7Lsl2: return true; 3050 case MCK_ConstantSImm9_0: return true; 3051 case MCK_ConstantSImm10_0: return true; 3052 case MCK_ConstantUImm10_0: return true; 3053 case MCK_SImm10Lsl1: return true; 3054 case MCK_ConstantSImm11_0: return true; 3055 case MCK_SImm10Lsl2: return true; 3056 case MCK_SImm10Lsl3: return true; 3057 case MCK_SImm16: return true; 3058 case MCK_SImm16_Relaxed: return true; 3059 case MCK_UImm16_Relaxed: return true; 3060 case MCK_ConstantUImm20_0: return true; 3061 case MCK_ConstantUImm26_0: return true; 3062 case MCK_SImm32: return true; 3063 case MCK_SImm32_Relaxed: return true; 3064 case MCK_UImm32_Coerced: return true; 3065 } 3066 3067 case MCK_UImm5Lsl2: 3068 switch (B) { 3069 default: return false; 3070 case MCK_ConstantSImm6_0: return true; 3071 case MCK_ConstantUImm6_0: return true; 3072 case MCK_UImm6Lsl2: return true; 3073 case MCK_ConstantUImm7_0: return true; 3074 case MCK_UImm7_N1: return true; 3075 case MCK_ConstantUImm8_0: return true; 3076 case MCK_SImm7Lsl2: return true; 3077 case MCK_ConstantSImm9_0: return true; 3078 case MCK_ConstantSImm10_0: return true; 3079 case MCK_ConstantUImm10_0: return true; 3080 case MCK_SImm10Lsl1: return true; 3081 case MCK_ConstantSImm11_0: return true; 3082 case MCK_SImm10Lsl2: return true; 3083 case MCK_SImm10Lsl3: return true; 3084 case MCK_SImm16: return true; 3085 case MCK_SImm16_Relaxed: return true; 3086 case MCK_UImm16_Relaxed: return true; 3087 case MCK_ConstantUImm20_0: return true; 3088 case MCK_ConstantUImm26_0: return true; 3089 case MCK_SImm32: return true; 3090 case MCK_SImm32_Relaxed: return true; 3091 case MCK_UImm32_Coerced: return true; 3092 } 3093 3094 case MCK_ConstantSImm6_0: 3095 switch (B) { 3096 default: return false; 3097 case MCK_ConstantUImm6_0: return true; 3098 case MCK_UImm6Lsl2: return true; 3099 case MCK_ConstantUImm7_0: return true; 3100 case MCK_UImm7_N1: return true; 3101 case MCK_ConstantUImm8_0: return true; 3102 case MCK_SImm7Lsl2: return true; 3103 case MCK_ConstantSImm9_0: return true; 3104 case MCK_ConstantSImm10_0: return true; 3105 case MCK_ConstantUImm10_0: return true; 3106 case MCK_SImm10Lsl1: return true; 3107 case MCK_ConstantSImm11_0: return true; 3108 case MCK_SImm10Lsl2: return true; 3109 case MCK_SImm10Lsl3: return true; 3110 case MCK_SImm16: return true; 3111 case MCK_SImm16_Relaxed: return true; 3112 case MCK_UImm16_Relaxed: return true; 3113 case MCK_ConstantUImm20_0: return true; 3114 case MCK_ConstantUImm26_0: return true; 3115 case MCK_SImm32: return true; 3116 case MCK_SImm32_Relaxed: return true; 3117 case MCK_UImm32_Coerced: return true; 3118 } 3119 3120 case MCK_ConstantUImm6_0: 3121 switch (B) { 3122 default: return false; 3123 case MCK_UImm6Lsl2: return true; 3124 case MCK_ConstantUImm7_0: return true; 3125 case MCK_UImm7_N1: return true; 3126 case MCK_ConstantUImm8_0: return true; 3127 case MCK_SImm7Lsl2: return true; 3128 case MCK_ConstantSImm9_0: return true; 3129 case MCK_ConstantSImm10_0: return true; 3130 case MCK_ConstantUImm10_0: return true; 3131 case MCK_SImm10Lsl1: return true; 3132 case MCK_ConstantSImm11_0: return true; 3133 case MCK_SImm10Lsl2: return true; 3134 case MCK_SImm10Lsl3: return true; 3135 case MCK_SImm16: return true; 3136 case MCK_SImm16_Relaxed: return true; 3137 case MCK_UImm16_Relaxed: return true; 3138 case MCK_ConstantUImm20_0: return true; 3139 case MCK_ConstantUImm26_0: return true; 3140 case MCK_SImm32: return true; 3141 case MCK_SImm32_Relaxed: return true; 3142 case MCK_UImm32_Coerced: return true; 3143 } 3144 3145 case MCK_UImm6Lsl2: 3146 switch (B) { 3147 default: return false; 3148 case MCK_ConstantUImm7_0: return true; 3149 case MCK_UImm7_N1: return true; 3150 case MCK_ConstantUImm8_0: return true; 3151 case MCK_SImm7Lsl2: return true; 3152 case MCK_ConstantSImm9_0: return true; 3153 case MCK_ConstantSImm10_0: return true; 3154 case MCK_ConstantUImm10_0: return true; 3155 case MCK_SImm10Lsl1: return true; 3156 case MCK_ConstantSImm11_0: return true; 3157 case MCK_SImm10Lsl2: return true; 3158 case MCK_SImm10Lsl3: return true; 3159 case MCK_SImm16: return true; 3160 case MCK_SImm16_Relaxed: return true; 3161 case MCK_UImm16_Relaxed: return true; 3162 case MCK_ConstantUImm20_0: return true; 3163 case MCK_ConstantUImm26_0: return true; 3164 case MCK_SImm32: return true; 3165 case MCK_SImm32_Relaxed: return true; 3166 case MCK_UImm32_Coerced: return true; 3167 } 3168 3169 case MCK_ConstantUImm7_0: 3170 switch (B) { 3171 default: return false; 3172 case MCK_UImm7_N1: return true; 3173 case MCK_ConstantUImm8_0: return true; 3174 case MCK_SImm7Lsl2: return true; 3175 case MCK_ConstantSImm9_0: return true; 3176 case MCK_ConstantSImm10_0: return true; 3177 case MCK_ConstantUImm10_0: return true; 3178 case MCK_SImm10Lsl1: return true; 3179 case MCK_ConstantSImm11_0: return true; 3180 case MCK_SImm10Lsl2: return true; 3181 case MCK_SImm10Lsl3: return true; 3182 case MCK_SImm16: return true; 3183 case MCK_SImm16_Relaxed: return true; 3184 case MCK_UImm16_Relaxed: return true; 3185 case MCK_ConstantUImm20_0: return true; 3186 case MCK_ConstantUImm26_0: return true; 3187 case MCK_SImm32: return true; 3188 case MCK_SImm32_Relaxed: return true; 3189 case MCK_UImm32_Coerced: return true; 3190 } 3191 3192 case MCK_UImm7_N1: 3193 switch (B) { 3194 default: return false; 3195 case MCK_ConstantUImm8_0: return true; 3196 case MCK_SImm7Lsl2: return true; 3197 case MCK_ConstantSImm9_0: return true; 3198 case MCK_ConstantSImm10_0: return true; 3199 case MCK_ConstantUImm10_0: return true; 3200 case MCK_SImm10Lsl1: return true; 3201 case MCK_ConstantSImm11_0: return true; 3202 case MCK_SImm10Lsl2: return true; 3203 case MCK_SImm10Lsl3: return true; 3204 case MCK_SImm16: return true; 3205 case MCK_SImm16_Relaxed: return true; 3206 case MCK_UImm16_Relaxed: return true; 3207 case MCK_ConstantUImm20_0: return true; 3208 case MCK_ConstantUImm26_0: return true; 3209 case MCK_SImm32: return true; 3210 case MCK_SImm32_Relaxed: return true; 3211 case MCK_UImm32_Coerced: return true; 3212 } 3213 3214 case MCK_ConstantUImm8_0: 3215 switch (B) { 3216 default: return false; 3217 case MCK_SImm7Lsl2: return true; 3218 case MCK_ConstantSImm9_0: return true; 3219 case MCK_ConstantSImm10_0: return true; 3220 case MCK_ConstantUImm10_0: return true; 3221 case MCK_SImm10Lsl1: return true; 3222 case MCK_ConstantSImm11_0: return true; 3223 case MCK_SImm10Lsl2: return true; 3224 case MCK_SImm10Lsl3: return true; 3225 case MCK_SImm16: return true; 3226 case MCK_SImm16_Relaxed: return true; 3227 case MCK_UImm16_Relaxed: return true; 3228 case MCK_ConstantUImm20_0: return true; 3229 case MCK_ConstantUImm26_0: return true; 3230 case MCK_SImm32: return true; 3231 case MCK_SImm32_Relaxed: return true; 3232 case MCK_UImm32_Coerced: return true; 3233 } 3234 3235 case MCK_SImm7Lsl2: 3236 switch (B) { 3237 default: return false; 3238 case MCK_ConstantSImm9_0: return true; 3239 case MCK_ConstantSImm10_0: return true; 3240 case MCK_ConstantUImm10_0: return true; 3241 case MCK_SImm10Lsl1: return true; 3242 case MCK_ConstantSImm11_0: return true; 3243 case MCK_SImm10Lsl2: return true; 3244 case MCK_SImm10Lsl3: return true; 3245 case MCK_SImm16: return true; 3246 case MCK_SImm16_Relaxed: return true; 3247 case MCK_UImm16_Relaxed: return true; 3248 case MCK_ConstantUImm20_0: return true; 3249 case MCK_ConstantUImm26_0: return true; 3250 case MCK_SImm32: return true; 3251 case MCK_SImm32_Relaxed: return true; 3252 case MCK_UImm32_Coerced: return true; 3253 } 3254 3255 case MCK_ConstantSImm9_0: 3256 switch (B) { 3257 default: return false; 3258 case MCK_ConstantSImm10_0: return true; 3259 case MCK_ConstantUImm10_0: return true; 3260 case MCK_SImm10Lsl1: return true; 3261 case MCK_ConstantSImm11_0: return true; 3262 case MCK_SImm10Lsl2: return true; 3263 case MCK_SImm10Lsl3: return true; 3264 case MCK_SImm16: return true; 3265 case MCK_SImm16_Relaxed: return true; 3266 case MCK_UImm16_Relaxed: return true; 3267 case MCK_ConstantUImm20_0: return true; 3268 case MCK_ConstantUImm26_0: return true; 3269 case MCK_SImm32: return true; 3270 case MCK_SImm32_Relaxed: return true; 3271 case MCK_UImm32_Coerced: return true; 3272 } 3273 3274 case MCK_ConstantSImm10_0: 3275 switch (B) { 3276 default: return false; 3277 case MCK_ConstantUImm10_0: return true; 3278 case MCK_SImm10Lsl1: return true; 3279 case MCK_ConstantSImm11_0: return true; 3280 case MCK_SImm10Lsl2: return true; 3281 case MCK_SImm10Lsl3: return true; 3282 case MCK_SImm16: return true; 3283 case MCK_SImm16_Relaxed: return true; 3284 case MCK_UImm16_Relaxed: return true; 3285 case MCK_ConstantUImm20_0: return true; 3286 case MCK_ConstantUImm26_0: return true; 3287 case MCK_SImm32: return true; 3288 case MCK_SImm32_Relaxed: return true; 3289 case MCK_UImm32_Coerced: return true; 3290 } 3291 3292 case MCK_ConstantUImm10_0: 3293 switch (B) { 3294 default: return false; 3295 case MCK_SImm10Lsl1: return true; 3296 case MCK_ConstantSImm11_0: return true; 3297 case MCK_SImm10Lsl2: return true; 3298 case MCK_SImm10Lsl3: return true; 3299 case MCK_SImm16: return true; 3300 case MCK_SImm16_Relaxed: return true; 3301 case MCK_UImm16_Relaxed: return true; 3302 case MCK_ConstantUImm20_0: return true; 3303 case MCK_ConstantUImm26_0: return true; 3304 case MCK_SImm32: return true; 3305 case MCK_SImm32_Relaxed: return true; 3306 case MCK_UImm32_Coerced: return true; 3307 } 3308 3309 case MCK_SImm10Lsl1: 3310 switch (B) { 3311 default: return false; 3312 case MCK_ConstantSImm11_0: return true; 3313 case MCK_SImm10Lsl2: return true; 3314 case MCK_SImm10Lsl3: return true; 3315 case MCK_SImm16: return true; 3316 case MCK_SImm16_Relaxed: return true; 3317 case MCK_UImm16_Relaxed: return true; 3318 case MCK_ConstantUImm20_0: return true; 3319 case MCK_ConstantUImm26_0: return true; 3320 case MCK_SImm32: return true; 3321 case MCK_SImm32_Relaxed: return true; 3322 case MCK_UImm32_Coerced: return true; 3323 } 3324 3325 case MCK_ConstantSImm11_0: 3326 switch (B) { 3327 default: return false; 3328 case MCK_SImm10Lsl2: return true; 3329 case MCK_SImm10Lsl3: return true; 3330 case MCK_SImm16: return true; 3331 case MCK_SImm16_Relaxed: return true; 3332 case MCK_UImm16_Relaxed: return true; 3333 case MCK_ConstantUImm20_0: return true; 3334 case MCK_ConstantUImm26_0: return true; 3335 case MCK_SImm32: return true; 3336 case MCK_SImm32_Relaxed: return true; 3337 case MCK_UImm32_Coerced: return true; 3338 } 3339 3340 case MCK_SImm10Lsl2: 3341 switch (B) { 3342 default: return false; 3343 case MCK_SImm10Lsl3: return true; 3344 case MCK_SImm16: return true; 3345 case MCK_SImm16_Relaxed: return true; 3346 case MCK_UImm16_Relaxed: return true; 3347 case MCK_ConstantUImm20_0: return true; 3348 case MCK_ConstantUImm26_0: return true; 3349 case MCK_SImm32: return true; 3350 case MCK_SImm32_Relaxed: return true; 3351 case MCK_UImm32_Coerced: return true; 3352 } 3353 3354 case MCK_SImm10Lsl3: 3355 switch (B) { 3356 default: return false; 3357 case MCK_SImm16: return true; 3358 case MCK_SImm16_Relaxed: return true; 3359 case MCK_UImm16_Relaxed: return true; 3360 case MCK_ConstantUImm20_0: return true; 3361 case MCK_ConstantUImm26_0: return true; 3362 case MCK_SImm32: return true; 3363 case MCK_SImm32_Relaxed: return true; 3364 case MCK_UImm32_Coerced: return true; 3365 } 3366 3367 case MCK_SImm16: 3368 switch (B) { 3369 default: return false; 3370 case MCK_SImm16_Relaxed: return true; 3371 case MCK_UImm16_Relaxed: return true; 3372 case MCK_ConstantUImm20_0: return true; 3373 case MCK_ConstantUImm26_0: return true; 3374 case MCK_SImm32: return true; 3375 case MCK_SImm32_Relaxed: return true; 3376 case MCK_UImm32_Coerced: return true; 3377 } 3378 3379 case MCK_SImm16_Relaxed: 3380 switch (B) { 3381 default: return false; 3382 case MCK_UImm16_Relaxed: return true; 3383 case MCK_ConstantUImm20_0: return true; 3384 case MCK_ConstantUImm26_0: return true; 3385 case MCK_SImm32: return true; 3386 case MCK_SImm32_Relaxed: return true; 3387 case MCK_UImm32_Coerced: return true; 3388 } 3389 3390 case MCK_UImm16_AltRelaxed: 3391 switch (B) { 3392 default: return false; 3393 case MCK_UImm16_Relaxed: return true; 3394 case MCK_ConstantUImm20_0: return true; 3395 case MCK_ConstantUImm26_0: return true; 3396 case MCK_SImm32: return true; 3397 case MCK_SImm32_Relaxed: return true; 3398 case MCK_UImm32_Coerced: return true; 3399 } 3400 3401 case MCK_UImm16: 3402 switch (B) { 3403 default: return false; 3404 case MCK_UImm16_Relaxed: return true; 3405 case MCK_ConstantUImm20_0: return true; 3406 case MCK_ConstantUImm26_0: return true; 3407 case MCK_SImm32: return true; 3408 case MCK_SImm32_Relaxed: return true; 3409 case MCK_UImm32_Coerced: return true; 3410 } 3411 3412 case MCK_SImm19Lsl2: 3413 switch (B) { 3414 default: return false; 3415 case MCK_ConstantUImm20_0: return true; 3416 case MCK_ConstantUImm26_0: return true; 3417 case MCK_SImm32: return true; 3418 case MCK_SImm32_Relaxed: return true; 3419 case MCK_UImm32_Coerced: return true; 3420 } 3421 3422 case MCK_UImm16_Relaxed: 3423 switch (B) { 3424 default: return false; 3425 case MCK_ConstantUImm20_0: return true; 3426 case MCK_ConstantUImm26_0: return true; 3427 case MCK_SImm32: return true; 3428 case MCK_SImm32_Relaxed: return true; 3429 case MCK_UImm32_Coerced: return true; 3430 } 3431 3432 case MCK_ConstantUImm20_0: 3433 switch (B) { 3434 default: return false; 3435 case MCK_ConstantUImm26_0: return true; 3436 case MCK_SImm32: return true; 3437 case MCK_SImm32_Relaxed: return true; 3438 case MCK_UImm32_Coerced: return true; 3439 } 3440 3441 case MCK_ConstantUImm26_0: 3442 switch (B) { 3443 default: return false; 3444 case MCK_SImm32: return true; 3445 case MCK_SImm32_Relaxed: return true; 3446 case MCK_UImm32_Coerced: return true; 3447 } 3448 3449 case MCK_SImm32: 3450 switch (B) { 3451 default: return false; 3452 case MCK_SImm32_Relaxed: return true; 3453 case MCK_UImm32_Coerced: return true; 3454 } 3455 3456 case MCK_SImm32_Relaxed: 3457 return B == MCK_UImm32_Coerced; 3458 } 3459} 3460 3461static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) { 3462 MipsOperand &Operand = (MipsOperand&)GOp; 3463 if (Kind == InvalidMatchClass) 3464 return MCTargetAsmParser::Match_InvalidOperand; 3465 3466 if (Operand.isToken() && Kind <= MCK_LAST_TOKEN) 3467 return isSubclass(matchTokenString(Operand.getToken()), Kind) ? 3468 MCTargetAsmParser::Match_Success : 3469 MCTargetAsmParser::Match_InvalidOperand; 3470 3471 switch (Kind) { 3472 default: break; 3473 // 'ACC64DSPAsmReg' class 3474 case MCK_ACC64DSPAsmReg: { 3475 DiagnosticPredicate DP(Operand.isACCAsmReg()); 3476 if (DP.isMatch()) 3477 return MCTargetAsmParser::Match_Success; 3478 break; 3479 } 3480 // 'AFGR64AsmReg' class 3481 case MCK_AFGR64AsmReg: { 3482 DiagnosticPredicate DP(Operand.isFGRAsmReg()); 3483 if (DP.isMatch()) 3484 return MCTargetAsmParser::Match_Success; 3485 break; 3486 } 3487 // 'CCRAsmReg' class 3488 case MCK_CCRAsmReg: { 3489 DiagnosticPredicate DP(Operand.isCCRAsmReg()); 3490 if (DP.isMatch()) 3491 return MCTargetAsmParser::Match_Success; 3492 break; 3493 } 3494 // 'COP0AsmReg' class 3495 case MCK_COP0AsmReg: { 3496 DiagnosticPredicate DP(Operand.isCOP0AsmReg()); 3497 if (DP.isMatch()) 3498 return MCTargetAsmParser::Match_Success; 3499 break; 3500 } 3501 // 'COP2AsmReg' class 3502 case MCK_COP2AsmReg: { 3503 DiagnosticPredicate DP(Operand.isCOP2AsmReg()); 3504 if (DP.isMatch()) 3505 return MCTargetAsmParser::Match_Success; 3506 break; 3507 } 3508 // 'COP3AsmReg' class 3509 case MCK_COP3AsmReg: { 3510 DiagnosticPredicate DP(Operand.isCOP3AsmReg()); 3511 if (DP.isMatch()) 3512 return MCTargetAsmParser::Match_Success; 3513 break; 3514 } 3515 // 'FCCAsmReg' class 3516 case MCK_FCCAsmReg: { 3517 DiagnosticPredicate DP(Operand.isFCCAsmReg()); 3518 if (DP.isMatch()) 3519 return MCTargetAsmParser::Match_Success; 3520 break; 3521 } 3522 // 'FGR32AsmReg' class 3523 case MCK_FGR32AsmReg: { 3524 DiagnosticPredicate DP(Operand.isFGRAsmReg()); 3525 if (DP.isMatch()) 3526 return MCTargetAsmParser::Match_Success; 3527 break; 3528 } 3529 // 'FGR64AsmReg' class 3530 case MCK_FGR64AsmReg: { 3531 DiagnosticPredicate DP(Operand.isFGRAsmReg()); 3532 if (DP.isMatch()) 3533 return MCTargetAsmParser::Match_Success; 3534 break; 3535 } 3536 // 'GPR32AsmReg' class 3537 case MCK_GPR32AsmReg: { 3538 DiagnosticPredicate DP(Operand.isGPRAsmReg()); 3539 if (DP.isMatch()) 3540 return MCTargetAsmParser::Match_Success; 3541 break; 3542 } 3543 // 'GPR32NonZeroAsmReg' class 3544 case MCK_GPR32NonZeroAsmReg: { 3545 DiagnosticPredicate DP(Operand.isGPRNonZeroAsmReg()); 3546 if (DP.isMatch()) 3547 return MCTargetAsmParser::Match_Success; 3548 break; 3549 } 3550 // 'GPR32ZeroAsmReg' class 3551 case MCK_GPR32ZeroAsmReg: { 3552 DiagnosticPredicate DP(Operand.isGPRZeroAsmReg()); 3553 if (DP.isMatch()) 3554 return MCTargetAsmParser::Match_Success; 3555 break; 3556 } 3557 // 'GPR64AsmReg' class 3558 case MCK_GPR64AsmReg: { 3559 DiagnosticPredicate DP(Operand.isGPRAsmReg()); 3560 if (DP.isMatch()) 3561 return MCTargetAsmParser::Match_Success; 3562 break; 3563 } 3564 // 'GPRMM16AsmReg' class 3565 case MCK_GPRMM16AsmReg: { 3566 DiagnosticPredicate DP(Operand.isMM16AsmReg()); 3567 if (DP.isMatch()) 3568 return MCTargetAsmParser::Match_Success; 3569 break; 3570 } 3571 // 'GPRMM16AsmRegMoveP' class 3572 case MCK_GPRMM16AsmRegMoveP: { 3573 DiagnosticPredicate DP(Operand.isMM16AsmRegMoveP()); 3574 if (DP.isMatch()) 3575 return MCTargetAsmParser::Match_Success; 3576 break; 3577 } 3578 // 'GPRMM16AsmRegMovePPairFirst' class 3579 case MCK_GPRMM16AsmRegMovePPairFirst: { 3580 DiagnosticPredicate DP(Operand.isMM16AsmRegMovePPairFirst()); 3581 if (DP.isMatch()) 3582 return MCTargetAsmParser::Match_Success; 3583 break; 3584 } 3585 // 'GPRMM16AsmRegMovePPairSecond' class 3586 case MCK_GPRMM16AsmRegMovePPairSecond: { 3587 DiagnosticPredicate DP(Operand.isMM16AsmRegMovePPairSecond()); 3588 if (DP.isMatch()) 3589 return MCTargetAsmParser::Match_Success; 3590 break; 3591 } 3592 // 'GPRMM16AsmRegZero' class 3593 case MCK_GPRMM16AsmRegZero: { 3594 DiagnosticPredicate DP(Operand.isMM16AsmRegZero()); 3595 if (DP.isMatch()) 3596 return MCTargetAsmParser::Match_Success; 3597 break; 3598 } 3599 // 'HI32DSPAsmReg' class 3600 case MCK_HI32DSPAsmReg: { 3601 DiagnosticPredicate DP(Operand.isACCAsmReg()); 3602 if (DP.isMatch()) 3603 return MCTargetAsmParser::Match_Success; 3604 break; 3605 } 3606 // 'HWRegsAsmReg' class 3607 case MCK_HWRegsAsmReg: { 3608 DiagnosticPredicate DP(Operand.isHWRegsAsmReg()); 3609 if (DP.isMatch()) 3610 return MCTargetAsmParser::Match_Success; 3611 break; 3612 } 3613 // 'Imm' class 3614 case MCK_Imm: { 3615 DiagnosticPredicate DP(Operand.isImm()); 3616 if (DP.isMatch()) 3617 return MCTargetAsmParser::Match_Success; 3618 break; 3619 } 3620 // 'LO32DSPAsmReg' class 3621 case MCK_LO32DSPAsmReg: { 3622 DiagnosticPredicate DP(Operand.isACCAsmReg()); 3623 if (DP.isMatch()) 3624 return MCTargetAsmParser::Match_Success; 3625 break; 3626 } 3627 // 'MSA128AsmReg' class 3628 case MCK_MSA128AsmReg: { 3629 DiagnosticPredicate DP(Operand.isMSA128AsmReg()); 3630 if (DP.isMatch()) 3631 return MCTargetAsmParser::Match_Success; 3632 break; 3633 } 3634 // 'MSACtrlAsmReg' class 3635 case MCK_MSACtrlAsmReg: { 3636 DiagnosticPredicate DP(Operand.isMSACtrlAsmReg()); 3637 if (DP.isMatch()) 3638 return MCTargetAsmParser::Match_Success; 3639 break; 3640 } 3641 // 'MicroMipsMemGP' class 3642 case MCK_MicroMipsMemGP: { 3643 DiagnosticPredicate DP(Operand.isMemWithSimmWordAlignedOffsetGP<9>()); 3644 if (DP.isMatch()) 3645 return MCTargetAsmParser::Match_Success; 3646 break; 3647 } 3648 // 'MicroMipsMem' class 3649 case MCK_MicroMipsMem: { 3650 DiagnosticPredicate DP(Operand.isMemWithGRPMM16Base()); 3651 if (DP.isMatch()) 3652 return MCTargetAsmParser::Match_Success; 3653 break; 3654 } 3655 // 'MicroMipsMemSP' class 3656 case MCK_MicroMipsMemSP: { 3657 DiagnosticPredicate DP(Operand.isMemWithUimmWordAlignedOffsetSP<7>()); 3658 if (DP.isMatch()) 3659 return MCTargetAsmParser::Match_Success; 3660 break; 3661 } 3662 // 'InvNum' class 3663 case MCK_InvNum: { 3664 DiagnosticPredicate DP(Operand.isInvNum()); 3665 if (DP.isMatch()) 3666 return MCTargetAsmParser::Match_Success; 3667 break; 3668 } 3669 // 'JumpTarget' class 3670 case MCK_JumpTarget: { 3671 DiagnosticPredicate DP(Operand.isImm()); 3672 if (DP.isMatch()) 3673 return MCTargetAsmParser::Match_Success; 3674 break; 3675 } 3676 // 'MemOffsetSimmPtr' class 3677 case MCK_MemOffsetSimmPtr: { 3678 DiagnosticPredicate DP(Operand.isMemWithPtrSizeOffset()); 3679 if (DP.isMatch()) 3680 return MCTargetAsmParser::Match_Success; 3681 if (DP.isNearMatch()) 3682 return MipsAsmParser::Match_MemSImmPtr; 3683 break; 3684 } 3685 // 'MemOffsetUimm4' class 3686 case MCK_MemOffsetUimm4: { 3687 DiagnosticPredicate DP(Operand.isMemWithUimmOffsetSP<6>()); 3688 if (DP.isMatch()) 3689 return MCTargetAsmParser::Match_Success; 3690 break; 3691 } 3692 // 'MemOffsetSimm9_0' class 3693 case MCK_MemOffsetSimm9_0: { 3694 DiagnosticPredicate DP(Operand.isMemWithSimmOffset<9, 0>()); 3695 if (DP.isMatch()) 3696 return MCTargetAsmParser::Match_Success; 3697 if (DP.isNearMatch()) 3698 return MipsAsmParser::Match_MemSImm9; 3699 break; 3700 } 3701 // 'MemOffsetSimm10_0' class 3702 case MCK_MemOffsetSimm10_0: { 3703 DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 0>()); 3704 if (DP.isMatch()) 3705 return MCTargetAsmParser::Match_Success; 3706 if (DP.isNearMatch()) 3707 return MipsAsmParser::Match_MemSImm10; 3708 break; 3709 } 3710 // 'MemOffsetSimm11_0' class 3711 case MCK_MemOffsetSimm11_0: { 3712 DiagnosticPredicate DP(Operand.isMemWithSimmOffset<11, 0>()); 3713 if (DP.isMatch()) 3714 return MCTargetAsmParser::Match_Success; 3715 if (DP.isNearMatch()) 3716 return MipsAsmParser::Match_MemSImm11; 3717 break; 3718 } 3719 // 'MemOffsetSimm12_0' class 3720 case MCK_MemOffsetSimm12_0: { 3721 DiagnosticPredicate DP(Operand.isMemWithSimmOffset<12, 0>()); 3722 if (DP.isMatch()) 3723 return MCTargetAsmParser::Match_Success; 3724 if (DP.isNearMatch()) 3725 return MipsAsmParser::Match_MemSImm12; 3726 break; 3727 } 3728 // 'MemOffsetSimm16_0' class 3729 case MCK_MemOffsetSimm16_0: { 3730 DiagnosticPredicate DP(Operand.isMemWithSimmOffset<16, 0>()); 3731 if (DP.isMatch()) 3732 return MCTargetAsmParser::Match_Success; 3733 if (DP.isNearMatch()) 3734 return MipsAsmParser::Match_MemSImm16; 3735 break; 3736 } 3737 // 'MemOffsetSimm10_1' class 3738 case MCK_MemOffsetSimm10_1: { 3739 DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 1>()); 3740 if (DP.isMatch()) 3741 return MCTargetAsmParser::Match_Success; 3742 if (DP.isNearMatch()) 3743 return MipsAsmParser::Match_MemSImm10Lsl1; 3744 break; 3745 } 3746 // 'MemOffsetSimm10_2' class 3747 case MCK_MemOffsetSimm10_2: { 3748 DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 2>()); 3749 if (DP.isMatch()) 3750 return MCTargetAsmParser::Match_Success; 3751 if (DP.isNearMatch()) 3752 return MipsAsmParser::Match_MemSImm10Lsl2; 3753 break; 3754 } 3755 // 'MemOffsetSimm10_3' class 3756 case MCK_MemOffsetSimm10_3: { 3757 DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 3>()); 3758 if (DP.isMatch()) 3759 return MCTargetAsmParser::Match_Success; 3760 if (DP.isNearMatch()) 3761 return MipsAsmParser::Match_MemSImm10Lsl3; 3762 break; 3763 } 3764 // 'Mem' class 3765 case MCK_Mem: { 3766 DiagnosticPredicate DP(Operand.isMem()); 3767 if (DP.isMatch()) 3768 return MCTargetAsmParser::Match_Success; 3769 break; 3770 } 3771 // 'RegList16' class 3772 case MCK_RegList16: { 3773 DiagnosticPredicate DP(Operand.isRegList16()); 3774 if (DP.isMatch()) 3775 return MCTargetAsmParser::Match_Success; 3776 break; 3777 } 3778 // 'RegList' class 3779 case MCK_RegList: { 3780 DiagnosticPredicate DP(Operand.isRegList()); 3781 if (DP.isMatch()) 3782 return MCTargetAsmParser::Match_Success; 3783 break; 3784 } 3785 // 'Simm19_Lsl2' class 3786 case MCK_Simm19_Lsl2: { 3787 DiagnosticPredicate DP(Operand.isScaledSImm<19, 2>()); 3788 if (DP.isMatch()) 3789 return MCTargetAsmParser::Match_Success; 3790 if (DP.isNearMatch()) 3791 return MipsAsmParser::Match_SImm19_Lsl2; 3792 break; 3793 } 3794 // 'StrictlyAFGR64AsmReg' class 3795 case MCK_StrictlyAFGR64AsmReg: { 3796 DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg()); 3797 if (DP.isMatch()) 3798 return MCTargetAsmParser::Match_Success; 3799 break; 3800 } 3801 // 'StrictlyFGR32AsmReg' class 3802 case MCK_StrictlyFGR32AsmReg: { 3803 DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg()); 3804 if (DP.isMatch()) 3805 return MCTargetAsmParser::Match_Success; 3806 break; 3807 } 3808 // 'StrictlyFGR64AsmReg' class 3809 case MCK_StrictlyFGR64AsmReg: { 3810 DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg()); 3811 if (DP.isMatch()) 3812 return MCTargetAsmParser::Match_Success; 3813 break; 3814 } 3815 // 'ConstantImmz' class 3816 case MCK_ConstantImmz: { 3817 DiagnosticPredicate DP(Operand.isConstantImmz()); 3818 if (DP.isMatch()) 3819 return MCTargetAsmParser::Match_Success; 3820 if (DP.isNearMatch()) 3821 return MipsAsmParser::Match_Immz; 3822 break; 3823 } 3824 // 'ConstantUImm1_0' class 3825 case MCK_ConstantUImm1_0: { 3826 DiagnosticPredicate DP(Operand.isConstantUImm<1, 0>()); 3827 if (DP.isMatch()) 3828 return MCTargetAsmParser::Match_Success; 3829 if (DP.isNearMatch()) 3830 return MipsAsmParser::Match_UImm1_0; 3831 break; 3832 } 3833 // 'ConstantUImm2_0' class 3834 case MCK_ConstantUImm2_0: { 3835 DiagnosticPredicate DP(Operand.isConstantUImm<2, 0>()); 3836 if (DP.isMatch()) 3837 return MCTargetAsmParser::Match_Success; 3838 if (DP.isNearMatch()) 3839 return MipsAsmParser::Match_UImm2_0; 3840 break; 3841 } 3842 // 'ConstantUImm2_1' class 3843 case MCK_ConstantUImm2_1: { 3844 DiagnosticPredicate DP(Operand.isConstantUImm<2, 1>()); 3845 if (DP.isMatch()) 3846 return MCTargetAsmParser::Match_Success; 3847 if (DP.isNearMatch()) 3848 return MipsAsmParser::Match_UImm2_1; 3849 break; 3850 } 3851 // 'ConstantUImm3_0' class 3852 case MCK_ConstantUImm3_0: { 3853 DiagnosticPredicate DP(Operand.isConstantUImm<3, 0>()); 3854 if (DP.isMatch()) 3855 return MCTargetAsmParser::Match_Success; 3856 if (DP.isNearMatch()) 3857 return MipsAsmParser::Match_UImm3_0; 3858 break; 3859 } 3860 // 'ConstantSImm4_0' class 3861 case MCK_ConstantSImm4_0: { 3862 DiagnosticPredicate DP(Operand.isConstantSImm<4, 0>()); 3863 if (DP.isMatch()) 3864 return MCTargetAsmParser::Match_Success; 3865 if (DP.isNearMatch()) 3866 return MipsAsmParser::Match_SImm4_0; 3867 break; 3868 } 3869 // 'ConstantUImm4_0' class 3870 case MCK_ConstantUImm4_0: { 3871 DiagnosticPredicate DP(Operand.isConstantUImm<4, 0>()); 3872 if (DP.isMatch()) 3873 return MCTargetAsmParser::Match_Success; 3874 if (DP.isNearMatch()) 3875 return MipsAsmParser::Match_UImm4_0; 3876 break; 3877 } 3878 // 'ConstantSImm5_0' class 3879 case MCK_ConstantSImm5_0: { 3880 DiagnosticPredicate DP(Operand.isConstantSImm<5, 0>()); 3881 if (DP.isMatch()) 3882 return MCTargetAsmParser::Match_Success; 3883 if (DP.isNearMatch()) 3884 return MipsAsmParser::Match_SImm5_0; 3885 break; 3886 } 3887 // 'ConstantUImm5_0' class 3888 case MCK_ConstantUImm5_0: { 3889 DiagnosticPredicate DP(Operand.isConstantUImm<5, 0>()); 3890 if (DP.isMatch()) 3891 return MCTargetAsmParser::Match_Success; 3892 if (DP.isNearMatch()) 3893 return MipsAsmParser::Match_UImm5_0; 3894 break; 3895 } 3896 // 'ConstantUImm5_1' class 3897 case MCK_ConstantUImm5_1: { 3898 DiagnosticPredicate DP(Operand.isConstantUImm<5, 1>()); 3899 if (DP.isMatch()) 3900 return MCTargetAsmParser::Match_Success; 3901 if (DP.isNearMatch()) 3902 return MipsAsmParser::Match_UImm5_1; 3903 break; 3904 } 3905 // 'ConstantUImm5_Plus1_Report_UImm6' class 3906 case MCK_ConstantUImm5_Plus1_Report_UImm6: { 3907 DiagnosticPredicate DP(Operand.isConstantUImm<5, 1>()); 3908 if (DP.isMatch()) 3909 return MCTargetAsmParser::Match_Success; 3910 if (DP.isNearMatch()) 3911 return MipsAsmParser::Match_UImm5_1; 3912 break; 3913 } 3914 // 'ConstantUImm5_32_Norm' class 3915 case MCK_ConstantUImm5_32_Norm: { 3916 DiagnosticPredicate DP(Operand.isConstantUImm<5, 32>()); 3917 if (DP.isMatch()) 3918 return MCTargetAsmParser::Match_Success; 3919 if (DP.isNearMatch()) 3920 return MipsAsmParser::Match_UImm5_32; 3921 break; 3922 } 3923 // 'ConstantUImm5_32' class 3924 case MCK_ConstantUImm5_32: { 3925 DiagnosticPredicate DP(Operand.isConstantUImm<5, 32>()); 3926 if (DP.isMatch()) 3927 return MCTargetAsmParser::Match_Success; 3928 if (DP.isNearMatch()) 3929 return MipsAsmParser::Match_UImm5_32; 3930 break; 3931 } 3932 // 'ConstantUImm5_0_Report_UImm6' class 3933 case MCK_ConstantUImm5_0_Report_UImm6: { 3934 DiagnosticPredicate DP(Operand.isConstantUImm<5, 0>()); 3935 if (DP.isMatch()) 3936 return MCTargetAsmParser::Match_Success; 3937 if (DP.isNearMatch()) 3938 return MipsAsmParser::Match_UImm5_0_Report_UImm6; 3939 break; 3940 } 3941 // 'ConstantUImm5_33' class 3942 case MCK_ConstantUImm5_33: { 3943 DiagnosticPredicate DP(Operand.isConstantUImm<5, 33>()); 3944 if (DP.isMatch()) 3945 return MCTargetAsmParser::Match_Success; 3946 if (DP.isNearMatch()) 3947 return MipsAsmParser::Match_UImm5_33; 3948 break; 3949 } 3950 // 'ConstantUImmRange2_64' class 3951 case MCK_ConstantUImmRange2_64: { 3952 DiagnosticPredicate DP(Operand.isConstantUImmRange<2, 64>()); 3953 if (DP.isMatch()) 3954 return MCTargetAsmParser::Match_Success; 3955 if (DP.isNearMatch()) 3956 return MipsAsmParser::Match_UImmRange2_64; 3957 break; 3958 } 3959 // 'UImm5Lsl2' class 3960 case MCK_UImm5Lsl2: { 3961 DiagnosticPredicate DP(Operand.isScaledUImm<5, 2>()); 3962 if (DP.isMatch()) 3963 return MCTargetAsmParser::Match_Success; 3964 if (DP.isNearMatch()) 3965 return MipsAsmParser::Match_UImm5_Lsl2; 3966 break; 3967 } 3968 // 'ConstantSImm6_0' class 3969 case MCK_ConstantSImm6_0: { 3970 DiagnosticPredicate DP(Operand.isConstantSImm<6, 0>()); 3971 if (DP.isMatch()) 3972 return MCTargetAsmParser::Match_Success; 3973 if (DP.isNearMatch()) 3974 return MipsAsmParser::Match_SImm6_0; 3975 break; 3976 } 3977 // 'ConstantUImm6_0' class 3978 case MCK_ConstantUImm6_0: { 3979 DiagnosticPredicate DP(Operand.isConstantUImm<6, 0>()); 3980 if (DP.isMatch()) 3981 return MCTargetAsmParser::Match_Success; 3982 if (DP.isNearMatch()) 3983 return MipsAsmParser::Match_UImm6_0; 3984 break; 3985 } 3986 // 'UImm6Lsl2' class 3987 case MCK_UImm6Lsl2: { 3988 DiagnosticPredicate DP(Operand.isScaledUImm<6, 2>()); 3989 if (DP.isMatch()) 3990 return MCTargetAsmParser::Match_Success; 3991 if (DP.isNearMatch()) 3992 return MipsAsmParser::Match_UImm6_Lsl2; 3993 break; 3994 } 3995 // 'ConstantUImm7_0' class 3996 case MCK_ConstantUImm7_0: { 3997 DiagnosticPredicate DP(Operand.isConstantUImm<7, 0>()); 3998 if (DP.isMatch()) 3999 return MCTargetAsmParser::Match_Success; 4000 if (DP.isNearMatch()) 4001 return MipsAsmParser::Match_UImm7_0; 4002 break; 4003 } 4004 // 'UImm7_N1' class 4005 case MCK_UImm7_N1: { 4006 DiagnosticPredicate DP(Operand.isConstantUImm<7, -1>()); 4007 if (DP.isMatch()) 4008 return MCTargetAsmParser::Match_Success; 4009 if (DP.isNearMatch()) 4010 return MipsAsmParser::Match_UImm7_N1; 4011 break; 4012 } 4013 // 'ConstantUImm8_0' class 4014 case MCK_ConstantUImm8_0: { 4015 DiagnosticPredicate DP(Operand.isConstantUImm<8, 0>()); 4016 if (DP.isMatch()) 4017 return MCTargetAsmParser::Match_Success; 4018 if (DP.isNearMatch()) 4019 return MipsAsmParser::Match_UImm8_0; 4020 break; 4021 } 4022 // 'SImm7Lsl2' class 4023 case MCK_SImm7Lsl2: { 4024 DiagnosticPredicate DP(Operand.isScaledSImm<7, 2>()); 4025 if (DP.isMatch()) 4026 return MCTargetAsmParser::Match_Success; 4027 if (DP.isNearMatch()) 4028 return MipsAsmParser::Match_SImm7_Lsl2; 4029 break; 4030 } 4031 // 'ConstantSImm9_0' class 4032 case MCK_ConstantSImm9_0: { 4033 DiagnosticPredicate DP(Operand.isConstantSImm<9, 0>()); 4034 if (DP.isMatch()) 4035 return MCTargetAsmParser::Match_Success; 4036 if (DP.isNearMatch()) 4037 return MipsAsmParser::Match_SImm9_0; 4038 break; 4039 } 4040 // 'ConstantSImm10_0' class 4041 case MCK_ConstantSImm10_0: { 4042 DiagnosticPredicate DP(Operand.isConstantSImm<10, 0>()); 4043 if (DP.isMatch()) 4044 return MCTargetAsmParser::Match_Success; 4045 if (DP.isNearMatch()) 4046 return MipsAsmParser::Match_SImm10_0; 4047 break; 4048 } 4049 // 'ConstantUImm10_0' class 4050 case MCK_ConstantUImm10_0: { 4051 DiagnosticPredicate DP(Operand.isConstantUImm<10, 0>()); 4052 if (DP.isMatch()) 4053 return MCTargetAsmParser::Match_Success; 4054 if (DP.isNearMatch()) 4055 return MipsAsmParser::Match_UImm10_0; 4056 break; 4057 } 4058 // 'SImm10Lsl1' class 4059 case MCK_SImm10Lsl1: { 4060 DiagnosticPredicate DP(Operand.isScaledSImm<10, 1>()); 4061 if (DP.isMatch()) 4062 return MCTargetAsmParser::Match_Success; 4063 if (DP.isNearMatch()) 4064 return MipsAsmParser::Match_SImm10_Lsl1; 4065 break; 4066 } 4067 // 'ConstantSImm11_0' class 4068 case MCK_ConstantSImm11_0: { 4069 DiagnosticPredicate DP(Operand.isConstantSImm<11, 0>()); 4070 if (DP.isMatch()) 4071 return MCTargetAsmParser::Match_Success; 4072 if (DP.isNearMatch()) 4073 return MipsAsmParser::Match_SImm11_0; 4074 break; 4075 } 4076 // 'SImm10Lsl2' class 4077 case MCK_SImm10Lsl2: { 4078 DiagnosticPredicate DP(Operand.isScaledSImm<10, 2>()); 4079 if (DP.isMatch()) 4080 return MCTargetAsmParser::Match_Success; 4081 if (DP.isNearMatch()) 4082 return MipsAsmParser::Match_SImm10_Lsl2; 4083 break; 4084 } 4085 // 'SImm10Lsl3' class 4086 case MCK_SImm10Lsl3: { 4087 DiagnosticPredicate DP(Operand.isScaledSImm<10, 3>()); 4088 if (DP.isMatch()) 4089 return MCTargetAsmParser::Match_Success; 4090 if (DP.isNearMatch()) 4091 return MipsAsmParser::Match_SImm10_Lsl3; 4092 break; 4093 } 4094 // 'SImm16' class 4095 case MCK_SImm16: { 4096 DiagnosticPredicate DP(Operand.isSImm<16>()); 4097 if (DP.isMatch()) 4098 return MCTargetAsmParser::Match_Success; 4099 if (DP.isNearMatch()) 4100 return MipsAsmParser::Match_SImm16; 4101 break; 4102 } 4103 // 'SImm16_Relaxed' class 4104 case MCK_SImm16_Relaxed: { 4105 DiagnosticPredicate DP(Operand.isAnyImm<16>()); 4106 if (DP.isMatch()) 4107 return MCTargetAsmParser::Match_Success; 4108 if (DP.isNearMatch()) 4109 return MipsAsmParser::Match_SImm16_Relaxed; 4110 break; 4111 } 4112 // 'UImm16_AltRelaxed' class 4113 case MCK_UImm16_AltRelaxed: { 4114 DiagnosticPredicate DP(Operand.isUImm<16>()); 4115 if (DP.isMatch()) 4116 return MCTargetAsmParser::Match_Success; 4117 if (DP.isNearMatch()) 4118 return MipsAsmParser::Match_UImm16_AltRelaxed; 4119 break; 4120 } 4121 // 'UImm16' class 4122 case MCK_UImm16: { 4123 DiagnosticPredicate DP(Operand.isUImm<16>()); 4124 if (DP.isMatch()) 4125 return MCTargetAsmParser::Match_Success; 4126 if (DP.isNearMatch()) 4127 return MipsAsmParser::Match_UImm16; 4128 break; 4129 } 4130 // 'SImm19Lsl2' class 4131 case MCK_SImm19Lsl2: { 4132 DiagnosticPredicate DP(Operand.isScaledSImm<19, 2>()); 4133 if (DP.isMatch()) 4134 return MCTargetAsmParser::Match_Success; 4135 if (DP.isNearMatch()) 4136 return MipsAsmParser::Match_SImm19_Lsl2; 4137 break; 4138 } 4139 // 'UImm16_Relaxed' class 4140 case MCK_UImm16_Relaxed: { 4141 DiagnosticPredicate DP(Operand.isAnyImm<16>()); 4142 if (DP.isMatch()) 4143 return MCTargetAsmParser::Match_Success; 4144 if (DP.isNearMatch()) 4145 return MipsAsmParser::Match_UImm16_Relaxed; 4146 break; 4147 } 4148 // 'ConstantUImm20_0' class 4149 case MCK_ConstantUImm20_0: { 4150 DiagnosticPredicate DP(Operand.isConstantUImm<20, 0>()); 4151 if (DP.isMatch()) 4152 return MCTargetAsmParser::Match_Success; 4153 if (DP.isNearMatch()) 4154 return MipsAsmParser::Match_UImm20_0; 4155 break; 4156 } 4157 // 'ConstantUImm26_0' class 4158 case MCK_ConstantUImm26_0: { 4159 DiagnosticPredicate DP(Operand.isConstantUImm<26, 0>()); 4160 if (DP.isMatch()) 4161 return MCTargetAsmParser::Match_Success; 4162 if (DP.isNearMatch()) 4163 return MipsAsmParser::Match_UImm26_0; 4164 break; 4165 } 4166 // 'SImm32' class 4167 case MCK_SImm32: { 4168 DiagnosticPredicate DP(Operand.isSImm<32>()); 4169 if (DP.isMatch()) 4170 return MCTargetAsmParser::Match_Success; 4171 if (DP.isNearMatch()) 4172 return MipsAsmParser::Match_SImm32; 4173 break; 4174 } 4175 // 'SImm32_Relaxed' class 4176 case MCK_SImm32_Relaxed: { 4177 DiagnosticPredicate DP(Operand.isAnyImm<33>()); 4178 if (DP.isMatch()) 4179 return MCTargetAsmParser::Match_Success; 4180 if (DP.isNearMatch()) 4181 return MipsAsmParser::Match_SImm32_Relaxed; 4182 break; 4183 } 4184 // 'UImm32_Coerced' class 4185 case MCK_UImm32_Coerced: { 4186 DiagnosticPredicate DP(Operand.isSImm<33>()); 4187 if (DP.isMatch()) 4188 return MCTargetAsmParser::Match_Success; 4189 if (DP.isNearMatch()) 4190 return MipsAsmParser::Match_UImm32_Coerced; 4191 break; 4192 } 4193 } // end switch (Kind) 4194 4195 if (Operand.isReg()) { 4196 MatchClassKind OpKind; 4197 switch (Operand.getReg()) { 4198 default: OpKind = InvalidMatchClass; break; 4199 case Mips::ZERO: OpKind = MCK_GPR32ZERO; break; 4200 case Mips::AT: OpKind = MCK_GPR32NONZERO; break; 4201 case Mips::V0: OpKind = MCK_Reg11; break; 4202 case Mips::V1: OpKind = MCK_Reg11; break; 4203 case Mips::A0: OpKind = MCK_GPRMM16MovePPairFirst; break; 4204 case Mips::A1: OpKind = MCK_Reg13; break; 4205 case Mips::A2: OpKind = MCK_Reg13; break; 4206 case Mips::A3: OpKind = MCK_Reg14; break; 4207 case Mips::T0: OpKind = MCK_GPR32NONZERO; break; 4208 case Mips::T1: OpKind = MCK_GPR32NONZERO; break; 4209 case Mips::T2: OpKind = MCK_GPR32NONZERO; break; 4210 case Mips::T3: OpKind = MCK_GPR32NONZERO; break; 4211 case Mips::T4: OpKind = MCK_GPR32NONZERO; break; 4212 case Mips::T5: OpKind = MCK_GPR32NONZERO; break; 4213 case Mips::T6: OpKind = MCK_GPR32NONZERO; break; 4214 case Mips::T7: OpKind = MCK_GPR32NONZERO; break; 4215 case Mips::S0: OpKind = MCK_Reg9; break; 4216 case Mips::S1: OpKind = MCK_Reg11; break; 4217 case Mips::S2: OpKind = MCK_Reg10; break; 4218 case Mips::S3: OpKind = MCK_Reg10; break; 4219 case Mips::S4: OpKind = MCK_Reg10; break; 4220 case Mips::S5: OpKind = MCK_GPRMM16MovePPairSecond; break; 4221 case Mips::S6: OpKind = MCK_GPRMM16MovePPairSecond; break; 4222 case Mips::S7: OpKind = MCK_GPR32NONZERO; break; 4223 case Mips::T8: OpKind = MCK_GPR32NONZERO; break; 4224 case Mips::T9: OpKind = MCK_GPR32NONZERO; break; 4225 case Mips::K0: OpKind = MCK_GPR32NONZERO; break; 4226 case Mips::K1: OpKind = MCK_GPR32NONZERO; break; 4227 case Mips::GP: OpKind = MCK_GP32; break; 4228 case Mips::SP: OpKind = MCK_CPUSPReg; break; 4229 case Mips::FP: OpKind = MCK_GPR32NONZERO; break; 4230 case Mips::RA: OpKind = MCK_CPURAReg; break; 4231 case Mips::ZERO_64: OpKind = MCK_Reg19; break; 4232 case Mips::AT_64: OpKind = MCK_Reg24; break; 4233 case Mips::V0_64: OpKind = MCK_Reg30; break; 4234 case Mips::V1_64: OpKind = MCK_Reg30; break; 4235 case Mips::A0_64: OpKind = MCK_Reg31; break; 4236 case Mips::A1_64: OpKind = MCK_Reg32; break; 4237 case Mips::A2_64: OpKind = MCK_Reg32; break; 4238 case Mips::A3_64: OpKind = MCK_Reg33; break; 4239 case Mips::T0_64: OpKind = MCK_Reg24; break; 4240 case Mips::T1_64: OpKind = MCK_Reg24; break; 4241 case Mips::T2_64: OpKind = MCK_Reg24; break; 4242 case Mips::T3_64: OpKind = MCK_Reg24; break; 4243 case Mips::T4_64: OpKind = MCK_Reg24; break; 4244 case Mips::T5_64: OpKind = MCK_Reg24; break; 4245 case Mips::T6_64: OpKind = MCK_Reg24; break; 4246 case Mips::T7_64: OpKind = MCK_Reg24; break; 4247 case Mips::S0_64: OpKind = MCK_Reg28; break; 4248 case Mips::S1_64: OpKind = MCK_Reg30; break; 4249 case Mips::S2_64: OpKind = MCK_Reg29; break; 4250 case Mips::S3_64: OpKind = MCK_Reg29; break; 4251 case Mips::S4_64: OpKind = MCK_Reg29; break; 4252 case Mips::S5_64: OpKind = MCK_Reg34; break; 4253 case Mips::S6_64: OpKind = MCK_Reg34; break; 4254 case Mips::S7_64: OpKind = MCK_Reg24; break; 4255 case Mips::T8_64: OpKind = MCK_Reg24; break; 4256 case Mips::T9_64: OpKind = MCK_Reg24; break; 4257 case Mips::K0_64: OpKind = MCK_Reg24; break; 4258 case Mips::K1_64: OpKind = MCK_Reg24; break; 4259 case Mips::GP_64: OpKind = MCK_GP64; break; 4260 case Mips::SP_64: OpKind = MCK_SP64; break; 4261 case Mips::FP_64: OpKind = MCK_Reg24; break; 4262 case Mips::RA_64: OpKind = MCK_Reg37; break; 4263 case Mips::F0: OpKind = MCK_FGR32; break; 4264 case Mips::F1: OpKind = MCK_FGR32; break; 4265 case Mips::F2: OpKind = MCK_FGR32; break; 4266 case Mips::F3: OpKind = MCK_FGR32; break; 4267 case Mips::F4: OpKind = MCK_FGR32; break; 4268 case Mips::F5: OpKind = MCK_FGR32; break; 4269 case Mips::F6: OpKind = MCK_FGR32; break; 4270 case Mips::F7: OpKind = MCK_FGR32; break; 4271 case Mips::F8: OpKind = MCK_FGR32; break; 4272 case Mips::F9: OpKind = MCK_FGR32; break; 4273 case Mips::F10: OpKind = MCK_FGR32; break; 4274 case Mips::F11: OpKind = MCK_FGR32; break; 4275 case Mips::F12: OpKind = MCK_FGR32; break; 4276 case Mips::F13: OpKind = MCK_FGR32; break; 4277 case Mips::F14: OpKind = MCK_FGR32; break; 4278 case Mips::F15: OpKind = MCK_FGR32; break; 4279 case Mips::F16: OpKind = MCK_FGR32; break; 4280 case Mips::F17: OpKind = MCK_FGR32; break; 4281 case Mips::F18: OpKind = MCK_FGR32; break; 4282 case Mips::F19: OpKind = MCK_FGR32; break; 4283 case Mips::F20: OpKind = MCK_FGR32; break; 4284 case Mips::F21: OpKind = MCK_FGR32; break; 4285 case Mips::F22: OpKind = MCK_FGR32; break; 4286 case Mips::F23: OpKind = MCK_FGR32; break; 4287 case Mips::F24: OpKind = MCK_FGR32; break; 4288 case Mips::F25: OpKind = MCK_FGR32; break; 4289 case Mips::F26: OpKind = MCK_FGR32; break; 4290 case Mips::F27: OpKind = MCK_FGR32; break; 4291 case Mips::F28: OpKind = MCK_FGR32; break; 4292 case Mips::F29: OpKind = MCK_FGR32; break; 4293 case Mips::F30: OpKind = MCK_FGR32; break; 4294 case Mips::F31: OpKind = MCK_FGR32; break; 4295 case Mips::D0: OpKind = MCK_AFGR64; break; 4296 case Mips::D1: OpKind = MCK_AFGR64; break; 4297 case Mips::D2: OpKind = MCK_AFGR64; break; 4298 case Mips::D3: OpKind = MCK_AFGR64; break; 4299 case Mips::D4: OpKind = MCK_AFGR64; break; 4300 case Mips::D5: OpKind = MCK_AFGR64; break; 4301 case Mips::D6: OpKind = MCK_AFGR64; break; 4302 case Mips::D7: OpKind = MCK_AFGR64; break; 4303 case Mips::D8: OpKind = MCK_AFGR64; break; 4304 case Mips::D9: OpKind = MCK_AFGR64; break; 4305 case Mips::D10: OpKind = MCK_AFGR64; break; 4306 case Mips::D11: OpKind = MCK_AFGR64; break; 4307 case Mips::D12: OpKind = MCK_AFGR64; break; 4308 case Mips::D13: OpKind = MCK_AFGR64; break; 4309 case Mips::D14: OpKind = MCK_AFGR64; break; 4310 case Mips::D15: OpKind = MCK_AFGR64; break; 4311 case Mips::D0_64: OpKind = MCK_FGR64; break; 4312 case Mips::D1_64: OpKind = MCK_FGR64; break; 4313 case Mips::D2_64: OpKind = MCK_FGR64; break; 4314 case Mips::D3_64: OpKind = MCK_FGR64; break; 4315 case Mips::D4_64: OpKind = MCK_FGR64; break; 4316 case Mips::D5_64: OpKind = MCK_FGR64; break; 4317 case Mips::D6_64: OpKind = MCK_FGR64; break; 4318 case Mips::D7_64: OpKind = MCK_FGR64; break; 4319 case Mips::D8_64: OpKind = MCK_FGR64; break; 4320 case Mips::D9_64: OpKind = MCK_FGR64; break; 4321 case Mips::D10_64: OpKind = MCK_FGR64; break; 4322 case Mips::D11_64: OpKind = MCK_FGR64; break; 4323 case Mips::D12_64: OpKind = MCK_FGR64; break; 4324 case Mips::D13_64: OpKind = MCK_FGR64; break; 4325 case Mips::D14_64: OpKind = MCK_FGR64; break; 4326 case Mips::D15_64: OpKind = MCK_FGR64; break; 4327 case Mips::D16_64: OpKind = MCK_FGR64; break; 4328 case Mips::D17_64: OpKind = MCK_FGR64; break; 4329 case Mips::D18_64: OpKind = MCK_FGR64; break; 4330 case Mips::D19_64: OpKind = MCK_FGR64; break; 4331 case Mips::D20_64: OpKind = MCK_FGR64; break; 4332 case Mips::D21_64: OpKind = MCK_FGR64; break; 4333 case Mips::D22_64: OpKind = MCK_FGR64; break; 4334 case Mips::D23_64: OpKind = MCK_FGR64; break; 4335 case Mips::D24_64: OpKind = MCK_FGR64; break; 4336 case Mips::D25_64: OpKind = MCK_FGR64; break; 4337 case Mips::D26_64: OpKind = MCK_FGR64; break; 4338 case Mips::D27_64: OpKind = MCK_FGR64; break; 4339 case Mips::D28_64: OpKind = MCK_FGR64; break; 4340 case Mips::D29_64: OpKind = MCK_FGR64; break; 4341 case Mips::D30_64: OpKind = MCK_FGR64; break; 4342 case Mips::D31_64: OpKind = MCK_FGR64; break; 4343 case Mips::W0: OpKind = MCK_MSA128WEvens; break; 4344 case Mips::W1: OpKind = MCK_MSA128F16; break; 4345 case Mips::W2: OpKind = MCK_MSA128WEvens; break; 4346 case Mips::W3: OpKind = MCK_MSA128F16; break; 4347 case Mips::W4: OpKind = MCK_MSA128WEvens; break; 4348 case Mips::W5: OpKind = MCK_MSA128F16; break; 4349 case Mips::W6: OpKind = MCK_MSA128WEvens; break; 4350 case Mips::W7: OpKind = MCK_MSA128F16; break; 4351 case Mips::W8: OpKind = MCK_MSA128WEvens; break; 4352 case Mips::W9: OpKind = MCK_MSA128F16; break; 4353 case Mips::W10: OpKind = MCK_MSA128WEvens; break; 4354 case Mips::W11: OpKind = MCK_MSA128F16; break; 4355 case Mips::W12: OpKind = MCK_MSA128WEvens; break; 4356 case Mips::W13: OpKind = MCK_MSA128F16; break; 4357 case Mips::W14: OpKind = MCK_MSA128WEvens; break; 4358 case Mips::W15: OpKind = MCK_MSA128F16; break; 4359 case Mips::W16: OpKind = MCK_MSA128WEvens; break; 4360 case Mips::W17: OpKind = MCK_MSA128F16; break; 4361 case Mips::W18: OpKind = MCK_MSA128WEvens; break; 4362 case Mips::W19: OpKind = MCK_MSA128F16; break; 4363 case Mips::W20: OpKind = MCK_MSA128WEvens; break; 4364 case Mips::W21: OpKind = MCK_MSA128F16; break; 4365 case Mips::W22: OpKind = MCK_MSA128WEvens; break; 4366 case Mips::W23: OpKind = MCK_MSA128F16; break; 4367 case Mips::W24: OpKind = MCK_MSA128WEvens; break; 4368 case Mips::W25: OpKind = MCK_MSA128F16; break; 4369 case Mips::W26: OpKind = MCK_MSA128WEvens; break; 4370 case Mips::W27: OpKind = MCK_MSA128F16; break; 4371 case Mips::W28: OpKind = MCK_MSA128WEvens; break; 4372 case Mips::W29: OpKind = MCK_MSA128F16; break; 4373 case Mips::W30: OpKind = MCK_MSA128WEvens; break; 4374 case Mips::W31: OpKind = MCK_MSA128F16; break; 4375 case Mips::HI0: OpKind = MCK_HI32; break; 4376 case Mips::HI1: OpKind = MCK_HI32DSP; break; 4377 case Mips::HI2: OpKind = MCK_HI32DSP; break; 4378 case Mips::HI3: OpKind = MCK_HI32DSP; break; 4379 case Mips::LO0: OpKind = MCK_LO32; break; 4380 case Mips::LO1: OpKind = MCK_LO32DSP; break; 4381 case Mips::LO2: OpKind = MCK_LO32DSP; break; 4382 case Mips::LO3: OpKind = MCK_LO32DSP; break; 4383 case Mips::HI0_64: OpKind = MCK_HI64; break; 4384 case Mips::LO0_64: OpKind = MCK_LO64; break; 4385 case Mips::FCR0: OpKind = MCK_CCR; break; 4386 case Mips::FCR1: OpKind = MCK_CCR; break; 4387 case Mips::FCR2: OpKind = MCK_CCR; break; 4388 case Mips::FCR3: OpKind = MCK_CCR; break; 4389 case Mips::FCR4: OpKind = MCK_CCR; break; 4390 case Mips::FCR5: OpKind = MCK_CCR; break; 4391 case Mips::FCR6: OpKind = MCK_CCR; break; 4392 case Mips::FCR7: OpKind = MCK_CCR; break; 4393 case Mips::FCR8: OpKind = MCK_CCR; break; 4394 case Mips::FCR9: OpKind = MCK_CCR; break; 4395 case Mips::FCR10: OpKind = MCK_CCR; break; 4396 case Mips::FCR11: OpKind = MCK_CCR; break; 4397 case Mips::FCR12: OpKind = MCK_CCR; break; 4398 case Mips::FCR13: OpKind = MCK_CCR; break; 4399 case Mips::FCR14: OpKind = MCK_CCR; break; 4400 case Mips::FCR15: OpKind = MCK_CCR; break; 4401 case Mips::FCR16: OpKind = MCK_CCR; break; 4402 case Mips::FCR17: OpKind = MCK_CCR; break; 4403 case Mips::FCR18: OpKind = MCK_CCR; break; 4404 case Mips::FCR19: OpKind = MCK_CCR; break; 4405 case Mips::FCR20: OpKind = MCK_CCR; break; 4406 case Mips::FCR21: OpKind = MCK_CCR; break; 4407 case Mips::FCR22: OpKind = MCK_CCR; break; 4408 case Mips::FCR23: OpKind = MCK_CCR; break; 4409 case Mips::FCR24: OpKind = MCK_CCR; break; 4410 case Mips::FCR25: OpKind = MCK_CCR; break; 4411 case Mips::FCR26: OpKind = MCK_CCR; break; 4412 case Mips::FCR27: OpKind = MCK_CCR; break; 4413 case Mips::FCR28: OpKind = MCK_CCR; break; 4414 case Mips::FCR29: OpKind = MCK_CCR; break; 4415 case Mips::FCR30: OpKind = MCK_CCR; break; 4416 case Mips::FCR31: OpKind = MCK_CCR; break; 4417 case Mips::FCC0: OpKind = MCK_FCC; break; 4418 case Mips::FCC1: OpKind = MCK_FCC; break; 4419 case Mips::FCC2: OpKind = MCK_FCC; break; 4420 case Mips::FCC3: OpKind = MCK_FCC; break; 4421 case Mips::FCC4: OpKind = MCK_FCC; break; 4422 case Mips::FCC5: OpKind = MCK_FCC; break; 4423 case Mips::FCC6: OpKind = MCK_FCC; break; 4424 case Mips::FCC7: OpKind = MCK_FCC; break; 4425 case Mips::COP00: OpKind = MCK_COP0; break; 4426 case Mips::COP01: OpKind = MCK_COP0; break; 4427 case Mips::COP02: OpKind = MCK_COP0; break; 4428 case Mips::COP03: OpKind = MCK_COP0; break; 4429 case Mips::COP04: OpKind = MCK_COP0; break; 4430 case Mips::COP05: OpKind = MCK_COP0; break; 4431 case Mips::COP06: OpKind = MCK_COP0; break; 4432 case Mips::COP07: OpKind = MCK_COP0; break; 4433 case Mips::COP08: OpKind = MCK_COP0; break; 4434 case Mips::COP09: OpKind = MCK_COP0; break; 4435 case Mips::COP010: OpKind = MCK_COP0; break; 4436 case Mips::COP011: OpKind = MCK_COP0; break; 4437 case Mips::COP012: OpKind = MCK_COP0; break; 4438 case Mips::COP013: OpKind = MCK_COP0; break; 4439 case Mips::COP014: OpKind = MCK_COP0; break; 4440 case Mips::COP015: OpKind = MCK_COP0; break; 4441 case Mips::COP016: OpKind = MCK_COP0; break; 4442 case Mips::COP017: OpKind = MCK_COP0; break; 4443 case Mips::COP018: OpKind = MCK_COP0; break; 4444 case Mips::COP019: OpKind = MCK_COP0; break; 4445 case Mips::COP020: OpKind = MCK_COP0; break; 4446 case Mips::COP021: OpKind = MCK_COP0; break; 4447 case Mips::COP022: OpKind = MCK_COP0; break; 4448 case Mips::COP023: OpKind = MCK_COP0; break; 4449 case Mips::COP024: OpKind = MCK_COP0; break; 4450 case Mips::COP025: OpKind = MCK_COP0; break; 4451 case Mips::COP026: OpKind = MCK_COP0; break; 4452 case Mips::COP027: OpKind = MCK_COP0; break; 4453 case Mips::COP028: OpKind = MCK_COP0; break; 4454 case Mips::COP029: OpKind = MCK_COP0; break; 4455 case Mips::COP030: OpKind = MCK_COP0; break; 4456 case Mips::COP031: OpKind = MCK_COP0; break; 4457 case Mips::COP20: OpKind = MCK_COP2; break; 4458 case Mips::COP21: OpKind = MCK_COP2; break; 4459 case Mips::COP22: OpKind = MCK_COP2; break; 4460 case Mips::COP23: OpKind = MCK_COP2; break; 4461 case Mips::COP24: OpKind = MCK_COP2; break; 4462 case Mips::COP25: OpKind = MCK_COP2; break; 4463 case Mips::COP26: OpKind = MCK_COP2; break; 4464 case Mips::COP27: OpKind = MCK_COP2; break; 4465 case Mips::COP28: OpKind = MCK_COP2; break; 4466 case Mips::COP29: OpKind = MCK_COP2; break; 4467 case Mips::COP210: OpKind = MCK_COP2; break; 4468 case Mips::COP211: OpKind = MCK_COP2; break; 4469 case Mips::COP212: OpKind = MCK_COP2; break; 4470 case Mips::COP213: OpKind = MCK_COP2; break; 4471 case Mips::COP214: OpKind = MCK_COP2; break; 4472 case Mips::COP215: OpKind = MCK_COP2; break; 4473 case Mips::COP216: OpKind = MCK_COP2; break; 4474 case Mips::COP217: OpKind = MCK_COP2; break; 4475 case Mips::COP218: OpKind = MCK_COP2; break; 4476 case Mips::COP219: OpKind = MCK_COP2; break; 4477 case Mips::COP220: OpKind = MCK_COP2; break; 4478 case Mips::COP221: OpKind = MCK_COP2; break; 4479 case Mips::COP222: OpKind = MCK_COP2; break; 4480 case Mips::COP223: OpKind = MCK_COP2; break; 4481 case Mips::COP224: OpKind = MCK_COP2; break; 4482 case Mips::COP225: OpKind = MCK_COP2; break; 4483 case Mips::COP226: OpKind = MCK_COP2; break; 4484 case Mips::COP227: OpKind = MCK_COP2; break; 4485 case Mips::COP228: OpKind = MCK_COP2; break; 4486 case Mips::COP229: OpKind = MCK_COP2; break; 4487 case Mips::COP230: OpKind = MCK_COP2; break; 4488 case Mips::COP231: OpKind = MCK_COP2; break; 4489 case Mips::COP30: OpKind = MCK_COP3; break; 4490 case Mips::COP31: OpKind = MCK_COP3; break; 4491 case Mips::COP32: OpKind = MCK_COP3; break; 4492 case Mips::COP33: OpKind = MCK_COP3; break; 4493 case Mips::COP34: OpKind = MCK_COP3; break; 4494 case Mips::COP35: OpKind = MCK_COP3; break; 4495 case Mips::COP36: OpKind = MCK_COP3; break; 4496 case Mips::COP37: OpKind = MCK_COP3; break; 4497 case Mips::COP38: OpKind = MCK_COP3; break; 4498 case Mips::COP39: OpKind = MCK_COP3; break; 4499 case Mips::COP310: OpKind = MCK_COP3; break; 4500 case Mips::COP311: OpKind = MCK_COP3; break; 4501 case Mips::COP312: OpKind = MCK_COP3; break; 4502 case Mips::COP313: OpKind = MCK_COP3; break; 4503 case Mips::COP314: OpKind = MCK_COP3; break; 4504 case Mips::COP315: OpKind = MCK_COP3; break; 4505 case Mips::COP316: OpKind = MCK_COP3; break; 4506 case Mips::COP317: OpKind = MCK_COP3; break; 4507 case Mips::COP318: OpKind = MCK_COP3; break; 4508 case Mips::COP319: OpKind = MCK_COP3; break; 4509 case Mips::COP320: OpKind = MCK_COP3; break; 4510 case Mips::COP321: OpKind = MCK_COP3; break; 4511 case Mips::COP322: OpKind = MCK_COP3; break; 4512 case Mips::COP323: OpKind = MCK_COP3; break; 4513 case Mips::COP324: OpKind = MCK_COP3; break; 4514 case Mips::COP325: OpKind = MCK_COP3; break; 4515 case Mips::COP326: OpKind = MCK_COP3; break; 4516 case Mips::COP327: OpKind = MCK_COP3; break; 4517 case Mips::COP328: OpKind = MCK_COP3; break; 4518 case Mips::COP329: OpKind = MCK_COP3; break; 4519 case Mips::COP330: OpKind = MCK_COP3; break; 4520 case Mips::COP331: OpKind = MCK_COP3; break; 4521 case Mips::PC: OpKind = MCK_PC; break; 4522 case Mips::HWR0: OpKind = MCK_HWRegs; break; 4523 case Mips::HWR1: OpKind = MCK_HWRegs; break; 4524 case Mips::HWR2: OpKind = MCK_HWRegs; break; 4525 case Mips::HWR3: OpKind = MCK_HWRegs; break; 4526 case Mips::HWR4: OpKind = MCK_HWRegs; break; 4527 case Mips::HWR5: OpKind = MCK_HWRegs; break; 4528 case Mips::HWR6: OpKind = MCK_HWRegs; break; 4529 case Mips::HWR7: OpKind = MCK_HWRegs; break; 4530 case Mips::HWR8: OpKind = MCK_HWRegs; break; 4531 case Mips::HWR9: OpKind = MCK_HWRegs; break; 4532 case Mips::HWR10: OpKind = MCK_HWRegs; break; 4533 case Mips::HWR11: OpKind = MCK_HWRegs; break; 4534 case Mips::HWR12: OpKind = MCK_HWRegs; break; 4535 case Mips::HWR13: OpKind = MCK_HWRegs; break; 4536 case Mips::HWR14: OpKind = MCK_HWRegs; break; 4537 case Mips::HWR15: OpKind = MCK_HWRegs; break; 4538 case Mips::HWR16: OpKind = MCK_HWRegs; break; 4539 case Mips::HWR17: OpKind = MCK_HWRegs; break; 4540 case Mips::HWR18: OpKind = MCK_HWRegs; break; 4541 case Mips::HWR19: OpKind = MCK_HWRegs; break; 4542 case Mips::HWR20: OpKind = MCK_HWRegs; break; 4543 case Mips::HWR21: OpKind = MCK_HWRegs; break; 4544 case Mips::HWR22: OpKind = MCK_HWRegs; break; 4545 case Mips::HWR23: OpKind = MCK_HWRegs; break; 4546 case Mips::HWR24: OpKind = MCK_HWRegs; break; 4547 case Mips::HWR25: OpKind = MCK_HWRegs; break; 4548 case Mips::HWR26: OpKind = MCK_HWRegs; break; 4549 case Mips::HWR27: OpKind = MCK_HWRegs; break; 4550 case Mips::HWR28: OpKind = MCK_HWRegs; break; 4551 case Mips::HWR29: OpKind = MCK_HWRegs; break; 4552 case Mips::HWR30: OpKind = MCK_HWRegs; break; 4553 case Mips::HWR31: OpKind = MCK_HWRegs; break; 4554 case Mips::AC0: OpKind = MCK_ACC64; break; 4555 case Mips::AC1: OpKind = MCK_ACC64DSP; break; 4556 case Mips::AC2: OpKind = MCK_ACC64DSP; break; 4557 case Mips::AC3: OpKind = MCK_ACC64DSP; break; 4558 case Mips::AC0_64: OpKind = MCK_ACC128; break; 4559 case Mips::DSPCCond: OpKind = MCK_DSPCC; break; 4560 case Mips::MSAIR: OpKind = MCK_MSACtrl; break; 4561 case Mips::MSACSR: OpKind = MCK_MSACtrl; break; 4562 case Mips::MSAAccess: OpKind = MCK_MSACtrl; break; 4563 case Mips::MSASave: OpKind = MCK_MSACtrl; break; 4564 case Mips::MSAModify: OpKind = MCK_MSACtrl; break; 4565 case Mips::MSARequest: OpKind = MCK_MSACtrl; break; 4566 case Mips::MSAMap: OpKind = MCK_MSACtrl; break; 4567 case Mips::MSAUnmap: OpKind = MCK_MSACtrl; break; 4568 case Mips::MSA8: OpKind = MCK_MSACtrl; break; 4569 case Mips::MSA9: OpKind = MCK_MSACtrl; break; 4570 case Mips::MSA10: OpKind = MCK_MSACtrl; break; 4571 case Mips::MSA11: OpKind = MCK_MSACtrl; break; 4572 case Mips::MSA12: OpKind = MCK_MSACtrl; break; 4573 case Mips::MSA13: OpKind = MCK_MSACtrl; break; 4574 case Mips::MSA14: OpKind = MCK_MSACtrl; break; 4575 case Mips::MSA15: OpKind = MCK_MSACtrl; break; 4576 case Mips::MSA16: OpKind = MCK_MSACtrl; break; 4577 case Mips::MSA17: OpKind = MCK_MSACtrl; break; 4578 case Mips::MSA18: OpKind = MCK_MSACtrl; break; 4579 case Mips::MSA19: OpKind = MCK_MSACtrl; break; 4580 case Mips::MSA20: OpKind = MCK_MSACtrl; break; 4581 case Mips::MSA21: OpKind = MCK_MSACtrl; break; 4582 case Mips::MSA22: OpKind = MCK_MSACtrl; break; 4583 case Mips::MSA23: OpKind = MCK_MSACtrl; break; 4584 case Mips::MSA24: OpKind = MCK_MSACtrl; break; 4585 case Mips::MSA25: OpKind = MCK_MSACtrl; break; 4586 case Mips::MSA26: OpKind = MCK_MSACtrl; break; 4587 case Mips::MSA27: OpKind = MCK_MSACtrl; break; 4588 case Mips::MSA28: OpKind = MCK_MSACtrl; break; 4589 case Mips::MSA29: OpKind = MCK_MSACtrl; break; 4590 case Mips::MSA30: OpKind = MCK_MSACtrl; break; 4591 case Mips::MSA31: OpKind = MCK_MSACtrl; break; 4592 case Mips::MPL0: OpKind = MCK_OCTEON_MPL; break; 4593 case Mips::MPL1: OpKind = MCK_OCTEON_MPL; break; 4594 case Mips::MPL2: OpKind = MCK_OCTEON_MPL; break; 4595 case Mips::P0: OpKind = MCK_OCTEON_P; break; 4596 case Mips::P1: OpKind = MCK_OCTEON_P; break; 4597 case Mips::P2: OpKind = MCK_OCTEON_P; break; 4598 } 4599 return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success : 4600 getDiagKindFromRegisterClass(Kind); 4601 } 4602 4603 if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER) 4604 return getDiagKindFromRegisterClass(Kind); 4605 4606 return MCTargetAsmParser::Match_InvalidOperand; 4607} 4608 4609#ifndef NDEBUG 4610const char *getMatchClassName(MatchClassKind Kind) { 4611 switch (Kind) { 4612 case InvalidMatchClass: return "InvalidMatchClass"; 4613 case OptionalMatchClass: return "OptionalMatchClass"; 4614 case MCK__HASH_: return "MCK__HASH_"; 4615 case MCK__40_: return "MCK__40_"; 4616 case MCK__41_: return "MCK__41_"; 4617 case MCK_0: return "MCK_0"; 4618 case MCK_16: return "MCK_16"; 4619 case MCK__91_: return "MCK__91_"; 4620 case MCK__93_: return "MCK__93_"; 4621 case MCK_bit: return "MCK_bit"; 4622 case MCK_inst: return "MCK_inst"; 4623 case MCK_Reg37: return "MCK_Reg37"; 4624 case MCK_Reg19: return "MCK_Reg19"; 4625 case MCK_ACC128: return "MCK_ACC128"; 4626 case MCK_ACC64: return "MCK_ACC64"; 4627 case MCK_CPURAReg: return "MCK_CPURAReg"; 4628 case MCK_CPUSPReg: return "MCK_CPUSPReg"; 4629 case MCK_DSPCC: return "MCK_DSPCC"; 4630 case MCK_GP32: return "MCK_GP32"; 4631 case MCK_GP64: return "MCK_GP64"; 4632 case MCK_GPR32ZERO: return "MCK_GPR32ZERO"; 4633 case MCK_HI32: return "MCK_HI32"; 4634 case MCK_HI64: return "MCK_HI64"; 4635 case MCK_LO32: return "MCK_LO32"; 4636 case MCK_LO64: return "MCK_LO64"; 4637 case MCK_PC: return "MCK_PC"; 4638 case MCK_SP64: return "MCK_SP64"; 4639 case MCK_Reg32: return "MCK_Reg32"; 4640 case MCK_Reg13: return "MCK_Reg13"; 4641 case MCK_Reg33: return "MCK_Reg33"; 4642 case MCK_Reg31: return "MCK_Reg31"; 4643 case MCK_Reg30: return "MCK_Reg30"; 4644 case MCK_Reg14: return "MCK_Reg14"; 4645 case MCK_Reg11: return "MCK_Reg11"; 4646 case MCK_GPRMM16MovePPairFirst: return "MCK_GPRMM16MovePPairFirst"; 4647 case MCK_OCTEON_MPL: return "MCK_OCTEON_MPL"; 4648 case MCK_OCTEON_P: return "MCK_OCTEON_P"; 4649 case MCK_Reg28: return "MCK_Reg28"; 4650 case MCK_Reg23: return "MCK_Reg23"; 4651 case MCK_Reg9: return "MCK_Reg9"; 4652 case MCK_Reg4: return "MCK_Reg4"; 4653 case MCK_ACC64DSP: return "MCK_ACC64DSP"; 4654 case MCK_HI32DSP: return "MCK_HI32DSP"; 4655 case MCK_LO32DSP: return "MCK_LO32DSP"; 4656 case MCK_Reg34: return "MCK_Reg34"; 4657 case MCK_GPRMM16MovePPairSecond: return "MCK_GPRMM16MovePPairSecond"; 4658 case MCK_Reg29: return "MCK_Reg29"; 4659 case MCK_Reg27: return "MCK_Reg27"; 4660 case MCK_Reg10: return "MCK_Reg10"; 4661 case MCK_Reg8: return "MCK_Reg8"; 4662 case MCK_Reg25: return "MCK_Reg25"; 4663 case MCK_Reg22: return "MCK_Reg22"; 4664 case MCK_Reg21: return "MCK_Reg21"; 4665 case MCK_CPU16Regs: return "MCK_CPU16Regs"; 4666 case MCK_FCC: return "MCK_FCC"; 4667 case MCK_GPRMM16MoveP: return "MCK_GPRMM16MoveP"; 4668 case MCK_GPRMM16Zero: return "MCK_GPRMM16Zero"; 4669 case MCK_Reg26: return "MCK_Reg26"; 4670 case MCK_CPU16RegsPlusSP: return "MCK_CPU16RegsPlusSP"; 4671 case MCK_AFGR64: return "MCK_AFGR64"; 4672 case MCK_MSA128WEvens: return "MCK_MSA128WEvens"; 4673 case MCK_Reg24: return "MCK_Reg24"; 4674 case MCK_GPR32NONZERO: return "MCK_GPR32NONZERO"; 4675 case MCK_CCR: return "MCK_CCR"; 4676 case MCK_COP0: return "MCK_COP0"; 4677 case MCK_COP2: return "MCK_COP2"; 4678 case MCK_COP3: return "MCK_COP3"; 4679 case MCK_DSPR: return "MCK_DSPR"; 4680 case MCK_FGR32: return "MCK_FGR32"; 4681 case MCK_FGR64: return "MCK_FGR64"; 4682 case MCK_GPR64: return "MCK_GPR64"; 4683 case MCK_HWRegs: return "MCK_HWRegs"; 4684 case MCK_MSA128F16: return "MCK_MSA128F16"; 4685 case MCK_MSACtrl: return "MCK_MSACtrl"; 4686 case MCK_ACC64DSPAsmReg: return "MCK_ACC64DSPAsmReg"; 4687 case MCK_AFGR64AsmReg: return "MCK_AFGR64AsmReg"; 4688 case MCK_CCRAsmReg: return "MCK_CCRAsmReg"; 4689 case MCK_COP0AsmReg: return "MCK_COP0AsmReg"; 4690 case MCK_COP2AsmReg: return "MCK_COP2AsmReg"; 4691 case MCK_COP3AsmReg: return "MCK_COP3AsmReg"; 4692 case MCK_FCCAsmReg: return "MCK_FCCAsmReg"; 4693 case MCK_FGR32AsmReg: return "MCK_FGR32AsmReg"; 4694 case MCK_FGR64AsmReg: return "MCK_FGR64AsmReg"; 4695 case MCK_GPR32AsmReg: return "MCK_GPR32AsmReg"; 4696 case MCK_GPR32NonZeroAsmReg: return "MCK_GPR32NonZeroAsmReg"; 4697 case MCK_GPR32ZeroAsmReg: return "MCK_GPR32ZeroAsmReg"; 4698 case MCK_GPR64AsmReg: return "MCK_GPR64AsmReg"; 4699 case MCK_GPRMM16AsmReg: return "MCK_GPRMM16AsmReg"; 4700 case MCK_GPRMM16AsmRegMoveP: return "MCK_GPRMM16AsmRegMoveP"; 4701 case MCK_GPRMM16AsmRegMovePPairFirst: return "MCK_GPRMM16AsmRegMovePPairFirst"; 4702 case MCK_GPRMM16AsmRegMovePPairSecond: return "MCK_GPRMM16AsmRegMovePPairSecond"; 4703 case MCK_GPRMM16AsmRegZero: return "MCK_GPRMM16AsmRegZero"; 4704 case MCK_HI32DSPAsmReg: return "MCK_HI32DSPAsmReg"; 4705 case MCK_HWRegsAsmReg: return "MCK_HWRegsAsmReg"; 4706 case MCK_Imm: return "MCK_Imm"; 4707 case MCK_LO32DSPAsmReg: return "MCK_LO32DSPAsmReg"; 4708 case MCK_MSA128AsmReg: return "MCK_MSA128AsmReg"; 4709 case MCK_MSACtrlAsmReg: return "MCK_MSACtrlAsmReg"; 4710 case MCK_MicroMipsMemGP: return "MCK_MicroMipsMemGP"; 4711 case MCK_MicroMipsMem: return "MCK_MicroMipsMem"; 4712 case MCK_MicroMipsMemSP: return "MCK_MicroMipsMemSP"; 4713 case MCK_InvNum: return "MCK_InvNum"; 4714 case MCK_JumpTarget: return "MCK_JumpTarget"; 4715 case MCK_MemOffsetSimmPtr: return "MCK_MemOffsetSimmPtr"; 4716 case MCK_MemOffsetUimm4: return "MCK_MemOffsetUimm4"; 4717 case MCK_MemOffsetSimm9_0: return "MCK_MemOffsetSimm9_0"; 4718 case MCK_MemOffsetSimm10_0: return "MCK_MemOffsetSimm10_0"; 4719 case MCK_MemOffsetSimm11_0: return "MCK_MemOffsetSimm11_0"; 4720 case MCK_MemOffsetSimm12_0: return "MCK_MemOffsetSimm12_0"; 4721 case MCK_MemOffsetSimm16_0: return "MCK_MemOffsetSimm16_0"; 4722 case MCK_MemOffsetSimm10_1: return "MCK_MemOffsetSimm10_1"; 4723 case MCK_MemOffsetSimm10_2: return "MCK_MemOffsetSimm10_2"; 4724 case MCK_MemOffsetSimm10_3: return "MCK_MemOffsetSimm10_3"; 4725 case MCK_Mem: return "MCK_Mem"; 4726 case MCK_RegList16: return "MCK_RegList16"; 4727 case MCK_RegList: return "MCK_RegList"; 4728 case MCK_Simm19_Lsl2: return "MCK_Simm19_Lsl2"; 4729 case MCK_StrictlyAFGR64AsmReg: return "MCK_StrictlyAFGR64AsmReg"; 4730 case MCK_StrictlyFGR32AsmReg: return "MCK_StrictlyFGR32AsmReg"; 4731 case MCK_StrictlyFGR64AsmReg: return "MCK_StrictlyFGR64AsmReg"; 4732 case MCK_ConstantImmz: return "MCK_ConstantImmz"; 4733 case MCK_ConstantUImm1_0: return "MCK_ConstantUImm1_0"; 4734 case MCK_ConstantUImm2_0: return "MCK_ConstantUImm2_0"; 4735 case MCK_ConstantUImm2_1: return "MCK_ConstantUImm2_1"; 4736 case MCK_ConstantUImm3_0: return "MCK_ConstantUImm3_0"; 4737 case MCK_ConstantSImm4_0: return "MCK_ConstantSImm4_0"; 4738 case MCK_ConstantUImm4_0: return "MCK_ConstantUImm4_0"; 4739 case MCK_ConstantSImm5_0: return "MCK_ConstantSImm5_0"; 4740 case MCK_ConstantUImm5_0: return "MCK_ConstantUImm5_0"; 4741 case MCK_ConstantUImm5_1: return "MCK_ConstantUImm5_1"; 4742 case MCK_ConstantUImm5_Plus1_Report_UImm6: return "MCK_ConstantUImm5_Plus1_Report_UImm6"; 4743 case MCK_ConstantUImm5_32_Norm: return "MCK_ConstantUImm5_32_Norm"; 4744 case MCK_ConstantUImm5_32: return "MCK_ConstantUImm5_32"; 4745 case MCK_ConstantUImm5_0_Report_UImm6: return "MCK_ConstantUImm5_0_Report_UImm6"; 4746 case MCK_ConstantUImm5_33: return "MCK_ConstantUImm5_33"; 4747 case MCK_ConstantUImmRange2_64: return "MCK_ConstantUImmRange2_64"; 4748 case MCK_UImm5Lsl2: return "MCK_UImm5Lsl2"; 4749 case MCK_ConstantSImm6_0: return "MCK_ConstantSImm6_0"; 4750 case MCK_ConstantUImm6_0: return "MCK_ConstantUImm6_0"; 4751 case MCK_UImm6Lsl2: return "MCK_UImm6Lsl2"; 4752 case MCK_ConstantUImm7_0: return "MCK_ConstantUImm7_0"; 4753 case MCK_UImm7_N1: return "MCK_UImm7_N1"; 4754 case MCK_ConstantUImm8_0: return "MCK_ConstantUImm8_0"; 4755 case MCK_SImm7Lsl2: return "MCK_SImm7Lsl2"; 4756 case MCK_ConstantSImm9_0: return "MCK_ConstantSImm9_0"; 4757 case MCK_ConstantSImm10_0: return "MCK_ConstantSImm10_0"; 4758 case MCK_ConstantUImm10_0: return "MCK_ConstantUImm10_0"; 4759 case MCK_SImm10Lsl1: return "MCK_SImm10Lsl1"; 4760 case MCK_ConstantSImm11_0: return "MCK_ConstantSImm11_0"; 4761 case MCK_SImm10Lsl2: return "MCK_SImm10Lsl2"; 4762 case MCK_SImm10Lsl3: return "MCK_SImm10Lsl3"; 4763 case MCK_SImm16: return "MCK_SImm16"; 4764 case MCK_SImm16_Relaxed: return "MCK_SImm16_Relaxed"; 4765 case MCK_UImm16_AltRelaxed: return "MCK_UImm16_AltRelaxed"; 4766 case MCK_UImm16: return "MCK_UImm16"; 4767 case MCK_SImm19Lsl2: return "MCK_SImm19Lsl2"; 4768 case MCK_UImm16_Relaxed: return "MCK_UImm16_Relaxed"; 4769 case MCK_ConstantUImm20_0: return "MCK_ConstantUImm20_0"; 4770 case MCK_ConstantUImm26_0: return "MCK_ConstantUImm26_0"; 4771 case MCK_SImm32: return "MCK_SImm32"; 4772 case MCK_SImm32_Relaxed: return "MCK_SImm32_Relaxed"; 4773 case MCK_UImm32_Coerced: return "MCK_UImm32_Coerced"; 4774 case NumMatchClassKinds: return "NumMatchClassKinds"; 4775 } 4776 llvm_unreachable("unhandled MatchClassKind!"); 4777} 4778 4779#endif // NDEBUG 4780FeatureBitset MipsAsmParser:: 4781ComputeAvailableFeatures(const FeatureBitset& FB) const { 4782 FeatureBitset Features; 4783 if ((FB[Mips::FeatureMips2])) 4784 Features.set(Feature_HasMips2Bit); 4785 if ((FB[Mips::FeatureMips3_32])) 4786 Features.set(Feature_HasMips3_32Bit); 4787 if ((FB[Mips::FeatureMips3_32r2])) 4788 Features.set(Feature_HasMips3_32r2Bit); 4789 if ((FB[Mips::FeatureMips3])) 4790 Features.set(Feature_HasMips3Bit); 4791 if ((!FB[Mips::FeatureMips3])) 4792 Features.set(Feature_NotMips3Bit); 4793 if ((FB[Mips::FeatureMips4_32])) 4794 Features.set(Feature_HasMips4_32Bit); 4795 if ((!FB[Mips::FeatureMips4_32])) 4796 Features.set(Feature_NotMips4_32Bit); 4797 if ((FB[Mips::FeatureMips4_32r2])) 4798 Features.set(Feature_HasMips4_32r2Bit); 4799 if ((FB[Mips::FeatureMips5_32r2])) 4800 Features.set(Feature_HasMips5_32r2Bit); 4801 if ((FB[Mips::FeatureMips32])) 4802 Features.set(Feature_HasMips32Bit); 4803 if ((FB[Mips::FeatureMips32r2])) 4804 Features.set(Feature_HasMips32r2Bit); 4805 if ((FB[Mips::FeatureMips32r5])) 4806 Features.set(Feature_HasMips32r5Bit); 4807 if ((FB[Mips::FeatureMips32r6])) 4808 Features.set(Feature_HasMips32r6Bit); 4809 if ((!FB[Mips::FeatureMips32r6])) 4810 Features.set(Feature_NotMips32r6Bit); 4811 if ((FB[Mips::FeatureGP64Bit])) 4812 Features.set(Feature_IsGP64bitBit); 4813 if ((!FB[Mips::FeatureGP64Bit])) 4814 Features.set(Feature_IsGP32bitBit); 4815 if ((FB[Mips::FeaturePTR64Bit])) 4816 Features.set(Feature_IsPTR64bitBit); 4817 if ((!FB[Mips::FeaturePTR64Bit])) 4818 Features.set(Feature_IsPTR32bitBit); 4819 if ((FB[Mips::FeatureMips64])) 4820 Features.set(Feature_HasMips64Bit); 4821 if ((!FB[Mips::FeatureMips64])) 4822 Features.set(Feature_NotMips64Bit); 4823 if ((FB[Mips::FeatureMips64r2])) 4824 Features.set(Feature_HasMips64r2Bit); 4825 if ((FB[Mips::FeatureMips64r5])) 4826 Features.set(Feature_HasMips64r5Bit); 4827 if ((FB[Mips::FeatureMips64r6])) 4828 Features.set(Feature_HasMips64r6Bit); 4829 if ((!FB[Mips::FeatureMips64r6])) 4830 Features.set(Feature_NotMips64r6Bit); 4831 if ((FB[Mips::FeatureMips16])) 4832 Features.set(Feature_InMips16ModeBit); 4833 if ((!FB[Mips::FeatureMips16])) 4834 Features.set(Feature_NotInMips16ModeBit); 4835 if ((FB[Mips::FeatureCnMips])) 4836 Features.set(Feature_HasCnMipsBit); 4837 if ((!FB[Mips::FeatureCnMips])) 4838 Features.set(Feature_NotCnMipsBit); 4839 if ((FB[Mips::FeatureCnMipsP])) 4840 Features.set(Feature_HasCnMipsPBit); 4841 if ((!FB[Mips::FeatureCnMipsP])) 4842 Features.set(Feature_NotCnMipsPBit); 4843 if ((FB[Mips::FeatureSym32])) 4844 Features.set(Feature_IsSym32Bit); 4845 if ((!FB[Mips::FeatureSym32])) 4846 Features.set(Feature_IsSym64Bit); 4847 if ((!FB[Mips::FeatureMips16])) 4848 Features.set(Feature_HasStdEncBit); 4849 if ((FB[Mips::FeatureMicroMips])) 4850 Features.set(Feature_InMicroMipsBit); 4851 if ((!FB[Mips::FeatureMicroMips])) 4852 Features.set(Feature_NotInMicroMipsBit); 4853 if ((FB[Mips::FeatureEVA])) 4854 Features.set(Feature_HasEVABit); 4855 if ((FB[Mips::FeatureMSA])) 4856 Features.set(Feature_HasMSABit); 4857 if ((!FB[Mips::FeatureMadd4])) 4858 Features.set(Feature_HasMadd4Bit); 4859 if ((FB[Mips::FeatureMT])) 4860 Features.set(Feature_HasMTBit); 4861 if ((FB[Mips::FeatureUseIndirectJumpsHazard])) 4862 Features.set(Feature_UseIndirectJumpsHazardBit); 4863 if ((!FB[Mips::FeatureUseIndirectJumpsHazard])) 4864 Features.set(Feature_NoIndirectJumpGuardsBit); 4865 if ((FB[Mips::FeatureCRC])) 4866 Features.set(Feature_HasCRCBit); 4867 if ((FB[Mips::FeatureVirt])) 4868 Features.set(Feature_HasVirtBit); 4869 if ((FB[Mips::FeatureGINV])) 4870 Features.set(Feature_HasGINVBit); 4871 if ((FB[Mips::FeatureFP64Bit])) 4872 Features.set(Feature_IsFP64bitBit); 4873 if ((!FB[Mips::FeatureFP64Bit])) 4874 Features.set(Feature_NotFP64bitBit); 4875 if ((FB[Mips::FeatureSingleFloat])) 4876 Features.set(Feature_IsSingleFloatBit); 4877 if ((!FB[Mips::FeatureSingleFloat])) 4878 Features.set(Feature_IsNotSingleFloatBit); 4879 if ((!FB[Mips::FeatureSoftFloat])) 4880 Features.set(Feature_IsNotSoftFloatBit); 4881 if ((FB[Mips::FeatureDSP])) 4882 Features.set(Feature_HasDSPBit); 4883 if ((FB[Mips::FeatureDSPR2])) 4884 Features.set(Feature_HasDSPR2Bit); 4885 if ((FB[Mips::FeatureDSPR3])) 4886 Features.set(Feature_HasDSPR3Bit); 4887 return Features; 4888} 4889 4890static bool checkAsmTiedOperandConstraints(const MipsAsmParser&AsmParser, 4891 unsigned Kind, 4892 const OperandVector &Operands, 4893 uint64_t &ErrorInfo) { 4894 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); 4895 const uint8_t *Converter = ConversionTable[Kind]; 4896 for (const uint8_t *p = Converter; *p; p+= 2) { 4897 switch (*p) { 4898 case CVT_Tied: { 4899 unsigned OpIdx = *(p+1); 4900 assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) - 4901 std::begin(TiedAsmOperandTable)) && 4902 "Tied operand not found"); 4903 unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1]; 4904 unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2]; 4905 if (OpndNum1 != OpndNum2) { 4906 auto &SrcOp1 = Operands[OpndNum1]; 4907 auto &SrcOp2 = Operands[OpndNum2]; 4908 if (SrcOp1->isReg() && SrcOp2->isReg()) { 4909 if (!AsmParser.regsEqual(*SrcOp1, *SrcOp2)) { 4910 ErrorInfo = OpndNum2; 4911 return false; 4912 } 4913 } 4914 } 4915 break; 4916 } 4917 default: 4918 break; 4919 } 4920 } 4921 return true; 4922} 4923 4924static const char *const MnemonicTable = 4925 "\003abs\005abs.d\005abs.s\tabsq_s.ph\tabsq_s.qb\010absq_s.w\003add\005a" 4926 "dd.d\005add.s\007add_a.b\007add_a.d\007add_a.h\007add_a.w\004addi\005ad" 4927 "diu\007addiupc\taddiur1sp\007addiur2\007addius5\007addiusp\007addq.ph\t" 4928 "addq_s.ph\010addq_s.w\010addqh.ph\007addqh.w\naddqh_r.ph\taddqh_r.w\010" 4929 "adds_a.b\010adds_a.d\010adds_a.h\010adds_a.w\010adds_s.b\010adds_s.d\010" 4930 "adds_s.h\010adds_s.w\010adds_u.b\010adds_u.d\010adds_u.h\010adds_u.w\005" 4931 "addsc\004addu\007addu.ph\007addu.qb\006addu16\taddu_s.ph\taddu_s.qb\010" 4932 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"copy_s.h\010copy_s.w\010copy_u.b\010copy_u.h\010copy_u.w\006crc32b\007c" 4981 "rc32cb\007crc32cd\007crc32ch\007crc32cw\006crc32d\006crc32h\006crc32w\004" 4982 "ctc1\004ctc2\006ctcmsa\005cttc1\007cvt.d.l\007cvt.d.s\007cvt.d.w\007cvt" 4983 ".l.d\007cvt.l.s\010cvt.ps.s\007cvt.s.d\007cvt.s.l\010cvt.s.pl\010cvt.s." 4984 "pu\007cvt.s.w\007cvt.w.d\007cvt.w.s\004dadd\005daddi\006daddiu\005daddu" 4985 "\004dahi\006dalign\004dati\004daui\010dbitswap\004dclo\004dclz\004ddiv\005" 4986 "ddivu\005deret\004dext\005dextm\005dextu\002di\004dins\005dinsm\005dins" 4987 "u\003div\005div.d\005div.s\007div_s.b\007div_s.d\007div_s.h\007div_s.w\007" 4988 "div_u.b\007div_u.d\007div_u.h\007div_u.w\004divu\003dla\003dli\004dlsa\005" 4989 "dmfc0\005dmfc1\005dmfc2\006dmfgc0\004dmod\005dmodu\003dmt\005dmtc0\005d" 4990 "mtc1\005dmtc2\006dmtgc0\004dmuh\005dmuhu\004dmul\005dmulo\006dmulou\005" 4991 "dmult\006dmultu\005dmulu\004dneg\005dnegu\010dotp_s.d\010dotp_s.h\010do" 4992 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"fsor.d\006fsor.w\007fsqrt.d\007fsqrt.w\006fsub.d\006fsub.w\007fsueq.d\007" 5017 "fsueq.w\007fsule.d\007fsule.w\007fsult.d\007fsult.w\006fsun.d\006fsun.w" 5018 "\007fsune.d\007fsune.w\tftint_s.d\tftint_s.w\tftint_u.d\tftint_u.w\005f" 5019 "tq.h\005ftq.w\nftrunc_s.d\nftrunc_s.w\nftrunc_u.d\nftrunc_u.w\005ginvi\005" 5020 "ginvt\010hadd_s.d\010hadd_s.h\010hadd_s.w\010hadd_u.d\010hadd_u.h\010ha" 5021 "dd_u.w\010hsub_s.d\010hsub_s.h\010hsub_s.w\010hsub_u.d\010hsub_u.h\010h" 5022 "sub_u.w\007hypcall\007ilvev.b\007ilvev.d\007ilvev.h\007ilvev.w\006ilvl." 5023 "b\006ilvl.d\006ilvl.h\006ilvl.w\007ilvod.b\007ilvod.d\007ilvod.h\007ilv" 5024 "od.w\006ilvr.b\006ilvr.d\006ilvr.h\006ilvr.w\003ins\010insert.b\010inse" 5025 "rt.d\010insert.h\010insert.w\004insv\007insve.b\007insve.d\007insve.h\007" 5026 "insve.w\001j\003jal\004jalr\007jalr.hb\005jalrc\010jalrc.hb\005jalrs\007" 5027 "jalrs16\004jals\004jalx\005jialc\003jic\002jr\005jr.hb\004jr16\tjraddiu" 5028 "sp\003jrc\005jrc16\njrcaddiusp\003l.d\003l.s\002la\004lapc\002lb\003lbe" 5029 "\003lbu\005lbu16\004lbue\004lbux\002ld\004ld.b\004ld.d\004ld.h\004ld.w\004" 5030 "ldc1\004ldc2\004ldc3\005ldi.b\005ldi.d\005ldi.h\005ldi.w\003ldl\004ldpc" 5031 "\003ldr\005ldxc1\002lh\003lhe\003lhu\005lhu16\004lhue\003lhx\002li\004l" 5032 "i.d\004li.s\004li16\002ll\003lld\003lle\003lsa\003lui\005luxc1\002lw\004" 5033 "lw16\004lwc1\004lwc2\004lwc3\003lwe\003lwl\004lwle\003lwm\005lwm16\005l" 5034 "wm32\003lwp\004lwpc\003lwr\004lwre\003lwu\005lwupc\003lwx\005lwxc1\004l" 5035 "wxs\004madd\006madd.d\006madd.s\010madd_q.h\010madd_q.w\007maddf.d\007m" 5036 "addf.s\tmaddr_q.h\tmaddr_q.w\005maddu\007maddv.b\007maddv.d\007maddv.h\007" 5037 "maddv.w\013maq_s.w.phl\013maq_s.w.phr\014maq_sa.w.phl\014maq_sa.w.phr\005" 5038 "max.d\005max.s\007max_a.b\007max_a.d\007max_a.h\007max_a.w\007max_s.b\007" 5039 "max_s.d\007max_s.h\007max_s.w\007max_u.b\007max_u.d\007max_u.h\007max_u" 5040 ".w\006maxa.d\006maxa.s\010maxi_s.b\010maxi_s.d\010maxi_s.h\010maxi_s.w\010" 5041 "maxi_u.b\010maxi_u.d\010maxi_u.h\010maxi_u.w\004mfc0\004mfc1\004mfc2\005" 5042 "mfgc0\005mfhc0\005mfhc1\005mfhc2\006mfhgc0\004mfhi\006mfhi16\004mflo\006" 5043 "mflo16\006mftacx\005mftc0\005mftc1\006mftdsp\006mftgpr\006mfthc1\005mft" 5044 "hi\005mftlo\004mftr\005min.d\005min.s\007min_a.b\007min_a.d\007min_a.h\007" 5045 "min_a.w\007min_s.b\007min_s.d\007min_s.h\007min_s.w\007min_u.b\007min_u" 5046 ".d\007min_u.h\007min_u.w\006mina.d\006mina.s\010mini_s.b\010mini_s.d\010" 5047 "mini_s.h\010mini_s.w\010mini_u.b\010mini_u.d\010mini_u.h\010mini_u.w\003" 5048 "mod\007mod_s.b\007mod_s.d\007mod_s.h\007mod_s.w\007mod_u.b\007mod_u.d\007" 5049 "mod_u.h\007mod_u.w\006modsub\004modu\005mov.d\005mov.s\004move\006move." 5050 "v\006move16\005movep\004movf\006movf.d\006movf.s\004movn\006movn.d\006m" 5051 "ovn.s\004movt\006movt.d\006movt.s\004movz\006movz.d\006movz.s\004msub\006" 5052 "msub.d\006msub.s\010msub_q.h\010msub_q.w\007msubf.d\007msubf.s\tmsubr_q" 5053 ".h\tmsubr_q.w\005msubu\007msubv.b\007msubv.d\007msubv.h\007msubv.w\004m" 5054 "tc0\004mtc1\004mtc2\005mtgc0\005mthc0\005mthc1\005mthc2\006mthgc0\004mt" 5055 "hi\006mthlip\004mtlo\004mtm0\004mtm1\004mtm2\004mtp0\004mtp1\004mtp2\006" 5056 "mttacx\005mttc0\005mttc1\006mttdsp\006mttgpr\006mtthc1\005mtthi\005mttl" 5057 "o\004mttr\003muh\004muhu\003mul\005mul.d\006mul.ph\005mul.s\007mul_q.h\007" 5058 "mul_q.w\010mul_s.ph\015muleq_s.w.phl\015muleq_s.w.phr\016muleu_s.ph.qbl" 5059 "\016muleu_s.ph.qbr\004mulo\005mulou\nmulq_rs.ph\tmulq_rs.w\tmulq_s.ph\010" 5060 "mulq_s.w\010mulr_q.h\010mulr_q.w\nmulsa.w.ph\015mulsaq_s.w.ph\004mult\005" 5061 "multu\004mulu\006mulv.b\006mulv.d\006mulv.h\006mulv.w\003neg\005neg.d\005" 5062 "neg.s\004negu\006nloc.b\006nloc.d\006nloc.h\006nloc.w\006nlzc.b\006nlzc" 5063 ".d\006nlzc.h\006nlzc.w\007nmadd.d\007nmadd.s\007nmsub.d\007nmsub.s\003n" 5064 "op\003nor\005nor.v\006nori.b\003not\005not16\002or\004or.v\004or16\003o" 5065 "ri\005ori.b\tpackrl.ph\005pause\007pckev.b\007pckev.d\007pckev.h\007pck" 5066 "ev.w\007pckod.b\007pckod.d\007pckod.h\007pckod.w\006pcnt.b\006pcnt.d\006" 5067 "pcnt.h\006pcnt.w\007pick.ph\007pick.qb\006pll.ps\006plu.ps\003pop\014pr" 5068 "eceq.w.phl\014preceq.w.phr\016precequ.ph.qbl\017precequ.ph.qbla\016prec" 5069 "equ.ph.qbr\017precequ.ph.qbra\015preceu.ph.qbl\016preceu.ph.qbla\015pre" 5070 "ceu.ph.qbr\016preceu.ph.qbra\013precr.qb.ph\016precr_sra.ph.w\020precr_" 5071 "sra_r.ph.w\013precrq.ph.w\014precrq.qb.ph\016precrq_rs.ph.w\017precrqu_" 5072 "s.qb.ph\004pref\005prefe\005prefx\007prepend\nraddu.w.qb\005rddsp\005rd" 5073 "hwr\006rdpgpr\007recip.d\007recip.s\003rem\004remu\007repl.ph\007repl.q" 5074 "b\010replv.ph\010replv.qb\006rint.d\006rint.s\003rol\003ror\004rotr\005" 5075 "rotrv\tround.l.d\tround.l.s\tround.w.d\tround.w.s\007rsqrt.d\007rsqrt.s" 5076 "\003s.d\003s.s\003saa\004saad\007sat_s.b\007sat_s.d\007sat_s.h\007sat_s" 5077 ".w\007sat_u.b\007sat_u.d\007sat_u.h\007sat_u.w\002sb\004sb16\003sbe\002" 5078 "sc\003scd\003sce\002sd\005sdbbp\007sdbbp16\004sdc1\004sdc2\004sdc3\003s" 5079 "dl\003sdr\005sdxc1\003seb\003seh\005sel.d\005sel.s\006seleqz\010seleqz." 5080 "d\010seleqz.s\006selnez\010selnez.d\010selnez.s\003seq\004seqi\003sge\004" 5081 "sgeu\003sgt\004sgtu\002sh\004sh16\003she\005shf.b\005shf.h\005shf.w\005" 5082 "shilo\006shilov\007shll.ph\007shll.qb\tshll_s.ph\010shll_s.w\010shllv.p" 5083 "h\010shllv.qb\nshllv_s.ph\tshllv_s.w\007shra.ph\007shra.qb\tshra_r.ph\t" 5084 "shra_r.qb\010shra_r.w\010shrav.ph\010shrav.qb\nshrav_r.ph\nshrav_r.qb\t" 5085 "shrav_r.w\007shrl.ph\007shrl.qb\010shrlv.ph\010shrlv.qb\006sigrie\005sl" 5086 "d.b\005sld.d\005sld.h\005sld.w\006sldi.b\006sldi.d\006sldi.h\006sldi.w\003" 5087 "sll\005sll.b\005sll.d\005sll.h\005sll.w\005sll16\006slli.b\006slli.d\006" 5088 "slli.h\006slli.w\004sllv\003slt\004slti\005sltiu\004sltu\003sne\004snei" 5089 "\007splat.b\007splat.d\007splat.h\007splat.w\010splati.b\010splati.d\010" 5090 "splati.h\010splati.w\006sqrt.d\006sqrt.s\003sra\005sra.b\005sra.d\005sr" 5091 "a.h\005sra.w\006srai.b\006srai.d\006srai.h\006srai.w\006srar.b\006srar." 5092 "d\006srar.h\006srar.w\007srari.b\007srari.d\007srari.h\007srari.w\004sr" 5093 "av\003srl\005srl.b\005srl.d\005srl.h\005srl.w\005srl16\006srli.b\006srl" 5094 "i.d\006srli.h\006srli.w\006srlr.b\006srlr.d\006srlr.h\006srlr.w\007srlr" 5095 "i.b\007srlri.d\007srlri.h\007srlri.w\004srlv\005ssnop\004st.b\004st.d\004" 5096 "st.h\004st.w\003sub\005sub.d\005sub.s\007subq.ph\tsubq_s.ph\010subq_s.w" 5097 "\010subqh.ph\007subqh.w\nsubqh_r.ph\tsubqh_r.w\010subs_s.b\010subs_s.d\010" 5098 "subs_s.h\010subs_s.w\010subs_u.b\010subs_u.d\010subs_u.h\010subs_u.w\ns" 5099 "ubsus_u.b\nsubsus_u.d\nsubsus_u.h\nsubsus_u.w\nsubsuu_s.b\nsubsuu_s.d\n" 5100 "subsuu_s.h\nsubsuu_s.w\004subu\007subu.ph\007subu.qb\006subu16\tsubu_s." 5101 "ph\tsubu_s.qb\010subuh.qb\nsubuh_r.qb\006subv.b\006subv.d\006subv.h\006" 5102 "subv.w\007subvi.b\007subvi.d\007subvi.h\007subvi.w\005suxc1\002sw\004sw" 5103 "16\004swc1\004swc2\004swc3\003swe\003swl\004swle\003swm\005swm16\005swm" 5104 "32\003swp\003swr\004swre\004swsp\005swxc1\004sync\005synci\nsynciobdma\005" 5105 "syncs\005syncw\006syncws\007syscall\003teq\004teqi\003tge\004tgei\005tg" 5106 "eiu\004tgeu\007tlbginv\010tlbginvf\005tlbgp\005tlbgr\006tlbgwi\006tlbgw" 5107 "r\006tlbinv\007tlbinvf\004tlbp\004tlbr\005tlbwi\005tlbwr\003tlt\004tlti" 5108 "\005tltiu\004tltu\003tne\004tnei\ttrunc.l.d\ttrunc.l.s\ttrunc.w.d\ttrun" 5109 "c.w.s\003ulh\004ulhu\003ulw\003ush\003usw\006v3mulu\004vmm0\005vmulu\006" 5110 "vshf.b\006vshf.d\006vshf.h\006vshf.w\004wait\005wrdsp\006wrpgpr\004wsbh" 5111 "\003xor\005xor.v\005xor16\004xori\006xori.b\005yield"; 5112 5113// Feature bitsets. 5114enum : uint8_t { 5115 AMFBS_None, 5116 AMFBS_HasCnMips, 5117 AMFBS_HasCnMipsP, 5118 AMFBS_HasDSP, 5119 AMFBS_HasDSPR2, 5120 AMFBS_HasMT, 5121 AMFBS_InMicroMips, 5122 AMFBS_InMips16Mode, 5123 AMFBS_IsGP32bit, 5124 AMFBS_IsGP64bit, 5125 AMFBS_IsNotSoftFloat, 5126 AMFBS_NotCnMips, 5127 AMFBS_NotInMicroMips, 5128 AMFBS_HasDSP_InMicroMips, 5129 AMFBS_HasDSP_NotInMicroMips, 5130 AMFBS_HasMT_NotInMicroMips, 5131 AMFBS_HasMips64_HasCnMips, 5132 AMFBS_HasStdEnc_HasMSA, 5133 AMFBS_HasStdEnc_HasMips3, 5134 AMFBS_HasStdEnc_HasMips32, 5135 AMFBS_HasStdEnc_HasMips32r6, 5136 AMFBS_HasStdEnc_HasMips64, 5137 AMFBS_HasStdEnc_HasMips64r6, 5138 AMFBS_HasStdEnc_IsNotSoftFloat, 5139 AMFBS_HasStdEnc_NotInMicroMips, 5140 AMFBS_HasStdEnc_NotMips3, 5141 AMFBS_InMicroMips_HasDSP, 5142 AMFBS_InMicroMips_HasDSPR2, 5143 AMFBS_InMicroMips_HasDSPR3, 5144 AMFBS_InMicroMips_HasEVA, 5145 AMFBS_InMicroMips_HasMips32r6, 5146 AMFBS_InMicroMips_IsNotSoftFloat, 5147 AMFBS_InMicroMips_NotMips32r6, 5148 AMFBS_IsFP64bit_IsNotSoftFloat, 5149 AMFBS_IsGP32bit_NotInMicroMips, 5150 AMFBS_IsGP64bit_NotInMicroMips, 5151 AMFBS_NotFP64bit_IsNotSoftFloat, 5152 AMFBS_NotInMips16Mode_HasDSP, 5153 AMFBS_NotInMips16Mode_IsPTR64bit, 5154 AMFBS_HasMips3_NotMips64r6_NotCnMips, 5155 AMFBS_HasMips64_HasCnMips_NotInMicroMips, 5156 AMFBS_HasStdEnc_HasMSA_HasMips64, 5157 AMFBS_HasStdEnc_HasMT_NotInMicroMips, 5158 AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat, 5159 AMFBS_HasStdEnc_HasMips2_NotInMicroMips, 5160 AMFBS_HasStdEnc_HasMips3_NotInMicroMips, 5161 AMFBS_HasStdEnc_HasMips32_NotInMicroMips, 5162 AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, 5163 AMFBS_HasStdEnc_HasMips32r5_NotInMicroMips, 5164 AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, 5165 AMFBS_HasStdEnc_HasMips3_32_NotInMicroMips, 5166 AMFBS_HasStdEnc_HasMips64_NotInMicroMips, 5167 AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, 5168 AMFBS_HasStdEnc_HasMips64r5_HasVirt, 5169 AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, 5170 AMFBS_HasStdEnc_IsGP32bit_HasMips32r6, 5171 AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, 5172 AMFBS_HasStdEnc_IsGP64bit_HasMips3, 5173 AMFBS_HasStdEnc_IsGP64bit_HasMips32r6, 5174 AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, 5175 AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, 5176 AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, 5177 AMFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, 5178 AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, 5179 AMFBS_InMicroMips_HasMips32r5_HasVirt, 5180 AMFBS_InMicroMips_HasMips32r6_HasGINV, 5181 AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, 5182 AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, 5183 AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, 5184 AMFBS_InMicroMips_NotMips32r6_HasDSP, 5185 AMFBS_InMicroMips_NotMips32r6_HasEVA, 5186 AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, 5187 AMFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips, 5188 AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, 5189 AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, 5190 AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, 5191 AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, 5192 AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, 5193 AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, 5194 AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, 5195 AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6, 5196 AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, 5197 AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, 5198 AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, 5199 AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, 5200 AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, 5201 AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, 5202 AMFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips, 5203 AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips, 5204 AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, 5205 AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat, 5206 AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, 5207 AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, 5208 AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, 5209 AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, 5210 AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, 5211 AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat, 5212 AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, 5213 AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, 5214 AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, 5215 AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, 5216 AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, 5217 AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, 5218 AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, 5219 AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, 5220 AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, 5221 AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, 5222 AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, 5223 AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, 5224 AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, 5225 AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, 5226 AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, 5227 AMFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, 5228 AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, 5229 AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, 5230 AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, 5231 AMFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, 5232 AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, 5233 AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 5234 AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, 5235 AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, 5236 AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 5237 AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, 5238 AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 5239 AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, 5240 AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 5241 AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, 5242 AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, 5243 AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 5244 AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, 5245 AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, 5246 AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 5247 AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 5248 AMFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 5249 AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 5250 AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 5251 AMFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 5252 AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, 5253 AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, 5254 AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, 5255 AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, 5256}; 5257 5258static constexpr FeatureBitset FeatureBitsets[] = { 5259 {}, // AMFBS_None 5260 {Feature_HasCnMipsBit, }, 5261 {Feature_HasCnMipsPBit, }, 5262 {Feature_HasDSPBit, }, 5263 {Feature_HasDSPR2Bit, }, 5264 {Feature_HasMTBit, }, 5265 {Feature_InMicroMipsBit, }, 5266 {Feature_InMips16ModeBit, }, 5267 {Feature_IsGP32bitBit, }, 5268 {Feature_IsGP64bitBit, }, 5269 {Feature_IsNotSoftFloatBit, }, 5270 {Feature_NotCnMipsBit, }, 5271 {Feature_NotInMicroMipsBit, }, 5272 {Feature_HasDSPBit, Feature_InMicroMipsBit, }, 5273 {Feature_HasDSPBit, Feature_NotInMicroMipsBit, }, 5274 {Feature_HasMTBit, Feature_NotInMicroMipsBit, }, 5275 {Feature_HasMips64Bit, Feature_HasCnMipsBit, }, 5276 {Feature_HasStdEncBit, Feature_HasMSABit, }, 5277 {Feature_HasStdEncBit, Feature_HasMips3Bit, }, 5278 {Feature_HasStdEncBit, Feature_HasMips32Bit, }, 5279 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, }, 5280 {Feature_HasStdEncBit, Feature_HasMips64Bit, }, 5281 {Feature_HasStdEncBit, Feature_HasMips64r6Bit, }, 5282 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, }, 5283 {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, }, 5284 {Feature_HasStdEncBit, Feature_NotMips3Bit, }, 5285 {Feature_InMicroMipsBit, Feature_HasDSPBit, }, 5286 {Feature_InMicroMipsBit, Feature_HasDSPR2Bit, }, 5287 {Feature_InMicroMipsBit, Feature_HasDSPR3Bit, }, 5288 {Feature_InMicroMipsBit, Feature_HasEVABit, }, 5289 {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, }, 5290 {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, }, 5291 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, }, 5292 {Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, }, 5293 {Feature_IsGP32bitBit, Feature_NotInMicroMipsBit, }, 5294 {Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, }, 5295 {Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, 5296 {Feature_NotInMips16ModeBit, Feature_HasDSPBit, }, 5297 {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, }, 5298 {Feature_HasMips3Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, }, 5299 {Feature_HasMips64Bit, Feature_HasCnMipsBit, Feature_NotInMicroMipsBit, }, 5300 {Feature_HasStdEncBit, Feature_HasMSABit, Feature_HasMips64Bit, }, 5301 {Feature_HasStdEncBit, Feature_HasMTBit, Feature_NotInMicroMipsBit, }, 5302 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, }, 5303 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotInMicroMipsBit, }, 5304 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotInMicroMipsBit, }, 5305 {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotInMicroMipsBit, }, 5306 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotInMicroMipsBit, }, 5307 {Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_NotInMicroMipsBit, }, 5308 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, 5309 {Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotInMicroMipsBit, }, 5310 {Feature_HasStdEncBit, Feature_HasMips64Bit, Feature_NotInMicroMipsBit, }, 5311 {Feature_HasStdEncBit, Feature_HasMips64r2Bit, Feature_NotInMicroMipsBit, }, 5312 {Feature_HasStdEncBit, Feature_HasMips64r5Bit, Feature_HasVirtBit, }, 5313 {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, }, 5314 {Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_HasMips32r6Bit, }, 5315 {Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_NotInMicroMipsBit, }, 5316 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips3Bit, }, 5317 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r6Bit, }, 5318 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64r6Bit, }, 5319 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 5320 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, 5321 {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, 5322 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, 5323 {Feature_InMicroMipsBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, }, 5324 {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, }, 5325 {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, }, 5326 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, }, 5327 {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, 5328 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasDSPBit, }, 5329 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasEVABit, }, 5330 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, 5331 {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NotInMicroMipsBit, }, 5332 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 5333 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, }, 5334 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, 5335 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 5336 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, 5337 {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, 5338 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, }, 5339 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, 5340 {Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, Feature_NotInMicroMipsBit, }, 5341 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, }, 5342 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, Feature_NotInMicroMipsBit, }, 5343 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 5344 {Feature_HasStdEncBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 5345 {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 5346 {Feature_HasStdEncBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 5347 {Feature_HasStdEncBit, Feature_HasMips64r5Bit, Feature_HasVirtBit, Feature_NotInMicroMipsBit, }, 5348 {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, }, 5349 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, }, 5350 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 5351 {Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, 5352 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips3Bit, Feature_NotInMicroMipsBit, }, 5353 {Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, 5354 {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, }, 5355 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, }, 5356 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 5357 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 5358 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, }, 5359 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, 5360 {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, 5361 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, }, 5362 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 5363 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 5364 {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 5365 {Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 5366 {Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 5367 {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, 5368 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 5369 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 5370 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 5371 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 5372 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 5373 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 5374 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 5375 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 5376 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 5377 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 5378 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, }, 5379 {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, }, 5380 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 5381 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, }, 5382 {Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 5383 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, 5384 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 5385 {Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 5386 {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 5387 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 5388 {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, 5389 {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, 5390 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 5391 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 5392 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 5393 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 5394 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 5395 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 5396 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, 5397 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, 5398 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, 5399 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, 5400}; 5401 5402namespace { 5403 struct MatchEntry { 5404 uint16_t Mnemonic; 5405 uint16_t Opcode; 5406 uint16_t ConvertFn; 5407 uint8_t RequiredFeaturesIdx; 5408 uint8_t Classes[8]; 5409 StringRef getMnemonic() const { 5410 return StringRef(MnemonicTable + Mnemonic + 1, 5411 MnemonicTable[Mnemonic]); 5412 } 5413 }; 5414 5415 // Predicate for searching for an opcode. 5416 struct LessOpcode { 5417 bool operator()(const MatchEntry &LHS, StringRef RHS) { 5418 return LHS.getMnemonic() < RHS; 5419 } 5420 bool operator()(StringRef LHS, const MatchEntry &RHS) { 5421 return LHS < RHS.getMnemonic(); 5422 } 5423 bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) { 5424 return LHS.getMnemonic() < RHS.getMnemonic(); 5425 } 5426 }; 5427} // end anonymous namespace 5428 5429static const MatchEntry MatchTable0[] = { 5430 { 0 /* abs */, Mips::ABSMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5431 { 4 /* abs.d */, Mips::FABS_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5432 { 4 /* abs.d */, Mips::FABS_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5433 { 4 /* abs.d */, Mips::FABS_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5434 { 4 /* abs.d */, Mips::FABS_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5435 { 10 /* abs.s */, Mips::FABS_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5436 { 10 /* abs.s */, Mips::FABS_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5437 { 16 /* absq_s.ph */, Mips::ABSQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5438 { 16 /* absq_s.ph */, Mips::ABSQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5439 { 26 /* absq_s.qb */, Mips::ABSQ_S_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5440 { 26 /* absq_s.qb */, Mips::ABSQ_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5441 { 36 /* absq_s.w */, Mips::ABSQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5442 { 36 /* absq_s.w */, Mips::ABSQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5443 { 45 /* add */, Mips::ADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5444 { 45 /* add */, Mips::ADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5445 { 45 /* add */, Mips::ADD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5446 { 45 /* add */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 5447 { 45 /* add */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 5448 { 45 /* add */, Mips::ADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5449 { 45 /* add */, Mips::ADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5450 { 45 /* add */, Mips::ADD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5451 { 45 /* add */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 5452 { 45 /* add */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 5453 { 49 /* add.d */, Mips::FADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5454 { 49 /* add.d */, Mips::FADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5455 { 49 /* add.d */, Mips::FADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5456 { 49 /* add.d */, Mips::FADD_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5457 { 55 /* add.s */, Mips::FADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5458 { 55 /* add.s */, Mips::FADD_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5459 { 55 /* add.s */, Mips::FADD_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5460 { 61 /* add_a.b */, Mips::ADD_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5461 { 69 /* add_a.d */, Mips::ADD_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5462 { 77 /* add_a.h */, Mips::ADD_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5463 { 85 /* add_a.w */, Mips::ADD_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5464 { 93 /* addi */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 5465 { 93 /* addi */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, }, 5466 { 93 /* addi */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, 5467 { 93 /* addi */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, }, 5468 { 98 /* addiu */, Mips::AddiuSpImmX16, Convert__SImm161_1, AMFBS_InMips16Mode, { MCK_CPUSPReg, MCK_SImm16 }, }, 5469 { 98 /* addiu */, Mips::AddiuRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, }, 5470 { 98 /* addiu */, Mips::ADDIU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 5471 { 98 /* addiu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 5472 { 98 /* addiu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, }, 5473 { 98 /* addiu */, Mips::AddiuRxPcImmX16, Convert__Reg1_0__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_PC, MCK_SImm16 }, }, 5474 { 98 /* addiu */, Mips::AddiuRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, }, 5475 { 98 /* addiu */, Mips::ADDIU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, 5476 { 98 /* addiu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, 5477 { 98 /* addiu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, }, 5478 { 98 /* addiu */, Mips::AddiuSpImm16, Convert__SImm161_1, AMFBS_InMips16Mode, { MCK_CPUSPReg, MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, }, 5479 { 98 /* addiu */, Mips::AddiuRxRxImm16, Convert__Reg1_0__Tie0_1_1__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, }, 5480 { 104 /* addiupc */, Mips::ADDIUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, }, 5481 { 104 /* addiupc */, Mips::ADDIUPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, }, 5482 { 104 /* addiupc */, Mips::ADDIUPC_MM, Convert__GPRMM16AsmReg1_0__Imm1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_Imm }, }, 5483 { 112 /* addiur1sp */, Mips::ADDIUR1SP_MM, Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_UImm6Lsl2 }, }, 5484 { 122 /* addiur2 */, Mips::ADDIUR2_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, }, 5485 { 130 /* addius5 */, Mips::ADDIUS5_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantSImm4_0 }, }, 5486 { 138 /* addiusp */, Mips::ADDIUSP_MM, Convert__Imm1_0, AMFBS_InMicroMips, { MCK_Imm }, }, 5487 { 146 /* addq.ph */, Mips::ADDQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5488 { 146 /* addq.ph */, Mips::ADDQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5489 { 154 /* addq_s.ph */, Mips::ADDQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5490 { 154 /* addq_s.ph */, Mips::ADDQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5491 { 164 /* addq_s.w */, Mips::ADDQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5492 { 164 /* addq_s.w */, Mips::ADDQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5493 { 173 /* addqh.ph */, Mips::ADDQH_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5494 { 173 /* addqh.ph */, Mips::ADDQH_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5495 { 182 /* addqh.w */, Mips::ADDQH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5496 { 182 /* addqh.w */, Mips::ADDQH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5497 { 190 /* addqh_r.ph */, Mips::ADDQH_R_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5498 { 190 /* addqh_r.ph */, Mips::ADDQH_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5499 { 201 /* addqh_r.w */, Mips::ADDQH_R_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5500 { 201 /* addqh_r.w */, Mips::ADDQH_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5501 { 211 /* adds_a.b */, Mips::ADDS_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5502 { 220 /* adds_a.d */, Mips::ADDS_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5503 { 229 /* adds_a.h */, Mips::ADDS_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5504 { 238 /* adds_a.w */, Mips::ADDS_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5505 { 247 /* adds_s.b */, Mips::ADDS_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5506 { 256 /* adds_s.d */, Mips::ADDS_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5507 { 265 /* adds_s.h */, Mips::ADDS_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5508 { 274 /* adds_s.w */, Mips::ADDS_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5509 { 283 /* adds_u.b */, Mips::ADDS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5510 { 292 /* adds_u.d */, Mips::ADDS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5511 { 301 /* adds_u.h */, Mips::ADDS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5512 { 310 /* adds_u.w */, Mips::ADDS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5513 { 319 /* addsc */, Mips::ADDSC_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5514 { 319 /* addsc */, Mips::ADDSC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5515 { 325 /* addu */, Mips::ADDU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5516 { 325 /* addu */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5517 { 325 /* addu */, Mips::ADDu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5518 { 325 /* addu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 5519 { 325 /* addu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 5520 { 325 /* addu */, Mips::AdduRxRyRz16, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_CPU16Regs }, }, 5521 { 325 /* addu */, Mips::ADDU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5522 { 325 /* addu */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5523 { 325 /* addu */, Mips::ADDu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5524 { 325 /* addu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 5525 { 325 /* addu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 5526 { 330 /* addu.ph */, Mips::ADDU_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5527 { 330 /* addu.ph */, Mips::ADDU_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5528 { 338 /* addu.qb */, Mips::ADDU_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5529 { 338 /* addu.qb */, Mips::ADDU_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5530 { 346 /* addu16 */, Mips::ADDU16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, 5531 { 346 /* addu16 */, Mips::ADDU16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, 5532 { 353 /* addu_s.ph */, Mips::ADDU_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5533 { 353 /* addu_s.ph */, Mips::ADDU_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5534 { 363 /* addu_s.qb */, Mips::ADDU_S_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5535 { 363 /* addu_s.qb */, Mips::ADDU_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5536 { 373 /* adduh.qb */, Mips::ADDUH_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5537 { 373 /* adduh.qb */, Mips::ADDUH_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5538 { 382 /* adduh_r.qb */, Mips::ADDUH_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5539 { 382 /* adduh_r.qb */, Mips::ADDUH_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5540 { 393 /* addv.b */, Mips::ADDV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5541 { 400 /* addv.d */, Mips::ADDV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5542 { 407 /* addv.h */, Mips::ADDV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5543 { 414 /* addv.w */, Mips::ADDV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5544 { 421 /* addvi.b */, Mips::ADDVI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 5545 { 429 /* addvi.d */, Mips::ADDVI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 5546 { 437 /* addvi.h */, Mips::ADDVI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 5547 { 445 /* addvi.w */, Mips::ADDVI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 5548 { 453 /* addwc */, Mips::ADDWC_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5549 { 453 /* addwc */, Mips::ADDWC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5550 { 459 /* align */, Mips::ALIGN, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, }, 5551 { 459 /* align */, Mips::ALIGN_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, }, 5552 { 465 /* aluipc */, Mips::ALUIPC, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 5553 { 465 /* aluipc */, Mips::ALUIPC_MMR6, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 5554 { 472 /* and */, Mips::AndRxRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, 5555 { 472 /* and */, Mips::AND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5556 { 472 /* and */, Mips::AND_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5557 { 472 /* and */, Mips::AND_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5558 { 472 /* and */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, 5559 { 472 /* and */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 5560 { 472 /* and */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 5561 { 472 /* and */, Mips::ANDi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, }, 5562 { 472 /* and */, Mips::AND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5563 { 472 /* and */, Mips::AND_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5564 { 472 /* and */, Mips::AND_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5565 { 472 /* and */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, 5566 { 472 /* and */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 5567 { 472 /* and */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 5568 { 472 /* and */, Mips::ANDi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, 5569 { 476 /* and.v */, Mips::AND_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5570 { 482 /* and16 */, Mips::AND16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, 5571 { 482 /* and16 */, Mips::AND16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, 5572 { 488 /* andi */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, 5573 { 488 /* andi */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, }, 5574 { 488 /* andi */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, 5575 { 488 /* andi */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, 5576 { 488 /* andi */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, 5577 { 488 /* andi */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, 5578 { 493 /* andi.b */, Mips::ANDI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, 5579 { 500 /* andi16 */, Mips::ANDI16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, }, 5580 { 500 /* andi16 */, Mips::ANDI16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, }, 5581 { 507 /* append */, Mips::APPEND_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 5582 { 507 /* append */, Mips::APPEND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 5583 { 514 /* asub_s.b */, Mips::ASUB_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5584 { 523 /* asub_s.d */, Mips::ASUB_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5585 { 532 /* asub_s.h */, Mips::ASUB_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5586 { 541 /* asub_s.w */, Mips::ASUB_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5587 { 550 /* asub_u.b */, Mips::ASUB_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5588 { 559 /* asub_u.d */, Mips::ASUB_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5589 { 568 /* asub_u.h */, Mips::ASUB_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5590 { 577 /* asub_u.w */, Mips::ASUB_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5591 { 586 /* aui */, Mips::AUI, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, 5592 { 586 /* aui */, Mips::AUI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, 5593 { 590 /* auipc */, Mips::AUIPC, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 5594 { 590 /* auipc */, Mips::AUIPC_MMR6, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 5595 { 596 /* ave_s.b */, Mips::AVE_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5596 { 604 /* ave_s.d */, Mips::AVE_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5597 { 612 /* ave_s.h */, Mips::AVE_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5598 { 620 /* ave_s.w */, Mips::AVE_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5599 { 628 /* ave_u.b */, Mips::AVE_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5600 { 636 /* ave_u.d */, Mips::AVE_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5601 { 644 /* ave_u.h */, Mips::AVE_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5602 { 652 /* ave_u.w */, Mips::AVE_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5603 { 660 /* aver_s.b */, Mips::AVER_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5604 { 669 /* aver_s.d */, Mips::AVER_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5605 { 678 /* aver_s.h */, Mips::AVER_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5606 { 687 /* aver_s.w */, Mips::AVER_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5607 { 696 /* aver_u.b */, Mips::AVER_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5608 { 705 /* aver_u.d */, Mips::AVER_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5609 { 714 /* aver_u.h */, Mips::AVER_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5610 { 723 /* aver_u.w */, Mips::AVER_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5611 { 732 /* b */, Mips::BEQ, Convert__regZERO__regZERO__JumpTarget1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_JumpTarget }, }, 5612 { 732 /* b */, Mips::B_MM_Pseudo, Convert__JumpTarget1_0, AMFBS_InMicroMips, { MCK_JumpTarget }, }, 5613 { 732 /* b */, Mips::BimmX16, Convert__JumpTarget1_0, AMFBS_InMips16Mode, { MCK_JumpTarget }, }, 5614 { 732 /* b */, Mips::B_MMR6_Pseudo, Convert__JumpTarget1_0, AMFBS_None, { MCK_JumpTarget }, }, 5615 { 732 /* b */, Mips::Bimm16, Convert__JumpTarget1_0, AMFBS_InMips16Mode, { MCK_JumpTarget, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, }, 5616 { 734 /* b16 */, Mips::BC16_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, }, 5617 { 734 /* b16 */, Mips::B16_MM, Convert__JumpTarget1_0, AMFBS_InMicroMips, { MCK_JumpTarget }, }, 5618 { 738 /* baddu */, Mips::BADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 5619 { 738 /* baddu */, Mips::BADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 5620 { 744 /* bal */, Mips::BGEZAL, Convert__regZERO__JumpTarget1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_JumpTarget }, }, 5621 { 744 /* bal */, Mips::BAL, Convert__JumpTarget1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_JumpTarget }, }, 5622 { 744 /* bal */, Mips::BGEZAL_MM, Convert__regZERO__JumpTarget1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_JumpTarget }, }, 5623 { 748 /* balc */, Mips::BALC, Convert__JumpTarget1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_JumpTarget }, }, 5624 { 748 /* balc */, Mips::BALC_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, }, 5625 { 753 /* balign */, Mips::BALIGN_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, }, 5626 { 753 /* balign */, Mips::BALIGN, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, }, 5627 { 760 /* bbit0 */, Mips::BBIT032, Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_JumpTarget }, }, 5628 { 760 /* bbit0 */, Mips::BBIT0, Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_JumpTarget }, }, 5629 { 766 /* bbit032 */, Mips::BBIT032, Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_JumpTarget }, }, 5630 { 774 /* bbit1 */, Mips::BBIT132, Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_JumpTarget }, }, 5631 { 774 /* bbit1 */, Mips::BBIT1, Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_JumpTarget }, }, 5632 { 780 /* bbit132 */, Mips::BBIT132, Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_JumpTarget }, }, 5633 { 788 /* bc */, Mips::BC, Convert__JumpTarget1_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_JumpTarget }, }, 5634 { 788 /* bc */, Mips::BC_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, }, 5635 { 791 /* bc16 */, Mips::BC16_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, }, 5636 { 796 /* bc1eqz */, Mips::BC1EQZ, Convert__FGR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_JumpTarget }, }, 5637 { 803 /* bc1eqzc */, Mips::BC1EQZC_MMR6, Convert__FGR64AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_JumpTarget }, }, 5638 { 811 /* bc1f */, Mips::BC1F, Convert__regFCC0__JumpTarget1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_JumpTarget }, }, 5639 { 811 /* bc1f */, Mips::BC1F_MM, Convert__regFCC0__JumpTarget1_0, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_JumpTarget }, }, 5640 { 811 /* bc1f */, Mips::BC1F, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, }, 5641 { 811 /* bc1f */, Mips::BC1F_MM, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_JumpTarget }, }, 5642 { 816 /* bc1fl */, Mips::BC1FL, Convert__regFCC0__JumpTarget1_0, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_JumpTarget }, }, 5643 { 816 /* bc1fl */, Mips::BC1FL, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, }, 5644 { 822 /* bc1nez */, Mips::BC1NEZ, Convert__FGR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_JumpTarget }, }, 5645 { 829 /* bc1nezc */, Mips::BC1NEZC_MMR6, Convert__FGR64AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_JumpTarget }, }, 5646 { 837 /* bc1t */, Mips::BC1T, Convert__regFCC0__JumpTarget1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_JumpTarget }, }, 5647 { 837 /* bc1t */, Mips::BC1T_MM, Convert__regFCC0__JumpTarget1_0, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_JumpTarget }, }, 5648 { 837 /* bc1t */, Mips::BC1T, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, }, 5649 { 837 /* bc1t */, Mips::BC1T_MM, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_JumpTarget }, }, 5650 { 842 /* bc1tl */, Mips::BC1TL, Convert__regFCC0__JumpTarget1_0, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_JumpTarget }, }, 5651 { 842 /* bc1tl */, Mips::BC1TL, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, }, 5652 { 848 /* bc2eqz */, Mips::BC2EQZ, Convert__COP2AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_JumpTarget }, }, 5653 { 855 /* bc2eqzc */, Mips::BC2EQZC_MMR6, Convert__COP2AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_JumpTarget }, }, 5654 { 863 /* bc2nez */, Mips::BC2NEZ, Convert__COP2AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_JumpTarget }, }, 5655 { 870 /* bc2nezc */, Mips::BC2NEZC_MMR6, Convert__COP2AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_JumpTarget }, }, 5656 { 878 /* bclr.b */, Mips::BCLR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5657 { 885 /* bclr.d */, Mips::BCLR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5658 { 892 /* bclr.h */, Mips::BCLR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5659 { 899 /* bclr.w */, Mips::BCLR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5660 { 906 /* bclri.b */, Mips::BCLRI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, 5661 { 914 /* bclri.d */, Mips::BCLRI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, 5662 { 922 /* bclri.h */, Mips::BCLRI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, 5663 { 930 /* bclri.w */, Mips::BCLRI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 5664 { 938 /* beq */, Mips::BEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5665 { 938 /* beq */, Mips::BEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5666 { 938 /* beq */, Mips::BeqImm, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5667 { 942 /* beqc */, Mips::BEQC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5668 { 942 /* beqc */, Mips::BEQC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5669 { 942 /* beqc */, Mips::BEQC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, }, 5670 { 947 /* beql */, Mips::BEQL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5671 { 947 /* beql */, Mips::BEQLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5672 { 952 /* beqz */, Mips::BeqzRxImmX16, Convert__Reg1_0__JumpTarget1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget }, }, 5673 { 952 /* beqz */, Mips::BEQ, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5674 { 952 /* beqz */, Mips::BEQ_MM, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5675 { 952 /* beqz */, Mips::BeqzRxImm16, Convert__Reg1_0__JumpTarget1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, }, 5676 { 957 /* beqz16 */, Mips::BEQZ16_MM, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, }, 5677 { 957 /* beqz16 */, Mips::BEQZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, }, 5678 { 964 /* beqzalc */, Mips::BEQZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5679 { 964 /* beqzalc */, Mips::BEQZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5680 { 972 /* beqzc */, Mips::BEQZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5681 { 972 /* beqzc */, Mips::BEQZC_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5682 { 972 /* beqzc */, Mips::BEQZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5683 { 972 /* beqzc */, Mips::BEQZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, 5684 { 978 /* beqzc16 */, Mips::BEQZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, }, 5685 { 986 /* beqzl */, Mips::BEQL, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5686 { 992 /* bge */, Mips::BGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5687 { 992 /* bge */, Mips::BGEImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5688 { 996 /* bgec */, Mips::BGEC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5689 { 996 /* bgec */, Mips::BGEC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5690 { 996 /* bgec */, Mips::BGEC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, }, 5691 { 1001 /* bgel */, Mips::BGEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5692 { 1001 /* bgel */, Mips::BGELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5693 { 1006 /* bgeu */, Mips::BGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5694 { 1006 /* bgeu */, Mips::BGEUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5695 { 1011 /* bgeuc */, Mips::BGEUC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5696 { 1011 /* bgeuc */, Mips::BGEUC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5697 { 1011 /* bgeuc */, Mips::BGEUC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, }, 5698 { 1017 /* bgeul */, Mips::BGEUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5699 { 1017 /* bgeul */, Mips::BGEULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5700 { 1023 /* bgez */, Mips::BGEZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5701 { 1023 /* bgez */, Mips::BGEZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5702 { 1028 /* bgezal */, Mips::BGEZAL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5703 { 1028 /* bgezal */, Mips::BGEZAL_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5704 { 1035 /* bgezalc */, Mips::BGEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5705 { 1035 /* bgezalc */, Mips::BGEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5706 { 1043 /* bgezall */, Mips::BGEZALL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5707 { 1051 /* bgezals */, Mips::BGEZALS_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5708 { 1059 /* bgezc */, Mips::BGEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5709 { 1059 /* bgezc */, Mips::BGEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5710 { 1059 /* bgezc */, Mips::BGEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, 5711 { 1065 /* bgezl */, Mips::BGEZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5712 { 1071 /* bgt */, Mips::BGT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5713 { 1071 /* bgt */, Mips::BGTImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5714 { 1075 /* bgtl */, Mips::BGTL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5715 { 1075 /* bgtl */, Mips::BGTLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5716 { 1080 /* bgtu */, Mips::BGTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5717 { 1080 /* bgtu */, Mips::BGTUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5718 { 1085 /* bgtul */, Mips::BGTUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5719 { 1085 /* bgtul */, Mips::BGTULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5720 { 1091 /* bgtz */, Mips::BGTZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5721 { 1091 /* bgtz */, Mips::BGTZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5722 { 1096 /* bgtzalc */, Mips::BGTZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5723 { 1096 /* bgtzalc */, Mips::BGTZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5724 { 1104 /* bgtzc */, Mips::BGTZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5725 { 1104 /* bgtzc */, Mips::BGTZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5726 { 1104 /* bgtzc */, Mips::BGTZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, 5727 { 1110 /* bgtzl */, Mips::BGTZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5728 { 1116 /* binsl.b */, Mips::BINSL_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5729 { 1124 /* binsl.d */, Mips::BINSL_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5730 { 1132 /* binsl.h */, Mips::BINSL_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5731 { 1140 /* binsl.w */, Mips::BINSL_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5732 { 1148 /* binsli.b */, Mips::BINSLI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, 5733 { 1157 /* binsli.d */, Mips::BINSLI_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, 5734 { 1166 /* binsli.h */, Mips::BINSLI_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, 5735 { 1175 /* binsli.w */, Mips::BINSLI_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 5736 { 1184 /* binsr.b */, Mips::BINSR_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5737 { 1192 /* binsr.d */, Mips::BINSR_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5738 { 1200 /* binsr.h */, Mips::BINSR_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5739 { 1208 /* binsr.w */, Mips::BINSR_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5740 { 1216 /* binsri.b */, Mips::BINSRI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, 5741 { 1225 /* binsri.d */, Mips::BINSRI_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, 5742 { 1234 /* binsri.h */, Mips::BINSRI_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, 5743 { 1243 /* binsri.w */, Mips::BINSRI_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 5744 { 1252 /* bitrev */, Mips::BITREV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5745 { 1252 /* bitrev */, Mips::BITREV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5746 { 1259 /* bitswap */, Mips::BITSWAP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5747 { 1259 /* bitswap */, Mips::BITSWAP_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5748 { 1267 /* ble */, Mips::BLE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5749 { 1267 /* ble */, Mips::BLEImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5750 { 1271 /* blel */, Mips::BLEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5751 { 1271 /* blel */, Mips::BLELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5752 { 1276 /* bleu */, Mips::BLEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5753 { 1276 /* bleu */, Mips::BLEUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5754 { 1281 /* bleul */, Mips::BLEUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5755 { 1281 /* bleul */, Mips::BLEULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5756 { 1287 /* blez */, Mips::BLEZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5757 { 1287 /* blez */, Mips::BLEZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5758 { 1292 /* blezalc */, Mips::BLEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5759 { 1292 /* blezalc */, Mips::BLEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5760 { 1300 /* blezc */, Mips::BLEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5761 { 1300 /* blezc */, Mips::BLEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5762 { 1300 /* blezc */, Mips::BLEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, 5763 { 1306 /* blezl */, Mips::BLEZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5764 { 1312 /* blt */, Mips::BLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5765 { 1312 /* blt */, Mips::BLTImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5766 { 1316 /* bltc */, Mips::BLTC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5767 { 1316 /* bltc */, Mips::BLTC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5768 { 1316 /* bltc */, Mips::BLTC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, }, 5769 { 1321 /* bltl */, Mips::BLTL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5770 { 1321 /* bltl */, Mips::BLTLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5771 { 1326 /* bltu */, Mips::BLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5772 { 1326 /* bltu */, Mips::BLTUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5773 { 1331 /* bltuc */, Mips::BLTUC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5774 { 1331 /* bltuc */, Mips::BLTUC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5775 { 1331 /* bltuc */, Mips::BLTUC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, }, 5776 { 1337 /* bltul */, Mips::BLTUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5777 { 1337 /* bltul */, Mips::BLTULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5778 { 1343 /* bltz */, Mips::BLTZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5779 { 1343 /* bltz */, Mips::BLTZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5780 { 1348 /* bltzal */, Mips::BLTZAL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5781 { 1348 /* bltzal */, Mips::BLTZAL_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5782 { 1355 /* bltzalc */, Mips::BLTZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5783 { 1355 /* bltzalc */, Mips::BLTZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5784 { 1363 /* bltzall */, Mips::BLTZALL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5785 { 1371 /* bltzals */, Mips::BLTZALS_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5786 { 1379 /* bltzc */, Mips::BLTZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5787 { 1379 /* bltzc */, Mips::BLTZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5788 { 1379 /* bltzc */, Mips::BLTZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, 5789 { 1385 /* bltzl */, Mips::BLTZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5790 { 1391 /* bmnz.v */, Mips::BMNZ_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5791 { 1398 /* bmnzi.b */, Mips::BMNZI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, 5792 { 1406 /* bmz.v */, Mips::BMZ_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5793 { 1412 /* bmzi.b */, Mips::BMZI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, 5794 { 1419 /* bne */, Mips::BNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5795 { 1419 /* bne */, Mips::BNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5796 { 1419 /* bne */, Mips::BneImm, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5797 { 1423 /* bnec */, Mips::BNEC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5798 { 1423 /* bnec */, Mips::BNEC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5799 { 1423 /* bnec */, Mips::BNEC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, }, 5800 { 1428 /* bneg.b */, Mips::BNEG_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5801 { 1435 /* bneg.d */, Mips::BNEG_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5802 { 1442 /* bneg.h */, Mips::BNEG_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5803 { 1449 /* bneg.w */, Mips::BNEG_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5804 { 1456 /* bnegi.b */, Mips::BNEGI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, 5805 { 1464 /* bnegi.d */, Mips::BNEGI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, 5806 { 1472 /* bnegi.h */, Mips::BNEGI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, 5807 { 1480 /* bnegi.w */, Mips::BNEGI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 5808 { 1488 /* bnel */, Mips::BNEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5809 { 1488 /* bnel */, Mips::BNELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5810 { 1493 /* bnez */, Mips::BnezRxImmX16, Convert__Reg1_0__JumpTarget1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget }, }, 5811 { 1493 /* bnez */, Mips::BNE, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5812 { 1493 /* bnez */, Mips::BNE_MM, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5813 { 1493 /* bnez */, Mips::BnezRxImm16, Convert__Reg1_0__JumpTarget1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, }, 5814 { 1498 /* bnez16 */, Mips::BNEZ16_MM, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, }, 5815 { 1498 /* bnez16 */, Mips::BNEZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, }, 5816 { 1505 /* bnezalc */, Mips::BNEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5817 { 1505 /* bnezalc */, Mips::BNEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5818 { 1513 /* bnezc */, Mips::BNEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5819 { 1513 /* bnezc */, Mips::BNEZC_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5820 { 1513 /* bnezc */, Mips::BNEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5821 { 1513 /* bnezc */, Mips::BNEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, 5822 { 1519 /* bnezc16 */, Mips::BNEZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, }, 5823 { 1527 /* bnezl */, Mips::BNEL, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5824 { 1533 /* bnvc */, Mips::BNVC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5825 { 1533 /* bnvc */, Mips::BNVC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5826 { 1538 /* bnz.b */, Mips::BNZ_B, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, 5827 { 1544 /* bnz.d */, Mips::BNZ_D, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, 5828 { 1550 /* bnz.h */, Mips::BNZ_H, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, 5829 { 1556 /* bnz.v */, Mips::BNZ_V, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, 5830 { 1562 /* bnz.w */, Mips::BNZ_W, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, 5831 { 1568 /* bovc */, Mips::BOVC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5832 { 1568 /* bovc */, Mips::BOVC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5833 { 1573 /* bposge32 */, Mips::BPOSGE32_MM, Convert__JumpTarget1_0, AMFBS_InMicroMips_NotMips32r6_HasDSP, { MCK_JumpTarget }, }, 5834 { 1573 /* bposge32 */, Mips::BPOSGE32, Convert__JumpTarget1_0, AMFBS_HasDSP_NotInMicroMips, { MCK_JumpTarget }, }, 5835 { 1582 /* bposge32c */, Mips::BPOSGE32C_MMR3, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasDSPR3, { MCK_JumpTarget }, }, 5836 { 1592 /* break */, Mips::BREAK, Convert__imm_95_0__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { }, }, 5837 { 1592 /* break */, Mips::BREAK_MM, Convert__imm_95_0__imm_95_0, AMFBS_InMicroMips, { }, }, 5838 { 1592 /* break */, Mips::Break16, Convert_NoOperands, AMFBS_InMips16Mode, { MCK_0 }, }, 5839 { 1592 /* break */, Mips::BREAK, Convert__ConstantUImm10_01_0__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_ConstantUImm10_0 }, }, 5840 { 1592 /* break */, Mips::BREAK_MM, Convert__ConstantUImm10_01_0__imm_95_0, AMFBS_InMicroMips, { MCK_ConstantUImm10_0 }, }, 5841 { 1592 /* break */, Mips::BREAK, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, }, 5842 { 1592 /* break */, Mips::BREAK_MMR6, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, }, 5843 { 1592 /* break */, Mips::BREAK_MM, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, AMFBS_InMicroMips, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, }, 5844 { 1598 /* break16 */, Mips::BREAK16_MM, Convert__ConstantUImm4_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm4_0 }, }, 5845 { 1598 /* break16 */, Mips::BREAK16_MMR6, Convert__ConstantUImm4_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm4_0 }, }, 5846 { 1606 /* bsel.v */, Mips::BSEL_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5847 { 1613 /* bseli.b */, Mips::BSELI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, 5848 { 1621 /* bset.b */, Mips::BSET_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5849 { 1628 /* bset.d */, Mips::BSET_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5850 { 1635 /* bset.h */, Mips::BSET_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5851 { 1642 /* bset.w */, Mips::BSET_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5852 { 1649 /* bseti.b */, Mips::BSETI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, 5853 { 1657 /* bseti.d */, Mips::BSETI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, 5854 { 1665 /* bseti.h */, Mips::BSETI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, 5855 { 1673 /* bseti.w */, Mips::BSETI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 5856 { 1681 /* bteqz */, Mips::BteqzX16, Convert__SImm161_0, AMFBS_InMips16Mode, { MCK_SImm16 }, }, 5857 { 1681 /* bteqz */, Mips::Bteqz16, Convert__SImm161_0, AMFBS_InMips16Mode, { MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, }, 5858 { 1687 /* btnez */, Mips::BtnezX16, Convert__SImm161_0, AMFBS_InMips16Mode, { MCK_SImm16 }, }, 5859 { 1687 /* btnez */, Mips::Btnez16, Convert__SImm161_0, AMFBS_InMips16Mode, { MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, }, 5860 { 1693 /* bz.b */, Mips::BZ_B, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, 5861 { 1698 /* bz.d */, Mips::BZ_D, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, 5862 { 1703 /* bz.h */, Mips::BZ_H, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, 5863 { 1708 /* bz.v */, Mips::BZ_V, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, 5864 { 1713 /* bz.w */, Mips::BZ_W, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, 5865 { 1718 /* c.eq.d */, Mips::C_EQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5866 { 1718 /* c.eq.d */, Mips::C_EQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5867 { 1718 /* c.eq.d */, Mips::C_EQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5868 { 1718 /* c.eq.d */, Mips::C_EQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5869 { 1718 /* c.eq.d */, Mips::C_EQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5870 { 1718 /* c.eq.d */, Mips::C_EQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5871 { 1718 /* c.eq.d */, Mips::C_EQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5872 { 1718 /* c.eq.d */, Mips::C_EQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5873 { 1725 /* c.eq.s */, Mips::C_EQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5874 { 1725 /* c.eq.s */, Mips::C_EQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5875 { 1725 /* c.eq.s */, Mips::C_EQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5876 { 1725 /* c.eq.s */, Mips::C_EQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5877 { 1732 /* c.f.d */, Mips::C_F_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5878 { 1732 /* c.f.d */, Mips::C_F_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5879 { 1732 /* c.f.d */, Mips::C_F_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5880 { 1732 /* c.f.d */, Mips::C_F_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5881 { 1732 /* c.f.d */, Mips::C_F_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5882 { 1732 /* c.f.d */, Mips::C_F_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5883 { 1732 /* c.f.d */, Mips::C_F_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5884 { 1732 /* c.f.d */, Mips::C_F_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5885 { 1738 /* c.f.s */, Mips::C_F_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5886 { 1738 /* c.f.s */, Mips::C_F_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5887 { 1738 /* c.f.s */, Mips::C_F_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5888 { 1738 /* c.f.s */, Mips::C_F_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5889 { 1744 /* c.le.d */, Mips::C_LE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5890 { 1744 /* c.le.d */, Mips::C_LE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5891 { 1744 /* c.le.d */, Mips::C_LE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5892 { 1744 /* c.le.d */, Mips::C_LE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5893 { 1744 /* c.le.d */, Mips::C_LE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5894 { 1744 /* c.le.d */, Mips::C_LE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5895 { 1744 /* c.le.d */, Mips::C_LE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5896 { 1744 /* c.le.d */, Mips::C_LE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5897 { 1751 /* c.le.s */, Mips::C_LE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5898 { 1751 /* c.le.s */, Mips::C_LE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5899 { 1751 /* c.le.s */, Mips::C_LE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5900 { 1751 /* c.le.s */, Mips::C_LE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5901 { 1758 /* c.lt.d */, Mips::C_LT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5902 { 1758 /* c.lt.d */, Mips::C_LT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5903 { 1758 /* c.lt.d */, Mips::C_LT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5904 { 1758 /* c.lt.d */, Mips::C_LT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5905 { 1758 /* c.lt.d */, Mips::C_LT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5906 { 1758 /* c.lt.d */, Mips::C_LT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5907 { 1758 /* c.lt.d */, Mips::C_LT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5908 { 1758 /* c.lt.d */, Mips::C_LT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5909 { 1765 /* c.lt.s */, Mips::C_LT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5910 { 1765 /* c.lt.s */, Mips::C_LT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5911 { 1765 /* c.lt.s */, Mips::C_LT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5912 { 1765 /* c.lt.s */, Mips::C_LT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5913 { 1772 /* c.nge.d */, Mips::C_NGE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5914 { 1772 /* c.nge.d */, Mips::C_NGE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5915 { 1772 /* c.nge.d */, Mips::C_NGE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5916 { 1772 /* c.nge.d */, Mips::C_NGE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5917 { 1772 /* c.nge.d */, Mips::C_NGE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5918 { 1772 /* c.nge.d */, Mips::C_NGE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5919 { 1772 /* c.nge.d */, Mips::C_NGE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5920 { 1772 /* c.nge.d */, Mips::C_NGE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5921 { 1780 /* c.nge.s */, Mips::C_NGE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5922 { 1780 /* c.nge.s */, Mips::C_NGE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5923 { 1780 /* c.nge.s */, Mips::C_NGE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5924 { 1780 /* c.nge.s */, Mips::C_NGE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5925 { 1788 /* c.ngl.d */, Mips::C_NGL_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5926 { 1788 /* c.ngl.d */, Mips::C_NGL_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5927 { 1788 /* c.ngl.d */, Mips::C_NGL_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5928 { 1788 /* c.ngl.d */, Mips::C_NGL_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5929 { 1788 /* c.ngl.d */, Mips::C_NGL_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5930 { 1788 /* c.ngl.d */, Mips::C_NGL_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5931 { 1788 /* c.ngl.d */, Mips::C_NGL_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5932 { 1788 /* c.ngl.d */, Mips::C_NGL_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5933 { 1796 /* c.ngl.s */, Mips::C_NGL_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5934 { 1796 /* c.ngl.s */, Mips::C_NGL_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5935 { 1796 /* c.ngl.s */, Mips::C_NGL_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5936 { 1796 /* c.ngl.s */, Mips::C_NGL_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5937 { 1804 /* c.ngle.d */, Mips::C_NGLE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5938 { 1804 /* c.ngle.d */, Mips::C_NGLE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5939 { 1804 /* c.ngle.d */, Mips::C_NGLE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5940 { 1804 /* c.ngle.d */, Mips::C_NGLE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5941 { 1804 /* c.ngle.d */, Mips::C_NGLE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5942 { 1804 /* c.ngle.d */, Mips::C_NGLE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5943 { 1804 /* c.ngle.d */, Mips::C_NGLE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5944 { 1804 /* c.ngle.d */, Mips::C_NGLE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5945 { 1813 /* c.ngle.s */, Mips::C_NGLE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5946 { 1813 /* c.ngle.s */, Mips::C_NGLE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5947 { 1813 /* c.ngle.s */, Mips::C_NGLE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5948 { 1813 /* c.ngle.s */, Mips::C_NGLE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5949 { 1822 /* c.ngt.d */, Mips::C_NGT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5950 { 1822 /* c.ngt.d */, Mips::C_NGT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5951 { 1822 /* c.ngt.d */, Mips::C_NGT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5952 { 1822 /* c.ngt.d */, Mips::C_NGT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5953 { 1822 /* c.ngt.d */, Mips::C_NGT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5954 { 1822 /* c.ngt.d */, Mips::C_NGT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5955 { 1822 /* c.ngt.d */, Mips::C_NGT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5956 { 1822 /* c.ngt.d */, Mips::C_NGT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5957 { 1830 /* c.ngt.s */, Mips::C_NGT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5958 { 1830 /* c.ngt.s */, Mips::C_NGT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5959 { 1830 /* c.ngt.s */, Mips::C_NGT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5960 { 1830 /* c.ngt.s */, Mips::C_NGT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5961 { 1838 /* c.ole.d */, Mips::C_OLE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5962 { 1838 /* c.ole.d */, Mips::C_OLE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5963 { 1838 /* c.ole.d */, Mips::C_OLE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5964 { 1838 /* c.ole.d */, Mips::C_OLE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5965 { 1838 /* c.ole.d */, Mips::C_OLE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5966 { 1838 /* c.ole.d */, Mips::C_OLE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5967 { 1838 /* c.ole.d */, Mips::C_OLE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5968 { 1838 /* c.ole.d */, Mips::C_OLE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5969 { 1846 /* c.ole.s */, Mips::C_OLE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5970 { 1846 /* c.ole.s */, Mips::C_OLE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5971 { 1846 /* c.ole.s */, Mips::C_OLE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5972 { 1846 /* c.ole.s */, Mips::C_OLE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5973 { 1854 /* c.olt.d */, Mips::C_OLT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5974 { 1854 /* c.olt.d */, Mips::C_OLT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5975 { 1854 /* c.olt.d */, Mips::C_OLT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5976 { 1854 /* c.olt.d */, Mips::C_OLT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5977 { 1854 /* c.olt.d */, Mips::C_OLT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5978 { 1854 /* c.olt.d */, Mips::C_OLT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5979 { 1854 /* c.olt.d */, Mips::C_OLT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5980 { 1854 /* c.olt.d */, Mips::C_OLT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5981 { 1862 /* c.olt.s */, Mips::C_OLT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5982 { 1862 /* c.olt.s */, Mips::C_OLT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5983 { 1862 /* c.olt.s */, Mips::C_OLT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5984 { 1862 /* c.olt.s */, Mips::C_OLT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5985 { 1870 /* c.seq.d */, Mips::C_SEQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5986 { 1870 /* c.seq.d */, Mips::C_SEQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5987 { 1870 /* c.seq.d */, Mips::C_SEQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5988 { 1870 /* c.seq.d */, Mips::C_SEQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5989 { 1870 /* c.seq.d */, Mips::C_SEQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5990 { 1870 /* c.seq.d */, Mips::C_SEQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5991 { 1870 /* c.seq.d */, Mips::C_SEQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5992 { 1870 /* c.seq.d */, Mips::C_SEQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5993 { 1878 /* c.seq.s */, Mips::C_SEQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5994 { 1878 /* c.seq.s */, Mips::C_SEQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5995 { 1878 /* c.seq.s */, Mips::C_SEQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5996 { 1878 /* c.seq.s */, Mips::C_SEQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5997 { 1886 /* c.sf.d */, Mips::C_SF_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5998 { 1886 /* c.sf.d */, Mips::C_SF_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5999 { 1886 /* c.sf.d */, Mips::C_SF_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6000 { 1886 /* c.sf.d */, Mips::C_SF_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6001 { 1886 /* c.sf.d */, Mips::C_SF_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6002 { 1886 /* c.sf.d */, Mips::C_SF_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6003 { 1886 /* c.sf.d */, Mips::C_SF_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6004 { 1886 /* c.sf.d */, Mips::C_SF_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6005 { 1893 /* c.sf.s */, Mips::C_SF_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6006 { 1893 /* c.sf.s */, Mips::C_SF_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6007 { 1893 /* c.sf.s */, Mips::C_SF_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6008 { 1893 /* c.sf.s */, Mips::C_SF_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6009 { 1900 /* c.ueq.d */, Mips::C_UEQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6010 { 1900 /* c.ueq.d */, Mips::C_UEQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6011 { 1900 /* c.ueq.d */, Mips::C_UEQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6012 { 1900 /* c.ueq.d */, Mips::C_UEQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6013 { 1900 /* c.ueq.d */, Mips::C_UEQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6014 { 1900 /* c.ueq.d */, Mips::C_UEQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6015 { 1900 /* c.ueq.d */, Mips::C_UEQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6016 { 1900 /* c.ueq.d */, Mips::C_UEQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6017 { 1908 /* c.ueq.s */, Mips::C_UEQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6018 { 1908 /* c.ueq.s */, Mips::C_UEQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6019 { 1908 /* c.ueq.s */, Mips::C_UEQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6020 { 1908 /* c.ueq.s */, Mips::C_UEQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6021 { 1916 /* c.ule.d */, Mips::C_ULE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6022 { 1916 /* c.ule.d */, Mips::C_ULE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6023 { 1916 /* c.ule.d */, Mips::C_ULE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6024 { 1916 /* c.ule.d */, Mips::C_ULE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6025 { 1916 /* c.ule.d */, Mips::C_ULE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6026 { 1916 /* c.ule.d */, Mips::C_ULE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6027 { 1916 /* c.ule.d */, Mips::C_ULE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6028 { 1916 /* c.ule.d */, Mips::C_ULE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6029 { 1924 /* c.ule.s */, Mips::C_ULE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6030 { 1924 /* c.ule.s */, Mips::C_ULE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6031 { 1924 /* c.ule.s */, Mips::C_ULE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6032 { 1924 /* c.ule.s */, Mips::C_ULE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6033 { 1932 /* c.ult.d */, Mips::C_ULT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6034 { 1932 /* c.ult.d */, Mips::C_ULT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6035 { 1932 /* c.ult.d */, Mips::C_ULT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6036 { 1932 /* c.ult.d */, Mips::C_ULT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6037 { 1932 /* c.ult.d */, Mips::C_ULT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6038 { 1932 /* c.ult.d */, Mips::C_ULT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6039 { 1932 /* c.ult.d */, Mips::C_ULT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6040 { 1932 /* c.ult.d */, Mips::C_ULT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6041 { 1940 /* c.ult.s */, Mips::C_ULT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6042 { 1940 /* c.ult.s */, Mips::C_ULT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6043 { 1940 /* c.ult.s */, Mips::C_ULT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6044 { 1940 /* c.ult.s */, Mips::C_ULT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6045 { 1948 /* c.un.d */, Mips::C_UN_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6046 { 1948 /* c.un.d */, Mips::C_UN_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6047 { 1948 /* c.un.d */, Mips::C_UN_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6048 { 1948 /* c.un.d */, Mips::C_UN_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6049 { 1948 /* c.un.d */, Mips::C_UN_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6050 { 1948 /* c.un.d */, Mips::C_UN_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6051 { 1948 /* c.un.d */, Mips::C_UN_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6052 { 1948 /* c.un.d */, Mips::C_UN_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6053 { 1955 /* c.un.s */, Mips::C_UN_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6054 { 1955 /* c.un.s */, Mips::C_UN_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6055 { 1955 /* c.un.s */, Mips::C_UN_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6056 { 1955 /* c.un.s */, Mips::C_UN_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6057 { 1962 /* cache */, Mips::CACHE_R6, Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9_0 }, }, 6058 { 1962 /* cache */, Mips::CACHE, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_Mem }, }, 6059 { 1962 /* cache */, Mips::CACHE_MM, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, }, 6060 { 1962 /* cache */, Mips::CACHE_MMR6, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, }, 6061 { 1968 /* cachee */, Mips::CACHEE, Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9_0 }, }, 6062 { 1968 /* cachee */, Mips::CACHEE_MM, Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasEVA, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9_0 }, }, 6063 { 1975 /* ceil.l.d */, Mips::CEIL_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6064 { 1975 /* ceil.l.d */, Mips::CEIL_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6065 { 1984 /* ceil.l.s */, Mips::CEIL_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 6066 { 1984 /* ceil.l.s */, Mips::CEIL_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 6067 { 1993 /* ceil.w.d */, Mips::CEIL_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 6068 { 1993 /* ceil.w.d */, Mips::CEIL_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 6069 { 1993 /* ceil.w.d */, Mips::CEIL_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 6070 { 1993 /* ceil.w.d */, Mips::CEIL_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, 6071 { 2002 /* ceil.w.s */, Mips::CEIL_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6072 { 2002 /* ceil.w.s */, Mips::CEIL_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6073 { 2002 /* ceil.w.s */, Mips::CEIL_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6074 { 2011 /* ceq.b */, Mips::CEQ_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6075 { 2017 /* ceq.d */, Mips::CEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6076 { 2023 /* ceq.h */, Mips::CEQ_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6077 { 2029 /* ceq.w */, Mips::CEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6078 { 2035 /* ceqi.b */, Mips::CEQI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 6079 { 2042 /* ceqi.d */, Mips::CEQI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 6080 { 2049 /* ceqi.h */, Mips::CEQI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 6081 { 2056 /* ceqi.w */, Mips::CEQI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 6082 { 2063 /* cfc1 */, Mips::CFC1, Convert__GPR32AsmReg1_0__CCRAsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, }, 6083 { 2063 /* cfc1 */, Mips::CFC1_MM, Convert__GPR32AsmReg1_0__CCRAsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, }, 6084 { 2068 /* cfc2 */, Mips::CFC2_MM, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, 6085 { 2073 /* cfcmsa */, Mips::CFCMSA, Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSACtrlAsmReg }, }, 6086 { 2080 /* cftc1 */, Mips::CFTC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, 6087 { 2086 /* cins */, Mips::CINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, 6088 { 2086 /* cins */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, }, 6089 { 2086 /* cins */, Mips::CINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, 6090 { 2086 /* cins */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, }, 6091 { 2091 /* cins32 */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, 6092 { 2091 /* cins32 */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, 6093 { 2098 /* class.d */, Mips::CLASS_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6094 { 2098 /* class.d */, Mips::CLASS_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6095 { 2106 /* class.s */, Mips::CLASS_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6096 { 2106 /* class.s */, Mips::CLASS_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6097 { 2114 /* cle_s.b */, Mips::CLE_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6098 { 2122 /* cle_s.d */, Mips::CLE_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6099 { 2130 /* cle_s.h */, Mips::CLE_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6100 { 2138 /* cle_s.w */, Mips::CLE_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6101 { 2146 /* cle_u.b */, Mips::CLE_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6102 { 2154 /* cle_u.d */, Mips::CLE_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6103 { 2162 /* cle_u.h */, Mips::CLE_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6104 { 2170 /* cle_u.w */, Mips::CLE_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6105 { 2178 /* clei_s.b */, Mips::CLEI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 6106 { 2187 /* clei_s.d */, Mips::CLEI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 6107 { 2196 /* clei_s.h */, Mips::CLEI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 6108 { 2205 /* clei_s.w */, Mips::CLEI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 6109 { 2214 /* clei_u.b */, Mips::CLEI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 6110 { 2223 /* clei_u.d */, Mips::CLEI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 6111 { 2232 /* clei_u.h */, Mips::CLEI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 6112 { 2241 /* clei_u.w */, Mips::CLEI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 6113 { 2250 /* clo */, Mips::CLO, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6114 { 2250 /* clo */, Mips::CLO_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6115 { 2250 /* clo */, Mips::CLO_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6116 { 2250 /* clo */, Mips::CLO_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6117 { 2254 /* clt_s.b */, Mips::CLT_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6118 { 2262 /* clt_s.d */, Mips::CLT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6119 { 2270 /* clt_s.h */, Mips::CLT_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6120 { 2278 /* clt_s.w */, Mips::CLT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6121 { 2286 /* clt_u.b */, Mips::CLT_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6122 { 2294 /* clt_u.d */, Mips::CLT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6123 { 2302 /* clt_u.h */, Mips::CLT_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6124 { 2310 /* clt_u.w */, Mips::CLT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6125 { 2318 /* clti_s.b */, Mips::CLTI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 6126 { 2327 /* clti_s.d */, Mips::CLTI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 6127 { 2336 /* clti_s.h */, Mips::CLTI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 6128 { 2345 /* clti_s.w */, Mips::CLTI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 6129 { 2354 /* clti_u.b */, Mips::CLTI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 6130 { 2363 /* clti_u.d */, Mips::CLTI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 6131 { 2372 /* clti_u.h */, Mips::CLTI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 6132 { 2381 /* clti_u.w */, Mips::CLTI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 6133 { 2390 /* clz */, Mips::CLZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6134 { 2390 /* clz */, Mips::CLZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6135 { 2390 /* clz */, Mips::CLZ_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6136 { 2390 /* clz */, Mips::CLZ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6137 { 2394 /* cmp */, Mips::CmpRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, 6138 { 2398 /* cmp.af.d */, Mips::CMP_F_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6139 { 2398 /* cmp.af.d */, Mips::CMP_AF_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6140 { 2407 /* cmp.af.s */, Mips::CMP_F_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6141 { 2407 /* cmp.af.s */, Mips::CMP_AF_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6142 { 2416 /* cmp.eq.d */, Mips::CMP_EQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6143 { 2416 /* cmp.eq.d */, Mips::CMP_EQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6144 { 2425 /* cmp.eq.ph */, Mips::CMP_EQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6145 { 2425 /* cmp.eq.ph */, Mips::CMP_EQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6146 { 2435 /* cmp.eq.s */, Mips::CMP_EQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6147 { 2435 /* cmp.eq.s */, Mips::CMP_EQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6148 { 2444 /* cmp.le.d */, Mips::CMP_LE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6149 { 2444 /* cmp.le.d */, Mips::CMP_LE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6150 { 2453 /* cmp.le.ph */, Mips::CMP_LE_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6151 { 2453 /* cmp.le.ph */, Mips::CMP_LE_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6152 { 2463 /* cmp.le.s */, Mips::CMP_LE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6153 { 2463 /* cmp.le.s */, Mips::CMP_LE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6154 { 2472 /* cmp.lt.d */, Mips::CMP_LT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6155 { 2472 /* cmp.lt.d */, Mips::CMP_LT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6156 { 2481 /* cmp.lt.ph */, Mips::CMP_LT_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6157 { 2481 /* cmp.lt.ph */, Mips::CMP_LT_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6158 { 2491 /* cmp.lt.s */, Mips::CMP_LT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6159 { 2491 /* cmp.lt.s */, Mips::CMP_LT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6160 { 2500 /* cmp.saf.d */, Mips::CMP_SAF_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6161 { 2500 /* cmp.saf.d */, Mips::CMP_SAF_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6162 { 2510 /* cmp.saf.s */, Mips::CMP_SAF_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6163 { 2510 /* cmp.saf.s */, Mips::CMP_SAF_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6164 { 2520 /* cmp.seq.d */, Mips::CMP_SEQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6165 { 2520 /* cmp.seq.d */, Mips::CMP_SEQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6166 { 2530 /* cmp.seq.s */, Mips::CMP_SEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6167 { 2530 /* cmp.seq.s */, Mips::CMP_SEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6168 { 2540 /* cmp.sle.d */, Mips::CMP_SLE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6169 { 2540 /* cmp.sle.d */, Mips::CMP_SLE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6170 { 2550 /* cmp.sle.s */, Mips::CMP_SLE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6171 { 2550 /* cmp.sle.s */, Mips::CMP_SLE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6172 { 2560 /* cmp.slt.d */, Mips::CMP_SLT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6173 { 2560 /* cmp.slt.d */, Mips::CMP_SLT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6174 { 2570 /* cmp.slt.s */, Mips::CMP_SLT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6175 { 2570 /* cmp.slt.s */, Mips::CMP_SLT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6176 { 2580 /* cmp.sueq.d */, Mips::CMP_SUEQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6177 { 2580 /* cmp.sueq.d */, Mips::CMP_SUEQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6178 { 2591 /* cmp.sueq.s */, Mips::CMP_SUEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6179 { 2591 /* cmp.sueq.s */, Mips::CMP_SUEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6180 { 2602 /* cmp.sule.d */, Mips::CMP_SULE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6181 { 2602 /* cmp.sule.d */, Mips::CMP_SULE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6182 { 2613 /* cmp.sule.s */, Mips::CMP_SULE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6183 { 2613 /* cmp.sule.s */, Mips::CMP_SULE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6184 { 2624 /* cmp.sult.d */, Mips::CMP_SULT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6185 { 2624 /* cmp.sult.d */, Mips::CMP_SULT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6186 { 2635 /* cmp.sult.s */, Mips::CMP_SULT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6187 { 2635 /* cmp.sult.s */, Mips::CMP_SULT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6188 { 2646 /* cmp.sun.d */, Mips::CMP_SUN_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6189 { 2646 /* cmp.sun.d */, Mips::CMP_SUN_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6190 { 2656 /* cmp.sun.s */, Mips::CMP_SUN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6191 { 2656 /* cmp.sun.s */, Mips::CMP_SUN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6192 { 2666 /* cmp.ueq.d */, Mips::CMP_UEQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6193 { 2666 /* cmp.ueq.d */, Mips::CMP_UEQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6194 { 2676 /* cmp.ueq.s */, Mips::CMP_UEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6195 { 2676 /* cmp.ueq.s */, Mips::CMP_UEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6196 { 2686 /* cmp.ule.d */, Mips::CMP_ULE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6197 { 2686 /* cmp.ule.d */, Mips::CMP_ULE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6198 { 2696 /* cmp.ule.s */, Mips::CMP_ULE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6199 { 2696 /* cmp.ule.s */, Mips::CMP_ULE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6200 { 2706 /* cmp.ult.d */, Mips::CMP_ULT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6201 { 2706 /* cmp.ult.d */, Mips::CMP_ULT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6202 { 2716 /* cmp.ult.s */, Mips::CMP_ULT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6203 { 2716 /* cmp.ult.s */, Mips::CMP_ULT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6204 { 2726 /* cmp.un.d */, Mips::CMP_UN_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6205 { 2726 /* cmp.un.d */, Mips::CMP_UN_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6206 { 2735 /* cmp.un.s */, Mips::CMP_UN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6207 { 2735 /* cmp.un.s */, Mips::CMP_UN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6208 { 2744 /* cmpgdu.eq.qb */, Mips::CMPGDU_EQ_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6209 { 2744 /* cmpgdu.eq.qb */, Mips::CMPGDU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6210 { 2757 /* cmpgdu.le.qb */, Mips::CMPGDU_LE_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6211 { 2757 /* cmpgdu.le.qb */, Mips::CMPGDU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6212 { 2770 /* cmpgdu.lt.qb */, Mips::CMPGDU_LT_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6213 { 2770 /* cmpgdu.lt.qb */, Mips::CMPGDU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6214 { 2783 /* cmpgu.eq.qb */, Mips::CMPGU_EQ_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6215 { 2783 /* cmpgu.eq.qb */, Mips::CMPGU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6216 { 2795 /* cmpgu.le.qb */, Mips::CMPGU_LE_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6217 { 2795 /* cmpgu.le.qb */, Mips::CMPGU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6218 { 2807 /* cmpgu.lt.qb */, Mips::CMPGU_LT_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6219 { 2807 /* cmpgu.lt.qb */, Mips::CMPGU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6220 { 2819 /* cmpi */, Mips::CmpiRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, }, 6221 { 2819 /* cmpi */, Mips::CmpiRxImm16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, }, 6222 { 2824 /* cmpu.eq.qb */, Mips::CMPU_EQ_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6223 { 2824 /* cmpu.eq.qb */, Mips::CMPU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6224 { 2835 /* cmpu.le.qb */, Mips::CMPU_LE_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6225 { 2835 /* cmpu.le.qb */, Mips::CMPU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6226 { 2846 /* cmpu.lt.qb */, Mips::CMPU_LT_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6227 { 2846 /* cmpu.lt.qb */, Mips::CMPU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6228 { 2857 /* copy_s.b */, Mips::COPY_S_B, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, }, 6229 { 2866 /* copy_s.d */, Mips::COPY_S_D, Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, AMFBS_HasStdEnc_HasMSA_HasMips64, { MCK_GPR64AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, }, 6230 { 2875 /* copy_s.h */, Mips::COPY_S_H, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, }, 6231 { 2884 /* copy_s.w */, Mips::COPY_S_W, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, }, 6232 { 2893 /* copy_u.b */, Mips::COPY_U_B, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, }, 6233 { 2902 /* copy_u.h */, Mips::COPY_U_H, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, }, 6234 { 2911 /* copy_u.w */, Mips::COPY_U_W, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMSA_HasMips64, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, }, 6235 { 2920 /* crc32b */, Mips::CRC32B, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6236 { 2927 /* crc32cb */, Mips::CRC32CB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6237 { 2935 /* crc32cd */, Mips::CRC32CD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6238 { 2943 /* crc32ch */, Mips::CRC32CH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6239 { 2951 /* crc32cw */, Mips::CRC32CW, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6240 { 2959 /* crc32d */, Mips::CRC32D, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6241 { 2966 /* crc32h */, Mips::CRC32H, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6242 { 2973 /* crc32w */, Mips::CRC32W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6243 { 2980 /* ctc1 */, Mips::CTC1, Convert__CCRAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, }, 6244 { 2980 /* ctc1 */, Mips::CTC1_MM, Convert__CCRAsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, }, 6245 { 2985 /* ctc2 */, Mips::CTC2_MM, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, 6246 { 2990 /* ctcmsa */, Mips::CTCMSA, Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSACtrlAsmReg, MCK_GPR32AsmReg }, }, 6247 { 2997 /* cttc1 */, Mips::CTTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, 6248 { 3003 /* cvt.d.l */, Mips::CVT_D64_L, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6249 { 3003 /* cvt.d.l */, Mips::CVT_D_L_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6250 { 3011 /* cvt.d.s */, Mips::CVT_D32_S, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, }, 6251 { 3011 /* cvt.d.s */, Mips::CVT_D32_S_MM, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, }, 6252 { 3011 /* cvt.d.s */, Mips::CVT_D64_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 6253 { 3011 /* cvt.d.s */, Mips::CVT_D64_S_MM, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 6254 { 3019 /* cvt.d.w */, Mips::CVT_D32_W, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, }, 6255 { 3019 /* cvt.d.w */, Mips::CVT_D32_W_MM, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, }, 6256 { 3019 /* cvt.d.w */, Mips::CVT_D64_W, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 6257 { 3019 /* cvt.d.w */, Mips::CVT_D64_W_MM, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 6258 { 3027 /* cvt.l.d */, Mips::CVT_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6259 { 3027 /* cvt.l.d */, Mips::CVT_L_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6260 { 3027 /* cvt.l.d */, Mips::CVT_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6261 { 3035 /* cvt.l.s */, Mips::CVT_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 6262 { 3035 /* cvt.l.s */, Mips::CVT_L_S_MM, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 6263 { 3035 /* cvt.l.s */, Mips::CVT_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 6264 { 3043 /* cvt.ps.s */, Mips::CVT_PS_S64, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6265 { 3052 /* cvt.s.d */, Mips::CVT_S_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 6266 { 3052 /* cvt.s.d */, Mips::CVT_S_D32_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 6267 { 3052 /* cvt.s.d */, Mips::CVT_S_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, 6268 { 3052 /* cvt.s.d */, Mips::CVT_S_D64_MM, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, 6269 { 3060 /* cvt.s.l */, Mips::CVT_S_L, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, 6270 { 3060 /* cvt.s.l */, Mips::CVT_S_L_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 6271 { 3068 /* cvt.s.pl */, Mips::CVT_S_PL64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, 6272 { 3077 /* cvt.s.pu */, Mips::CVT_S_PU64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, 6273 { 3086 /* cvt.s.w */, Mips::CVT_S_W, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6274 { 3086 /* cvt.s.w */, Mips::CVT_S_W_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6275 { 3086 /* cvt.s.w */, Mips::CVT_S_W_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6276 { 3094 /* cvt.w.d */, Mips::CVT_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 6277 { 3094 /* cvt.w.d */, Mips::CVT_W_D32_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 6278 { 3094 /* cvt.w.d */, Mips::CVT_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, 6279 { 3094 /* cvt.w.d */, Mips::CVT_W_D64_MM, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, 6280 { 3102 /* cvt.w.s */, Mips::CVT_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6281 { 3102 /* cvt.w.s */, Mips::CVT_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6282 { 3102 /* cvt.w.s */, Mips::CVT_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6283 { 3110 /* dadd */, Mips::DADD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6284 { 3110 /* dadd */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, }, 6285 { 3110 /* dadd */, Mips::DADD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6286 { 3110 /* dadd */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, }, 6287 { 3115 /* daddi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_SImm16 }, }, 6288 { 3115 /* daddi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, }, 6289 { 3121 /* daddiu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, }, 6290 { 3121 /* daddiu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, }, 6291 { 3128 /* daddu */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6292 { 3128 /* daddu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, }, 6293 { 3128 /* daddu */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6294 { 3128 /* daddu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, }, 6295 { 3134 /* dahi */, Mips::DAHI, Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16_AltRelaxed }, }, 6296 { 3139 /* dalign */, Mips::DALIGN, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm3_0 }, }, 6297 { 3146 /* dati */, Mips::DATI, Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16_AltRelaxed }, }, 6298 { 3151 /* daui */, Mips::DAUI, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16 }, }, 6299 { 3156 /* dbitswap */, Mips::DBITSWAP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6300 { 3165 /* dclo */, Mips::DCLO, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6301 { 3165 /* dclo */, Mips::DCLO_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6302 { 3170 /* dclz */, Mips::DCLZ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6303 { 3170 /* dclz */, Mips::DCLZ_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6304 { 3175 /* ddiv */, Mips::DSDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6305 { 3175 /* ddiv */, Mips::DSDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, }, 6306 { 3175 /* ddiv */, Mips::DSDIV, Convert__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6307 { 3175 /* ddiv */, Mips::DSDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6308 { 3175 /* ddiv */, Mips::DDIV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6309 { 3175 /* ddiv */, Mips::DSDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, 6310 { 3180 /* ddivu */, Mips::DUDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6311 { 3180 /* ddivu */, Mips::DUDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, }, 6312 { 3180 /* ddivu */, Mips::DUDIV, Convert__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6313 { 3180 /* ddivu */, Mips::DUDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6314 { 3180 /* ddivu */, Mips::DDIVU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6315 { 3180 /* ddivu */, Mips::DUDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, 6316 { 3186 /* deret */, Mips::DERET, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32_NotInMicroMips, { }, }, 6317 { 3186 /* deret */, Mips::DERET_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, }, 6318 { 3186 /* deret */, Mips::DERET_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, }, 6319 { 3192 /* dext */, Mips::DEXTM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_33 }, }, 6320 { 3192 /* dext */, Mips::DEXTU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, }, 6321 { 3192 /* dext */, Mips::DEXT, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_ConstantUImm5_Plus1_Report_UImm6 }, }, 6322 { 3197 /* dextm */, Mips::DEXTM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_33 }, }, 6323 { 3203 /* dextu */, Mips::DEXTU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, }, 6324 { 3209 /* di */, Mips::DI, Convert__regZERO, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { }, }, 6325 { 3209 /* di */, Mips::DI_MMR6, Convert__regZERO, AMFBS_InMicroMips_HasMips32r6, { }, }, 6326 { 3209 /* di */, Mips::DI_MM, Convert__regZERO, AMFBS_InMicroMips, { }, }, 6327 { 3209 /* di */, Mips::DI, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6328 { 3209 /* di */, Mips::DI_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, 6329 { 3209 /* di */, Mips::DI_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg }, }, 6330 { 3212 /* dins */, Mips::DINSM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImmRange2_64 }, }, 6331 { 3212 /* dins */, Mips::DINSU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, }, 6332 { 3212 /* dins */, Mips::DINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0, MCK_ConstantUImm5_1 }, }, 6333 { 3217 /* dinsm */, Mips::DINSM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImmRange2_64 }, }, 6334 { 3223 /* dinsu */, Mips::DINSU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, }, 6335 { 3229 /* div */, Mips::DIV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6336 { 3229 /* div */, Mips::SDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32 }, }, 6337 { 3229 /* div */, Mips::SDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg }, }, 6338 { 3229 /* div */, Mips::SDIV, Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32ZeroAsmReg, MCK_GPR32AsmReg }, }, 6339 { 3229 /* div */, Mips::DivRxRy16, Convert__Reg1_1__Reg1_2, AMFBS_InMips16Mode, { MCK_GPR32ZERO, MCK_CPU16Regs, MCK_CPU16Regs }, }, 6340 { 3229 /* div */, Mips::SDIV, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6341 { 3229 /* div */, Mips::SDIV_MM, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6342 { 3229 /* div */, Mips::DIV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6343 { 3229 /* div */, Mips::DIV_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6344 { 3229 /* div */, Mips::SDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, }, 6345 { 3229 /* div */, Mips::SDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6346 { 3233 /* div.d */, Mips::FDIV_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6347 { 3233 /* div.d */, Mips::FDIV_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6348 { 3233 /* div.d */, Mips::FDIV_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6349 { 3233 /* div.d */, Mips::FDIV_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6350 { 3239 /* div.s */, Mips::FDIV_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6351 { 3239 /* div.s */, Mips::FDIV_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6352 { 3239 /* div.s */, Mips::FDIV_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6353 { 3245 /* div_s.b */, Mips::DIV_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6354 { 3253 /* div_s.d */, Mips::DIV_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6355 { 3261 /* div_s.h */, Mips::DIV_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6356 { 3269 /* div_s.w */, Mips::DIV_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6357 { 3277 /* div_u.b */, Mips::DIV_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6358 { 3285 /* div_u.d */, Mips::DIV_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6359 { 3293 /* div_u.h */, Mips::DIV_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6360 { 3301 /* div_u.w */, Mips::DIV_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6361 { 3309 /* divu */, Mips::DIVU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6362 { 3309 /* divu */, Mips::UDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32 }, }, 6363 { 3309 /* divu */, Mips::UDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg }, }, 6364 { 3309 /* divu */, Mips::UDIV, Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32ZeroAsmReg, MCK_GPR32AsmReg }, }, 6365 { 3309 /* divu */, Mips::DivuRxRy16, Convert__Reg1_1__Reg1_2, AMFBS_InMips16Mode, { MCK_GPR32ZERO, MCK_CPU16Regs, MCK_CPU16Regs }, }, 6366 { 3309 /* divu */, Mips::UDIV, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6367 { 3309 /* divu */, Mips::UDIV_MM, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6368 { 3309 /* divu */, Mips::UDivMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6369 { 3309 /* divu */, Mips::DIVU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6370 { 3309 /* divu */, Mips::DIVU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6371 { 3309 /* divu */, Mips::UDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, }, 6372 { 3314 /* dla */, Mips::LoadAddrImm64, Convert__GPR64AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR64AsmReg, MCK_Imm }, }, 6373 { 3314 /* dla */, Mips::LoadAddrReg64, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR64AsmReg, MCK_Mem }, }, 6374 { 3318 /* dli */, Mips::LoadImm64, Convert__GPR64AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR64AsmReg, MCK_Imm }, }, 6375 { 3322 /* dlsa */, Mips::DLSA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3, AMFBS_HasStdEnc_HasMSA_HasMips64, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm2_1 }, }, 6376 { 3322 /* dlsa */, Mips::DLSA_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm2_1 }, }, 6377 { 3327 /* dmfc0 */, Mips::DMFC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, }, 6378 { 3327 /* dmfc0 */, Mips::DMFC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 6379 { 3333 /* dmfc1 */, Mips::DMFC1, Convert__GPR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, { MCK_GPR64AsmReg, MCK_FGR64AsmReg }, }, 6380 { 3339 /* dmfc2 */, Mips::DMFC2, Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0, AMFBS_None, { MCK_GPR64AsmReg, MCK_COP2AsmReg }, }, 6381 { 3339 /* dmfc2 */, Mips::DMFC2_OCTEON, Convert__GPR64AsmReg1_0__UImm161_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_UImm16 }, }, 6382 { 3339 /* dmfc2 */, Mips::DMFC2, Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3, { MCK_GPR64AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, }, 6383 { 3345 /* dmfgc0 */, Mips::DMFGC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, }, 6384 { 3345 /* dmfgc0 */, Mips::DMFGC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips64r5_HasVirt, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 6385 { 3352 /* dmod */, Mips::DMOD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6386 { 3357 /* dmodu */, Mips::DMODU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6387 { 3363 /* dmt */, Mips::DMT, Convert__regZERO, AMFBS_HasMT_NotInMicroMips, { }, }, 6388 { 3363 /* dmt */, Mips::DMT, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6389 { 3367 /* dmtc0 */, Mips::DMTC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0, AMFBS_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, }, 6390 { 3367 /* dmtc0 */, Mips::DMTC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 6391 { 3373 /* dmtc1 */, Mips::DMTC1, Convert__FGR64AsmReg1_1__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, { MCK_GPR64AsmReg, MCK_FGR64AsmReg }, }, 6392 { 3379 /* dmtc2 */, Mips::DMTC2, Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0, AMFBS_None, { MCK_GPR64AsmReg, MCK_COP2AsmReg }, }, 6393 { 3379 /* dmtc2 */, Mips::DMTC2_OCTEON, Convert__GPR64AsmReg1_0__UImm161_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_UImm16 }, }, 6394 { 3379 /* dmtc2 */, Mips::DMTC2, Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3, { MCK_GPR64AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, }, 6395 { 3385 /* dmtgc0 */, Mips::DMTGC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, }, 6396 { 3385 /* dmtgc0 */, Mips::DMTGC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips64r5_HasVirt, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 6397 { 3392 /* dmuh */, Mips::DMUH, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6398 { 3397 /* dmuhu */, Mips::DMUHU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6399 { 3403 /* dmul */, Mips::DMUL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6400 { 3403 /* dmul */, Mips::DMULMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasMips3_NotMips64r6_NotCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6401 { 3403 /* dmul */, Mips::DMUL_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6402 { 3403 /* dmul */, Mips::DMUL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6403 { 3403 /* dmul */, Mips::DMULImmMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, }, 6404 { 3408 /* dmulo */, Mips::DMULOMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6405 { 3414 /* dmulou */, Mips::DMULOUMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6406 { 3421 /* dmult */, Mips::DMULT, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6407 { 3427 /* dmultu */, Mips::DMULTu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6408 { 3434 /* dmulu */, Mips::DMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6409 { 3440 /* dneg */, Mips::DSUB, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg }, }, 6410 { 3440 /* dneg */, Mips::DSUB, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6411 { 3445 /* dnegu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg }, }, 6412 { 3445 /* dnegu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6413 { 3451 /* dotp_s.d */, Mips::DOTP_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6414 { 3460 /* dotp_s.h */, Mips::DOTP_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6415 { 3469 /* dotp_s.w */, Mips::DOTP_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6416 { 3478 /* dotp_u.d */, Mips::DOTP_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6417 { 3487 /* dotp_u.h */, Mips::DOTP_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6418 { 3496 /* dotp_u.w */, Mips::DOTP_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6419 { 3505 /* dpa.w.ph */, Mips::DPA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6420 { 3505 /* dpa.w.ph */, Mips::DPA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6421 { 3514 /* dpadd_s.d */, Mips::DPADD_S_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6422 { 3524 /* dpadd_s.h */, Mips::DPADD_S_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6423 { 3534 /* dpadd_s.w */, Mips::DPADD_S_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6424 { 3544 /* dpadd_u.d */, Mips::DPADD_U_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6425 { 3554 /* dpadd_u.h */, Mips::DPADD_U_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6426 { 3564 /* dpadd_u.w */, Mips::DPADD_U_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6427 { 3574 /* dpaq_s.w.ph */, Mips::DPAQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6428 { 3574 /* dpaq_s.w.ph */, Mips::DPAQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6429 { 3586 /* dpaq_sa.l.w */, Mips::DPAQ_SA_L_W_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6430 { 3586 /* dpaq_sa.l.w */, Mips::DPAQ_SA_L_W, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6431 { 3598 /* dpaqx_s.w.ph */, Mips::DPAQX_S_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6432 { 3598 /* dpaqx_s.w.ph */, Mips::DPAQX_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6433 { 3611 /* dpaqx_sa.w.ph */, Mips::DPAQX_SA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6434 { 3611 /* dpaqx_sa.w.ph */, Mips::DPAQX_SA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6435 { 3625 /* dpau.h.qbl */, Mips::DPAU_H_QBL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6436 { 3625 /* dpau.h.qbl */, Mips::DPAU_H_QBL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6437 { 3636 /* dpau.h.qbr */, Mips::DPAU_H_QBR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6438 { 3636 /* dpau.h.qbr */, Mips::DPAU_H_QBR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6439 { 3647 /* dpax.w.ph */, Mips::DPAX_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6440 { 3647 /* dpax.w.ph */, Mips::DPAX_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6441 { 3657 /* dpop */, Mips::DPOP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, }, 6442 { 3657 /* dpop */, Mips::DPOP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6443 { 3662 /* dps.w.ph */, Mips::DPS_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6444 { 3662 /* dps.w.ph */, Mips::DPS_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6445 { 3671 /* dpsq_s.w.ph */, Mips::DPSQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6446 { 3671 /* dpsq_s.w.ph */, Mips::DPSQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6447 { 3683 /* dpsq_sa.l.w */, Mips::DPSQ_SA_L_W_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6448 { 3683 /* dpsq_sa.l.w */, Mips::DPSQ_SA_L_W, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6449 { 3695 /* dpsqx_s.w.ph */, Mips::DPSQX_S_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6450 { 3695 /* dpsqx_s.w.ph */, Mips::DPSQX_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6451 { 3708 /* dpsqx_sa.w.ph */, Mips::DPSQX_SA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6452 { 3708 /* dpsqx_sa.w.ph */, Mips::DPSQX_SA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6453 { 3722 /* dpsu.h.qbl */, Mips::DPSU_H_QBL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6454 { 3722 /* dpsu.h.qbl */, Mips::DPSU_H_QBL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6455 { 3733 /* dpsu.h.qbr */, Mips::DPSU_H_QBR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6456 { 3733 /* dpsu.h.qbr */, Mips::DPSU_H_QBR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6457 { 3744 /* dpsub_s.d */, Mips::DPSUB_S_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6458 { 3754 /* dpsub_s.h */, Mips::DPSUB_S_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6459 { 3764 /* dpsub_s.w */, Mips::DPSUB_S_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6460 { 3774 /* dpsub_u.d */, Mips::DPSUB_U_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6461 { 3784 /* dpsub_u.h */, Mips::DPSUB_U_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6462 { 3794 /* dpsub_u.w */, Mips::DPSUB_U_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6463 { 3804 /* dpsx.w.ph */, Mips::DPSX_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6464 { 3804 /* dpsx.w.ph */, Mips::DPSX_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6465 { 3814 /* drem */, Mips::DSRemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6466 { 3814 /* drem */, Mips::DSRemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, }, 6467 { 3814 /* drem */, Mips::DSRemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6468 { 3814 /* drem */, Mips::DSRemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, }, 6469 { 3819 /* dremu */, Mips::DURemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6470 { 3819 /* dremu */, Mips::DURemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, }, 6471 { 3819 /* dremu */, Mips::DURemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6472 { 3819 /* dremu */, Mips::DURemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, }, 6473 { 3825 /* drol */, Mips::DROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6474 { 3825 /* drol */, Mips::DROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 6475 { 3825 /* drol */, Mips::DROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6476 { 3825 /* drol */, Mips::DROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, 6477 { 3830 /* dror */, Mips::DROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6478 { 3830 /* dror */, Mips::DRORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 6479 { 3830 /* dror */, Mips::DROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6480 { 3830 /* dror */, Mips::DRORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, 6481 { 3835 /* drotr */, Mips::DROTR, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, 6482 { 3835 /* drotr */, Mips::DROTR, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, 6483 { 3841 /* drotr32 */, Mips::DROTR32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, 6484 { 3841 /* drotr32 */, Mips::DROTR32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, 6485 { 3849 /* drotrv */, Mips::DROTRV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, 6486 { 3856 /* dsbh */, Mips::DSBH, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6487 { 3861 /* dshd */, Mips::DSHD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6488 { 3866 /* dsll */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, 6489 { 3866 /* dsll */, Mips::DSLL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, 6490 { 3866 /* dsll */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, 6491 { 3866 /* dsll */, Mips::DSLL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, 6492 { 3871 /* dsll32 */, Mips::DSLL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, 6493 { 3871 /* dsll32 */, Mips::DSLL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, 6494 { 3878 /* dsllv */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, 6495 { 3884 /* dsra */, Mips::DSRA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, 6496 { 3884 /* dsra */, Mips::DSRAV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, 6497 { 3884 /* dsra */, Mips::DSRA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, 6498 { 3889 /* dsra32 */, Mips::DSRA32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, 6499 { 3889 /* dsra32 */, Mips::DSRA32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, 6500 { 3896 /* dsrav */, Mips::DSRAV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, 6501 { 3902 /* dsrl */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, 6502 { 3902 /* dsrl */, Mips::DSRL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, 6503 { 3902 /* dsrl */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, 6504 { 3902 /* dsrl */, Mips::DSRL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, 6505 { 3907 /* dsrl32 */, Mips::DSRL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, 6506 { 3907 /* dsrl32 */, Mips::DSRL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, 6507 { 3914 /* dsrlv */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, 6508 { 3920 /* dsub */, Mips::DSUB, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6509 { 3920 /* dsub */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_InvNum }, }, 6510 { 3920 /* dsub */, Mips::DSUB, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6511 { 3920 /* dsub */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, }, 6512 { 3925 /* dsubi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_InvNum }, }, 6513 { 3925 /* dsubi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, }, 6514 { 3931 /* dsubu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6515 { 3931 /* dsubu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_InvNum }, }, 6516 { 3931 /* dsubu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6517 { 3931 /* dsubu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, }, 6518 { 3937 /* dvp */, Mips::DVP, Convert__regZERO, AMFBS_HasStdEnc_HasMips32r6, { }, }, 6519 { 3937 /* dvp */, Mips::DVP_MMR6, Convert__regZERO, AMFBS_InMicroMips_HasMips32r6, { }, }, 6520 { 3937 /* dvp */, Mips::DVP, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg }, }, 6521 { 3937 /* dvp */, Mips::DVP_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, 6522 { 3941 /* dvpe */, Mips::DVPE, Convert__regZERO, AMFBS_HasMT_NotInMicroMips, { }, }, 6523 { 3941 /* dvpe */, Mips::DVPE, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6524 { 3946 /* ehb */, Mips::EHB, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, { }, }, 6525 { 3946 /* ehb */, Mips::EHB_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, }, 6526 { 3946 /* ehb */, Mips::EHB_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, }, 6527 { 3950 /* ei */, Mips::EI, Convert__regZERO, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { }, }, 6528 { 3950 /* ei */, Mips::EI_MMR6, Convert__regZERO, AMFBS_InMicroMips_HasMips32r6, { }, }, 6529 { 3950 /* ei */, Mips::EI_MM, Convert__regZERO, AMFBS_InMicroMips, { }, }, 6530 { 3950 /* ei */, Mips::EI, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6531 { 3950 /* ei */, Mips::EI_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, 6532 { 3950 /* ei */, Mips::EI_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg }, }, 6533 { 3953 /* emt */, Mips::EMT, Convert__regZERO, AMFBS_HasMT_NotInMicroMips, { }, }, 6534 { 3953 /* emt */, Mips::EMT, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6535 { 3957 /* eret */, Mips::ERET, Convert_NoOperands, AMFBS_HasStdEnc_HasMips3_32_NotInMicroMips, { }, }, 6536 { 3957 /* eret */, Mips::ERET_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, }, 6537 { 3957 /* eret */, Mips::ERET_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, }, 6538 { 3962 /* eretnc */, Mips::ERETNC, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_NotInMicroMips, { }, }, 6539 { 3962 /* eretnc */, Mips::ERETNC_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, }, 6540 { 3969 /* evp */, Mips::EVP, Convert__regZERO, AMFBS_HasStdEnc_HasMips32r6, { }, }, 6541 { 3969 /* evp */, Mips::EVP_MMR6, Convert__regZERO, AMFBS_InMicroMips_HasMips32r6, { }, }, 6542 { 3969 /* evp */, Mips::EVP, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg }, }, 6543 { 3969 /* evp */, Mips::EVP_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, 6544 { 3973 /* evpe */, Mips::EVPE, Convert__regZERO, AMFBS_HasMT_NotInMicroMips, { }, }, 6545 { 3973 /* evpe */, Mips::EVPE, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6546 { 3978 /* ext */, Mips::EXT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, }, 6547 { 3978 /* ext */, Mips::EXT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, }, 6548 { 3978 /* ext */, Mips::EXT_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, }, 6549 { 3982 /* extp */, Mips::EXTP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, 6550 { 3982 /* extp */, Mips::EXTP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, 6551 { 3987 /* extpdp */, Mips::EXTPDP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, 6552 { 3987 /* extpdp */, Mips::EXTPDP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, 6553 { 3994 /* extpdpv */, Mips::EXTPDPV_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, 6554 { 3994 /* extpdpv */, Mips::EXTPDPV, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, 6555 { 4002 /* extpv */, Mips::EXTPV_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, 6556 { 4002 /* extpv */, Mips::EXTPV, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, 6557 { 4008 /* extr.w */, Mips::EXTR_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, 6558 { 4008 /* extr.w */, Mips::EXTR_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, 6559 { 4015 /* extr_r.w */, Mips::EXTR_R_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, 6560 { 4015 /* extr_r.w */, Mips::EXTR_R_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, 6561 { 4024 /* extr_rs.w */, Mips::EXTR_RS_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, 6562 { 4024 /* extr_rs.w */, Mips::EXTR_RS_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, 6563 { 4034 /* extr_s.h */, Mips::EXTR_S_H_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, 6564 { 4034 /* extr_s.h */, Mips::EXTR_S_H, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, 6565 { 4043 /* extrv.w */, Mips::EXTRV_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, 6566 { 4043 /* extrv.w */, Mips::EXTRV_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, 6567 { 4051 /* extrv_r.w */, Mips::EXTRV_R_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, 6568 { 4051 /* extrv_r.w */, Mips::EXTRV_R_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, 6569 { 4061 /* extrv_rs.w */, Mips::EXTRV_RS_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, 6570 { 4061 /* extrv_rs.w */, Mips::EXTRV_RS_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, 6571 { 4072 /* extrv_s.h */, Mips::EXTRV_S_H_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, 6572 { 4072 /* extrv_s.h */, Mips::EXTRV_S_H, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, 6573 { 4082 /* exts */, Mips::EXTS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, 6574 { 4082 /* exts */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, }, 6575 { 4082 /* exts */, Mips::EXTS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, 6576 { 4082 /* exts */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, }, 6577 { 4087 /* exts32 */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, 6578 { 4087 /* exts32 */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, 6579 { 4094 /* fadd.d */, Mips::FADD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6580 { 4101 /* fadd.w */, Mips::FADD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6581 { 4108 /* fcaf.d */, Mips::FCAF_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6582 { 4115 /* fcaf.w */, Mips::FCAF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6583 { 4122 /* fceq.d */, Mips::FCEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6584 { 4129 /* fceq.w */, Mips::FCEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6585 { 4136 /* fclass.d */, Mips::FCLASS_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6586 { 4145 /* fclass.w */, Mips::FCLASS_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6587 { 4154 /* fcle.d */, Mips::FCLE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6588 { 4161 /* fcle.w */, Mips::FCLE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6589 { 4168 /* fclt.d */, Mips::FCLT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6590 { 4175 /* fclt.w */, Mips::FCLT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6591 { 4182 /* fcne.d */, Mips::FCNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6592 { 4189 /* fcne.w */, Mips::FCNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6593 { 4196 /* fcor.d */, Mips::FCOR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6594 { 4203 /* fcor.w */, Mips::FCOR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6595 { 4210 /* fcueq.d */, Mips::FCUEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6596 { 4218 /* fcueq.w */, Mips::FCUEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6597 { 4226 /* fcule.d */, Mips::FCULE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6598 { 4234 /* fcule.w */, Mips::FCULE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6599 { 4242 /* fcult.d */, Mips::FCULT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6600 { 4250 /* fcult.w */, Mips::FCULT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6601 { 4258 /* fcun.d */, Mips::FCUN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6602 { 4265 /* fcun.w */, Mips::FCUN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6603 { 4272 /* fcune.d */, Mips::FCUNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6604 { 4280 /* fcune.w */, Mips::FCUNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6605 { 4288 /* fdiv.d */, Mips::FDIV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6606 { 4295 /* fdiv.w */, Mips::FDIV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6607 { 4302 /* fexdo.h */, Mips::FEXDO_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6608 { 4310 /* fexdo.w */, Mips::FEXDO_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6609 { 4318 /* fexp2.d */, Mips::FEXP2_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6610 { 4326 /* fexp2.w */, Mips::FEXP2_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6611 { 4334 /* fexupl.d */, Mips::FEXUPL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6612 { 4343 /* fexupl.w */, Mips::FEXUPL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6613 { 4352 /* fexupr.d */, Mips::FEXUPR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6614 { 4361 /* fexupr.w */, Mips::FEXUPR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6615 { 4370 /* ffint_s.d */, Mips::FFINT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6616 { 4380 /* ffint_s.w */, Mips::FFINT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6617 { 4390 /* ffint_u.d */, Mips::FFINT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6618 { 4400 /* ffint_u.w */, Mips::FFINT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6619 { 4410 /* ffql.d */, Mips::FFQL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6620 { 4417 /* ffql.w */, Mips::FFQL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6621 { 4424 /* ffqr.d */, Mips::FFQR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6622 { 4431 /* ffqr.w */, Mips::FFQR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6623 { 4438 /* fill.b */, Mips::FILL_B, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, }, 6624 { 4445 /* fill.d */, Mips::FILL_D, Convert__MSA128AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMSA_HasMips64, { MCK_MSA128AsmReg, MCK_GPR64AsmReg }, }, 6625 { 4452 /* fill.h */, Mips::FILL_H, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, }, 6626 { 4459 /* fill.w */, Mips::FILL_W, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, }, 6627 { 4466 /* flog2.d */, Mips::FLOG2_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6628 { 4474 /* flog2.w */, Mips::FLOG2_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6629 { 4482 /* floor.l.d */, Mips::FLOOR_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6630 { 4482 /* floor.l.d */, Mips::FLOOR_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6631 { 4492 /* floor.l.s */, Mips::FLOOR_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 6632 { 4492 /* floor.l.s */, Mips::FLOOR_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 6633 { 4502 /* floor.w.d */, Mips::FLOOR_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 6634 { 4502 /* floor.w.d */, Mips::FLOOR_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 6635 { 4502 /* floor.w.d */, Mips::FLOOR_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 6636 { 4502 /* floor.w.d */, Mips::FLOOR_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, 6637 { 4512 /* floor.w.s */, Mips::FLOOR_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6638 { 4512 /* floor.w.s */, Mips::FLOOR_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6639 { 4512 /* floor.w.s */, Mips::FLOOR_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6640 { 4522 /* fmadd.d */, Mips::FMADD_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6641 { 4530 /* fmadd.w */, Mips::FMADD_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6642 { 4538 /* fmax.d */, Mips::FMAX_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6643 { 4545 /* fmax.w */, Mips::FMAX_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6644 { 4552 /* fmax_a.d */, Mips::FMAX_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6645 { 4561 /* fmax_a.w */, Mips::FMAX_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6646 { 4570 /* fmin.d */, Mips::FMIN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6647 { 4577 /* fmin.w */, Mips::FMIN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6648 { 4584 /* fmin_a.d */, Mips::FMIN_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6649 { 4593 /* fmin_a.w */, Mips::FMIN_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6650 { 4602 /* fmsub.d */, Mips::FMSUB_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6651 { 4610 /* fmsub.w */, Mips::FMSUB_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6652 { 4618 /* fmul.d */, Mips::FMUL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6653 { 4625 /* fmul.w */, Mips::FMUL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6654 { 4632 /* fork */, Mips::FORK, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6655 { 4637 /* frcp.d */, Mips::FRCP_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6656 { 4644 /* frcp.w */, Mips::FRCP_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6657 { 4651 /* frint.d */, Mips::FRINT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6658 { 4659 /* frint.w */, Mips::FRINT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6659 { 4667 /* frsqrt.d */, Mips::FRSQRT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6660 { 4676 /* frsqrt.w */, Mips::FRSQRT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6661 { 4685 /* fsaf.d */, Mips::FSAF_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6662 { 4692 /* fsaf.w */, Mips::FSAF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6663 { 4699 /* fseq.d */, Mips::FSEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6664 { 4706 /* fseq.w */, Mips::FSEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6665 { 4713 /* fsle.d */, Mips::FSLE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6666 { 4720 /* fsle.w */, Mips::FSLE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6667 { 4727 /* fslt.d */, Mips::FSLT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6668 { 4734 /* fslt.w */, Mips::FSLT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6669 { 4741 /* fsne.d */, Mips::FSNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6670 { 4748 /* fsne.w */, Mips::FSNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6671 { 4755 /* fsor.d */, Mips::FSOR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6672 { 4762 /* fsor.w */, Mips::FSOR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6673 { 4769 /* fsqrt.d */, Mips::FSQRT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6674 { 4777 /* fsqrt.w */, Mips::FSQRT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6675 { 4785 /* fsub.d */, Mips::FSUB_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6676 { 4792 /* fsub.w */, Mips::FSUB_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6677 { 4799 /* fsueq.d */, Mips::FSUEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6678 { 4807 /* fsueq.w */, Mips::FSUEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6679 { 4815 /* fsule.d */, Mips::FSULE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6680 { 4823 /* fsule.w */, Mips::FSULE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6681 { 4831 /* fsult.d */, Mips::FSULT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6682 { 4839 /* fsult.w */, Mips::FSULT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6683 { 4847 /* fsun.d */, Mips::FSUN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6684 { 4854 /* fsun.w */, Mips::FSUN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6685 { 4861 /* fsune.d */, Mips::FSUNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6686 { 4869 /* fsune.w */, Mips::FSUNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6687 { 4877 /* ftint_s.d */, Mips::FTINT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6688 { 4887 /* ftint_s.w */, Mips::FTINT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6689 { 4897 /* ftint_u.d */, Mips::FTINT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6690 { 4907 /* ftint_u.w */, Mips::FTINT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6691 { 4917 /* ftq.h */, Mips::FTQ_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6692 { 4923 /* ftq.w */, Mips::FTQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6693 { 4929 /* ftrunc_s.d */, Mips::FTRUNC_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6694 { 4940 /* ftrunc_s.w */, Mips::FTRUNC_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6695 { 4951 /* ftrunc_u.d */, Mips::FTRUNC_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6696 { 4962 /* ftrunc_u.w */, Mips::FTRUNC_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6697 { 4973 /* ginvi */, Mips::GINVI, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6698 { 4973 /* ginvi */, Mips::GINVI_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6_HasGINV, { MCK_GPR32AsmReg }, }, 6699 { 4979 /* ginvt */, Mips::GINVT, Convert__GPR32AsmReg1_0__ConstantUImm2_01_1, AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, }, 6700 { 4979 /* ginvt */, Mips::GINVT_MMR6, Convert__GPR32AsmReg1_0__ConstantUImm2_01_1, AMFBS_InMicroMips_HasMips32r6_HasGINV, { MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, }, 6701 { 4985 /* hadd_s.d */, Mips::HADD_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6702 { 4994 /* hadd_s.h */, Mips::HADD_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6703 { 5003 /* hadd_s.w */, Mips::HADD_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6704 { 5012 /* hadd_u.d */, Mips::HADD_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6705 { 5021 /* hadd_u.h */, Mips::HADD_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6706 { 5030 /* hadd_u.w */, Mips::HADD_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6707 { 5039 /* hsub_s.d */, Mips::HSUB_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6708 { 5048 /* hsub_s.h */, Mips::HSUB_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6709 { 5057 /* hsub_s.w */, Mips::HSUB_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6710 { 5066 /* hsub_u.d */, Mips::HSUB_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6711 { 5075 /* hsub_u.h */, Mips::HSUB_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6712 { 5084 /* hsub_u.w */, Mips::HSUB_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6713 { 5093 /* hypcall */, Mips::HYPCALL, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, }, 6714 { 5093 /* hypcall */, Mips::HYPCALL_MM, Convert__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, }, 6715 { 5093 /* hypcall */, Mips::HYPCALL, Convert__ConstantUImm10_01_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_ConstantUImm10_0 }, }, 6716 { 5093 /* hypcall */, Mips::HYPCALL_MM, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_ConstantUImm10_0 }, }, 6717 { 5101 /* ilvev.b */, Mips::ILVEV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6718 { 5109 /* ilvev.d */, Mips::ILVEV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6719 { 5117 /* ilvev.h */, Mips::ILVEV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6720 { 5125 /* ilvev.w */, Mips::ILVEV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6721 { 5133 /* ilvl.b */, Mips::ILVL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6722 { 5140 /* ilvl.d */, Mips::ILVL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6723 { 5147 /* ilvl.h */, Mips::ILVL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6724 { 5154 /* ilvl.w */, Mips::ILVL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6725 { 5161 /* ilvod.b */, Mips::ILVOD_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6726 { 5169 /* ilvod.d */, Mips::ILVOD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6727 { 5177 /* ilvod.h */, Mips::ILVOD_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6728 { 5185 /* ilvod.w */, Mips::ILVOD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6729 { 5193 /* ilvr.b */, Mips::ILVR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6730 { 5200 /* ilvr.d */, Mips::ILVR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6731 { 5207 /* ilvr.h */, Mips::ILVR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6732 { 5214 /* ilvr.w */, Mips::ILVR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6733 { 5221 /* ins */, Mips::INS, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, }, 6734 { 5221 /* ins */, Mips::INS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, }, 6735 { 5221 /* ins */, Mips::INS_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, }, 6736 { 5225 /* insert.b */, Mips::INSERT_B, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_, MCK_GPR32AsmReg }, }, 6737 { 5234 /* insert.d */, Mips::INSERT_D, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2, AMFBS_HasStdEnc_HasMSA_HasMips64, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_, MCK_GPR64AsmReg }, }, 6738 { 5243 /* insert.h */, Mips::INSERT_H, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_, MCK_GPR32AsmReg }, }, 6739 { 5252 /* insert.w */, Mips::INSERT_W, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_, MCK_GPR32AsmReg }, }, 6740 { 5261 /* insv */, Mips::INSV_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6741 { 5261 /* insv */, Mips::INSV, Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6742 { 5266 /* insve.b */, Mips::INSVE_B, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, }, 6743 { 5274 /* insve.d */, Mips::INSVE_D, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, }, 6744 { 5282 /* insve.h */, Mips::INSVE_H, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, }, 6745 { 5290 /* insve.w */, Mips::INSVE_W, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, }, 6746 { 5298 /* j */, Mips::JR, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6747 { 5298 /* j */, Mips::JR_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, 6748 { 5298 /* j */, Mips::J_MM, Convert__Imm1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_Imm }, }, 6749 { 5298 /* j */, Mips::J, Convert__JumpTarget1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_JumpTarget }, }, 6750 { 5300 /* jal */, Mips::JalOneReg, Convert__GPR32AsmReg1_0, AMFBS_None, { MCK_GPR32AsmReg }, }, 6751 { 5300 /* jal */, Mips::JAL_MM, Convert__Imm1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_Imm }, }, 6752 { 5300 /* jal */, Mips::JAL, Convert__JumpTarget1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_JumpTarget }, }, 6753 { 5300 /* jal */, Mips::BALC_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, }, 6754 { 5300 /* jal */, Mips::JalTwoReg, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6755 { 5304 /* jalr */, Mips::JALR16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, 6756 { 5304 /* jalr */, Mips::JALRC16_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, 6757 { 5304 /* jalr */, Mips::JALR, Convert__regRA__GPR32AsmReg1_0, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6758 { 5304 /* jalr */, Mips::JALR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6759 { 5304 /* jalr */, Mips::JALR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6760 { 5304 /* jalr */, Mips::JALR64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_NotInMips16Mode_IsPTR64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6761 { 5309 /* jalr.hb */, Mips::JALR_HB, Convert__regRA__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6762 { 5309 /* jalr.hb */, Mips::JALR_HB64, Convert__regRA_64__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips64_NotInMicroMips, { MCK_GPR64AsmReg }, }, 6763 { 5309 /* jalr.hb */, Mips::JALR_HB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6764 { 5309 /* jalr.hb */, Mips::JALR_HB64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6765 { 5317 /* jalrc */, Mips::JumpLinkReg16, Convert__Reg1_0, AMFBS_InMips16Mode, { MCK_CPU16Regs }, }, 6766 { 5317 /* jalrc */, Mips::JIALC, Convert__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6767 { 5317 /* jalrc */, Mips::JALRC_MMR6, Convert__regRA__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, 6768 { 5317 /* jalrc */, Mips::JIALC64, Convert__GPR64AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips64r6, { MCK_GPR64AsmReg }, }, 6769 { 5317 /* jalrc */, Mips::JALRC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6770 { 5323 /* jalrc.hb */, Mips::JALRC_HB_MMR6, Convert__regRA__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, 6771 { 5323 /* jalrc.hb */, Mips::JALRC_HB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6772 { 5332 /* jalrs */, Mips::JALRS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6773 { 5338 /* jalrs16 */, Mips::JALRS16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, 6774 { 5346 /* jals */, Mips::JALS_MM, Convert__Imm1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_Imm }, }, 6775 { 5351 /* jalx */, Mips::JALX, Convert__JumpTarget1_0, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_JumpTarget }, }, 6776 { 5351 /* jalx */, Mips::JALX_MM, Convert__JumpTarget1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_JumpTarget }, }, 6777 { 5356 /* jialc */, Mips::JIALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 6778 { 5356 /* jialc */, Mips::JIALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 6779 { 5356 /* jialc */, Mips::JIALC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, 6780 { 5362 /* jic */, Mips::JIC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 6781 { 5362 /* jic */, Mips::JIC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 6782 { 5362 /* jic */, Mips::JIC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, 6783 { 5366 /* jr */, Mips::JrRa16, Convert_NoOperands, AMFBS_InMips16Mode, { MCK_CPURAReg }, }, 6784 { 5366 /* jr */, Mips::JR, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6785 { 5366 /* jr */, Mips::JALR, Convert__regZERO__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6786 { 5366 /* jr */, Mips::JR_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, 6787 { 5366 /* jr */, Mips::JR64, Convert__GPR64AsmReg1_0, AMFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips, { MCK_GPR64AsmReg }, }, 6788 { 5366 /* jr */, Mips::JALR64, Convert__regZERO_64__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips64r6, { MCK_GPR64AsmReg }, }, 6789 { 5369 /* jr.hb */, Mips::JR_HB, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg }, }, 6790 { 5369 /* jr.hb */, Mips::JR_HB_R6, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg }, }, 6791 { 5369 /* jr.hb */, Mips::JR_HB64, Convert__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg }, }, 6792 { 5369 /* jr.hb */, Mips::JR_HB64_R6, Convert__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR64AsmReg }, }, 6793 { 5375 /* jr16 */, Mips::JR16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, 6794 { 5380 /* jraddiusp */, Mips::JRADDIUSP, Convert__UImm5Lsl21_0, AMFBS_InMicroMips_NotMips32r6, { MCK_UImm5Lsl2 }, }, 6795 { 5390 /* jrc */, Mips::JrcRa16, Convert_NoOperands, AMFBS_InMips16Mode, { MCK_CPURAReg }, }, 6796 { 5390 /* jrc */, Mips::JrcRx16, Convert__Reg1_0, AMFBS_InMips16Mode, { MCK_CPU16Regs }, }, 6797 { 5390 /* jrc */, Mips::JIC, Convert__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6, { MCK_GPR32AsmReg }, }, 6798 { 5390 /* jrc */, Mips::JRC16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, 6799 { 5390 /* jrc */, Mips::JIC64, Convert__GPR64AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips64r6, { MCK_GPR64AsmReg }, }, 6800 { 5394 /* jrc16 */, Mips::JRC16_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, 6801 { 5400 /* jrcaddiusp */, Mips::JRCADDIUSP_MMR6, Convert__UImm5Lsl21_0, AMFBS_InMicroMips_HasMips32r6, { MCK_UImm5Lsl2 }, }, 6802 { 5411 /* l.d */, Mips::LDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, }, 6803 { 5411 /* l.d */, Mips::LDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16_0 }, }, 6804 { 5415 /* l.s */, Mips::LWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16_0 }, }, 6805 { 5419 /* la */, Mips::LoadAddrImm32, Convert__GPR32AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm }, }, 6806 { 5419 /* la */, Mips::LoadAddrReg32, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, }, 6807 { 5422 /* lapc */, Mips::ADDIUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, }, 6808 { 5422 /* lapc */, Mips::ADDIUPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, }, 6809 { 5427 /* lb */, Mips::LB, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, 6810 { 5427 /* lb */, Mips::LB_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16_0 }, }, 6811 { 5427 /* lb */, Mips::LB_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16_0 }, }, 6812 { 5430 /* lbe */, Mips::LBE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, 6813 { 5430 /* lbe */, Mips::LBE_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_Mem }, }, 6814 { 5434 /* lbu */, Mips::LBu, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, 6815 { 5434 /* lbu */, Mips::LBU_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16_0 }, }, 6816 { 5434 /* lbu */, Mips::LBu_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16_0 }, }, 6817 { 5438 /* lbu16 */, Mips::LBU16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, }, 6818 { 5444 /* lbue */, Mips::LBuE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, 6819 { 5444 /* lbue */, Mips::LBuE_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_Mem }, }, 6820 { 5449 /* lbux */, Mips::LBUX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 6821 { 5449 /* lbux */, Mips::LBUX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 6822 { 5454 /* ld */, Mips::LDMacro, Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotMips3, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16_0 }, }, 6823 { 5454 /* ld */, Mips::LD, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, }, 6824 { 5457 /* ld.b */, Mips::LD_B, Convert__MSA128AsmReg1_0__MemOffsetSimm10_02_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_0 }, }, 6825 { 5462 /* ld.d */, Mips::LD_D, Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_3 }, }, 6826 { 5467 /* ld.h */, Mips::LD_H, Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_1 }, }, 6827 { 5472 /* ld.w */, Mips::LD_W, Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_2 }, }, 6828 { 5477 /* ldc1 */, Mips::LDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, }, 6829 { 5477 /* ldc1 */, Mips::LDC1_MM, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, }, 6830 { 5477 /* ldc1 */, Mips::LDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16_0 }, }, 6831 { 5477 /* ldc1 */, Mips::LDC1_D64_MMR6, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16_0 }, }, 6832 { 5482 /* ldc2 */, Mips::LDC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, }, 6833 { 5482 /* ldc2 */, Mips::LDC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, }, 6834 { 5482 /* ldc2 */, Mips::LDC2, Convert__COP2AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16_0 }, }, 6835 { 5487 /* ldc3 */, Mips::LDC3, Convert__COP3AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, }, 6836 { 5492 /* ldi.b */, Mips::LDI_B, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, }, 6837 { 5498 /* ldi.d */, Mips::LDI_D, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, }, 6838 { 5504 /* ldi.h */, Mips::LDI_H, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, }, 6839 { 5510 /* ldi.w */, Mips::LDI_W, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, }, 6840 { 5516 /* ldl */, Mips::LDL, Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, }, 6841 { 5520 /* ldpc */, Mips::LDPC, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, 6842 { 5525 /* ldr */, Mips::LDR, Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, }, 6843 { 5529 /* ldxc1 */, Mips::LDXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 6844 { 5529 /* ldxc1 */, Mips::LDXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 6845 { 5535 /* lh */, Mips::LH, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, 6846 { 5535 /* lh */, Mips::LH_MM, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, 6847 { 5538 /* lhe */, Mips::LHE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, 6848 { 5538 /* lhe */, Mips::LHE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, 6849 { 5542 /* lhu */, Mips::LHu, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, 6850 { 5542 /* lhu */, Mips::LHu_MM, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, 6851 { 5546 /* lhu16 */, Mips::LHU16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, }, 6852 { 5552 /* lhue */, Mips::LHuE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, 6853 { 5552 /* lhue */, Mips::LHuE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, 6854 { 5557 /* lhx */, Mips::LHX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 6855 { 5557 /* lhx */, Mips::LHX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 6856 { 5561 /* li */, Mips::LiRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, }, 6857 { 5561 /* li */, Mips::LoadImm32, Convert__GPR32AsmReg1_0__UImm32_Coerced1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_UImm32_Coerced }, }, 6858 { 5561 /* li */, Mips::LiRxImm16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, }, 6859 { 5564 /* li.d */, Mips::LoadImmDoubleGPR, Convert__GPR32AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm }, }, 6860 { 5564 /* li.d */, Mips::LoadImmDoubleFGR_32, Convert__StrictlyAFGR64AsmReg1_0__Imm1_1, AMFBS_NotFP64bit_IsNotSoftFloat, { MCK_StrictlyAFGR64AsmReg, MCK_Imm }, }, 6861 { 5564 /* li.d */, Mips::LoadImmDoubleFGR, Convert__StrictlyFGR64AsmReg1_0__Imm1_1, AMFBS_IsFP64bit_IsNotSoftFloat, { MCK_StrictlyFGR64AsmReg, MCK_Imm }, }, 6862 { 5569 /* li.s */, Mips::LoadImmSingleGPR, Convert__GPR32AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm }, }, 6863 { 5569 /* li.s */, Mips::LoadImmSingleFGR, Convert__StrictlyFGR32AsmReg1_0__Imm1_1, AMFBS_IsNotSoftFloat, { MCK_StrictlyFGR32AsmReg, MCK_Imm }, }, 6864 { 5574 /* li16 */, Mips::LI16_MM, Convert__GPRMM16AsmReg1_0__UImm7_N11_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_UImm7_N1 }, }, 6865 { 5574 /* li16 */, Mips::LI16_MMR6, Convert__GPRMM16AsmReg1_0__UImm7_N11_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_UImm7_N1 }, }, 6866 { 5579 /* ll */, Mips::LL64_R6, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, 6867 { 5579 /* ll */, Mips::LL_R6, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, 6868 { 5579 /* ll */, Mips::LL_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, 6869 { 5579 /* ll */, Mips::LL, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 6870 { 5579 /* ll */, Mips::LL64, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 6871 { 5579 /* ll */, Mips::LL_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, 6872 { 5582 /* lld */, Mips::LLD, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, }, 6873 { 5582 /* lld */, Mips::LLD_R6, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, }, 6874 { 5586 /* lle */, Mips::LLE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, 6875 { 5586 /* lle */, Mips::LLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, 6876 { 5590 /* lsa */, Mips::LSA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, }, 6877 { 5590 /* lsa */, Mips::LSA_MMR6, Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, }, 6878 { 5590 /* lsa */, Mips::LSA_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, }, 6879 { 5594 /* lui */, Mips::LUI_MMR6, Convert__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, 6880 { 5594 /* lui */, Mips::LUi, Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16_Relaxed }, }, 6881 { 5594 /* lui */, Mips::LUi_MM, Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16_Relaxed }, }, 6882 { 5598 /* luxc1 */, Mips::LUXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 6883 { 5598 /* luxc1 */, Mips::LUXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 6884 { 5598 /* luxc1 */, Mips::LUXC1_MM, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 6885 { 5604 /* lw */, Mips::LwRxPcTcpX16, Convert__Reg1_0__Imm1_1__imm_95_0, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_Imm }, }, 6886 { 5604 /* lw */, Mips::LWSP_MM, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, }, 6887 { 5604 /* lw */, Mips::LW, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 6888 { 5604 /* lw */, Mips::LWDSP, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_NotInMips16Mode_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, }, 6889 { 5604 /* lw */, Mips::LWDSP_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, }, 6890 { 5604 /* lw */, Mips::LW_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, 6891 { 5604 /* lw */, Mips::LW_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 6892 { 5604 /* lw */, Mips::LWGP_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMemGP }, }, 6893 { 5604 /* lw */, Mips::LwRxSpImmX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, }, 6894 { 5604 /* lw */, Mips::LwRxPcTcp16, Convert__Reg1_0__Imm1_1__imm_95_0, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_Imm, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, }, 6895 { 5607 /* lw16 */, Mips::LW16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, }, 6896 { 5612 /* lwc1 */, Mips::LWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16_0 }, }, 6897 { 5612 /* lwc1 */, Mips::LWC1_MM, Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16_0 }, }, 6898 { 5617 /* lwc2 */, Mips::LWC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, }, 6899 { 5617 /* lwc2 */, Mips::LWC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, }, 6900 { 5617 /* lwc2 */, Mips::LWC2, Convert__COP2AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16_0 }, }, 6901 { 5622 /* lwc3 */, Mips::LWC3, Convert__COP3AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, }, 6902 { 5627 /* lwe */, Mips::LWE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, 6903 { 5627 /* lwe */, Mips::LWE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, 6904 { 5631 /* lwl */, Mips::LWL, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 6905 { 5631 /* lwl */, Mips::LWL_MM, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, 6906 { 5635 /* lwle */, Mips::LWLE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1__Tie0_1_1, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, 6907 { 5635 /* lwle */, Mips::LWLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, 6908 { 5640 /* lwm */, Mips::LWM_MM, Convert__RegList1_0__Mem2_1, AMFBS_InMicroMips, { MCK_RegList, MCK_Mem }, }, 6909 { 5644 /* lwm16 */, Mips::LWM16_MM, Convert__RegList161_0__MemOffsetUimm42_1, AMFBS_InMicroMips_NotMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, }, 6910 { 5644 /* lwm16 */, Mips::LWM16_MMR6, Convert__RegList161_0__MemOffsetUimm42_1, AMFBS_InMicroMips_HasMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, }, 6911 { 5650 /* lwm32 */, Mips::LWM32_MM, Convert__RegList1_0__Mem2_1, AMFBS_InMicroMips, { MCK_RegList, MCK_Mem }, }, 6912 { 5656 /* lwp */, Mips::LWP_MM, ConvertCustom_ConvertXWPOperands, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm12_0 }, }, 6913 { 5660 /* lwpc */, Mips::LWPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, }, 6914 { 5660 /* lwpc */, Mips::LWPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, }, 6915 { 5665 /* lwr */, Mips::LWR, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 6916 { 5665 /* lwr */, Mips::LWR_MM, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, 6917 { 5669 /* lwre */, Mips::LWRE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1__Tie0_1_1, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, 6918 { 5669 /* lwre */, Mips::LWRE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, 6919 { 5674 /* lwu */, Mips::LWU_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm12_02_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm12_0 }, }, 6920 { 5674 /* lwu */, Mips::LWu, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Mem }, }, 6921 { 5678 /* lwupc */, Mips::LWUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_HasStdEnc_HasMips64r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, }, 6922 { 5684 /* lwx */, Mips::LWX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 6923 { 5684 /* lwx */, Mips::LWX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 6924 { 5688 /* lwxc1 */, Mips::LWXC1, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 6925 { 5688 /* lwxc1 */, Mips::LWXC1_MM, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 6926 { 5694 /* lwxs */, Mips::LWXS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 6927 { 5699 /* madd */, Mips::MADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6928 { 5699 /* madd */, Mips::MADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6929 { 5699 /* madd */, Mips::MADD_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6930 { 5699 /* madd */, Mips::MADD_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6931 { 5704 /* madd.d */, Mips::MADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6932 { 5704 /* madd.d */, Mips::MADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6933 { 5704 /* madd.d */, Mips::MADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6934 { 5711 /* madd.s */, Mips::MADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6935 { 5711 /* madd.s */, Mips::MADD_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6936 { 5718 /* madd_q.h */, Mips::MADD_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6937 { 5727 /* madd_q.w */, Mips::MADD_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6938 { 5736 /* maddf.d */, Mips::MADDF_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6939 { 5736 /* maddf.d */, Mips::MADDF_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6940 { 5744 /* maddf.s */, Mips::MADDF_S, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6941 { 5744 /* maddf.s */, Mips::MADDF_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6942 { 5752 /* maddr_q.h */, Mips::MADDR_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6943 { 5762 /* maddr_q.w */, Mips::MADDR_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6944 { 5772 /* maddu */, Mips::MADDU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6945 { 5772 /* maddu */, Mips::MADDU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6946 { 5772 /* maddu */, Mips::MADDU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6947 { 5772 /* maddu */, Mips::MADDU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6948 { 5778 /* maddv.b */, Mips::MADDV_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6949 { 5786 /* maddv.d */, Mips::MADDV_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6950 { 5794 /* maddv.h */, Mips::MADDV_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6951 { 5802 /* maddv.w */, Mips::MADDV_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6952 { 5810 /* maq_s.w.phl */, Mips::MAQ_S_W_PHL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6953 { 5810 /* maq_s.w.phl */, Mips::MAQ_S_W_PHL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6954 { 5822 /* maq_s.w.phr */, Mips::MAQ_S_W_PHR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6955 { 5822 /* maq_s.w.phr */, Mips::MAQ_S_W_PHR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6956 { 5834 /* maq_sa.w.phl */, Mips::MAQ_SA_W_PHL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6957 { 5834 /* maq_sa.w.phl */, Mips::MAQ_SA_W_PHL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6958 { 5847 /* maq_sa.w.phr */, Mips::MAQ_SA_W_PHR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6959 { 5847 /* maq_sa.w.phr */, Mips::MAQ_SA_W_PHR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6960 { 5860 /* max.d */, Mips::MAX_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6961 { 5860 /* max.d */, Mips::MAX_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6962 { 5866 /* max.s */, Mips::MAX_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6963 { 5866 /* max.s */, Mips::MAX_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6964 { 5872 /* max_a.b */, Mips::MAX_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6965 { 5880 /* max_a.d */, Mips::MAX_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6966 { 5888 /* max_a.h */, Mips::MAX_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6967 { 5896 /* max_a.w */, Mips::MAX_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6968 { 5904 /* max_s.b */, Mips::MAX_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6969 { 5912 /* max_s.d */, Mips::MAX_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6970 { 5920 /* max_s.h */, Mips::MAX_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6971 { 5928 /* max_s.w */, Mips::MAX_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6972 { 5936 /* max_u.b */, Mips::MAX_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6973 { 5944 /* max_u.d */, Mips::MAX_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6974 { 5952 /* max_u.h */, Mips::MAX_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6975 { 5960 /* max_u.w */, Mips::MAX_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6976 { 5968 /* maxa.d */, Mips::MAXA_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6977 { 5968 /* maxa.d */, Mips::MAXA_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6978 { 5975 /* maxa.s */, Mips::MAXA_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6979 { 5975 /* maxa.s */, Mips::MAXA_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6980 { 5982 /* maxi_s.b */, Mips::MAXI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 6981 { 5991 /* maxi_s.d */, Mips::MAXI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 6982 { 6000 /* maxi_s.h */, Mips::MAXI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 6983 { 6009 /* maxi_s.w */, Mips::MAXI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 6984 { 6018 /* maxi_u.b */, Mips::MAXI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 6985 { 6027 /* maxi_u.d */, Mips::MAXI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 6986 { 6036 /* maxi_u.h */, Mips::MAXI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 6987 { 6045 /* maxi_u.w */, Mips::MAXI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 6988 { 6054 /* mfc0 */, Mips::MFC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 6989 { 6054 /* mfc0 */, Mips::MFC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 6990 { 6054 /* mfc0 */, Mips::MFC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 6991 { 6054 /* mfc0 */, Mips::MFC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 6992 { 6059 /* mfc1 */, Mips::MFC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, 6993 { 6059 /* mfc1 */, Mips::MFC1_MMR6, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, 6994 { 6059 /* mfc1 */, Mips::MFC1_MM, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, 6995 { 6059 /* mfc1 */, Mips::MFC1_D64, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, }, 6996 { 6064 /* mfc2 */, Mips::MFC2_MMR6, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, 6997 { 6064 /* mfc2 */, Mips::MFC2, Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, 6998 { 6064 /* mfc2 */, Mips::MFC2, Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, }, 6999 { 6069 /* mfgc0 */, Mips::MFGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 7000 { 6069 /* mfgc0 */, Mips::MFGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 7001 { 6069 /* mfgc0 */, Mips::MFGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 7002 { 6069 /* mfgc0 */, Mips::MFGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 7003 { 6075 /* mfhc0 */, Mips::MFHC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 7004 { 6075 /* mfhc0 */, Mips::MFHC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 7005 { 6081 /* mfhc1 */, Mips::MFHC1_D32, Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, }, 7006 { 6081 /* mfhc1 */, Mips::MFHC1_D32_MM, Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, }, 7007 { 6081 /* mfhc1 */, Mips::MFHC1_D64, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, }, 7008 { 6081 /* mfhc1 */, Mips::MFHC1_D64_MM, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, }, 7009 { 6087 /* mfhc2 */, Mips::MFHC2_MMR6, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, 7010 { 6093 /* mfhgc0 */, Mips::MFHGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 7011 { 6093 /* mfhgc0 */, Mips::MFHGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 7012 { 6093 /* mfhgc0 */, Mips::MFHGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 7013 { 6093 /* mfhgc0 */, Mips::MFHGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 7014 { 6100 /* mfhi */, Mips::Mfhi16, Convert__Reg1_0, AMFBS_InMips16Mode, { MCK_CPU16Regs }, }, 7015 { 6100 /* mfhi */, Mips::MFHI, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, }, 7016 { 6100 /* mfhi */, Mips::MFHI_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, 7017 { 6100 /* mfhi */, Mips::MFHI_DSP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, 7018 { 6100 /* mfhi */, Mips::MFHI_DSP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, 7019 { 6105 /* mfhi16 */, Mips::MFHI16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, 7020 { 6112 /* mflo */, Mips::Mflo16, Convert__Reg1_0, AMFBS_InMips16Mode, { MCK_CPU16Regs }, }, 7021 { 6112 /* mflo */, Mips::MFLO, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, }, 7022 { 6112 /* mflo */, Mips::MFLO_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, 7023 { 6112 /* mflo */, Mips::MFLO_DSP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, 7024 { 6112 /* mflo */, Mips::MFLO_DSP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, 7025 { 6117 /* mflo16 */, Mips::MFLO16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, 7026 { 6124 /* mftacx */, Mips::MFTACX, Convert__GPR32AsmReg1_0__regAC0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, 7027 { 6124 /* mftacx */, Mips::MFTACX, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, 7028 { 6131 /* mftc0 */, Mips::MFTC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 7029 { 6131 /* mftc0 */, Mips::MFTC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 7030 { 6137 /* mftc1 */, Mips::MFTC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, 7031 { 6143 /* mftdsp */, Mips::MFTDSP, Convert__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg }, }, 7032 { 6150 /* mftgpr */, Mips::MFTGPR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7033 { 6157 /* mfthc1 */, Mips::MFTHC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, 7034 { 6164 /* mfthi */, Mips::MFTHI, Convert__GPR32AsmReg1_0__regAC0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, 7035 { 6164 /* mfthi */, Mips::MFTHI, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, 7036 { 6170 /* mftlo */, Mips::MFTLO, Convert__GPR32AsmReg1_0__regAC0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, 7037 { 6170 /* mftlo */, Mips::MFTLO, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, 7038 { 6176 /* mftr */, Mips::MFTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm1_0, MCK_ConstantUImm3_0, MCK_ConstantUImm1_0 }, }, 7039 { 6181 /* min.d */, Mips::MIN_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7040 { 6181 /* min.d */, Mips::MIN_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7041 { 6187 /* min.s */, Mips::MIN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7042 { 6187 /* min.s */, Mips::MIN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7043 { 6193 /* min_a.b */, Mips::MIN_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7044 { 6201 /* min_a.d */, Mips::MIN_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7045 { 6209 /* min_a.h */, Mips::MIN_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7046 { 6217 /* min_a.w */, Mips::MIN_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7047 { 6225 /* min_s.b */, Mips::MIN_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7048 { 6233 /* min_s.d */, Mips::MIN_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7049 { 6241 /* min_s.h */, Mips::MIN_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7050 { 6249 /* min_s.w */, Mips::MIN_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7051 { 6257 /* min_u.b */, Mips::MIN_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7052 { 6265 /* min_u.d */, Mips::MIN_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7053 { 6273 /* min_u.h */, Mips::MIN_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7054 { 6281 /* min_u.w */, Mips::MIN_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7055 { 6289 /* mina.d */, Mips::MINA_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7056 { 6289 /* mina.d */, Mips::MINA_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7057 { 6296 /* mina.s */, Mips::MINA_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7058 { 6296 /* mina.s */, Mips::MINA_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7059 { 6303 /* mini_s.b */, Mips::MINI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 7060 { 6312 /* mini_s.d */, Mips::MINI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 7061 { 6321 /* mini_s.h */, Mips::MINI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 7062 { 6330 /* mini_s.w */, Mips::MINI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 7063 { 6339 /* mini_u.b */, Mips::MINI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 7064 { 6348 /* mini_u.d */, Mips::MINI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 7065 { 6357 /* mini_u.h */, Mips::MINI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 7066 { 6366 /* mini_u.w */, Mips::MINI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 7067 { 6375 /* mod */, Mips::MOD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7068 { 6375 /* mod */, Mips::MOD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7069 { 6379 /* mod_s.b */, Mips::MOD_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7070 { 6387 /* mod_s.d */, Mips::MOD_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7071 { 6395 /* mod_s.h */, Mips::MOD_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7072 { 6403 /* mod_s.w */, Mips::MOD_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7073 { 6411 /* mod_u.b */, Mips::MOD_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7074 { 6419 /* mod_u.d */, Mips::MOD_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7075 { 6427 /* mod_u.h */, Mips::MOD_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7076 { 6435 /* mod_u.w */, Mips::MOD_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7077 { 6443 /* modsub */, Mips::MODSUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7078 { 6443 /* modsub */, Mips::MODSUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7079 { 6450 /* modu */, Mips::MODU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7080 { 6450 /* modu */, Mips::MODU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7081 { 6455 /* mov.d */, Mips::FMOV_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7082 { 6455 /* mov.d */, Mips::FMOV_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7083 { 6455 /* mov.d */, Mips::FMOV_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7084 { 6455 /* mov.d */, Mips::FMOV_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7085 { 6455 /* mov.d */, Mips::FMOV_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7086 { 6461 /* mov.s */, Mips::FMOV_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7087 { 6461 /* mov.s */, Mips::FMOV_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7088 { 6461 /* mov.s */, Mips::FMOV_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7089 { 6467 /* move */, Mips::MoveR3216, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_DSPR }, }, 7090 { 6467 /* move */, Mips::Move32R16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_DSPR, MCK_CPU16Regs }, }, 7091 { 6467 /* move */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7092 { 6467 /* move */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7093 { 6467 /* move */, Mips::MOVE16_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7094 { 6467 /* move */, Mips::OR64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64, AMFBS_IsGP64bit_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 7095 { 6467 /* move */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64, AMFBS_IsGP64bit_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 7096 { 6472 /* move.v */, Mips::MOVE_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7097 { 6479 /* move16 */, Mips::MOVE16_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7098 { 6486 /* movep */, Mips::MOVEP_MM, Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmRegMovePPairFirst, MCK_GPRMM16AsmRegMovePPairSecond, MCK_GPRMM16AsmRegMoveP, MCK_GPRMM16AsmRegMoveP }, }, 7099 { 6486 /* movep */, Mips::MOVEP_MMR6, Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmRegMovePPairFirst, MCK_GPRMM16AsmRegMovePPairSecond, MCK_GPRMM16AsmRegMoveP, MCK_GPRMM16AsmRegMoveP }, }, 7100 { 6492 /* movf */, Mips::MOVF_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, }, 7101 { 6492 /* movf */, Mips::MOVF_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, }, 7102 { 6497 /* movf.d */, Mips::MOVF_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, }, 7103 { 6497 /* movf.d */, Mips::MOVF_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, }, 7104 { 6497 /* movf.d */, Mips::MOVF_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FCCAsmReg }, }, 7105 { 6504 /* movf.s */, Mips::MOVF_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, }, 7106 { 6504 /* movf.s */, Mips::MOVF_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, }, 7107 { 6511 /* movn */, Mips::MOVN_I_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7108 { 6511 /* movn */, Mips::MOVN_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7109 { 6516 /* movn.d */, Mips::MOVN_I_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, }, 7110 { 6516 /* movn.d */, Mips::MOVN_I_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, }, 7111 { 6516 /* movn.d */, Mips::MOVN_I_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, }, 7112 { 6523 /* movn.s */, Mips::MOVN_I_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, }, 7113 { 6523 /* movn.s */, Mips::MOVN_I_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, }, 7114 { 6530 /* movt */, Mips::MOVT_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, }, 7115 { 6530 /* movt */, Mips::MOVT_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, }, 7116 { 6535 /* movt.d */, Mips::MOVT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, }, 7117 { 6535 /* movt.d */, Mips::MOVT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, }, 7118 { 6535 /* movt.d */, Mips::MOVT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FCCAsmReg }, }, 7119 { 6542 /* movt.s */, Mips::MOVT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, }, 7120 { 6542 /* movt.s */, Mips::MOVT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, }, 7121 { 6549 /* movz */, Mips::MOVZ_I_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7122 { 6549 /* movz */, Mips::MOVZ_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7123 { 6554 /* movz.d */, Mips::MOVZ_I_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, }, 7124 { 6554 /* movz.d */, Mips::MOVZ_I_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, }, 7125 { 6554 /* movz.d */, Mips::MOVZ_I_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, }, 7126 { 6561 /* movz.s */, Mips::MOVZ_I_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, }, 7127 { 6561 /* movz.s */, Mips::MOVZ_I_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, }, 7128 { 6568 /* msub */, Mips::MSUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7129 { 6568 /* msub */, Mips::MSUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7130 { 6568 /* msub */, Mips::MSUB_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7131 { 6568 /* msub */, Mips::MSUB_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7132 { 6573 /* msub.d */, Mips::MSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7133 { 6573 /* msub.d */, Mips::MSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7134 { 6573 /* msub.d */, Mips::MSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7135 { 6580 /* msub.s */, Mips::MSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7136 { 6580 /* msub.s */, Mips::MSUB_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7137 { 6587 /* msub_q.h */, Mips::MSUB_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7138 { 6596 /* msub_q.w */, Mips::MSUB_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7139 { 6605 /* msubf.d */, Mips::MSUBF_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7140 { 6605 /* msubf.d */, Mips::MSUBF_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7141 { 6613 /* msubf.s */, Mips::MSUBF_S, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7142 { 6613 /* msubf.s */, Mips::MSUBF_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7143 { 6621 /* msubr_q.h */, Mips::MSUBR_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7144 { 6631 /* msubr_q.w */, Mips::MSUBR_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7145 { 6641 /* msubu */, Mips::MSUBU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7146 { 6641 /* msubu */, Mips::MSUBU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7147 { 6641 /* msubu */, Mips::MSUBU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7148 { 6641 /* msubu */, Mips::MSUBU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7149 { 6647 /* msubv.b */, Mips::MSUBV_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7150 { 6655 /* msubv.d */, Mips::MSUBV_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7151 { 6663 /* msubv.h */, Mips::MSUBV_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7152 { 6671 /* msubv.w */, Mips::MSUBV_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7153 { 6679 /* mtc0 */, Mips::MTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 7154 { 6679 /* mtc0 */, Mips::MTC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 7155 { 6679 /* mtc0 */, Mips::MTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 7156 { 6679 /* mtc0 */, Mips::MTC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 7157 { 6684 /* mtc1 */, Mips::MTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, 7158 { 6684 /* mtc1 */, Mips::MTC1_MMR6, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, 7159 { 6684 /* mtc1 */, Mips::MTC1_MM, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, 7160 { 6684 /* mtc1 */, Mips::MTC1_D64, Convert__FGR64AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, }, 7161 { 6684 /* mtc1 */, Mips::MTC1_D64_MM, Convert__FGR64AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, }, 7162 { 6689 /* mtc2 */, Mips::MTC2_MMR6, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, 7163 { 6689 /* mtc2 */, Mips::MTC2, Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, 7164 { 6689 /* mtc2 */, Mips::MTC2, Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, }, 7165 { 6694 /* mtgc0 */, Mips::MTGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 7166 { 6694 /* mtgc0 */, Mips::MTGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 7167 { 6694 /* mtgc0 */, Mips::MTGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 7168 { 6694 /* mtgc0 */, Mips::MTGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 7169 { 6700 /* mthc0 */, Mips::MTHC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 7170 { 6700 /* mthc0 */, Mips::MTHC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 7171 { 6706 /* mthc1 */, Mips::MTHC1_D32, Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, }, 7172 { 6706 /* mthc1 */, Mips::MTHC1_D32_MM, Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, }, 7173 { 6706 /* mthc1 */, Mips::MTHC1_D64, Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, }, 7174 { 6706 /* mthc1 */, Mips::MTHC1_D64_MM, Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, }, 7175 { 6712 /* mthc2 */, Mips::MTHC2_MMR6, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, 7176 { 6718 /* mthgc0 */, Mips::MTHGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 7177 { 6718 /* mthgc0 */, Mips::MTHGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 7178 { 6718 /* mthgc0 */, Mips::MTHGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 7179 { 6718 /* mthgc0 */, Mips::MTHGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 7180 { 6725 /* mthi */, Mips::MTHI, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, }, 7181 { 6725 /* mthi */, Mips::MTHI_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, 7182 { 6725 /* mthi */, Mips::MTHI_DSP_MM, Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_HI32DSPAsmReg }, }, 7183 { 6725 /* mthi */, Mips::MTHI_DSP, Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_HI32DSPAsmReg }, }, 7184 { 6730 /* mthlip */, Mips::MTHLIP_MM, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, 7185 { 6730 /* mthlip */, Mips::MTHLIP, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, 7186 { 6737 /* mtlo */, Mips::MTLO, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, }, 7187 { 6737 /* mtlo */, Mips::MTLO_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, 7188 { 6737 /* mtlo */, Mips::MTLO_DSP_MM, Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_LO32DSPAsmReg }, }, 7189 { 6737 /* mtlo */, Mips::MTLO_DSP, Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_LO32DSPAsmReg }, }, 7190 { 6742 /* mtm0 */, Mips::MTM0, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, }, 7191 { 6747 /* mtm1 */, Mips::MTM1, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, }, 7192 { 6752 /* mtm2 */, Mips::MTM2, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, }, 7193 { 6757 /* mtp0 */, Mips::MTP0, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, }, 7194 { 6762 /* mtp1 */, Mips::MTP1, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, }, 7195 { 6767 /* mtp2 */, Mips::MTP2, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, }, 7196 { 6772 /* mttacx */, Mips::MTTACX, Convert__regAC0__GPR32AsmReg1_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, 7197 { 6772 /* mttacx */, Mips::MTTACX, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, 7198 { 6779 /* mttc0 */, Mips::MTTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 7199 { 6779 /* mttc0 */, Mips::MTTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 7200 { 6785 /* mttc1 */, Mips::MTTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, 7201 { 6791 /* mttdsp */, Mips::MTTDSP, Convert__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg }, }, 7202 { 6798 /* mttgpr */, Mips::MTTGPR, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7203 { 6805 /* mtthc1 */, Mips::MTTHC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, 7204 { 6812 /* mtthi */, Mips::MTTHI, Convert__regAC0__GPR32AsmReg1_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, 7205 { 6812 /* mtthi */, Mips::MTTHI, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, 7206 { 6818 /* mttlo */, Mips::MTTLO, Convert__regAC0__GPR32AsmReg1_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, 7207 { 6818 /* mttlo */, Mips::MTTLO, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, 7208 { 6824 /* mttr */, Mips::MTTR, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm1_0, MCK_ConstantUImm3_0, MCK_ConstantUImm1_0 }, }, 7209 { 6829 /* muh */, Mips::MUH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7210 { 6829 /* muh */, Mips::MUH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7211 { 6829 /* muh */, Mips::MUH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7212 { 6833 /* muhu */, Mips::MUHU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7213 { 6833 /* muhu */, Mips::MUHU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7214 { 6833 /* muhu */, Mips::MUHU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7215 { 6838 /* mul */, Mips::MUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7216 { 6838 /* mul */, Mips::MUL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7217 { 6838 /* mul */, Mips::MUL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7218 { 6838 /* mul */, Mips::MUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7219 { 6838 /* mul */, Mips::MUL_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7220 { 6838 /* mul */, Mips::MUL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7221 { 6838 /* mul */, Mips::MUL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7222 { 6838 /* mul */, Mips::MULImmMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7223 { 6842 /* mul.d */, Mips::FMUL_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7224 { 6842 /* mul.d */, Mips::FMUL_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7225 { 6842 /* mul.d */, Mips::FMUL_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7226 { 6842 /* mul.d */, Mips::FMUL_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7227 { 6848 /* mul.ph */, Mips::MUL_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7228 { 6848 /* mul.ph */, Mips::MUL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7229 { 6855 /* mul.s */, Mips::FMUL_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7230 { 6855 /* mul.s */, Mips::FMUL_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7231 { 6855 /* mul.s */, Mips::FMUL_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7232 { 6861 /* mul_q.h */, Mips::MUL_Q_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7233 { 6869 /* mul_q.w */, Mips::MUL_Q_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7234 { 6877 /* mul_s.ph */, Mips::MUL_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7235 { 6877 /* mul_s.ph */, Mips::MUL_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7236 { 6886 /* muleq_s.w.phl */, Mips::MULEQ_S_W_PHL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7237 { 6886 /* muleq_s.w.phl */, Mips::MULEQ_S_W_PHL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7238 { 6900 /* muleq_s.w.phr */, Mips::MULEQ_S_W_PHR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7239 { 6900 /* muleq_s.w.phr */, Mips::MULEQ_S_W_PHR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7240 { 6914 /* muleu_s.ph.qbl */, Mips::MULEU_S_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7241 { 6914 /* muleu_s.ph.qbl */, Mips::MULEU_S_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7242 { 6929 /* muleu_s.ph.qbr */, Mips::MULEU_S_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7243 { 6929 /* muleu_s.ph.qbr */, Mips::MULEU_S_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7244 { 6944 /* mulo */, Mips::MULOMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7245 { 6944 /* mulo */, Mips::MULOMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7246 { 6949 /* mulou */, Mips::MULOUMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7247 { 6949 /* mulou */, Mips::MULOUMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7248 { 6955 /* mulq_rs.ph */, Mips::MULQ_RS_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7249 { 6955 /* mulq_rs.ph */, Mips::MULQ_RS_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7250 { 6966 /* mulq_rs.w */, Mips::MULQ_RS_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7251 { 6966 /* mulq_rs.w */, Mips::MULQ_RS_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7252 { 6976 /* mulq_s.ph */, Mips::MULQ_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7253 { 6976 /* mulq_s.ph */, Mips::MULQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7254 { 6986 /* mulq_s.w */, Mips::MULQ_S_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7255 { 6986 /* mulq_s.w */, Mips::MULQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7256 { 6995 /* mulr_q.h */, Mips::MULR_Q_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7257 { 7004 /* mulr_q.w */, Mips::MULR_Q_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7258 { 7013 /* mulsa.w.ph */, Mips::MULSA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7259 { 7013 /* mulsa.w.ph */, Mips::MULSA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7260 { 7024 /* mulsaq_s.w.ph */, Mips::MULSAQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7261 { 7024 /* mulsaq_s.w.ph */, Mips::MULSAQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7262 { 7038 /* mult */, Mips::MULT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7263 { 7038 /* mult */, Mips::MULT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7264 { 7038 /* mult */, Mips::MULT_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7265 { 7038 /* mult */, Mips::MULT_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7266 { 7043 /* multu */, Mips::MULTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7267 { 7043 /* multu */, Mips::MULTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7268 { 7043 /* multu */, Mips::MULTU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7269 { 7043 /* multu */, Mips::MULTU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7270 { 7049 /* mulu */, Mips::MULU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7271 { 7049 /* mulu */, Mips::MULU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7272 { 7049 /* mulu */, Mips::MULU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7273 { 7054 /* mulv.b */, Mips::MULV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7274 { 7061 /* mulv.d */, Mips::MULV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7275 { 7068 /* mulv.h */, Mips::MULV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7276 { 7075 /* mulv.w */, Mips::MULV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7277 { 7082 /* neg */, Mips::SUB, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg }, }, 7278 { 7082 /* neg */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, 7279 { 7082 /* neg */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, 7280 { 7082 /* neg */, Mips::NegRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, 7281 { 7082 /* neg */, Mips::SUB, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7282 { 7082 /* neg */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7283 { 7082 /* neg */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7284 { 7086 /* neg.d */, Mips::FNEG_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7285 { 7086 /* neg.d */, Mips::FNEG_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7286 { 7086 /* neg.d */, Mips::FNEG_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7287 { 7086 /* neg.d */, Mips::FNEG_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7288 { 7092 /* neg.s */, Mips::FNEG_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7289 { 7092 /* neg.s */, Mips::FNEG_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7290 { 7092 /* neg.s */, Mips::FNEG_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7291 { 7098 /* negu */, Mips::SUBu, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg }, }, 7292 { 7098 /* negu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, 7293 { 7098 /* negu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, 7294 { 7098 /* negu */, Mips::SUBu, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7295 { 7098 /* negu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7296 { 7098 /* negu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7297 { 7103 /* nloc.b */, Mips::NLOC_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7298 { 7110 /* nloc.d */, Mips::NLOC_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7299 { 7117 /* nloc.h */, Mips::NLOC_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7300 { 7124 /* nloc.w */, Mips::NLOC_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7301 { 7131 /* nlzc.b */, Mips::NLZC_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7302 { 7138 /* nlzc.d */, Mips::NLZC_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7303 { 7145 /* nlzc.h */, Mips::NLZC_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7304 { 7152 /* nlzc.w */, Mips::NLZC_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7305 { 7159 /* nmadd.d */, Mips::NMADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7306 { 7159 /* nmadd.d */, Mips::NMADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7307 { 7159 /* nmadd.d */, Mips::NMADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7308 { 7167 /* nmadd.s */, Mips::NMADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7309 { 7167 /* nmadd.s */, Mips::NMADD_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7310 { 7175 /* nmsub.d */, Mips::NMSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7311 { 7175 /* nmsub.d */, Mips::NMSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7312 { 7175 /* nmsub.d */, Mips::NMSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7313 { 7183 /* nmsub.s */, Mips::NMSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7314 { 7183 /* nmsub.s */, Mips::NMSUB_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7315 { 7191 /* nop */, Mips::SLL, Convert__regZERO__regZERO__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { }, }, 7316 { 7191 /* nop */, Mips::SLL_MMR6, Convert__regZERO__regZERO__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { }, }, 7317 { 7191 /* nop */, Mips::Move32R16, Convert__regZERO__regS0, AMFBS_InMips16Mode, { }, }, 7318 { 7191 /* nop */, Mips::SLL_MM, Convert__regZERO__regZERO__imm_95_0, AMFBS_InMicroMips, { }, }, 7319 { 7191 /* nop */, Mips::MOVE16_MM, Convert__regZERO__regZERO, AMFBS_InMicroMips, { }, }, 7320 { 7195 /* nor */, Mips::NORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_IsGP32bit, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7321 { 7195 /* nor */, Mips::NORImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, }, 7322 { 7195 /* nor */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7323 { 7195 /* nor */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7324 { 7195 /* nor */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7325 { 7195 /* nor */, Mips::NORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_IsGP32bit, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7326 { 7195 /* nor */, Mips::NORImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, 7327 { 7199 /* nor.v */, Mips::NOR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7328 { 7205 /* nori.b */, Mips::NORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, 7329 { 7212 /* not */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg }, }, 7330 { 7212 /* not */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, 7331 { 7212 /* not */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, 7332 { 7212 /* not */, Mips::NotRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, 7333 { 7212 /* not */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7334 { 7212 /* not */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7335 { 7212 /* not */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7336 { 7216 /* not16 */, Mips::NOT16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, 7337 { 7216 /* not16 */, Mips::NOT16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, 7338 { 7222 /* or */, Mips::OrRxRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, 7339 { 7222 /* or */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7340 { 7222 /* or */, Mips::OR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7341 { 7222 /* or */, Mips::OR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7342 { 7222 /* or */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, 7343 { 7222 /* or */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7344 { 7222 /* or */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7345 { 7222 /* or */, Mips::ORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, }, 7346 { 7222 /* or */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7347 { 7222 /* or */, Mips::OR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7348 { 7222 /* or */, Mips::OR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7349 { 7222 /* or */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, 7350 { 7222 /* or */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7351 { 7222 /* or */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7352 { 7222 /* or */, Mips::ORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, 7353 { 7225 /* or.v */, Mips::OR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7354 { 7230 /* or16 */, Mips::OR16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, 7355 { 7230 /* or16 */, Mips::OR16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, 7356 { 7235 /* ori */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, 7357 { 7235 /* ori */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, }, 7358 { 7235 /* ori */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, 7359 { 7235 /* ori */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, 7360 { 7235 /* ori */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, 7361 { 7235 /* ori */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, 7362 { 7239 /* ori.b */, Mips::ORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, 7363 { 7245 /* packrl.ph */, Mips::PACKRL_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7364 { 7245 /* packrl.ph */, Mips::PACKRL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7365 { 7255 /* pause */, Mips::PAUSE, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { }, }, 7366 { 7255 /* pause */, Mips::PAUSE_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, }, 7367 { 7255 /* pause */, Mips::PAUSE_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, }, 7368 { 7261 /* pckev.b */, Mips::PCKEV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7369 { 7269 /* pckev.d */, Mips::PCKEV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7370 { 7277 /* pckev.h */, Mips::PCKEV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7371 { 7285 /* pckev.w */, Mips::PCKEV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7372 { 7293 /* pckod.b */, Mips::PCKOD_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7373 { 7301 /* pckod.d */, Mips::PCKOD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7374 { 7309 /* pckod.h */, Mips::PCKOD_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7375 { 7317 /* pckod.w */, Mips::PCKOD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7376 { 7325 /* pcnt.b */, Mips::PCNT_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7377 { 7332 /* pcnt.d */, Mips::PCNT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7378 { 7339 /* pcnt.h */, Mips::PCNT_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7379 { 7346 /* pcnt.w */, Mips::PCNT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7380 { 7353 /* pick.ph */, Mips::PICK_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7381 { 7353 /* pick.ph */, Mips::PICK_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7382 { 7361 /* pick.qb */, Mips::PICK_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7383 { 7361 /* pick.qb */, Mips::PICK_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7384 { 7369 /* pll.ps */, Mips::PLL_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7385 { 7376 /* plu.ps */, Mips::PLU_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7386 { 7383 /* pop */, Mips::POP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR32AsmReg }, }, 7387 { 7383 /* pop */, Mips::POP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7388 { 7387 /* preceq.w.phl */, Mips::PRECEQ_W_PHL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7389 { 7387 /* preceq.w.phl */, Mips::PRECEQ_W_PHL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7390 { 7400 /* preceq.w.phr */, Mips::PRECEQ_W_PHR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7391 { 7400 /* preceq.w.phr */, Mips::PRECEQ_W_PHR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7392 { 7413 /* precequ.ph.qbl */, Mips::PRECEQU_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7393 { 7413 /* precequ.ph.qbl */, Mips::PRECEQU_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7394 { 7428 /* precequ.ph.qbla */, Mips::PRECEQU_PH_QBLA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7395 { 7428 /* precequ.ph.qbla */, Mips::PRECEQU_PH_QBLA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7396 { 7444 /* precequ.ph.qbr */, Mips::PRECEQU_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7397 { 7444 /* precequ.ph.qbr */, Mips::PRECEQU_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7398 { 7459 /* precequ.ph.qbra */, Mips::PRECEQU_PH_QBRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7399 { 7459 /* precequ.ph.qbra */, Mips::PRECEQU_PH_QBRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7400 { 7475 /* preceu.ph.qbl */, Mips::PRECEU_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7401 { 7475 /* preceu.ph.qbl */, Mips::PRECEU_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7402 { 7489 /* preceu.ph.qbla */, Mips::PRECEU_PH_QBLA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7403 { 7489 /* preceu.ph.qbla */, Mips::PRECEU_PH_QBLA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7404 { 7504 /* preceu.ph.qbr */, Mips::PRECEU_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7405 { 7504 /* preceu.ph.qbr */, Mips::PRECEU_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7406 { 7518 /* preceu.ph.qbra */, Mips::PRECEU_PH_QBRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7407 { 7518 /* preceu.ph.qbra */, Mips::PRECEU_PH_QBRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7408 { 7533 /* precr.qb.ph */, Mips::PRECR_QB_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7409 { 7533 /* precr.qb.ph */, Mips::PRECR_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7410 { 7545 /* precr_sra.ph.w */, Mips::PRECR_SRA_PH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7411 { 7545 /* precr_sra.ph.w */, Mips::PRECR_SRA_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7412 { 7560 /* precr_sra_r.ph.w */, Mips::PRECR_SRA_R_PH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7413 { 7560 /* precr_sra_r.ph.w */, Mips::PRECR_SRA_R_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7414 { 7577 /* precrq.ph.w */, Mips::PRECRQ_PH_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7415 { 7577 /* precrq.ph.w */, Mips::PRECRQ_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7416 { 7589 /* precrq.qb.ph */, Mips::PRECRQ_QB_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7417 { 7589 /* precrq.qb.ph */, Mips::PRECRQ_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7418 { 7602 /* precrq_rs.ph.w */, Mips::PRECRQ_RS_PH_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7419 { 7602 /* precrq_rs.ph.w */, Mips::PRECRQ_RS_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7420 { 7617 /* precrqu_s.qb.ph */, Mips::PRECRQU_S_QB_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7421 { 7617 /* precrqu_s.qb.ph */, Mips::PRECRQU_S_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7422 { 7633 /* pref */, Mips::PREF_R6, Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9_0 }, }, 7423 { 7633 /* pref */, Mips::PREF, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_Mem }, }, 7424 { 7633 /* pref */, Mips::PREF_MM, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, }, 7425 { 7633 /* pref */, Mips::PREF_MMR6, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, }, 7426 { 7638 /* prefe */, Mips::PREFE, Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9_0 }, }, 7427 { 7638 /* prefe */, Mips::PREFE_MM, Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasEVA, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9_0 }, }, 7428 { 7644 /* prefx */, Mips::PREFX_MM, Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm5_0, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 7429 { 7650 /* prepend */, Mips::PREPEND_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7430 { 7650 /* prepend */, Mips::PREPEND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7431 { 7658 /* raddu.w.qb */, Mips::RADDU_W_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7432 { 7658 /* raddu.w.qb */, Mips::RADDU_W_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7433 { 7669 /* rddsp */, Mips::RDDSP_MM, Convert__GPR32AsmReg1_0__ConstantUImm7_01_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm7_0 }, }, 7434 { 7669 /* rddsp */, Mips::RDDSP, Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, 7435 { 7675 /* rdhwr */, Mips::RDHWR, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, }, 7436 { 7675 /* rdhwr */, Mips::RDHWR_MM, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, }, 7437 { 7675 /* rdhwr */, Mips::RDHWR_MMR6, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, }, 7438 { 7675 /* rdhwr */, Mips::RDHWR64, Convert__GPR64AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_HWRegsAsmReg }, }, 7439 { 7675 /* rdhwr */, Mips::RDHWR_MMR6, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm3_0 }, }, 7440 { 7675 /* rdhwr */, Mips::RDHWR, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm8_0 }, }, 7441 { 7675 /* rdhwr */, Mips::RDHWR_MM, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm8_0 }, }, 7442 { 7681 /* rdpgpr */, Mips::RDPGPR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7443 { 7688 /* recip.d */, Mips::RECIP_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7444 { 7688 /* recip.d */, Mips::RECIP_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7445 { 7688 /* recip.d */, Mips::RECIP_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7446 { 7688 /* recip.d */, Mips::RECIP_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7447 { 7696 /* recip.s */, Mips::RECIP_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7448 { 7696 /* recip.s */, Mips::RECIP_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7449 { 7704 /* rem */, Mips::SRemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7450 { 7704 /* rem */, Mips::SRemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7451 { 7704 /* rem */, Mips::SRemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7452 { 7704 /* rem */, Mips::SRemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7453 { 7708 /* remu */, Mips::URemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7454 { 7708 /* remu */, Mips::URemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7455 { 7708 /* remu */, Mips::URemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7456 { 7708 /* remu */, Mips::URemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7457 { 7713 /* repl.ph */, Mips::REPL_PH_MM, Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantSImm10_0 }, }, 7458 { 7713 /* repl.ph */, Mips::REPL_PH, Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantSImm10_0 }, }, 7459 { 7721 /* repl.qb */, Mips::REPL_QB_MM, Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm8_0 }, }, 7460 { 7721 /* repl.qb */, Mips::REPL_QB, Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm8_0 }, }, 7461 { 7729 /* replv.ph */, Mips::REPLV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7462 { 7729 /* replv.ph */, Mips::REPLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7463 { 7738 /* replv.qb */, Mips::REPLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7464 { 7738 /* replv.qb */, Mips::REPLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7465 { 7747 /* rint.d */, Mips::RINT_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7466 { 7747 /* rint.d */, Mips::RINT_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7467 { 7754 /* rint.s */, Mips::RINT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7468 { 7754 /* rint.s */, Mips::RINT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7469 { 7761 /* rol */, Mips::ROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7470 { 7761 /* rol */, Mips::ROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 7471 { 7761 /* rol */, Mips::ROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7472 { 7761 /* rol */, Mips::ROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, 7473 { 7765 /* ror */, Mips::ROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7474 { 7765 /* ror */, Mips::RORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 7475 { 7765 /* ror */, Mips::ROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7476 { 7765 /* ror */, Mips::RORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, 7477 { 7769 /* rotr */, Mips::ROTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7478 { 7769 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7479 { 7769 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7480 { 7769 /* rotr */, Mips::ROTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7481 { 7769 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7482 { 7774 /* rotrv */, Mips::ROTRV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7483 { 7774 /* rotrv */, Mips::ROTRV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7484 { 7780 /* round.l.d */, Mips::ROUND_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7485 { 7780 /* round.l.d */, Mips::ROUND_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7486 { 7790 /* round.l.s */, Mips::ROUND_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 7487 { 7790 /* round.l.s */, Mips::ROUND_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 7488 { 7800 /* round.w.d */, Mips::ROUND_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 7489 { 7800 /* round.w.d */, Mips::ROUND_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 7490 { 7800 /* round.w.d */, Mips::ROUND_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, 7491 { 7800 /* round.w.d */, Mips::ROUND_W_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7492 { 7810 /* round.w.s */, Mips::ROUND_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7493 { 7810 /* round.w.s */, Mips::ROUND_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7494 { 7810 /* round.w.s */, Mips::ROUND_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7495 { 7820 /* rsqrt.d */, Mips::RSQRT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7496 { 7820 /* rsqrt.d */, Mips::RSQRT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7497 { 7820 /* rsqrt.d */, Mips::RSQRT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7498 { 7820 /* rsqrt.d */, Mips::RSQRT_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7499 { 7828 /* rsqrt.s */, Mips::RSQRT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7500 { 7828 /* rsqrt.s */, Mips::RSQRT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7501 { 7836 /* s.d */, Mips::SDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, }, 7502 { 7836 /* s.d */, Mips::SDC1_M1, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, }, 7503 { 7836 /* s.d */, Mips::SDC1_M1, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, }, 7504 { 7836 /* s.d */, Mips::SDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16_0 }, }, 7505 { 7840 /* s.s */, Mips::SWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16_0 }, }, 7506 { 7844 /* saa */, Mips::SaaAddr, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_HasCnMipsP, { MCK_GPR64AsmReg, MCK_Mem }, }, 7507 { 7844 /* saa */, Mips::SAA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_2, AMFBS_HasCnMipsP, { MCK_GPR64AsmReg, MCK__40_, MCK_GPR64AsmReg, MCK__41_ }, }, 7508 { 7848 /* saad */, Mips::SaadAddr, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_HasCnMipsP, { MCK_GPR64AsmReg, MCK_Mem }, }, 7509 { 7848 /* saad */, Mips::SAAD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_2, AMFBS_HasCnMipsP, { MCK_GPR64AsmReg, MCK__40_, MCK_GPR64AsmReg, MCK__41_ }, }, 7510 { 7853 /* sat_s.b */, Mips::SAT_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, 7511 { 7861 /* sat_s.d */, Mips::SAT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, 7512 { 7869 /* sat_s.h */, Mips::SAT_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, 7513 { 7877 /* sat_s.w */, Mips::SAT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 7514 { 7885 /* sat_u.b */, Mips::SAT_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, 7515 { 7893 /* sat_u.d */, Mips::SAT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, 7516 { 7901 /* sat_u.h */, Mips::SAT_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, 7517 { 7909 /* sat_u.w */, Mips::SAT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 7518 { 7917 /* sb */, Mips::SB, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 7519 { 7917 /* sb */, Mips::SB_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, 7520 { 7917 /* sb */, Mips::SB_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 7521 { 7917 /* sb */, Mips::SbRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_SImm16 }, }, 7522 { 7920 /* sb16 */, Mips::SB16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, }, 7523 { 7920 /* sb16 */, Mips::SB16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, }, 7524 { 7925 /* sbe */, Mips::SBE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, 7525 { 7925 /* sbe */, Mips::SBE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, 7526 { 7929 /* sc */, Mips::SC64_R6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, 7527 { 7929 /* sc */, Mips::SC_R6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, 7528 { 7929 /* sc */, Mips::SC_MMR6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, 7529 { 7929 /* sc */, Mips::SC, Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 7530 { 7929 /* sc */, Mips::SC64, Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 7531 { 7929 /* sc */, Mips::SC_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, 7532 { 7932 /* scd */, Mips::SCD_R6, Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, }, 7533 { 7932 /* scd */, Mips::SCD, Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, }, 7534 { 7936 /* sce */, Mips::SCE, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, 7535 { 7936 /* sce */, Mips::SCE_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, 7536 { 7940 /* sd */, Mips::SDMacro, Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotMips3, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16_0 }, }, 7537 { 7940 /* sd */, Mips::SD, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, }, 7538 { 7943 /* sdbbp */, Mips::SDBBP, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, { }, }, 7539 { 7943 /* sdbbp */, Mips::SDBBP_R6, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { }, }, 7540 { 7943 /* sdbbp */, Mips::SDBBP_MMR6, Convert__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { }, }, 7541 { 7943 /* sdbbp */, Mips::SDBBP_MM, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips, { MCK_ConstantUImm10_0 }, }, 7542 { 7943 /* sdbbp */, Mips::SDBBP, Convert__ConstantUImm20_01_0, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_ConstantUImm20_0 }, }, 7543 { 7943 /* sdbbp */, Mips::SDBBP_R6, Convert__ConstantUImm20_01_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_ConstantUImm20_0 }, }, 7544 { 7943 /* sdbbp */, Mips::SDBBP_MMR6, Convert__ConstantUImm20_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm20_0 }, }, 7545 { 7949 /* sdbbp16 */, Mips::SDBBP16_MM, Convert__ConstantUImm4_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm4_0 }, }, 7546 { 7949 /* sdbbp16 */, Mips::SDBBP16_MMR6, Convert__ConstantUImm4_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm4_0 }, }, 7547 { 7957 /* sdc1 */, Mips::SDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, }, 7548 { 7957 /* sdc1 */, Mips::SDC1_MM, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, }, 7549 { 7957 /* sdc1 */, Mips::SDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16_0 }, }, 7550 { 7957 /* sdc1 */, Mips::SDC1_D64_MMR6, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16_0 }, }, 7551 { 7962 /* sdc2 */, Mips::SDC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, }, 7552 { 7962 /* sdc2 */, Mips::SDC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, }, 7553 { 7962 /* sdc2 */, Mips::SDC2, Convert__COP2AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16_0 }, }, 7554 { 7967 /* sdc3 */, Mips::SDC3, Convert__COP3AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, }, 7555 { 7972 /* sdl */, Mips::SDL, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, }, 7556 { 7976 /* sdr */, Mips::SDR, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, }, 7557 { 7980 /* sdxc1 */, Mips::SDXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 7558 { 7980 /* sdxc1 */, Mips::SDXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 7559 { 7986 /* seb */, Mips::SebRx16, Convert__Reg1_0__Tie0_1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs }, }, 7560 { 7986 /* seb */, Mips::SEB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg }, }, 7561 { 7986 /* seb */, Mips::SEB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg }, }, 7562 { 7986 /* seb */, Mips::SEB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7563 { 7986 /* seb */, Mips::SEB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7564 { 7990 /* seh */, Mips::SehRx16, Convert__Reg1_0__Tie0_1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs }, }, 7565 { 7990 /* seh */, Mips::SEH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg }, }, 7566 { 7990 /* seh */, Mips::SEH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg }, }, 7567 { 7990 /* seh */, Mips::SEH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7568 { 7990 /* seh */, Mips::SEH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7569 { 7994 /* sel.d */, Mips::SEL_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7570 { 7994 /* sel.d */, Mips::SEL_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7571 { 8000 /* sel.s */, Mips::SEL_S, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7572 { 8000 /* sel.s */, Mips::SEL_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7573 { 8006 /* seleqz */, Mips::SELEQZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7574 { 8006 /* seleqz */, Mips::SELEQZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7575 { 8006 /* seleqz */, Mips::SELEQZ64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips32r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 7576 { 8013 /* seleqz.d */, Mips::SELEQZ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7577 { 8013 /* seleqz.d */, Mips::SELEQZ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7578 { 8022 /* seleqz.s */, Mips::SELEQZ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7579 { 8022 /* seleqz.s */, Mips::SELEQZ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7580 { 8031 /* selnez */, Mips::SELNEZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7581 { 8031 /* selnez */, Mips::SELNEZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7582 { 8031 /* selnez */, Mips::SELNEZ64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips32r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 7583 { 8038 /* selnez.d */, Mips::SELNEZ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7584 { 8038 /* selnez.d */, Mips::SELNEZ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7585 { 8047 /* selnez.s */, Mips::SELNEZ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7586 { 8047 /* selnez.s */, Mips::SELNEZ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7587 { 8056 /* seq */, Mips::SEQMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7588 { 8056 /* seq */, Mips::SEQIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_SImm32 }, }, 7589 { 8056 /* seq */, Mips::SEQ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 7590 { 8056 /* seq */, Mips::SEQMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7591 { 8056 /* seq */, Mips::SEQIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7592 { 8056 /* seq */, Mips::SEQ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 7593 { 8060 /* seqi */, Mips::SEQi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, }, 7594 { 8060 /* seqi */, Mips::SEQi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, }, 7595 { 8065 /* sge */, Mips::SGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7596 { 8065 /* sge */, Mips::SGEImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32 }, }, 7597 { 8065 /* sge */, Mips::SGEImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, }, 7598 { 8065 /* sge */, Mips::SGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7599 { 8065 /* sge */, Mips::SGEImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, }, 7600 { 8065 /* sge */, Mips::SGEImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, 7601 { 8069 /* sgeu */, Mips::SGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7602 { 8069 /* sgeu */, Mips::SGEUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm32_Coerced1_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm32_Coerced }, }, 7603 { 8069 /* sgeu */, Mips::SGEUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, }, 7604 { 8069 /* sgeu */, Mips::SGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7605 { 8069 /* sgeu */, Mips::SGEUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm32_Coerced1_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm32_Coerced }, }, 7606 { 8069 /* sgeu */, Mips::SGEUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, 7607 { 8074 /* sgt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7608 { 8074 /* sgt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7609 { 8074 /* sgt */, Mips::SGTImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32 }, }, 7610 { 8074 /* sgt */, Mips::SGTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, }, 7611 { 8074 /* sgt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7612 { 8074 /* sgt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7613 { 8074 /* sgt */, Mips::SGTImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, }, 7614 { 8074 /* sgt */, Mips::SGTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, 7615 { 8078 /* sgtu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7616 { 8078 /* sgtu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7617 { 8078 /* sgtu */, Mips::SGTUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm32_Coerced1_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm32_Coerced }, }, 7618 { 8078 /* sgtu */, Mips::SGTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, }, 7619 { 8078 /* sgtu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7620 { 8078 /* sgtu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7621 { 8078 /* sgtu */, Mips::SGTUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm32_Coerced1_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm32_Coerced }, }, 7622 { 8078 /* sgtu */, Mips::SGTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, 7623 { 8083 /* sh */, Mips::SH, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 7624 { 8083 /* sh */, Mips::SH_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, 7625 { 8083 /* sh */, Mips::SH_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 7626 { 8083 /* sh */, Mips::ShRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_SImm16 }, }, 7627 { 8086 /* sh16 */, Mips::SH16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, }, 7628 { 8086 /* sh16 */, Mips::SH16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, }, 7629 { 8091 /* she */, Mips::SHE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, 7630 { 8091 /* she */, Mips::SHE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, 7631 { 8095 /* shf.b */, Mips::SHF_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, 7632 { 8101 /* shf.h */, Mips::SHF_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, 7633 { 8107 /* shf.w */, Mips::SHF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, 7634 { 8113 /* shilo */, Mips::SHILO_MM, Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_ConstantSImm6_0 }, }, 7635 { 8113 /* shilo */, Mips::SHILO, Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_ConstantSImm6_0 }, }, 7636 { 8119 /* shilov */, Mips::SHILOV_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, 7637 { 8119 /* shilov */, Mips::SHILOV, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, 7638 { 8126 /* shll.ph */, Mips::SHLL_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 7639 { 8126 /* shll.ph */, Mips::SHLL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 7640 { 8134 /* shll.qb */, Mips::SHLL_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, 7641 { 8134 /* shll.qb */, Mips::SHLL_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, 7642 { 8142 /* shll_s.ph */, Mips::SHLL_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 7643 { 8142 /* shll_s.ph */, Mips::SHLL_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 7644 { 8152 /* shll_s.w */, Mips::SHLL_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7645 { 8152 /* shll_s.w */, Mips::SHLL_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7646 { 8161 /* shllv.ph */, Mips::SHLLV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7647 { 8161 /* shllv.ph */, Mips::SHLLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7648 { 8170 /* shllv.qb */, Mips::SHLLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7649 { 8170 /* shllv.qb */, Mips::SHLLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7650 { 8179 /* shllv_s.ph */, Mips::SHLLV_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7651 { 8179 /* shllv_s.ph */, Mips::SHLLV_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7652 { 8190 /* shllv_s.w */, Mips::SHLLV_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7653 { 8190 /* shllv_s.w */, Mips::SHLLV_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7654 { 8200 /* shra.ph */, Mips::SHRA_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 7655 { 8200 /* shra.ph */, Mips::SHRA_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 7656 { 8208 /* shra.qb */, Mips::SHRA_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, 7657 { 8208 /* shra.qb */, Mips::SHRA_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, 7658 { 8216 /* shra_r.ph */, Mips::SHRA_R_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 7659 { 8216 /* shra_r.ph */, Mips::SHRA_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 7660 { 8226 /* shra_r.qb */, Mips::SHRA_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, 7661 { 8226 /* shra_r.qb */, Mips::SHRA_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, 7662 { 8236 /* shra_r.w */, Mips::SHRA_R_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7663 { 8236 /* shra_r.w */, Mips::SHRA_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7664 { 8245 /* shrav.ph */, Mips::SHRAV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7665 { 8245 /* shrav.ph */, Mips::SHRAV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7666 { 8254 /* shrav.qb */, Mips::SHRAV_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7667 { 8254 /* shrav.qb */, Mips::SHRAV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7668 { 8263 /* shrav_r.ph */, Mips::SHRAV_R_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7669 { 8263 /* shrav_r.ph */, Mips::SHRAV_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7670 { 8274 /* shrav_r.qb */, Mips::SHRAV_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7671 { 8274 /* shrav_r.qb */, Mips::SHRAV_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7672 { 8285 /* shrav_r.w */, Mips::SHRAV_R_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7673 { 8285 /* shrav_r.w */, Mips::SHRAV_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7674 { 8295 /* shrl.ph */, Mips::SHRL_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 7675 { 8295 /* shrl.ph */, Mips::SHRL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 7676 { 8303 /* shrl.qb */, Mips::SHRL_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, 7677 { 8303 /* shrl.qb */, Mips::SHRL_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, 7678 { 8311 /* shrlv.ph */, Mips::SHRLV_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7679 { 8311 /* shrlv.ph */, Mips::SHRLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7680 { 8320 /* shrlv.qb */, Mips::SHRLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7681 { 8320 /* shrlv.qb */, Mips::SHRLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7682 { 8329 /* sigrie */, Mips::SIGRIE, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { }, }, 7683 { 8329 /* sigrie */, Mips::SIGRIE_MMR6, Convert__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { }, }, 7684 { 8329 /* sigrie */, Mips::SIGRIE, Convert__UImm161_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_UImm16 }, }, 7685 { 8329 /* sigrie */, Mips::SIGRIE_MMR6, Convert__UImm161_0, AMFBS_InMicroMips_HasMips32r6, { MCK_UImm16 }, }, 7686 { 8336 /* sld.b */, Mips::SLD_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, 7687 { 8342 /* sld.d */, Mips::SLD_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, 7688 { 8348 /* sld.h */, Mips::SLD_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, 7689 { 8354 /* sld.w */, Mips::SLD_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, 7690 { 8360 /* sldi.b */, Mips::SLDI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, }, 7691 { 8367 /* sldi.d */, Mips::SLDI_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, }, 7692 { 8374 /* sldi.h */, Mips::SLDI_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, }, 7693 { 8381 /* sldi.w */, Mips::SLDI_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, }, 7694 { 8388 /* sll */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7695 { 8388 /* sll */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7696 { 8388 /* sll */, Mips::SLL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7697 { 8388 /* sll */, Mips::SLL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7698 { 8388 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7699 { 8388 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7700 { 8388 /* sll */, Mips::SllX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, }, 7701 { 8388 /* sll */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7702 { 8388 /* sll */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7703 { 8388 /* sll */, Mips::SLL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7704 { 8388 /* sll */, Mips::SLL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7705 { 8388 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7706 { 8392 /* sll.b */, Mips::SLL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7707 { 8398 /* sll.d */, Mips::SLL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7708 { 8404 /* sll.h */, Mips::SLL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7709 { 8410 /* sll.w */, Mips::SLL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7710 { 8416 /* sll16 */, Mips::SLL16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, }, 7711 { 8416 /* sll16 */, Mips::SLL16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, }, 7712 { 8422 /* slli.b */, Mips::SLLI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, 7713 { 8429 /* slli.d */, Mips::SLLI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, 7714 { 8436 /* slli.h */, Mips::SLLI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, 7715 { 8443 /* slli.w */, Mips::SLLI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 7716 { 8450 /* sllv */, Mips::SllvRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, 7717 { 8450 /* sllv */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7718 { 8450 /* sllv */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7719 { 8455 /* slt */, Mips::SltRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, 7720 { 8455 /* slt */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7721 { 8455 /* slt */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7722 { 8455 /* slt */, Mips::SLTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, }, 7723 { 8455 /* slt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7724 { 8455 /* slt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7725 { 8455 /* slt */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7726 { 8455 /* slt */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7727 { 8455 /* slt */, Mips::SLTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, 7728 { 8459 /* slti */, Mips::SltiRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, }, 7729 { 8459 /* slti */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, 7730 { 8459 /* slti */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, 7731 { 8459 /* slti */, Mips::SltiRxImm16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, }, 7732 { 8464 /* sltiu */, Mips::SltiuRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, }, 7733 { 8464 /* sltiu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, 7734 { 8464 /* sltiu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, 7735 { 8464 /* sltiu */, Mips::SltiuRxImm16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, }, 7736 { 8470 /* sltu */, Mips::SltuRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, 7737 { 8470 /* sltu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7738 { 8470 /* sltu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7739 { 8470 /* sltu */, Mips::SLTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, }, 7740 { 8470 /* sltu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7741 { 8470 /* sltu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7742 { 8470 /* sltu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7743 { 8470 /* sltu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7744 { 8470 /* sltu */, Mips::SLTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, 7745 { 8475 /* sne */, Mips::SNE, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 7746 { 8475 /* sne */, Mips::SNE, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 7747 { 8479 /* snei */, Mips::SNEi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, }, 7748 { 8479 /* snei */, Mips::SNEi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, }, 7749 { 8484 /* splat.b */, Mips::SPLAT_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, 7750 { 8492 /* splat.d */, Mips::SPLAT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, 7751 { 8500 /* splat.h */, Mips::SPLAT_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, 7752 { 8508 /* splat.w */, Mips::SPLAT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, 7753 { 8516 /* splati.b */, Mips::SPLATI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, }, 7754 { 8525 /* splati.d */, Mips::SPLATI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, }, 7755 { 8534 /* splati.h */, Mips::SPLATI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, }, 7756 { 8543 /* splati.w */, Mips::SPLATI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, }, 7757 { 8552 /* sqrt.d */, Mips::FSQRT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7758 { 8552 /* sqrt.d */, Mips::FSQRT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7759 { 8552 /* sqrt.d */, Mips::FSQRT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7760 { 8552 /* sqrt.d */, Mips::FSQRT_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7761 { 8559 /* sqrt.s */, Mips::FSQRT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7762 { 8559 /* sqrt.s */, Mips::FSQRT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7763 { 8566 /* sra */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7764 { 8566 /* sra */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7765 { 8566 /* sra */, Mips::SRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7766 { 8566 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7767 { 8566 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7768 { 8566 /* sra */, Mips::SraX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, }, 7769 { 8566 /* sra */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7770 { 8566 /* sra */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7771 { 8566 /* sra */, Mips::SRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7772 { 8566 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7773 { 8570 /* sra.b */, Mips::SRA_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7774 { 8576 /* sra.d */, Mips::SRA_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7775 { 8582 /* sra.h */, Mips::SRA_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7776 { 8588 /* sra.w */, Mips::SRA_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7777 { 8594 /* srai.b */, Mips::SRAI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, 7778 { 8601 /* srai.d */, Mips::SRAI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, 7779 { 8608 /* srai.h */, Mips::SRAI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, 7780 { 8615 /* srai.w */, Mips::SRAI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 7781 { 8622 /* srar.b */, Mips::SRAR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7782 { 8629 /* srar.d */, Mips::SRAR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7783 { 8636 /* srar.h */, Mips::SRAR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7784 { 8643 /* srar.w */, Mips::SRAR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7785 { 8650 /* srari.b */, Mips::SRARI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, 7786 { 8658 /* srari.d */, Mips::SRARI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, 7787 { 8666 /* srari.h */, Mips::SRARI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, 7788 { 8674 /* srari.w */, Mips::SRARI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 7789 { 8682 /* srav */, Mips::SravRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, 7790 { 8682 /* srav */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7791 { 8682 /* srav */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7792 { 8687 /* srl */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7793 { 8687 /* srl */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7794 { 8687 /* srl */, Mips::SRL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7795 { 8687 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7796 { 8687 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7797 { 8687 /* srl */, Mips::SrlX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, }, 7798 { 8687 /* srl */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7799 { 8687 /* srl */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7800 { 8687 /* srl */, Mips::SRL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7801 { 8687 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7802 { 8691 /* srl.b */, Mips::SRL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7803 { 8697 /* srl.d */, Mips::SRL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7804 { 8703 /* srl.h */, Mips::SRL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7805 { 8709 /* srl.w */, Mips::SRL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7806 { 8715 /* srl16 */, Mips::SRL16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, }, 7807 { 8715 /* srl16 */, Mips::SRL16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, }, 7808 { 8721 /* srli.b */, Mips::SRLI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, 7809 { 8728 /* srli.d */, Mips::SRLI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, 7810 { 8735 /* srli.h */, Mips::SRLI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, 7811 { 8742 /* srli.w */, Mips::SRLI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 7812 { 8749 /* srlr.b */, Mips::SRLR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7813 { 8756 /* srlr.d */, Mips::SRLR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7814 { 8763 /* srlr.h */, Mips::SRLR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7815 { 8770 /* srlr.w */, Mips::SRLR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7816 { 8777 /* srlri.b */, Mips::SRLRI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, 7817 { 8785 /* srlri.d */, Mips::SRLRI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, 7818 { 8793 /* srlri.h */, Mips::SRLRI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, 7819 { 8801 /* srlri.w */, Mips::SRLRI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 7820 { 8809 /* srlv */, Mips::SrlvRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, 7821 { 8809 /* srlv */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7822 { 8809 /* srlv */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7823 { 8814 /* ssnop */, Mips::SSNOP, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, { }, }, 7824 { 8814 /* ssnop */, Mips::SSNOP_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, }, 7825 { 8814 /* ssnop */, Mips::SSNOP_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, }, 7826 { 8820 /* st.b */, Mips::ST_B, Convert__MSA128AsmReg1_0__MemOffsetSimm10_02_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_0 }, }, 7827 { 8825 /* st.d */, Mips::ST_D, Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_3 }, }, 7828 { 8830 /* st.h */, Mips::ST_H, Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_1 }, }, 7829 { 8835 /* st.w */, Mips::ST_W, Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_2 }, }, 7830 { 8840 /* sub */, Mips::SUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7831 { 8840 /* sub */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7832 { 8840 /* sub */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7833 { 8840 /* sub */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_InvNum }, }, 7834 { 8840 /* sub */, Mips::SUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7835 { 8840 /* sub */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7836 { 8840 /* sub */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7837 { 8840 /* sub */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_InvNum }, }, 7838 { 8844 /* sub.d */, Mips::FSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7839 { 8844 /* sub.d */, Mips::FSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7840 { 8844 /* sub.d */, Mips::FSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7841 { 8844 /* sub.d */, Mips::FSUB_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7842 { 8850 /* sub.s */, Mips::FSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7843 { 8850 /* sub.s */, Mips::FSUB_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7844 { 8850 /* sub.s */, Mips::FSUB_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7845 { 8856 /* subq.ph */, Mips::SUBQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7846 { 8856 /* subq.ph */, Mips::SUBQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7847 { 8864 /* subq_s.ph */, Mips::SUBQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7848 { 8864 /* subq_s.ph */, Mips::SUBQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7849 { 8874 /* subq_s.w */, Mips::SUBQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7850 { 8874 /* subq_s.w */, Mips::SUBQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7851 { 8883 /* subqh.ph */, Mips::SUBQH_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7852 { 8883 /* subqh.ph */, Mips::SUBQH_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7853 { 8892 /* subqh.w */, Mips::SUBQH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7854 { 8892 /* subqh.w */, Mips::SUBQH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7855 { 8900 /* subqh_r.ph */, Mips::SUBQH_R_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7856 { 8900 /* subqh_r.ph */, Mips::SUBQH_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7857 { 8911 /* subqh_r.w */, Mips::SUBQH_R_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7858 { 8911 /* subqh_r.w */, Mips::SUBQH_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7859 { 8921 /* subs_s.b */, Mips::SUBS_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7860 { 8930 /* subs_s.d */, Mips::SUBS_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7861 { 8939 /* subs_s.h */, Mips::SUBS_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7862 { 8948 /* subs_s.w */, Mips::SUBS_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7863 { 8957 /* subs_u.b */, Mips::SUBS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7864 { 8966 /* subs_u.d */, Mips::SUBS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7865 { 8975 /* subs_u.h */, Mips::SUBS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7866 { 8984 /* subs_u.w */, Mips::SUBS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7867 { 8993 /* subsus_u.b */, Mips::SUBSUS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7868 { 9004 /* subsus_u.d */, Mips::SUBSUS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7869 { 9015 /* subsus_u.h */, Mips::SUBSUS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7870 { 9026 /* subsus_u.w */, Mips::SUBSUS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7871 { 9037 /* subsuu_s.b */, Mips::SUBSUU_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7872 { 9048 /* subsuu_s.d */, Mips::SUBSUU_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7873 { 9059 /* subsuu_s.h */, Mips::SUBSUU_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7874 { 9070 /* subsuu_s.w */, Mips::SUBSUU_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7875 { 9081 /* subu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7876 { 9081 /* subu */, Mips::SUBu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7877 { 9081 /* subu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7878 { 9081 /* subu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_InvNum }, }, 7879 { 9081 /* subu */, Mips::SubuRxRyRz16, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_CPU16Regs }, }, 7880 { 9081 /* subu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7881 { 9081 /* subu */, Mips::SUBu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7882 { 9081 /* subu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7883 { 9081 /* subu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_InvNum }, }, 7884 { 9086 /* subu.ph */, Mips::SUBU_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7885 { 9086 /* subu.ph */, Mips::SUBU_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7886 { 9094 /* subu.qb */, Mips::SUBU_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7887 { 9094 /* subu.qb */, Mips::SUBU_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7888 { 9102 /* subu16 */, Mips::SUBU16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, 7889 { 9102 /* subu16 */, Mips::SUBU16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, 7890 { 9109 /* subu_s.ph */, Mips::SUBU_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7891 { 9109 /* subu_s.ph */, Mips::SUBU_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7892 { 9119 /* subu_s.qb */, Mips::SUBU_S_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7893 { 9119 /* subu_s.qb */, Mips::SUBU_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7894 { 9129 /* subuh.qb */, Mips::SUBUH_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7895 { 9129 /* subuh.qb */, Mips::SUBUH_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7896 { 9138 /* subuh_r.qb */, Mips::SUBUH_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7897 { 9138 /* subuh_r.qb */, Mips::SUBUH_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7898 { 9149 /* subv.b */, Mips::SUBV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7899 { 9156 /* subv.d */, Mips::SUBV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7900 { 9163 /* subv.h */, Mips::SUBV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7901 { 9170 /* subv.w */, Mips::SUBV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7902 { 9177 /* subvi.b */, Mips::SUBVI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 7903 { 9185 /* subvi.d */, Mips::SUBVI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 7904 { 9193 /* subvi.h */, Mips::SUBVI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 7905 { 9201 /* subvi.w */, Mips::SUBVI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 7906 { 9209 /* suxc1 */, Mips::SUXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 7907 { 9209 /* suxc1 */, Mips::SUXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 7908 { 9209 /* suxc1 */, Mips::SUXC1_MM, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 7909 { 9215 /* sw */, Mips::SWSP_MMR6, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, }, 7910 { 9215 /* sw */, Mips::SWSP_MM, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, }, 7911 { 9215 /* sw */, Mips::SW, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 7912 { 9215 /* sw */, Mips::SWDSP, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_NotInMips16Mode_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, }, 7913 { 9215 /* sw */, Mips::SWDSP_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, }, 7914 { 9215 /* sw */, Mips::SW_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, 7915 { 9215 /* sw */, Mips::SW_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 7916 { 9215 /* sw */, Mips::SwRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_SImm16 }, }, 7917 { 9215 /* sw */, Mips::SwRxSpImmX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, }, 7918 { 9218 /* sw16 */, Mips::SW16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, }, 7919 { 9218 /* sw16 */, Mips::SW16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, }, 7920 { 9223 /* swc1 */, Mips::SWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16_0 }, }, 7921 { 9223 /* swc1 */, Mips::SWC1_MM, Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16_0 }, }, 7922 { 9228 /* swc2 */, Mips::SWC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, }, 7923 { 9228 /* swc2 */, Mips::SWC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, }, 7924 { 9228 /* swc2 */, Mips::SWC2, Convert__COP2AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16_0 }, }, 7925 { 9233 /* swc3 */, Mips::SWC3, Convert__COP3AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, }, 7926 { 9238 /* swe */, Mips::SWE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, 7927 { 9238 /* swe */, Mips::SWE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, 7928 { 9242 /* swl */, Mips::SWL, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 7929 { 9242 /* swl */, Mips::SWL_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, 7930 { 9246 /* swle */, Mips::SWLE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, 7931 { 9246 /* swle */, Mips::SWLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_NotMips32r6_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, 7932 { 9251 /* swm */, Mips::SWM_MM, Convert__RegList1_0__Mem2_1, AMFBS_InMicroMips, { MCK_RegList, MCK_Mem }, }, 7933 { 9255 /* swm16 */, Mips::SWM16_MM, Convert__RegList161_0__MemOffsetUimm42_1, AMFBS_InMicroMips_NotMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, }, 7934 { 9255 /* swm16 */, Mips::SWM16_MMR6, Convert__RegList161_0__MemOffsetUimm42_1, AMFBS_InMicroMips_HasMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, }, 7935 { 9261 /* swm32 */, Mips::SWM32_MM, Convert__RegList1_0__Mem2_1, AMFBS_InMicroMips, { MCK_RegList, MCK_Mem }, }, 7936 { 9267 /* swp */, Mips::SWP_MM, ConvertCustom_ConvertXWPOperands, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm12_0 }, }, 7937 { 9271 /* swr */, Mips::SWR, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 7938 { 9271 /* swr */, Mips::SWR_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, 7939 { 9275 /* swre */, Mips::SWRE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, 7940 { 9275 /* swre */, Mips::SWRE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_NotMips32r6_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, 7941 { 9280 /* swsp */, Mips::SWSP_MM, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, }, 7942 { 9285 /* swxc1 */, Mips::SWXC1, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 7943 { 9285 /* swxc1 */, Mips::SWXC1_MM, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 7944 { 9291 /* sync */, Mips::SYNC, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { }, }, 7945 { 9291 /* sync */, Mips::SYNC_MMR6, Convert__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { }, }, 7946 { 9291 /* sync */, Mips::SYNC_MM, Convert__imm_95_0, AMFBS_InMicroMips, { }, }, 7947 { 9291 /* sync */, Mips::SYNC, Convert__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_ConstantUImm5_0 }, }, 7948 { 9291 /* sync */, Mips::SYNC_MMR6, Convert__ConstantUImm5_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm5_0 }, }, 7949 { 9291 /* sync */, Mips::SYNC_MM, Convert__ConstantUImm5_01_0, AMFBS_InMicroMips, { MCK_ConstantUImm5_0 }, }, 7950 { 9296 /* synci */, Mips::SYNCI, Convert__MemOffsetSimm16_02_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_MemOffsetSimm16_0 }, }, 7951 { 9296 /* synci */, Mips::SYNCI_MM, Convert__MemOffsetSimm16_02_0, AMFBS_InMicroMips_NotMips32r6, { MCK_MemOffsetSimm16_0 }, }, 7952 { 9296 /* synci */, Mips::SYNCI_MMR6, Convert__MemOffsetSimm16_02_0, AMFBS_InMicroMips_HasMips32r6, { MCK_MemOffsetSimm16_0 }, }, 7953 { 9302 /* synciobdma */, Mips::SYNC, Convert__imm_95_2, AMFBS_HasMips64_HasCnMips, { }, }, 7954 { 9313 /* syncs */, Mips::SYNC, Convert__imm_95_6, AMFBS_HasMips64_HasCnMips, { }, }, 7955 { 9319 /* syncw */, Mips::SYNC, Convert__imm_95_4, AMFBS_HasMips64_HasCnMips, { }, }, 7956 { 9325 /* syncws */, Mips::SYNC, Convert__imm_95_5, AMFBS_HasMips64_HasCnMips, { }, }, 7957 { 9332 /* syscall */, Mips::SYSCALL, Convert__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { }, }, 7958 { 9332 /* syscall */, Mips::SYSCALL_MM, Convert__imm_95_0, AMFBS_InMicroMips, { }, }, 7959 { 9332 /* syscall */, Mips::SYSCALL_MM, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips, { MCK_ConstantUImm10_0 }, }, 7960 { 9332 /* syscall */, Mips::SYSCALL, Convert__ConstantUImm20_01_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_ConstantUImm20_0 }, }, 7961 { 9340 /* teq */, Mips::TEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7962 { 9340 /* teq */, Mips::TEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7963 { 9340 /* teq */, Mips::TEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 7964 { 9340 /* teq */, Mips::TEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, 7965 { 9344 /* teqi */, Mips::TEQI, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 7966 { 9344 /* teqi */, Mips::TEQI_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 7967 { 9349 /* tge */, Mips::TGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7968 { 9349 /* tge */, Mips::TGE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7969 { 9349 /* tge */, Mips::TGE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 7970 { 9349 /* tge */, Mips::TGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, 7971 { 9353 /* tgei */, Mips::TGEI, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 7972 { 9353 /* tgei */, Mips::TGEI_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 7973 { 9358 /* tgeiu */, Mips::TGEIU, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 7974 { 9358 /* tgeiu */, Mips::TGEIU_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 7975 { 9364 /* tgeu */, Mips::TGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7976 { 9364 /* tgeu */, Mips::TGEU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7977 { 9364 /* tgeu */, Mips::TGEU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 7978 { 9364 /* tgeu */, Mips::TGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, 7979 { 9369 /* tlbginv */, Mips::TLBGINV, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, }, 7980 { 9369 /* tlbginv */, Mips::TLBGINV_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, }, 7981 { 9377 /* tlbginvf */, Mips::TLBGINVF, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, }, 7982 { 9377 /* tlbginvf */, Mips::TLBGINVF_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, }, 7983 { 9386 /* tlbgp */, Mips::TLBGP, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, }, 7984 { 9386 /* tlbgp */, Mips::TLBGP_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, }, 7985 { 9392 /* tlbgr */, Mips::TLBGR, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, }, 7986 { 9392 /* tlbgr */, Mips::TLBGR_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, }, 7987 { 9398 /* tlbgwi */, Mips::TLBGWI, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, }, 7988 { 9398 /* tlbgwi */, Mips::TLBGWI_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, }, 7989 { 9405 /* tlbgwr */, Mips::TLBGWR, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, }, 7990 { 9405 /* tlbgwr */, Mips::TLBGWR_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, }, 7991 { 9412 /* tlbinv */, Mips::TLBINV, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { }, }, 7992 { 9412 /* tlbinv */, Mips::TLBINV_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, }, 7993 { 9419 /* tlbinvf */, Mips::TLBINVF, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { }, }, 7994 { 9419 /* tlbinvf */, Mips::TLBINVF_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, }, 7995 { 9427 /* tlbp */, Mips::TLBP, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, { }, }, 7996 { 9427 /* tlbp */, Mips::TLBP_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, }, 7997 { 9432 /* tlbr */, Mips::TLBR, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, { }, }, 7998 { 9432 /* tlbr */, Mips::TLBR_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, }, 7999 { 9437 /* tlbwi */, Mips::TLBWI, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, { }, }, 8000 { 9437 /* tlbwi */, Mips::TLBWI_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, }, 8001 { 9443 /* tlbwr */, Mips::TLBWR, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, { }, }, 8002 { 9443 /* tlbwr */, Mips::TLBWR_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, }, 8003 { 9449 /* tlt */, Mips::TLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 8004 { 9449 /* tlt */, Mips::TLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 8005 { 9449 /* tlt */, Mips::TLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 8006 { 9449 /* tlt */, Mips::TLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, 8007 { 9453 /* tlti */, Mips::TLTI, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 8008 { 9453 /* tlti */, Mips::TLTI_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 8009 { 9458 /* tltiu */, Mips::TTLTIU, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 8010 { 9458 /* tltiu */, Mips::TLTIU_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 8011 { 9464 /* tltu */, Mips::TLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 8012 { 9464 /* tltu */, Mips::TLTU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 8013 { 9464 /* tltu */, Mips::TLTU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 8014 { 9464 /* tltu */, Mips::TLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, 8015 { 9469 /* tne */, Mips::TNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 8016 { 9469 /* tne */, Mips::TNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 8017 { 9469 /* tne */, Mips::TNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 8018 { 9469 /* tne */, Mips::TNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, 8019 { 9473 /* tnei */, Mips::TNEI, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 8020 { 9473 /* tnei */, Mips::TNEI_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 8021 { 9478 /* trunc.l.d */, Mips::TRUNC_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 8022 { 9478 /* trunc.l.d */, Mips::TRUNC_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 8023 { 9488 /* trunc.l.s */, Mips::TRUNC_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 8024 { 9488 /* trunc.l.s */, Mips::TRUNC_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 8025 { 9498 /* trunc.w.d */, Mips::TRUNC_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 8026 { 9498 /* trunc.w.d */, Mips::TRUNC_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 8027 { 9498 /* trunc.w.d */, Mips::TRUNC_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, 8028 { 9498 /* trunc.w.d */, Mips::TRUNC_W_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, 8029 { 9498 /* trunc.w.d */, Mips::PseudoTRUNC_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, }, 8030 { 9498 /* trunc.w.d */, Mips::PseudoTRUNC_W_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_IsFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, }, 8031 { 9508 /* trunc.w.s */, Mips::TRUNC_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 8032 { 9508 /* trunc.w.s */, Mips::TRUNC_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 8033 { 9508 /* trunc.w.s */, Mips::TRUNC_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 8034 { 9508 /* trunc.w.s */, Mips::PseudoTRUNC_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_None, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, }, 8035 { 9518 /* ulh */, Mips::Ulh, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, }, 8036 { 9522 /* ulhu */, Mips::Ulhu, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, }, 8037 { 9527 /* ulw */, Mips::Ulw, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, }, 8038 { 9531 /* ush */, Mips::Ush, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, }, 8039 { 9535 /* usw */, Mips::Usw, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, }, 8040 { 9539 /* v3mulu */, Mips::V3MULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 8041 { 9539 /* v3mulu */, Mips::V3MULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 8042 { 9546 /* vmm0 */, Mips::VMM0, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 8043 { 9546 /* vmm0 */, Mips::VMM0, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 8044 { 9551 /* vmulu */, Mips::VMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 8045 { 9551 /* vmulu */, Mips::VMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 8046 { 9557 /* vshf.b */, Mips::VSHF_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 8047 { 9564 /* vshf.d */, Mips::VSHF_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 8048 { 9571 /* vshf.h */, Mips::VSHF_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 8049 { 9578 /* vshf.w */, Mips::VSHF_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 8050 { 9585 /* wait */, Mips::WAIT, Convert_NoOperands, AMFBS_HasStdEnc_HasMips3_32_NotInMicroMips, { }, }, 8051 { 9585 /* wait */, Mips::WAIT_MM, Convert__imm_95_0, AMFBS_InMicroMips, { }, }, 8052 { 9585 /* wait */, Mips::WAIT_MMR6, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm10_0 }, }, 8053 { 9585 /* wait */, Mips::WAIT_MM, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips, { MCK_ConstantUImm10_0 }, }, 8054 { 9590 /* wrdsp */, Mips::WRDSP, Convert__GPR32AsmReg1_0__imm_95_31, AMFBS_HasDSP_NotInMicroMips, { MCK_GPR32AsmReg }, }, 8055 { 9590 /* wrdsp */, Mips::WRDSP_MM, Convert__GPR32AsmReg1_0__imm_95_31, AMFBS_HasDSP_InMicroMips, { MCK_GPR32AsmReg }, }, 8056 { 9590 /* wrdsp */, Mips::WRDSP_MM, Convert__GPR32AsmReg1_0__ConstantUImm7_01_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm7_0 }, }, 8057 { 9590 /* wrdsp */, Mips::WRDSP, Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, AMFBS_HasDSP_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, 8058 { 9596 /* wrpgpr */, Mips::WRPGPR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 8059 { 9603 /* wsbh */, Mips::WSBH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 8060 { 9603 /* wsbh */, Mips::WSBH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 8061 { 9603 /* wsbh */, Mips::WSBH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 8062 { 9608 /* xor */, Mips::XorRxRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, 8063 { 9608 /* xor */, Mips::XOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 8064 { 9608 /* xor */, Mips::XOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 8065 { 9608 /* xor */, Mips::XOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 8066 { 9608 /* xor */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, 8067 { 9608 /* xor */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 8068 { 9608 /* xor */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 8069 { 9608 /* xor */, Mips::XORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, }, 8070 { 9608 /* xor */, Mips::XOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 8071 { 9608 /* xor */, Mips::XOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 8072 { 9608 /* xor */, Mips::XOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 8073 { 9608 /* xor */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, 8074 { 9608 /* xor */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 8075 { 9608 /* xor */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 8076 { 9608 /* xor */, Mips::XORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, 8077 { 9612 /* xor.v */, Mips::XOR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 8078 { 9618 /* xor16 */, Mips::XOR16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, 8079 { 9618 /* xor16 */, Mips::XOR16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, 8080 { 9624 /* xori */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, 8081 { 9624 /* xori */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, }, 8082 { 9624 /* xori */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, 8083 { 9624 /* xori */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, 8084 { 9624 /* xori */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, 8085 { 9624 /* xori */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, 8086 { 9629 /* xori.b */, Mips::XORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, 8087 { 9636 /* yield */, Mips::YIELD, Convert__regZERO__GPR32AsmReg1_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, 8088 { 9636 /* yield */, Mips::YIELD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 8089}; 8090 8091#include "llvm/Support/Debug.h" 8092#include "llvm/Support/Format.h" 8093 8094unsigned MipsAsmParser:: 8095MatchInstructionImpl(const OperandVector &Operands, 8096 MCInst &Inst, 8097 uint64_t &ErrorInfo, 8098 FeatureBitset &MissingFeatures, 8099 bool matchingInlineAsm, unsigned VariantID) { 8100 // Eliminate obvious mismatches. 8101 if (Operands.size() > 9) { 8102 ErrorInfo = 9; 8103 return Match_InvalidOperand; 8104 } 8105 8106 // Get the current feature set. 8107 const FeatureBitset &AvailableFeatures = getAvailableFeatures(); 8108 8109 // Get the instruction mnemonic, which is the first token. 8110 StringRef Mnemonic = ((MipsOperand&)*Operands[0]).getToken(); 8111 8112 // Some state to try to produce better error messages. 8113 bool HadMatchOtherThanFeatures = false; 8114 bool HadMatchOtherThanPredicate = false; 8115 unsigned RetCode = Match_InvalidOperand; 8116 MissingFeatures.set(); 8117 // Set ErrorInfo to the operand that mismatches if it is 8118 // wrong for all instances of the instruction. 8119 ErrorInfo = ~0ULL; 8120 // Find the appropriate table for this asm variant. 8121 const MatchEntry *Start, *End; 8122 switch (VariantID) { 8123 default: llvm_unreachable("invalid variant!"); 8124 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break; 8125 } 8126 // Search the table. 8127 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode()); 8128 8129 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " << 8130 std::distance(MnemonicRange.first, MnemonicRange.second) << 8131 " encodings with mnemonic '" << Mnemonic << "'\n"); 8132 8133 // Return a more specific error code if no mnemonics match. 8134 if (MnemonicRange.first == MnemonicRange.second) 8135 return Match_MnemonicFail; 8136 8137 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second; 8138 it != ie; ++it) { 8139 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx]; 8140 bool HasRequiredFeatures = 8141 (AvailableFeatures & RequiredFeatures) == RequiredFeatures; 8142 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode " 8143 << MII.getName(it->Opcode) << "\n"); 8144 // equal_range guarantees that instruction mnemonic matches. 8145 assert(Mnemonic == it->getMnemonic()); 8146 bool OperandsValid = true; 8147 for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 8; ++FormalIdx) { 8148 auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]); 8149 DEBUG_WITH_TYPE("asm-matcher", 8150 dbgs() << " Matching formal operand class " << getMatchClassName(Formal) 8151 << " against actual operand at index " << ActualIdx); 8152 if (ActualIdx < Operands.size()) 8153 DEBUG_WITH_TYPE("asm-matcher", dbgs() << " ("; 8154 Operands[ActualIdx]->print(dbgs()); dbgs() << "): "); 8155 else 8156 DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": "); 8157 if (ActualIdx >= Operands.size()) { 8158 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range "); 8159 OperandsValid = (Formal == InvalidMatchClass) || isSubclass(Formal, OptionalMatchClass); 8160 if (!OperandsValid) ErrorInfo = ActualIdx; 8161 break; 8162 } 8163 MCParsedAsmOperand &Actual = *Operands[ActualIdx]; 8164 unsigned Diag = validateOperandClass(Actual, Formal); 8165 if (Diag == Match_Success) { 8166 DEBUG_WITH_TYPE("asm-matcher", 8167 dbgs() << "match success using generic matcher\n"); 8168 ++ActualIdx; 8169 continue; 8170 } 8171 // If the generic handler indicates an invalid operand 8172 // failure, check for a special case. 8173 if (Diag != Match_Success) { 8174 unsigned TargetDiag = validateTargetOperandClass(Actual, Formal); 8175 if (TargetDiag == Match_Success) { 8176 DEBUG_WITH_TYPE("asm-matcher", 8177 dbgs() << "match success using target matcher\n"); 8178 ++ActualIdx; 8179 continue; 8180 } 8181 // If the target matcher returned a specific error code use 8182 // that, else use the one from the generic matcher. 8183 if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures) 8184 Diag = TargetDiag; 8185 } 8186 // If current formal operand wasn't matched and it is optional 8187 // then try to match next formal operand 8188 if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) { 8189 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n"); 8190 continue; 8191 } 8192 // If this operand is broken for all of the instances of this 8193 // mnemonic, keep track of it so we can report loc info. 8194 // If we already had a match that only failed due to a 8195 // target predicate, that diagnostic is preferred. 8196 if (!HadMatchOtherThanPredicate && 8197 (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) { 8198 if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag != Match_InvalidOperand)) 8199 RetCode = Diag; 8200 ErrorInfo = ActualIdx; 8201 } 8202 // Otherwise, just reject this instance of the mnemonic. 8203 OperandsValid = false; 8204 break; 8205 } 8206 8207 if (!OperandsValid) { 8208 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple " 8209 "operand mismatches, ignoring " 8210 "this opcode\n"); 8211 continue; 8212 } 8213 if (!HasRequiredFeatures) { 8214 HadMatchOtherThanFeatures = true; 8215 FeatureBitset NewMissingFeatures = RequiredFeatures & ~AvailableFeatures; 8216 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features:"; 8217 for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I) 8218 if (NewMissingFeatures[I]) 8219 dbgs() << ' ' << I; 8220 dbgs() << "\n"); 8221 if (NewMissingFeatures.count() <= 8222 MissingFeatures.count()) 8223 MissingFeatures = NewMissingFeatures; 8224 continue; 8225 } 8226 8227 Inst.clear(); 8228 8229 Inst.setOpcode(it->Opcode); 8230 // We have a potential match but have not rendered the operands. 8231 // Check the target predicate to handle any context sensitive 8232 // constraints. 8233 // For example, Ties that are referenced multiple times must be 8234 // checked here to ensure the input is the same for each match 8235 // constraints. If we leave it any later the ties will have been 8236 // canonicalized 8237 unsigned MatchResult; 8238 if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) { 8239 Inst.clear(); 8240 DEBUG_WITH_TYPE( 8241 "asm-matcher", 8242 dbgs() << "Early target match predicate failed with diag code " 8243 << MatchResult << "\n"); 8244 RetCode = MatchResult; 8245 HadMatchOtherThanPredicate = true; 8246 continue; 8247 } 8248 8249 if (matchingInlineAsm) { 8250 convertToMapAndConstraints(it->ConvertFn, Operands); 8251 if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, ErrorInfo)) 8252 return Match_InvalidTiedOperand; 8253 8254 return Match_Success; 8255 } 8256 8257 // We have selected a definite instruction, convert the parsed 8258 // operands into the appropriate MCInst. 8259 convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands); 8260 8261 // We have a potential match. Check the target predicate to 8262 // handle any context sensitive constraints. 8263 if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) { 8264 DEBUG_WITH_TYPE("asm-matcher", 8265 dbgs() << "Target match predicate failed with diag code " 8266 << MatchResult << "\n"); 8267 Inst.clear(); 8268 RetCode = MatchResult; 8269 HadMatchOtherThanPredicate = true; 8270 continue; 8271 } 8272 8273 if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, ErrorInfo)) 8274 return Match_InvalidTiedOperand; 8275 8276 DEBUG_WITH_TYPE( 8277 "asm-matcher", 8278 dbgs() << "Opcode result: complete match, selecting this opcode\n"); 8279 return Match_Success; 8280 } 8281 8282 // Okay, we had no match. Try to return a useful error code. 8283 if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures) 8284 return RetCode; 8285 8286 ErrorInfo = 0; 8287 return Match_MissingFeature; 8288} 8289 8290namespace { 8291 struct OperandMatchEntry { 8292 uint16_t Mnemonic; 8293 uint8_t OperandMask; 8294 uint8_t Class; 8295 uint8_t RequiredFeaturesIdx; 8296 8297 StringRef getMnemonic() const { 8298 return StringRef(MnemonicTable + Mnemonic + 1, 8299 MnemonicTable[Mnemonic]); 8300 } 8301 }; 8302 8303 // Predicate for searching for an opcode. 8304 struct LessOpcodeOperand { 8305 bool operator()(const OperandMatchEntry &LHS, StringRef RHS) { 8306 return LHS.getMnemonic() < RHS; 8307 } 8308 bool operator()(StringRef LHS, const OperandMatchEntry &RHS) { 8309 return LHS < RHS.getMnemonic(); 8310 } 8311 bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) { 8312 return LHS.getMnemonic() < RHS.getMnemonic(); 8313 } 8314 }; 8315} // end anonymous namespace 8316 8317static const OperandMatchEntry OperandMatchTable[3284] = { 8318 /* Operand List Mnemonic, Mask, Operand Class, Features */ 8319 { 0 /* abs */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, 8320 { 4 /* abs.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, 8321 { 4 /* abs.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 8322 { 4 /* abs.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, 8323 { 4 /* abs.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, 8324 { 10 /* abs.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, 8325 { 10 /* abs.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, 8326 { 16 /* absq_s.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 8327 { 16 /* absq_s.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 8328 { 26 /* absq_s.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 8329 { 26 /* absq_s.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 8330 { 36 /* absq_s.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 8331 { 36 /* absq_s.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 8332 { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 8333 { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 8334 { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8335 { 45 /* add */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 8336 { 45 /* add */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 8337 { 45 /* add */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 8338 { 45 /* add */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 8339 { 45 /* add */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8340 { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 8341 { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 8342 { 49 /* add.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, 8343 { 49 /* add.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 8344 { 49 /* add.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, 8345 { 49 /* add.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, 8346 { 55 /* add.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, 8347 { 55 /* add.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 8348 { 55 /* add.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, 8349 { 61 /* add_a.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8350 { 69 /* add_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8351 { 77 /* add_a.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8352 { 85 /* add_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8353 { 93 /* addi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 8354 { 93 /* addi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 8355 { 93 /* addi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 8356 { 93 /* addi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 8357 { 98 /* addiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8358 { 98 /* addiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 8359 { 98 /* addiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 8360 { 98 /* addiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8361 { 98 /* addiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 8362 { 98 /* addiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 8363 { 104 /* addiupc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, 8364 { 104 /* addiupc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8365 { 104 /* addiupc */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 8366 { 112 /* addiur1sp */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips }, 8367 { 122 /* addiur2 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips }, 8368 { 130 /* addius5 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 8369 { 146 /* addq.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 8370 { 146 /* addq.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 8371 { 154 /* addq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 8372 { 154 /* addq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 8373 { 164 /* addq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 8374 { 164 /* addq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 8375 { 173 /* addqh.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 8376 { 173 /* addqh.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 8377 { 182 /* addqh.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 8378 { 182 /* addqh.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 8379 { 190 /* addqh_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 8380 { 190 /* addqh_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 8381 { 201 /* addqh_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 8382 { 201 /* addqh_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 8383 { 211 /* adds_a.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8384 { 220 /* adds_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8385 { 229 /* adds_a.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8386 { 238 /* adds_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8387 { 247 /* adds_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8388 { 256 /* adds_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8389 { 265 /* adds_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8390 { 274 /* adds_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8391 { 283 /* adds_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8392 { 292 /* adds_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8393 { 301 /* adds_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8394 { 310 /* adds_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8395 { 319 /* addsc */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 8396 { 319 /* addsc */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 8397 { 325 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8398 { 325 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 8399 { 325 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 8400 { 325 /* addu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 8401 { 325 /* addu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 8402 { 325 /* addu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8403 { 325 /* addu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 8404 { 325 /* addu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 8405 { 325 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 8406 { 325 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 8407 { 330 /* addu.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 8408 { 330 /* addu.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 8409 { 338 /* addu.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 8410 { 338 /* addu.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 8411 { 346 /* addu16 */, 7 /* 0, 1, 2 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 8412 { 346 /* addu16 */, 7 /* 0, 1, 2 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8413 { 353 /* addu_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 8414 { 353 /* addu_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 8415 { 363 /* addu_s.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 8416 { 363 /* addu_s.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 8417 { 373 /* adduh.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 8418 { 373 /* adduh.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 8419 { 382 /* adduh_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 8420 { 382 /* adduh_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 8421 { 393 /* addv.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8422 { 400 /* addv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8423 { 407 /* addv.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8424 { 414 /* addv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8425 { 421 /* addvi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8426 { 429 /* addvi.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8427 { 437 /* addvi.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8428 { 445 /* addvi.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8429 { 453 /* addwc */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 8430 { 453 /* addwc */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 8431 { 459 /* align */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, 8432 { 459 /* align */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8433 { 465 /* aluipc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, 8434 { 465 /* aluipc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8435 { 472 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 8436 { 472 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 8437 { 472 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8438 { 472 /* and */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8439 { 472 /* and */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, 8440 { 472 /* and */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 8441 { 472 /* and */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips }, 8442 { 472 /* and */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 8443 { 472 /* and */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 8444 { 472 /* and */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8445 { 472 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8446 { 472 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, 8447 { 472 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 8448 { 472 /* and */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips }, 8449 { 476 /* and.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8450 { 482 /* and16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 8451 { 482 /* and16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8452 { 488 /* andi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8453 { 488 /* andi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 8454 { 488 /* andi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 8455 { 488 /* andi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8456 { 488 /* andi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 8457 { 488 /* andi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 8458 { 493 /* andi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8459 { 500 /* andi16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 8460 { 500 /* andi16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8461 { 507 /* append */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 8462 { 507 /* append */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 8463 { 514 /* asub_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8464 { 523 /* asub_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8465 { 532 /* asub_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8466 { 541 /* asub_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8467 { 550 /* asub_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8468 { 559 /* asub_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8469 { 568 /* asub_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8470 { 577 /* asub_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8471 { 586 /* aui */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, 8472 { 586 /* aui */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8473 { 590 /* auipc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, 8474 { 590 /* auipc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8475 { 596 /* ave_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8476 { 604 /* ave_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8477 { 612 /* ave_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8478 { 620 /* ave_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8479 { 628 /* ave_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8480 { 636 /* ave_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8481 { 644 /* ave_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8482 { 652 /* ave_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8483 { 660 /* aver_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8484 { 669 /* aver_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8485 { 678 /* aver_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8486 { 687 /* aver_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8487 { 696 /* aver_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8488 { 705 /* aver_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8489 { 714 /* aver_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8490 { 723 /* aver_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8491 { 732 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, 8492 { 732 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips }, 8493 { 732 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMips16Mode }, 8494 { 732 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_None }, 8495 { 732 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMips16Mode }, 8496 { 734 /* b16 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 8497 { 734 /* b16 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips }, 8498 { 738 /* baddu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 8499 { 738 /* baddu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 8500 { 744 /* bal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 8501 { 744 /* bal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6 }, 8502 { 744 /* bal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, 8503 { 748 /* balc */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6 }, 8504 { 748 /* balc */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 8505 { 753 /* balign */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 8506 { 753 /* balign */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 8507 { 760 /* bbit0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 8508 { 760 /* bbit0 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips }, 8509 { 760 /* bbit0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 8510 { 760 /* bbit0 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips }, 8511 { 766 /* bbit032 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 8512 { 766 /* bbit032 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips }, 8513 { 774 /* bbit1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 8514 { 774 /* bbit1 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips }, 8515 { 774 /* bbit1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 8516 { 774 /* bbit1 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips }, 8517 { 780 /* bbit132 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 8518 { 780 /* bbit132 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips }, 8519 { 788 /* bc */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8520 { 788 /* bc */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 8521 { 791 /* bc16 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 8522 { 796 /* bc1eqz */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 8523 { 796 /* bc1eqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 8524 { 803 /* bc1eqzc */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 8525 { 803 /* bc1eqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 8526 { 811 /* bc1f */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8527 { 811 /* bc1f */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 8528 { 811 /* bc1f */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8529 { 811 /* bc1f */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8530 { 811 /* bc1f */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 8531 { 811 /* bc1f */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 8532 { 816 /* bc1fl */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8533 { 816 /* bc1fl */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8534 { 816 /* bc1fl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8535 { 822 /* bc1nez */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 8536 { 822 /* bc1nez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 8537 { 829 /* bc1nezc */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 8538 { 829 /* bc1nezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 8539 { 837 /* bc1t */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8540 { 837 /* bc1t */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 8541 { 837 /* bc1t */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8542 { 837 /* bc1t */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8543 { 837 /* bc1t */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 8544 { 837 /* bc1t */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 8545 { 842 /* bc1tl */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8546 { 842 /* bc1tl */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8547 { 842 /* bc1tl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8548 { 848 /* bc2eqz */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8549 { 848 /* bc2eqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8550 { 855 /* bc2eqzc */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8551 { 855 /* bc2eqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 8552 { 863 /* bc2nez */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8553 { 863 /* bc2nez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8554 { 870 /* bc2nezc */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8555 { 870 /* bc2nezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 8556 { 878 /* bclr.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8557 { 885 /* bclr.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8558 { 892 /* bclr.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8559 { 899 /* bclr.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8560 { 906 /* bclri.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8561 { 914 /* bclri.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8562 { 922 /* bclri.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8563 { 930 /* bclri.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8564 { 938 /* beq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 8565 { 938 /* beq */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, 8566 { 938 /* beq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 8567 { 938 /* beq */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, 8568 { 938 /* beq */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, 8569 { 938 /* beq */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, 8570 { 942 /* beqc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8571 { 942 /* beqc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8572 { 942 /* beqc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8573 { 942 /* beqc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 8574 { 942 /* beqc */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, 8575 { 942 /* beqc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, 8576 { 947 /* beql */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 8577 { 947 /* beql */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 8578 { 947 /* beql */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8579 { 947 /* beql */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8580 { 952 /* beqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMips16Mode }, 8581 { 952 /* beqz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 8582 { 952 /* beqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, 8583 { 952 /* beqz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 8584 { 952 /* beqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips }, 8585 { 952 /* beqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMips16Mode }, 8586 { 957 /* beqz16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 8587 { 957 /* beqz16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, 8588 { 957 /* beqz16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8589 { 957 /* beqz16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 8590 { 964 /* beqzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8591 { 964 /* beqzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8592 { 964 /* beqzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8593 { 964 /* beqzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 8594 { 972 /* beqzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8595 { 972 /* beqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8596 { 972 /* beqzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 8597 { 972 /* beqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, 8598 { 972 /* beqzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8599 { 972 /* beqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 8600 { 972 /* beqzc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, 8601 { 972 /* beqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, 8602 { 978 /* beqzc16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8603 { 978 /* beqzc16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 8604 { 986 /* beqzl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, 8605 { 986 /* beqzl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, 8606 { 992 /* bge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, 8607 { 992 /* bge */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, 8608 { 992 /* bge */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, 8609 { 992 /* bge */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, 8610 { 996 /* bgec */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8611 { 996 /* bgec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8612 { 996 /* bgec */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8613 { 996 /* bgec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 8614 { 996 /* bgec */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, 8615 { 996 /* bgec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, 8616 { 1001 /* bgel */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8617 { 1001 /* bgel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8618 { 1001 /* bgel */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8619 { 1001 /* bgel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8620 { 1006 /* bgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, 8621 { 1006 /* bgeu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, 8622 { 1006 /* bgeu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, 8623 { 1006 /* bgeu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, 8624 { 1011 /* bgeuc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8625 { 1011 /* bgeuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8626 { 1011 /* bgeuc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8627 { 1011 /* bgeuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 8628 { 1011 /* bgeuc */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, 8629 { 1011 /* bgeuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, 8630 { 1017 /* bgeul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8631 { 1017 /* bgeul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8632 { 1017 /* bgeul */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8633 { 1017 /* bgeul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8634 { 1023 /* bgez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 8635 { 1023 /* bgez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, 8636 { 1023 /* bgez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 8637 { 1023 /* bgez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, 8638 { 1028 /* bgezal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 8639 { 1028 /* bgezal */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 8640 { 1028 /* bgezal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 8641 { 1028 /* bgezal */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, 8642 { 1035 /* bgezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8643 { 1035 /* bgezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8644 { 1035 /* bgezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8645 { 1035 /* bgezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 8646 { 1043 /* bgezall */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 8647 { 1043 /* bgezall */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 8648 { 1051 /* bgezals */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 8649 { 1051 /* bgezals */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, 8650 { 1059 /* bgezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8651 { 1059 /* bgezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8652 { 1059 /* bgezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8653 { 1059 /* bgezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 8654 { 1059 /* bgezc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, 8655 { 1059 /* bgezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, 8656 { 1065 /* bgezl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 8657 { 1065 /* bgezl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 8658 { 1071 /* bgt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, 8659 { 1071 /* bgt */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, 8660 { 1071 /* bgt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, 8661 { 1071 /* bgt */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, 8662 { 1075 /* bgtl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8663 { 1075 /* bgtl */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8664 { 1075 /* bgtl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8665 { 1075 /* bgtl */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8666 { 1080 /* bgtu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, 8667 { 1080 /* bgtu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, 8668 { 1080 /* bgtu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, 8669 { 1080 /* bgtu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, 8670 { 1085 /* bgtul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8671 { 1085 /* bgtul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8672 { 1085 /* bgtul */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8673 { 1085 /* bgtul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8674 { 1091 /* bgtz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 8675 { 1091 /* bgtz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, 8676 { 1091 /* bgtz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 8677 { 1091 /* bgtz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, 8678 { 1096 /* bgtzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8679 { 1096 /* bgtzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8680 { 1096 /* bgtzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8681 { 1096 /* bgtzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 8682 { 1104 /* bgtzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8683 { 1104 /* bgtzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8684 { 1104 /* bgtzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8685 { 1104 /* bgtzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 8686 { 1104 /* bgtzc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, 8687 { 1104 /* bgtzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, 8688 { 1110 /* bgtzl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 8689 { 1110 /* bgtzl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 8690 { 1116 /* binsl.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8691 { 1124 /* binsl.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8692 { 1132 /* binsl.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8693 { 1140 /* binsl.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8694 { 1148 /* binsli.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8695 { 1157 /* binsli.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8696 { 1166 /* binsli.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8697 { 1175 /* binsli.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8698 { 1184 /* binsr.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8699 { 1192 /* binsr.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8700 { 1200 /* binsr.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8701 { 1208 /* binsr.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8702 { 1216 /* binsri.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8703 { 1225 /* binsri.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8704 { 1234 /* binsri.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8705 { 1243 /* binsri.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8706 { 1252 /* bitrev */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 8707 { 1252 /* bitrev */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 8708 { 1259 /* bitswap */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, 8709 { 1259 /* bitswap */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8710 { 1267 /* ble */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, 8711 { 1267 /* ble */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, 8712 { 1267 /* ble */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, 8713 { 1267 /* ble */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, 8714 { 1271 /* blel */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8715 { 1271 /* blel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8716 { 1271 /* blel */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8717 { 1271 /* blel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8718 { 1276 /* bleu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, 8719 { 1276 /* bleu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, 8720 { 1276 /* bleu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, 8721 { 1276 /* bleu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, 8722 { 1281 /* bleul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8723 { 1281 /* bleul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8724 { 1281 /* bleul */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8725 { 1281 /* bleul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8726 { 1287 /* blez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 8727 { 1287 /* blez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, 8728 { 1287 /* blez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 8729 { 1287 /* blez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, 8730 { 1292 /* blezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8731 { 1292 /* blezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8732 { 1292 /* blezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8733 { 1292 /* blezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 8734 { 1300 /* blezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8735 { 1300 /* blezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8736 { 1300 /* blezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8737 { 1300 /* blezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 8738 { 1300 /* blezc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, 8739 { 1300 /* blezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, 8740 { 1306 /* blezl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 8741 { 1306 /* blezl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 8742 { 1312 /* blt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, 8743 { 1312 /* blt */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, 8744 { 1312 /* blt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, 8745 { 1312 /* blt */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, 8746 { 1316 /* bltc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8747 { 1316 /* bltc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8748 { 1316 /* bltc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8749 { 1316 /* bltc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 8750 { 1316 /* bltc */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, 8751 { 1316 /* bltc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, 8752 { 1321 /* bltl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8753 { 1321 /* bltl */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8754 { 1321 /* bltl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8755 { 1321 /* bltl */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8756 { 1326 /* bltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, 8757 { 1326 /* bltu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, 8758 { 1326 /* bltu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, 8759 { 1326 /* bltu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, 8760 { 1331 /* bltuc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8761 { 1331 /* bltuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8762 { 1331 /* bltuc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8763 { 1331 /* bltuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 8764 { 1331 /* bltuc */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, 8765 { 1331 /* bltuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, 8766 { 1337 /* bltul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8767 { 1337 /* bltul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8768 { 1337 /* bltul */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8769 { 1337 /* bltul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8770 { 1343 /* bltz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 8771 { 1343 /* bltz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, 8772 { 1343 /* bltz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 8773 { 1343 /* bltz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, 8774 { 1348 /* bltzal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 8775 { 1348 /* bltzal */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 8776 { 1348 /* bltzal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 8777 { 1348 /* bltzal */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, 8778 { 1355 /* bltzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8779 { 1355 /* bltzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8780 { 1355 /* bltzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8781 { 1355 /* bltzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 8782 { 1363 /* bltzall */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 8783 { 1363 /* bltzall */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 8784 { 1371 /* bltzals */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 8785 { 1371 /* bltzals */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, 8786 { 1379 /* bltzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8787 { 1379 /* bltzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8788 { 1379 /* bltzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8789 { 1379 /* bltzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 8790 { 1379 /* bltzc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, 8791 { 1379 /* bltzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, 8792 { 1385 /* bltzl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 8793 { 1385 /* bltzl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 8794 { 1391 /* bmnz.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8795 { 1398 /* bmnzi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8796 { 1406 /* bmz.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8797 { 1412 /* bmzi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8798 { 1419 /* bne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 8799 { 1419 /* bne */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, 8800 { 1419 /* bne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 8801 { 1419 /* bne */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, 8802 { 1419 /* bne */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, 8803 { 1419 /* bne */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, 8804 { 1423 /* bnec */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8805 { 1423 /* bnec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8806 { 1423 /* bnec */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8807 { 1423 /* bnec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 8808 { 1423 /* bnec */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, 8809 { 1423 /* bnec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, 8810 { 1428 /* bneg.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8811 { 1435 /* bneg.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8812 { 1442 /* bneg.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8813 { 1449 /* bneg.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8814 { 1456 /* bnegi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8815 { 1464 /* bnegi.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8816 { 1472 /* bnegi.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8817 { 1480 /* bnegi.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8818 { 1488 /* bnel */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 8819 { 1488 /* bnel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 8820 { 1488 /* bnel */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8821 { 1488 /* bnel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, 8822 { 1493 /* bnez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMips16Mode }, 8823 { 1493 /* bnez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 8824 { 1493 /* bnez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, 8825 { 1493 /* bnez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 8826 { 1493 /* bnez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips }, 8827 { 1493 /* bnez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMips16Mode }, 8828 { 1498 /* bnez16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 8829 { 1498 /* bnez16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, 8830 { 1498 /* bnez16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8831 { 1498 /* bnez16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 8832 { 1505 /* bnezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8833 { 1505 /* bnezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8834 { 1505 /* bnezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8835 { 1505 /* bnezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 8836 { 1513 /* bnezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8837 { 1513 /* bnezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8838 { 1513 /* bnezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 8839 { 1513 /* bnezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, 8840 { 1513 /* bnezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8841 { 1513 /* bnezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 8842 { 1513 /* bnezc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, 8843 { 1513 /* bnezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, 8844 { 1519 /* bnezc16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8845 { 1519 /* bnezc16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 8846 { 1527 /* bnezl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, 8847 { 1527 /* bnezl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, 8848 { 1533 /* bnvc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8849 { 1533 /* bnvc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8850 { 1533 /* bnvc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8851 { 1533 /* bnvc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 8852 { 1538 /* bnz.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8853 { 1538 /* bnz.b */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, 8854 { 1544 /* bnz.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8855 { 1544 /* bnz.d */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, 8856 { 1550 /* bnz.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8857 { 1550 /* bnz.h */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, 8858 { 1556 /* bnz.v */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8859 { 1556 /* bnz.v */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, 8860 { 1562 /* bnz.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8861 { 1562 /* bnz.w */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, 8862 { 1568 /* bovc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8863 { 1568 /* bovc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 8864 { 1568 /* bovc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 8865 { 1568 /* bovc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 8866 { 1573 /* bposge32 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6_HasDSP }, 8867 { 1573 /* bposge32 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasDSP_NotInMicroMips }, 8868 { 1582 /* bposge32c */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasDSPR3 }, 8869 { 1606 /* bsel.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8870 { 1613 /* bseli.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8871 { 1621 /* bset.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8872 { 1628 /* bset.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8873 { 1635 /* bset.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8874 { 1642 /* bset.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8875 { 1649 /* bseti.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8876 { 1657 /* bseti.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8877 { 1665 /* bseti.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8878 { 1673 /* bseti.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8879 { 1693 /* bz.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8880 { 1693 /* bz.b */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, 8881 { 1698 /* bz.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8882 { 1698 /* bz.d */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, 8883 { 1703 /* bz.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8884 { 1703 /* bz.h */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, 8885 { 1708 /* bz.v */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8886 { 1708 /* bz.v */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, 8887 { 1713 /* bz.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8888 { 1713 /* bz.w */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, 8889 { 1718 /* c.eq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8890 { 1718 /* c.eq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 8891 { 1718 /* c.eq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8892 { 1718 /* c.eq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 8893 { 1718 /* c.eq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8894 { 1718 /* c.eq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8895 { 1718 /* c.eq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 8896 { 1718 /* c.eq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 8897 { 1718 /* c.eq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8898 { 1718 /* c.eq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8899 { 1718 /* c.eq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 8900 { 1718 /* c.eq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 8901 { 1725 /* c.eq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8902 { 1725 /* c.eq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 8903 { 1725 /* c.eq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8904 { 1725 /* c.eq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8905 { 1725 /* c.eq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 8906 { 1725 /* c.eq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 8907 { 1732 /* c.f.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8908 { 1732 /* c.f.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 8909 { 1732 /* c.f.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8910 { 1732 /* c.f.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 8911 { 1732 /* c.f.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8912 { 1732 /* c.f.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8913 { 1732 /* c.f.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 8914 { 1732 /* c.f.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 8915 { 1732 /* c.f.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8916 { 1732 /* c.f.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8917 { 1732 /* c.f.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 8918 { 1732 /* c.f.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 8919 { 1738 /* c.f.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8920 { 1738 /* c.f.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 8921 { 1738 /* c.f.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8922 { 1738 /* c.f.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8923 { 1738 /* c.f.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 8924 { 1738 /* c.f.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 8925 { 1744 /* c.le.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8926 { 1744 /* c.le.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 8927 { 1744 /* c.le.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8928 { 1744 /* c.le.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 8929 { 1744 /* c.le.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8930 { 1744 /* c.le.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8931 { 1744 /* c.le.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 8932 { 1744 /* c.le.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 8933 { 1744 /* c.le.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8934 { 1744 /* c.le.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8935 { 1744 /* c.le.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 8936 { 1744 /* c.le.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 8937 { 1751 /* c.le.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8938 { 1751 /* c.le.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 8939 { 1751 /* c.le.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8940 { 1751 /* c.le.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8941 { 1751 /* c.le.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 8942 { 1751 /* c.le.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 8943 { 1758 /* c.lt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8944 { 1758 /* c.lt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 8945 { 1758 /* c.lt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8946 { 1758 /* c.lt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 8947 { 1758 /* c.lt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8948 { 1758 /* c.lt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8949 { 1758 /* c.lt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 8950 { 1758 /* c.lt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 8951 { 1758 /* c.lt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8952 { 1758 /* c.lt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8953 { 1758 /* c.lt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 8954 { 1758 /* c.lt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 8955 { 1765 /* c.lt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8956 { 1765 /* c.lt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 8957 { 1765 /* c.lt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8958 { 1765 /* c.lt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8959 { 1765 /* c.lt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 8960 { 1765 /* c.lt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 8961 { 1772 /* c.nge.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8962 { 1772 /* c.nge.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 8963 { 1772 /* c.nge.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8964 { 1772 /* c.nge.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 8965 { 1772 /* c.nge.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8966 { 1772 /* c.nge.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8967 { 1772 /* c.nge.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 8968 { 1772 /* c.nge.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 8969 { 1772 /* c.nge.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8970 { 1772 /* c.nge.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8971 { 1772 /* c.nge.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 8972 { 1772 /* c.nge.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 8973 { 1780 /* c.nge.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8974 { 1780 /* c.nge.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 8975 { 1780 /* c.nge.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8976 { 1780 /* c.nge.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8977 { 1780 /* c.nge.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 8978 { 1780 /* c.nge.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 8979 { 1788 /* c.ngl.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8980 { 1788 /* c.ngl.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 8981 { 1788 /* c.ngl.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8982 { 1788 /* c.ngl.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 8983 { 1788 /* c.ngl.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8984 { 1788 /* c.ngl.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8985 { 1788 /* c.ngl.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 8986 { 1788 /* c.ngl.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 8987 { 1788 /* c.ngl.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8988 { 1788 /* c.ngl.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8989 { 1788 /* c.ngl.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 8990 { 1788 /* c.ngl.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 8991 { 1796 /* c.ngl.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8992 { 1796 /* c.ngl.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 8993 { 1796 /* c.ngl.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8994 { 1796 /* c.ngl.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8995 { 1796 /* c.ngl.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 8996 { 1796 /* c.ngl.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 8997 { 1804 /* c.ngle.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 8998 { 1804 /* c.ngle.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 8999 { 1804 /* c.ngle.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9000 { 1804 /* c.ngle.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 9001 { 1804 /* c.ngle.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9002 { 1804 /* c.ngle.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9003 { 1804 /* c.ngle.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 9004 { 1804 /* c.ngle.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 9005 { 1804 /* c.ngle.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9006 { 1804 /* c.ngle.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9007 { 1804 /* c.ngle.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 9008 { 1804 /* c.ngle.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 9009 { 1813 /* c.ngle.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9010 { 1813 /* c.ngle.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 9011 { 1813 /* c.ngle.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9012 { 1813 /* c.ngle.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9013 { 1813 /* c.ngle.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 9014 { 1813 /* c.ngle.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 9015 { 1822 /* c.ngt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9016 { 1822 /* c.ngt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 9017 { 1822 /* c.ngt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9018 { 1822 /* c.ngt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 9019 { 1822 /* c.ngt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9020 { 1822 /* c.ngt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9021 { 1822 /* c.ngt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 9022 { 1822 /* c.ngt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 9023 { 1822 /* c.ngt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9024 { 1822 /* c.ngt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9025 { 1822 /* c.ngt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 9026 { 1822 /* c.ngt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 9027 { 1830 /* c.ngt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9028 { 1830 /* c.ngt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 9029 { 1830 /* c.ngt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9030 { 1830 /* c.ngt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9031 { 1830 /* c.ngt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 9032 { 1830 /* c.ngt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 9033 { 1838 /* c.ole.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9034 { 1838 /* c.ole.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 9035 { 1838 /* c.ole.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9036 { 1838 /* c.ole.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 9037 { 1838 /* c.ole.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9038 { 1838 /* c.ole.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9039 { 1838 /* c.ole.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 9040 { 1838 /* c.ole.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 9041 { 1838 /* c.ole.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9042 { 1838 /* c.ole.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9043 { 1838 /* c.ole.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 9044 { 1838 /* c.ole.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 9045 { 1846 /* c.ole.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9046 { 1846 /* c.ole.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 9047 { 1846 /* c.ole.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9048 { 1846 /* c.ole.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9049 { 1846 /* c.ole.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 9050 { 1846 /* c.ole.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 9051 { 1854 /* c.olt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9052 { 1854 /* c.olt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 9053 { 1854 /* c.olt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9054 { 1854 /* c.olt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 9055 { 1854 /* c.olt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9056 { 1854 /* c.olt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9057 { 1854 /* c.olt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 9058 { 1854 /* c.olt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 9059 { 1854 /* c.olt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9060 { 1854 /* c.olt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9061 { 1854 /* c.olt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 9062 { 1854 /* c.olt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 9063 { 1862 /* c.olt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9064 { 1862 /* c.olt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 9065 { 1862 /* c.olt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9066 { 1862 /* c.olt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9067 { 1862 /* c.olt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 9068 { 1862 /* c.olt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 9069 { 1870 /* c.seq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9070 { 1870 /* c.seq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 9071 { 1870 /* c.seq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9072 { 1870 /* c.seq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 9073 { 1870 /* c.seq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9074 { 1870 /* c.seq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9075 { 1870 /* c.seq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 9076 { 1870 /* c.seq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 9077 { 1870 /* c.seq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9078 { 1870 /* c.seq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9079 { 1870 /* c.seq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 9080 { 1870 /* c.seq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 9081 { 1878 /* c.seq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9082 { 1878 /* c.seq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 9083 { 1878 /* c.seq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9084 { 1878 /* c.seq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9085 { 1878 /* c.seq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 9086 { 1878 /* c.seq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 9087 { 1886 /* c.sf.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9088 { 1886 /* c.sf.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 9089 { 1886 /* c.sf.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9090 { 1886 /* c.sf.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 9091 { 1886 /* c.sf.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9092 { 1886 /* c.sf.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9093 { 1886 /* c.sf.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 9094 { 1886 /* c.sf.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 9095 { 1886 /* c.sf.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9096 { 1886 /* c.sf.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9097 { 1886 /* c.sf.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 9098 { 1886 /* c.sf.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 9099 { 1893 /* c.sf.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9100 { 1893 /* c.sf.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 9101 { 1893 /* c.sf.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9102 { 1893 /* c.sf.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9103 { 1893 /* c.sf.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 9104 { 1893 /* c.sf.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 9105 { 1900 /* c.ueq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9106 { 1900 /* c.ueq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 9107 { 1900 /* c.ueq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9108 { 1900 /* c.ueq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 9109 { 1900 /* c.ueq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9110 { 1900 /* c.ueq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9111 { 1900 /* c.ueq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 9112 { 1900 /* c.ueq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 9113 { 1900 /* c.ueq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9114 { 1900 /* c.ueq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9115 { 1900 /* c.ueq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 9116 { 1900 /* c.ueq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 9117 { 1908 /* c.ueq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9118 { 1908 /* c.ueq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 9119 { 1908 /* c.ueq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9120 { 1908 /* c.ueq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9121 { 1908 /* c.ueq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 9122 { 1908 /* c.ueq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 9123 { 1916 /* c.ule.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9124 { 1916 /* c.ule.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 9125 { 1916 /* c.ule.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9126 { 1916 /* c.ule.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 9127 { 1916 /* c.ule.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9128 { 1916 /* c.ule.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9129 { 1916 /* c.ule.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 9130 { 1916 /* c.ule.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 9131 { 1916 /* c.ule.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9132 { 1916 /* c.ule.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9133 { 1916 /* c.ule.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 9134 { 1916 /* c.ule.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 9135 { 1924 /* c.ule.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9136 { 1924 /* c.ule.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 9137 { 1924 /* c.ule.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9138 { 1924 /* c.ule.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9139 { 1924 /* c.ule.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 9140 { 1924 /* c.ule.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 9141 { 1932 /* c.ult.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9142 { 1932 /* c.ult.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 9143 { 1932 /* c.ult.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9144 { 1932 /* c.ult.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 9145 { 1932 /* c.ult.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9146 { 1932 /* c.ult.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9147 { 1932 /* c.ult.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 9148 { 1932 /* c.ult.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 9149 { 1932 /* c.ult.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9150 { 1932 /* c.ult.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9151 { 1932 /* c.ult.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 9152 { 1932 /* c.ult.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 9153 { 1940 /* c.ult.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9154 { 1940 /* c.ult.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 9155 { 1940 /* c.ult.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9156 { 1940 /* c.ult.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9157 { 1940 /* c.ult.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 9158 { 1940 /* c.ult.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 9159 { 1948 /* c.un.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9160 { 1948 /* c.un.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 9161 { 1948 /* c.un.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9162 { 1948 /* c.un.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 9163 { 1948 /* c.un.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9164 { 1948 /* c.un.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9165 { 1948 /* c.un.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 9166 { 1948 /* c.un.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 9167 { 1948 /* c.un.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9168 { 1948 /* c.un.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9169 { 1948 /* c.un.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 9170 { 1948 /* c.un.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 9171 { 1955 /* c.un.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9172 { 1955 /* c.un.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 9173 { 1955 /* c.un.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9174 { 1955 /* c.un.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9175 { 1955 /* c.un.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 9176 { 1955 /* c.un.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 9177 { 1962 /* cache */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 9178 { 1962 /* cache */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips }, 9179 { 1962 /* cache */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 }, 9180 { 1962 /* cache */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 }, 9181 { 1968 /* cachee */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 9182 { 1968 /* cachee */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA }, 9183 { 1975 /* ceil.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips }, 9184 { 1975 /* ceil.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9185 { 1984 /* ceil.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 9186 { 1984 /* ceil.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 9187 { 1984 /* ceil.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9188 { 1984 /* ceil.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9189 { 1993 /* ceil.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 9190 { 1993 /* ceil.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 9191 { 1993 /* ceil.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9192 { 1993 /* ceil.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9193 { 1993 /* ceil.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 9194 { 1993 /* ceil.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 9195 { 1993 /* ceil.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 9196 { 1993 /* ceil.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 9197 { 2002 /* ceil.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips }, 9198 { 2002 /* ceil.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9199 { 2002 /* ceil.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, 9200 { 2011 /* ceq.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9201 { 2017 /* ceq.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9202 { 2023 /* ceq.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9203 { 2029 /* ceq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9204 { 2035 /* ceqi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9205 { 2042 /* ceqi.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9206 { 2049 /* ceqi.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9207 { 2056 /* ceqi.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9208 { 2063 /* cfc1 */, 2 /* 1 */, MCK_CCRAsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, 9209 { 2063 /* cfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, 9210 { 2063 /* cfc1 */, 2 /* 1 */, MCK_CCRAsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, 9211 { 2063 /* cfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, 9212 { 2068 /* cfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips }, 9213 { 2068 /* cfc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 9214 { 2073 /* cfcmsa */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, 9215 { 2073 /* cfcmsa */, 2 /* 1 */, MCK_MSACtrlAsmReg, AMFBS_HasStdEnc_HasMSA }, 9216 { 2080 /* cftc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT }, 9217 { 2080 /* cftc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, 9218 { 2086 /* cins */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips }, 9219 { 2086 /* cins */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips }, 9220 { 2086 /* cins */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips }, 9221 { 2086 /* cins */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips }, 9222 { 2091 /* cins32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips }, 9223 { 2091 /* cins32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips }, 9224 { 2098 /* class.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9225 { 2098 /* class.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 9226 { 2106 /* class.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9227 { 2106 /* class.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 9228 { 2114 /* cle_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9229 { 2122 /* cle_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9230 { 2130 /* cle_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9231 { 2138 /* cle_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9232 { 2146 /* cle_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9233 { 2154 /* cle_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9234 { 2162 /* cle_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9235 { 2170 /* cle_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9236 { 2178 /* clei_s.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9237 { 2187 /* clei_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9238 { 2196 /* clei_s.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9239 { 2205 /* clei_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9240 { 2214 /* clei_u.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9241 { 2223 /* clei_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9242 { 2232 /* clei_u.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9243 { 2241 /* clei_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9244 { 2250 /* clo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips }, 9245 { 2250 /* clo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 9246 { 2250 /* clo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, 9247 { 2250 /* clo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 9248 { 2254 /* clt_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9249 { 2262 /* clt_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9250 { 2270 /* clt_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9251 { 2278 /* clt_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9252 { 2286 /* clt_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9253 { 2294 /* clt_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9254 { 2302 /* clt_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9255 { 2310 /* clt_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9256 { 2318 /* clti_s.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9257 { 2327 /* clti_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9258 { 2336 /* clti_s.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9259 { 2345 /* clti_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9260 { 2354 /* clti_u.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9261 { 2363 /* clti_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9262 { 2372 /* clti_u.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9263 { 2381 /* clti_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9264 { 2390 /* clz */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips }, 9265 { 2390 /* clz */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 9266 { 2390 /* clz */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, 9267 { 2390 /* clz */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 9268 { 2398 /* cmp.af.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9269 { 2398 /* cmp.af.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9270 { 2398 /* cmp.af.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9271 { 2398 /* cmp.af.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9272 { 2407 /* cmp.af.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9273 { 2407 /* cmp.af.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9274 { 2416 /* cmp.eq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9275 { 2416 /* cmp.eq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9276 { 2416 /* cmp.eq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9277 { 2416 /* cmp.eq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9278 { 2425 /* cmp.eq.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 9279 { 2425 /* cmp.eq.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 9280 { 2435 /* cmp.eq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9281 { 2435 /* cmp.eq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9282 { 2444 /* cmp.le.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9283 { 2444 /* cmp.le.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9284 { 2444 /* cmp.le.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9285 { 2444 /* cmp.le.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9286 { 2453 /* cmp.le.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 9287 { 2453 /* cmp.le.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 9288 { 2463 /* cmp.le.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9289 { 2463 /* cmp.le.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9290 { 2472 /* cmp.lt.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9291 { 2472 /* cmp.lt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9292 { 2472 /* cmp.lt.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9293 { 2472 /* cmp.lt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9294 { 2481 /* cmp.lt.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 9295 { 2481 /* cmp.lt.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 9296 { 2491 /* cmp.lt.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9297 { 2491 /* cmp.lt.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9298 { 2500 /* cmp.saf.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9299 { 2500 /* cmp.saf.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9300 { 2500 /* cmp.saf.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9301 { 2500 /* cmp.saf.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9302 { 2510 /* cmp.saf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9303 { 2510 /* cmp.saf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9304 { 2520 /* cmp.seq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9305 { 2520 /* cmp.seq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9306 { 2520 /* cmp.seq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9307 { 2520 /* cmp.seq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9308 { 2530 /* cmp.seq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9309 { 2530 /* cmp.seq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9310 { 2540 /* cmp.sle.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9311 { 2540 /* cmp.sle.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9312 { 2540 /* cmp.sle.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9313 { 2540 /* cmp.sle.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9314 { 2550 /* cmp.sle.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9315 { 2550 /* cmp.sle.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9316 { 2560 /* cmp.slt.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9317 { 2560 /* cmp.slt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9318 { 2560 /* cmp.slt.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9319 { 2560 /* cmp.slt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9320 { 2570 /* cmp.slt.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9321 { 2570 /* cmp.slt.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9322 { 2580 /* cmp.sueq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9323 { 2580 /* cmp.sueq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9324 { 2580 /* cmp.sueq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9325 { 2580 /* cmp.sueq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9326 { 2591 /* cmp.sueq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9327 { 2591 /* cmp.sueq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9328 { 2602 /* cmp.sule.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9329 { 2602 /* cmp.sule.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9330 { 2602 /* cmp.sule.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9331 { 2602 /* cmp.sule.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9332 { 2613 /* cmp.sule.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9333 { 2613 /* cmp.sule.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9334 { 2624 /* cmp.sult.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9335 { 2624 /* cmp.sult.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9336 { 2624 /* cmp.sult.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9337 { 2624 /* cmp.sult.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9338 { 2635 /* cmp.sult.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9339 { 2635 /* cmp.sult.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9340 { 2646 /* cmp.sun.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9341 { 2646 /* cmp.sun.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9342 { 2646 /* cmp.sun.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9343 { 2646 /* cmp.sun.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9344 { 2656 /* cmp.sun.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9345 { 2656 /* cmp.sun.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9346 { 2666 /* cmp.ueq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9347 { 2666 /* cmp.ueq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9348 { 2666 /* cmp.ueq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9349 { 2666 /* cmp.ueq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9350 { 2676 /* cmp.ueq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9351 { 2676 /* cmp.ueq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9352 { 2686 /* cmp.ule.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9353 { 2686 /* cmp.ule.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9354 { 2686 /* cmp.ule.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9355 { 2686 /* cmp.ule.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9356 { 2696 /* cmp.ule.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9357 { 2696 /* cmp.ule.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9358 { 2706 /* cmp.ult.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9359 { 2706 /* cmp.ult.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9360 { 2706 /* cmp.ult.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9361 { 2706 /* cmp.ult.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9362 { 2716 /* cmp.ult.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9363 { 2716 /* cmp.ult.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9364 { 2726 /* cmp.un.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9365 { 2726 /* cmp.un.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9366 { 2726 /* cmp.un.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9367 { 2726 /* cmp.un.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9368 { 2735 /* cmp.un.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 9369 { 2735 /* cmp.un.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9370 { 2744 /* cmpgdu.eq.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 9371 { 2744 /* cmpgdu.eq.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 9372 { 2757 /* cmpgdu.le.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 9373 { 2757 /* cmpgdu.le.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 9374 { 2770 /* cmpgdu.lt.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 9375 { 2770 /* cmpgdu.lt.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 9376 { 2783 /* cmpgu.eq.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 9377 { 2783 /* cmpgu.eq.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 9378 { 2795 /* cmpgu.le.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 9379 { 2795 /* cmpgu.le.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 9380 { 2807 /* cmpgu.lt.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 9381 { 2807 /* cmpgu.lt.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 9382 { 2824 /* cmpu.eq.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 9383 { 2824 /* cmpu.eq.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 9384 { 2835 /* cmpu.le.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 9385 { 2835 /* cmpu.le.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 9386 { 2846 /* cmpu.lt.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 9387 { 2846 /* cmpu.lt.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 9388 { 2857 /* copy_s.b */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, 9389 { 2857 /* copy_s.b */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9390 { 2866 /* copy_s.d */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 }, 9391 { 2866 /* copy_s.d */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 }, 9392 { 2875 /* copy_s.h */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, 9393 { 2875 /* copy_s.h */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9394 { 2884 /* copy_s.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, 9395 { 2884 /* copy_s.w */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9396 { 2893 /* copy_u.b */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, 9397 { 2893 /* copy_u.b */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9398 { 2902 /* copy_u.h */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, 9399 { 2902 /* copy_u.h */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9400 { 2911 /* copy_u.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 }, 9401 { 2911 /* copy_u.w */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 }, 9402 { 2920 /* crc32b */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips }, 9403 { 2927 /* crc32cb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips }, 9404 { 2935 /* crc32cd */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips }, 9405 { 2943 /* crc32ch */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips }, 9406 { 2951 /* crc32cw */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips }, 9407 { 2959 /* crc32d */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips }, 9408 { 2966 /* crc32h */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips }, 9409 { 2973 /* crc32w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips }, 9410 { 2980 /* ctc1 */, 2 /* 1 */, MCK_CCRAsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, 9411 { 2980 /* ctc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, 9412 { 2980 /* ctc1 */, 2 /* 1 */, MCK_CCRAsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, 9413 { 2980 /* ctc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, 9414 { 2985 /* ctc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips }, 9415 { 2985 /* ctc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 9416 { 2990 /* ctcmsa */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, 9417 { 2990 /* ctcmsa */, 1 /* 0 */, MCK_MSACtrlAsmReg, AMFBS_HasStdEnc_HasMSA }, 9418 { 2997 /* cttc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT }, 9419 { 2997 /* cttc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, 9420 { 3003 /* cvt.d.l */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips }, 9421 { 3003 /* cvt.d.l */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat }, 9422 { 3011 /* cvt.d.s */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, 9423 { 3011 /* cvt.d.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, 9424 { 3011 /* cvt.d.s */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 9425 { 3011 /* cvt.d.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 9426 { 3011 /* cvt.d.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, 9427 { 3011 /* cvt.d.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, 9428 { 3011 /* cvt.d.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, 9429 { 3011 /* cvt.d.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, 9430 { 3019 /* cvt.d.w */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, 9431 { 3019 /* cvt.d.w */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, 9432 { 3019 /* cvt.d.w */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 9433 { 3019 /* cvt.d.w */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 9434 { 3019 /* cvt.d.w */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, 9435 { 3019 /* cvt.d.w */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, 9436 { 3019 /* cvt.d.w */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, 9437 { 3019 /* cvt.d.w */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, 9438 { 3027 /* cvt.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips }, 9439 { 3027 /* cvt.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, 9440 { 3027 /* cvt.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9441 { 3035 /* cvt.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips }, 9442 { 3035 /* cvt.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips }, 9443 { 3035 /* cvt.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, 9444 { 3035 /* cvt.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, 9445 { 3035 /* cvt.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9446 { 3035 /* cvt.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9447 { 3043 /* cvt.ps.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9448 { 3043 /* cvt.ps.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9449 { 3052 /* cvt.s.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, 9450 { 3052 /* cvt.s.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, 9451 { 3052 /* cvt.s.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 9452 { 3052 /* cvt.s.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 9453 { 3052 /* cvt.s.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, 9454 { 3052 /* cvt.s.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, 9455 { 3052 /* cvt.s.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, 9456 { 3052 /* cvt.s.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, 9457 { 3060 /* cvt.s.l */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips }, 9458 { 3060 /* cvt.s.l */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips }, 9459 { 3060 /* cvt.s.l */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat }, 9460 { 3060 /* cvt.s.l */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat }, 9461 { 3068 /* cvt.s.pl */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9462 { 3068 /* cvt.s.pl */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9463 { 3077 /* cvt.s.pu */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9464 { 3077 /* cvt.s.pu */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 9465 { 3086 /* cvt.s.w */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, 9466 { 3086 /* cvt.s.w */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9467 { 3086 /* cvt.s.w */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, 9468 { 3094 /* cvt.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, 9469 { 3094 /* cvt.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, 9470 { 3094 /* cvt.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 9471 { 3094 /* cvt.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 9472 { 3094 /* cvt.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, 9473 { 3094 /* cvt.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, 9474 { 3094 /* cvt.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, 9475 { 3094 /* cvt.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, 9476 { 3102 /* cvt.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, 9477 { 3102 /* cvt.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9478 { 3102 /* cvt.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, 9479 { 3110 /* dadd */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9480 { 3110 /* dadd */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, 9481 { 3110 /* dadd */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9482 { 3110 /* dadd */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, 9483 { 3115 /* daddi */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, 9484 { 3115 /* daddi */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, 9485 { 3121 /* daddiu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9486 { 3121 /* daddiu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9487 { 3128 /* daddu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9488 { 3128 /* daddu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9489 { 3128 /* daddu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9490 { 3128 /* daddu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9491 { 3134 /* dahi */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, 9492 { 3139 /* dalign */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, 9493 { 3146 /* dati */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, 9494 { 3151 /* daui */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, 9495 { 3156 /* dbitswap */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, 9496 { 3165 /* dclo */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips }, 9497 { 3165 /* dclo */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, 9498 { 3170 /* dclz */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips }, 9499 { 3170 /* dclz */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, 9500 { 3175 /* ddiv */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, 9501 { 3175 /* ddiv */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, 9502 { 3175 /* ddiv */, 6 /* 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, 9503 { 3175 /* ddiv */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, 9504 { 3175 /* ddiv */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, 9505 { 3175 /* ddiv */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, 9506 { 3180 /* ddivu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, 9507 { 3180 /* ddivu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, 9508 { 3180 /* ddivu */, 6 /* 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, 9509 { 3180 /* ddivu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, 9510 { 3180 /* ddivu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, 9511 { 3180 /* ddivu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, 9512 { 3192 /* dext */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, 9513 { 3192 /* dext */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, 9514 { 3192 /* dext */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, 9515 { 3197 /* dextm */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, 9516 { 3203 /* dextu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, 9517 { 3209 /* di */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, 9518 { 3209 /* di */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 9519 { 3209 /* di */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 9520 { 3212 /* dins */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, 9521 { 3212 /* dins */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, 9522 { 3212 /* dins */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, 9523 { 3217 /* dinsm */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, 9524 { 3223 /* dinsu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, 9525 { 3229 /* div */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, 9526 { 3229 /* div */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 9527 { 3229 /* div */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 9528 { 3229 /* div */, 1 /* 0 */, MCK_GPR32NonZeroAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 9529 { 3229 /* div */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 9530 { 3229 /* div */, 1 /* 0 */, MCK_GPR32ZeroAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 9531 { 3229 /* div */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 9532 { 3229 /* div */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 9533 { 3229 /* div */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 9534 { 3229 /* div */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 9535 { 3229 /* div */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 9536 { 3229 /* div */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 9537 { 3229 /* div */, 1 /* 0 */, MCK_GPR32NonZeroAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 9538 { 3233 /* div.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, 9539 { 3233 /* div.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 9540 { 3233 /* div.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, 9541 { 3233 /* div.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, 9542 { 3239 /* div.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, 9543 { 3239 /* div.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9544 { 3239 /* div.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, 9545 { 3245 /* div_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9546 { 3253 /* div_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9547 { 3261 /* div_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9548 { 3269 /* div_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9549 { 3277 /* div_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9550 { 3285 /* div_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9551 { 3293 /* div_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9552 { 3301 /* div_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9553 { 3309 /* divu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, 9554 { 3309 /* divu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 9555 { 3309 /* divu */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 9556 { 3309 /* divu */, 1 /* 0 */, MCK_GPR32NonZeroAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 9557 { 3309 /* divu */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 9558 { 3309 /* divu */, 1 /* 0 */, MCK_GPR32ZeroAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 9559 { 3309 /* divu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 9560 { 3309 /* divu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 9561 { 3309 /* divu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 9562 { 3309 /* divu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 9563 { 3309 /* divu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 9564 { 3309 /* divu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 9565 { 3314 /* dla */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None }, 9566 { 3314 /* dla */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None }, 9567 { 3314 /* dla */, 2 /* 1 */, MCK_Mem, AMFBS_None }, 9568 { 3318 /* dli */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None }, 9569 { 3322 /* dlsa */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 }, 9570 { 3322 /* dlsa */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, 9571 { 3327 /* dmfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_NotInMicroMips }, 9572 { 3327 /* dmfc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_NotInMicroMips }, 9573 { 3327 /* dmfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 }, 9574 { 3327 /* dmfc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 }, 9575 { 3333 /* dmfc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips }, 9576 { 3333 /* dmfc1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips }, 9577 { 3339 /* dmfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_None }, 9578 { 3339 /* dmfc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None }, 9579 { 3339 /* dmfc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 9580 { 3339 /* dmfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 }, 9581 { 3339 /* dmfc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 }, 9582 { 3345 /* dmfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips }, 9583 { 3345 /* dmfgc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips }, 9584 { 3345 /* dmfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt }, 9585 { 3345 /* dmfgc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt }, 9586 { 3352 /* dmod */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, 9587 { 3357 /* dmodu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, 9588 { 3363 /* dmt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips }, 9589 { 3367 /* dmtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_NotInMicroMips }, 9590 { 3367 /* dmtc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_NotInMicroMips }, 9591 { 3367 /* dmtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 }, 9592 { 3367 /* dmtc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 }, 9593 { 3373 /* dmtc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips }, 9594 { 3373 /* dmtc1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips }, 9595 { 3379 /* dmtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_None }, 9596 { 3379 /* dmtc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None }, 9597 { 3379 /* dmtc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 9598 { 3379 /* dmtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 }, 9599 { 3379 /* dmtc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 }, 9600 { 3385 /* dmtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips }, 9601 { 3385 /* dmtgc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips }, 9602 { 3385 /* dmtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt }, 9603 { 3385 /* dmtgc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt }, 9604 { 3392 /* dmuh */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, 9605 { 3397 /* dmuhu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, 9606 { 3403 /* dmul */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 9607 { 3403 /* dmul */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasMips3_NotMips64r6_NotCnMips }, 9608 { 3403 /* dmul */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, 9609 { 3403 /* dmul */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 9610 { 3403 /* dmul */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, 9611 { 3408 /* dmulo */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, 9612 { 3414 /* dmulou */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, 9613 { 3421 /* dmult */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, 9614 { 3427 /* dmultu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, 9615 { 3434 /* dmulu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, 9616 { 3440 /* dneg */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9617 { 3440 /* dneg */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9618 { 3445 /* dnegu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9619 { 3445 /* dnegu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9620 { 3451 /* dotp_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9621 { 3460 /* dotp_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9622 { 3469 /* dotp_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9623 { 3478 /* dotp_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9624 { 3487 /* dotp_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9625 { 3496 /* dotp_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9626 { 3505 /* dpa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 }, 9627 { 3505 /* dpa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 9628 { 3505 /* dpa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 }, 9629 { 3505 /* dpa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 9630 { 3514 /* dpadd_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9631 { 3524 /* dpadd_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9632 { 3534 /* dpadd_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9633 { 3544 /* dpadd_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9634 { 3554 /* dpadd_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9635 { 3564 /* dpadd_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9636 { 3574 /* dpaq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 9637 { 3574 /* dpaq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 9638 { 3574 /* dpaq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 9639 { 3574 /* dpaq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 9640 { 3586 /* dpaq_sa.l.w */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 9641 { 3586 /* dpaq_sa.l.w */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 9642 { 3586 /* dpaq_sa.l.w */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 9643 { 3586 /* dpaq_sa.l.w */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 9644 { 3598 /* dpaqx_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 }, 9645 { 3598 /* dpaqx_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 9646 { 3598 /* dpaqx_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 }, 9647 { 3598 /* dpaqx_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 9648 { 3611 /* dpaqx_sa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 }, 9649 { 3611 /* dpaqx_sa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 9650 { 3611 /* dpaqx_sa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 }, 9651 { 3611 /* dpaqx_sa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 9652 { 3625 /* dpau.h.qbl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 9653 { 3625 /* dpau.h.qbl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 9654 { 3625 /* dpau.h.qbl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 9655 { 3625 /* dpau.h.qbl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 9656 { 3636 /* dpau.h.qbr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 9657 { 3636 /* dpau.h.qbr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 9658 { 3636 /* dpau.h.qbr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 9659 { 3636 /* dpau.h.qbr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 9660 { 3647 /* dpax.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 }, 9661 { 3647 /* dpax.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 9662 { 3647 /* dpax.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 }, 9663 { 3647 /* dpax.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 9664 { 3657 /* dpop */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 9665 { 3657 /* dpop */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 9666 { 3662 /* dps.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 }, 9667 { 3662 /* dps.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 9668 { 3662 /* dps.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 }, 9669 { 3662 /* dps.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 9670 { 3671 /* dpsq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 9671 { 3671 /* dpsq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 9672 { 3671 /* dpsq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 9673 { 3671 /* dpsq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 9674 { 3683 /* dpsq_sa.l.w */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 9675 { 3683 /* dpsq_sa.l.w */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 9676 { 3683 /* dpsq_sa.l.w */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 9677 { 3683 /* dpsq_sa.l.w */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 9678 { 3695 /* dpsqx_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 }, 9679 { 3695 /* dpsqx_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 9680 { 3695 /* dpsqx_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 }, 9681 { 3695 /* dpsqx_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 9682 { 3708 /* dpsqx_sa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 }, 9683 { 3708 /* dpsqx_sa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 9684 { 3708 /* dpsqx_sa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 }, 9685 { 3708 /* dpsqx_sa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 9686 { 3722 /* dpsu.h.qbl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 9687 { 3722 /* dpsu.h.qbl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 9688 { 3722 /* dpsu.h.qbl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 9689 { 3722 /* dpsu.h.qbl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 9690 { 3733 /* dpsu.h.qbr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 9691 { 3733 /* dpsu.h.qbr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 9692 { 3733 /* dpsu.h.qbr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 9693 { 3733 /* dpsu.h.qbr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 9694 { 3744 /* dpsub_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9695 { 3754 /* dpsub_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9696 { 3764 /* dpsub_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9697 { 3774 /* dpsub_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9698 { 3784 /* dpsub_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9699 { 3794 /* dpsub_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9700 { 3804 /* dpsx.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 }, 9701 { 3804 /* dpsx.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 9702 { 3804 /* dpsx.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 }, 9703 { 3804 /* dpsx.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 9704 { 3814 /* drem */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, 9705 { 3814 /* drem */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, 9706 { 3814 /* drem */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, 9707 { 3814 /* drem */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, 9708 { 3819 /* dremu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, 9709 { 3819 /* dremu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, 9710 { 3819 /* dremu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, 9711 { 3819 /* dremu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, 9712 { 3825 /* drol */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 }, 9713 { 3825 /* drol */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 }, 9714 { 3825 /* drol */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 }, 9715 { 3825 /* drol */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 }, 9716 { 3830 /* dror */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 }, 9717 { 3830 /* dror */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 }, 9718 { 3830 /* dror */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 }, 9719 { 3830 /* dror */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 }, 9720 { 3835 /* drotr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, 9721 { 3835 /* drotr */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, 9722 { 3841 /* drotr32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, 9723 { 3841 /* drotr32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, 9724 { 3849 /* drotrv */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, 9725 { 3849 /* drotrv */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, 9726 { 3856 /* dsbh */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, 9727 { 3861 /* dshd */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, 9728 { 3866 /* dsll */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9729 { 3866 /* dsll */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9730 { 3866 /* dsll */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9731 { 3866 /* dsll */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9732 { 3866 /* dsll */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9733 { 3866 /* dsll */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9734 { 3871 /* dsll32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9735 { 3871 /* dsll32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9736 { 3878 /* dsllv */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9737 { 3878 /* dsllv */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9738 { 3884 /* dsra */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9739 { 3884 /* dsra */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3 }, 9740 { 3884 /* dsra */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3 }, 9741 { 3884 /* dsra */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9742 { 3889 /* dsra32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9743 { 3889 /* dsra32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9744 { 3896 /* dsrav */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9745 { 3896 /* dsrav */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9746 { 3902 /* dsrl */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9747 { 3902 /* dsrl */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9748 { 3902 /* dsrl */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9749 { 3902 /* dsrl */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9750 { 3902 /* dsrl */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9751 { 3902 /* dsrl */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9752 { 3907 /* dsrl32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9753 { 3907 /* dsrl32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9754 { 3914 /* dsrlv */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9755 { 3914 /* dsrlv */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9756 { 3920 /* dsub */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9757 { 3920 /* dsub */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, 9758 { 3920 /* dsub */, 2 /* 1 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, 9759 { 3920 /* dsub */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9760 { 3920 /* dsub */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, 9761 { 3920 /* dsub */, 4 /* 2 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, 9762 { 3925 /* dsubi */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, 9763 { 3925 /* dsubi */, 2 /* 1 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, 9764 { 3925 /* dsubi */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, 9765 { 3925 /* dsubi */, 4 /* 2 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, 9766 { 3931 /* dsubu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9767 { 3931 /* dsubu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9768 { 3931 /* dsubu */, 2 /* 1 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9769 { 3931 /* dsubu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9770 { 3931 /* dsubu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9771 { 3931 /* dsubu */, 4 /* 2 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 9772 { 3937 /* dvp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, 9773 { 3937 /* dvp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 9774 { 3941 /* dvpe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips }, 9775 { 3950 /* ei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, 9776 { 3950 /* ei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 9777 { 3950 /* ei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 9778 { 3953 /* emt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips }, 9779 { 3969 /* evp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, 9780 { 3969 /* evp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 9781 { 3973 /* evpe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips }, 9782 { 3978 /* ext */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, 9783 { 3978 /* ext */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 9784 { 3978 /* ext */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 9785 { 3982 /* extp */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 9786 { 3982 /* extp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 9787 { 3982 /* extp */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 9788 { 3982 /* extp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 9789 { 3987 /* extpdp */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 9790 { 3987 /* extpdp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 9791 { 3987 /* extpdp */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 9792 { 3987 /* extpdp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 9793 { 3994 /* extpdpv */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 9794 { 3994 /* extpdpv */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 9795 { 3994 /* extpdpv */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 9796 { 3994 /* extpdpv */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 9797 { 4002 /* extpv */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 9798 { 4002 /* extpv */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 9799 { 4002 /* extpv */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 9800 { 4002 /* extpv */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 9801 { 4008 /* extr.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 9802 { 4008 /* extr.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 9803 { 4008 /* extr.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 9804 { 4008 /* extr.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 9805 { 4015 /* extr_r.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 9806 { 4015 /* extr_r.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 9807 { 4015 /* extr_r.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 9808 { 4015 /* extr_r.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 9809 { 4024 /* extr_rs.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 9810 { 4024 /* extr_rs.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 9811 { 4024 /* extr_rs.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 9812 { 4024 /* extr_rs.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 9813 { 4034 /* extr_s.h */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 9814 { 4034 /* extr_s.h */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 9815 { 4034 /* extr_s.h */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 9816 { 4034 /* extr_s.h */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 9817 { 4043 /* extrv.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 9818 { 4043 /* extrv.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 9819 { 4043 /* extrv.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 9820 { 4043 /* extrv.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 9821 { 4051 /* extrv_r.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 9822 { 4051 /* extrv_r.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 9823 { 4051 /* extrv_r.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 9824 { 4051 /* extrv_r.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 9825 { 4061 /* extrv_rs.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 9826 { 4061 /* extrv_rs.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 9827 { 4061 /* extrv_rs.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 9828 { 4061 /* extrv_rs.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 9829 { 4072 /* extrv_s.h */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 9830 { 4072 /* extrv_s.h */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 9831 { 4072 /* extrv_s.h */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 9832 { 4072 /* extrv_s.h */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 9833 { 4082 /* exts */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips }, 9834 { 4082 /* exts */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips }, 9835 { 4082 /* exts */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips }, 9836 { 4082 /* exts */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips }, 9837 { 4087 /* exts32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips }, 9838 { 4087 /* exts32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips }, 9839 { 4094 /* fadd.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9840 { 4101 /* fadd.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9841 { 4108 /* fcaf.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9842 { 4115 /* fcaf.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9843 { 4122 /* fceq.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9844 { 4129 /* fceq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9845 { 4136 /* fclass.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9846 { 4145 /* fclass.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9847 { 4154 /* fcle.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9848 { 4161 /* fcle.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9849 { 4168 /* fclt.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9850 { 4175 /* fclt.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9851 { 4182 /* fcne.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9852 { 4189 /* fcne.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9853 { 4196 /* fcor.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9854 { 4203 /* fcor.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9855 { 4210 /* fcueq.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9856 { 4218 /* fcueq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9857 { 4226 /* fcule.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9858 { 4234 /* fcule.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9859 { 4242 /* fcult.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9860 { 4250 /* fcult.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9861 { 4258 /* fcun.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9862 { 4265 /* fcun.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9863 { 4272 /* fcune.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9864 { 4280 /* fcune.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9865 { 4288 /* fdiv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9866 { 4295 /* fdiv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9867 { 4302 /* fexdo.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9868 { 4310 /* fexdo.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9869 { 4318 /* fexp2.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9870 { 4326 /* fexp2.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9871 { 4334 /* fexupl.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9872 { 4343 /* fexupl.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9873 { 4352 /* fexupr.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9874 { 4361 /* fexupr.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9875 { 4370 /* ffint_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9876 { 4380 /* ffint_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9877 { 4390 /* ffint_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9878 { 4400 /* ffint_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9879 { 4410 /* ffql.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9880 { 4417 /* ffql.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9881 { 4424 /* ffqr.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9882 { 4431 /* ffqr.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9883 { 4438 /* fill.b */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, 9884 { 4438 /* fill.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9885 { 4445 /* fill.d */, 2 /* 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 }, 9886 { 4445 /* fill.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 }, 9887 { 4452 /* fill.h */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, 9888 { 4452 /* fill.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9889 { 4459 /* fill.w */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, 9890 { 4459 /* fill.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9891 { 4466 /* flog2.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9892 { 4474 /* flog2.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9893 { 4482 /* floor.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips }, 9894 { 4482 /* floor.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9895 { 4492 /* floor.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 9896 { 4492 /* floor.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 9897 { 4492 /* floor.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9898 { 4492 /* floor.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9899 { 4502 /* floor.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 9900 { 4502 /* floor.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 9901 { 4502 /* floor.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9902 { 4502 /* floor.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9903 { 4502 /* floor.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 9904 { 4502 /* floor.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 9905 { 4502 /* floor.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 9906 { 4502 /* floor.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 9907 { 4512 /* floor.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips }, 9908 { 4512 /* floor.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 9909 { 4512 /* floor.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, 9910 { 4522 /* fmadd.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9911 { 4530 /* fmadd.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9912 { 4538 /* fmax.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9913 { 4545 /* fmax.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9914 { 4552 /* fmax_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9915 { 4561 /* fmax_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9916 { 4570 /* fmin.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9917 { 4577 /* fmin.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9918 { 4584 /* fmin_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9919 { 4593 /* fmin_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9920 { 4602 /* fmsub.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9921 { 4610 /* fmsub.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9922 { 4618 /* fmul.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9923 { 4625 /* fmul.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9924 { 4632 /* fork */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips }, 9925 { 4637 /* frcp.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9926 { 4644 /* frcp.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9927 { 4651 /* frint.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9928 { 4659 /* frint.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9929 { 4667 /* frsqrt.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9930 { 4676 /* frsqrt.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9931 { 4685 /* fsaf.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9932 { 4692 /* fsaf.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9933 { 4699 /* fseq.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9934 { 4706 /* fseq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9935 { 4713 /* fsle.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9936 { 4720 /* fsle.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9937 { 4727 /* fslt.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9938 { 4734 /* fslt.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9939 { 4741 /* fsne.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9940 { 4748 /* fsne.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9941 { 4755 /* fsor.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9942 { 4762 /* fsor.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9943 { 4769 /* fsqrt.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9944 { 4777 /* fsqrt.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9945 { 4785 /* fsub.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9946 { 4792 /* fsub.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9947 { 4799 /* fsueq.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9948 { 4807 /* fsueq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9949 { 4815 /* fsule.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9950 { 4823 /* fsule.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9951 { 4831 /* fsult.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9952 { 4839 /* fsult.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9953 { 4847 /* fsun.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9954 { 4854 /* fsun.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9955 { 4861 /* fsune.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9956 { 4869 /* fsune.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9957 { 4877 /* ftint_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9958 { 4887 /* ftint_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9959 { 4897 /* ftint_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9960 { 4907 /* ftint_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9961 { 4917 /* ftq.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9962 { 4923 /* ftq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9963 { 4929 /* ftrunc_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9964 { 4940 /* ftrunc_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9965 { 4951 /* ftrunc_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9966 { 4962 /* ftrunc_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9967 { 4973 /* ginvi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips }, 9968 { 4973 /* ginvi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6_HasGINV }, 9969 { 4979 /* ginvt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips }, 9970 { 4979 /* ginvt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6_HasGINV }, 9971 { 4985 /* hadd_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9972 { 4994 /* hadd_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9973 { 5003 /* hadd_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9974 { 5012 /* hadd_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9975 { 5021 /* hadd_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9976 { 5030 /* hadd_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9977 { 5039 /* hsub_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9978 { 5048 /* hsub_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9979 { 5057 /* hsub_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9980 { 5066 /* hsub_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9981 { 5075 /* hsub_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9982 { 5084 /* hsub_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9983 { 5101 /* ilvev.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9984 { 5109 /* ilvev.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9985 { 5117 /* ilvev.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9986 { 5125 /* ilvev.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9987 { 5133 /* ilvl.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9988 { 5140 /* ilvl.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9989 { 5147 /* ilvl.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9990 { 5154 /* ilvl.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9991 { 5161 /* ilvod.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9992 { 5169 /* ilvod.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9993 { 5177 /* ilvod.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9994 { 5185 /* ilvod.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9995 { 5193 /* ilvr.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9996 { 5200 /* ilvr.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9997 { 5207 /* ilvr.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9998 { 5214 /* ilvr.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 9999 { 5221 /* ins */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, 10000 { 5221 /* ins */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10001 { 5221 /* ins */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10002 { 5225 /* insert.b */, 16 /* 4 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, 10003 { 5225 /* insert.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10004 { 5234 /* insert.d */, 16 /* 4 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 }, 10005 { 5234 /* insert.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 }, 10006 { 5243 /* insert.h */, 16 /* 4 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, 10007 { 5243 /* insert.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10008 { 5252 /* insert.w */, 16 /* 4 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, 10009 { 5252 /* insert.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10010 { 5261 /* insv */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10011 { 5261 /* insv */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10012 { 5266 /* insve.b */, 17 /* 0, 4 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10013 { 5274 /* insve.d */, 17 /* 0, 4 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10014 { 5282 /* insve.h */, 17 /* 0, 4 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10015 { 5290 /* insve.w */, 17 /* 0, 4 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10016 { 5298 /* j */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10017 { 5298 /* j */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10018 { 5298 /* j */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, 10019 { 5300 /* jal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, 10020 { 5300 /* jal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, 10021 { 5300 /* jal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 10022 { 5300 /* jal */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, 10023 { 5304 /* jalr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10024 { 5304 /* jalr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10025 { 5304 /* jalr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips }, 10026 { 5304 /* jalr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards }, 10027 { 5304 /* jalr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10028 { 5304 /* jalr */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_NotInMips16Mode_IsPTR64bit }, 10029 { 5309 /* jalr.hb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotInMicroMips }, 10030 { 5309 /* jalr.hb */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64_NotInMicroMips }, 10031 { 5309 /* jalr.hb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32 }, 10032 { 5309 /* jalr.hb */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, 10033 { 5317 /* jalrc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips }, 10034 { 5317 /* jalrc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10035 { 5317 /* jalrc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6 }, 10036 { 5317 /* jalrc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10037 { 5323 /* jalrc.hb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10038 { 5323 /* jalrc.hb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10039 { 5332 /* jalrs */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10040 { 5338 /* jalrs16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10041 { 5351 /* jalx */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips }, 10042 { 5351 /* jalx */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, 10043 { 5356 /* jialc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, 10044 { 5356 /* jialc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6 }, 10045 { 5356 /* jialc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10046 { 5356 /* jialc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 10047 { 5356 /* jialc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, 10048 { 5356 /* jialc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, 10049 { 5362 /* jic */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, 10050 { 5362 /* jic */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6 }, 10051 { 5362 /* jic */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10052 { 5362 /* jic */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, 10053 { 5362 /* jic */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, 10054 { 5362 /* jic */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, 10055 { 5366 /* jr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 10056 { 5366 /* jr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips }, 10057 { 5366 /* jr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10058 { 5366 /* jr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips }, 10059 { 5366 /* jr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6 }, 10060 { 5369 /* jr.hb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6 }, 10061 { 5369 /* jr.hb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, 10062 { 5369 /* jr.hb */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips }, 10063 { 5369 /* jr.hb */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, 10064 { 5375 /* jr16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10065 { 5390 /* jrc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6 }, 10066 { 5390 /* jrc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10067 { 5390 /* jrc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6 }, 10068 { 5394 /* jrc16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10069 { 5411 /* l.d */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat }, 10070 { 5411 /* l.d */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat }, 10071 { 5411 /* l.d */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat }, 10072 { 5411 /* l.d */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat }, 10073 { 5415 /* l.s */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat }, 10074 { 5415 /* l.s */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat }, 10075 { 5419 /* la */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, 10076 { 5419 /* la */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, 10077 { 5419 /* la */, 2 /* 1 */, MCK_Mem, AMFBS_None }, 10078 { 5422 /* lapc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, 10079 { 5422 /* lapc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10080 { 5427 /* lb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10081 { 5427 /* lb */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_NotInMicroMips }, 10082 { 5427 /* lb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10083 { 5427 /* lb */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_HasMips32r6 }, 10084 { 5427 /* lb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 10085 { 5427 /* lb */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips }, 10086 { 5430 /* lbe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 10087 { 5430 /* lbe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 10088 { 5430 /* lbe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA }, 10089 { 5430 /* lbe */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasEVA }, 10090 { 5434 /* lbu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10091 { 5434 /* lbu */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_NotInMicroMips }, 10092 { 5434 /* lbu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10093 { 5434 /* lbu */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_HasMips32r6 }, 10094 { 5434 /* lbu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 10095 { 5434 /* lbu */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips }, 10096 { 5438 /* lbu16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips }, 10097 { 5438 /* lbu16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips }, 10098 { 5444 /* lbue */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 10099 { 5444 /* lbue */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 10100 { 5444 /* lbue */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA }, 10101 { 5444 /* lbue */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasEVA }, 10102 { 5449 /* lbux */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10103 { 5449 /* lbux */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10104 { 5454 /* ld */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips3 }, 10105 { 5454 /* ld */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotMips3 }, 10106 { 5454 /* ld */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 10107 { 5454 /* ld */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 10108 { 5457 /* ld.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10109 { 5457 /* ld.b */, 2 /* 1 */, MCK_MemOffsetSimm10_0, AMFBS_HasStdEnc_HasMSA }, 10110 { 5462 /* ld.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10111 { 5462 /* ld.d */, 2 /* 1 */, MCK_MemOffsetSimm10_3, AMFBS_HasStdEnc_HasMSA }, 10112 { 5467 /* ld.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10113 { 5467 /* ld.h */, 2 /* 1 */, MCK_MemOffsetSimm10_1, AMFBS_HasStdEnc_HasMSA }, 10114 { 5472 /* ld.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10115 { 5472 /* ld.w */, 2 /* 1 */, MCK_MemOffsetSimm10_2, AMFBS_HasStdEnc_HasMSA }, 10116 { 5477 /* ldc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 10117 { 5477 /* ldc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 10118 { 5477 /* ldc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 10119 { 5477 /* ldc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 10120 { 5477 /* ldc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 10121 { 5477 /* ldc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 10122 { 5477 /* ldc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat }, 10123 { 5477 /* ldc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat }, 10124 { 5482 /* ldc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 10125 { 5482 /* ldc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 10126 { 5482 /* ldc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10127 { 5482 /* ldc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_InMicroMips_HasMips32r6 }, 10128 { 5482 /* ldc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 10129 { 5482 /* ldc2 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 10130 { 5487 /* ldc3 */, 1 /* 0 */, MCK_COP3AsmReg, AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips }, 10131 { 5487 /* ldc3 */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips }, 10132 { 5492 /* ldi.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10133 { 5498 /* ldi.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10134 { 5504 /* ldi.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10135 { 5510 /* ldi.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10136 { 5516 /* ldl */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, 10137 { 5516 /* ldl */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, 10138 { 5520 /* ldpc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6 }, 10139 { 5520 /* ldpc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips64r6 }, 10140 { 5525 /* ldr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, 10141 { 5525 /* ldr */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, 10142 { 5529 /* ldxc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10143 { 5529 /* ldxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10144 { 5529 /* ldxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat }, 10145 { 5529 /* ldxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat }, 10146 { 5535 /* lh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10147 { 5535 /* lh */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_NotInMicroMips }, 10148 { 5535 /* lh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 10149 { 5535 /* lh */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_InMicroMips }, 10150 { 5538 /* lhe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 10151 { 5538 /* lhe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 10152 { 5538 /* lhe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA }, 10153 { 5538 /* lhe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA }, 10154 { 5542 /* lhu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10155 { 5542 /* lhu */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_NotInMicroMips }, 10156 { 5542 /* lhu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 10157 { 5542 /* lhu */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_InMicroMips }, 10158 { 5546 /* lhu16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips }, 10159 { 5546 /* lhu16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips }, 10160 { 5552 /* lhue */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 10161 { 5552 /* lhue */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 10162 { 5552 /* lhue */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA }, 10163 { 5552 /* lhue */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA }, 10164 { 5557 /* lhx */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10165 { 5557 /* lhx */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10166 { 5561 /* li */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, 10167 { 5564 /* li.d */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, 10168 { 5564 /* li.d */, 1 /* 0 */, MCK_StrictlyAFGR64AsmReg, AMFBS_NotFP64bit_IsNotSoftFloat }, 10169 { 5564 /* li.d */, 1 /* 0 */, MCK_StrictlyFGR64AsmReg, AMFBS_IsFP64bit_IsNotSoftFloat }, 10170 { 5569 /* li.s */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, 10171 { 5569 /* li.s */, 1 /* 0 */, MCK_StrictlyFGR32AsmReg, AMFBS_IsNotSoftFloat }, 10172 { 5574 /* li16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10173 { 5574 /* li16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10174 { 5579 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips }, 10175 { 5579 /* ll */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips }, 10176 { 5579 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips }, 10177 { 5579 /* ll */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips }, 10178 { 5579 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10179 { 5579 /* ll */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasMips32r6 }, 10180 { 5579 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 10181 { 5579 /* ll */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 10182 { 5579 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 10183 { 5579 /* ll */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 10184 { 5579 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10185 { 5579 /* ll */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 }, 10186 { 5582 /* lld */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, 10187 { 5582 /* lld */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, 10188 { 5582 /* lld */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, 10189 { 5582 /* lld */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, 10190 { 5586 /* lle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 10191 { 5586 /* lle */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 10192 { 5586 /* lle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA }, 10193 { 5586 /* lle */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA }, 10194 { 5590 /* lsa */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, 10195 { 5590 /* lsa */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10196 { 5590 /* lsa */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, 10197 { 5594 /* lui */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10198 { 5594 /* lui */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10199 { 5594 /* lui */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10200 { 5598 /* luxc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10201 { 5598 /* luxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10202 { 5598 /* luxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10203 { 5598 /* luxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10204 { 5598 /* luxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 10205 { 5598 /* luxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 10206 { 5604 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 10207 { 5604 /* lw */, 2 /* 1 */, MCK_MicroMipsMemSP, AMFBS_InMicroMips }, 10208 { 5604 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10209 { 5604 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotInMicroMips }, 10210 { 5604 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_NotInMips16Mode_HasDSP }, 10211 { 5604 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_NotInMips16Mode_HasDSP }, 10212 { 5604 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10213 { 5604 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasDSP }, 10214 { 5604 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10215 { 5604 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 }, 10216 { 5604 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 10217 { 5604 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips }, 10218 { 5604 /* lw */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips }, 10219 { 5604 /* lw */, 2 /* 1 */, MCK_MicroMipsMemGP, AMFBS_InMicroMips }, 10220 { 5607 /* lw16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips }, 10221 { 5607 /* lw16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips }, 10222 { 5612 /* lwc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, 10223 { 5612 /* lwc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, 10224 { 5612 /* lwc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, 10225 { 5612 /* lwc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_IsNotSoftFloat }, 10226 { 5617 /* lwc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 10227 { 5617 /* lwc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 10228 { 5617 /* lwc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10229 { 5617 /* lwc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_InMicroMips_HasMips32r6 }, 10230 { 5617 /* lwc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 10231 { 5617 /* lwc2 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 10232 { 5622 /* lwc3 */, 1 /* 0 */, MCK_COP3AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips }, 10233 { 5622 /* lwc3 */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips }, 10234 { 5627 /* lwe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 10235 { 5627 /* lwe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 10236 { 5627 /* lwe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA }, 10237 { 5627 /* lwe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA }, 10238 { 5631 /* lwl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 10239 { 5631 /* lwl */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 10240 { 5631 /* lwl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10241 { 5631 /* lwl */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 }, 10242 { 5635 /* lwle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips }, 10243 { 5635 /* lwle */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips }, 10244 { 5635 /* lwle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_HasEVA }, 10245 { 5635 /* lwle */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_NotMips32r6_HasEVA }, 10246 { 5640 /* lwm */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips }, 10247 { 5640 /* lwm */, 1 /* 0 */, MCK_RegList, AMFBS_InMicroMips }, 10248 { 5644 /* lwm16 */, 2 /* 1 */, MCK_MemOffsetUimm4, AMFBS_InMicroMips_NotMips32r6 }, 10249 { 5644 /* lwm16 */, 1 /* 0 */, MCK_RegList16, AMFBS_InMicroMips_NotMips32r6 }, 10250 { 5644 /* lwm16 */, 2 /* 1 */, MCK_MemOffsetUimm4, AMFBS_InMicroMips_HasMips32r6 }, 10251 { 5644 /* lwm16 */, 1 /* 0 */, MCK_RegList16, AMFBS_InMicroMips_HasMips32r6 }, 10252 { 5650 /* lwm32 */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips }, 10253 { 5650 /* lwm32 */, 1 /* 0 */, MCK_RegList, AMFBS_InMicroMips }, 10254 { 5656 /* lwp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 10255 { 5656 /* lwp */, 2 /* 1 */, MCK_MemOffsetSimm12_0, AMFBS_InMicroMips }, 10256 { 5660 /* lwpc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, 10257 { 5660 /* lwpc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10258 { 5665 /* lwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 10259 { 5665 /* lwr */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 10260 { 5665 /* lwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10261 { 5665 /* lwr */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 }, 10262 { 5669 /* lwre */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips }, 10263 { 5669 /* lwre */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips }, 10264 { 5669 /* lwre */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_HasEVA }, 10265 { 5669 /* lwre */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_NotMips32r6_HasEVA }, 10266 { 5674 /* lwu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10267 { 5674 /* lwu */, 2 /* 1 */, MCK_MemOffsetSimm12_0, AMFBS_InMicroMips_NotMips32r6 }, 10268 { 5674 /* lwu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 10269 { 5674 /* lwu */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 10270 { 5678 /* lwupc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64r6 }, 10271 { 5684 /* lwx */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10272 { 5684 /* lwx */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10273 { 5688 /* lwxc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat }, 10274 { 5688 /* lwxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat }, 10275 { 5688 /* lwxc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 10276 { 5688 /* lwxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 10277 { 5694 /* lwxs */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 10278 { 5699 /* madd */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips }, 10279 { 5699 /* madd */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10280 { 5699 /* madd */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 10281 { 5699 /* madd */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10282 { 5699 /* madd */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 10283 { 5699 /* madd */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10284 { 5704 /* madd.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 }, 10285 { 5704 /* madd.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4 }, 10286 { 5704 /* madd.d */, 15 /* 0, 1, 2, 3 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 }, 10287 { 5711 /* madd.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 }, 10288 { 5711 /* madd.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4 }, 10289 { 5718 /* madd_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10290 { 5727 /* madd_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10291 { 5736 /* maddf.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 10292 { 5736 /* maddf.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 10293 { 5744 /* maddf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 10294 { 5744 /* maddf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 10295 { 5752 /* maddr_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10296 { 5762 /* maddr_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10297 { 5772 /* maddu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips }, 10298 { 5772 /* maddu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10299 { 5772 /* maddu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 10300 { 5772 /* maddu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10301 { 5772 /* maddu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 10302 { 5772 /* maddu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10303 { 5778 /* maddv.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10304 { 5786 /* maddv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10305 { 5794 /* maddv.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10306 { 5802 /* maddv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10307 { 5810 /* maq_s.w.phl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 10308 { 5810 /* maq_s.w.phl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10309 { 5810 /* maq_s.w.phl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 10310 { 5810 /* maq_s.w.phl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10311 { 5822 /* maq_s.w.phr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 10312 { 5822 /* maq_s.w.phr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10313 { 5822 /* maq_s.w.phr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 10314 { 5822 /* maq_s.w.phr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10315 { 5834 /* maq_sa.w.phl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 10316 { 5834 /* maq_sa.w.phl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10317 { 5834 /* maq_sa.w.phl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 10318 { 5834 /* maq_sa.w.phl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10319 { 5847 /* maq_sa.w.phr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 10320 { 5847 /* maq_sa.w.phr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10321 { 5847 /* maq_sa.w.phr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 10322 { 5847 /* maq_sa.w.phr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10323 { 5860 /* max.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 10324 { 5860 /* max.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 10325 { 5866 /* max.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 10326 { 5866 /* max.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 10327 { 5872 /* max_a.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10328 { 5880 /* max_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10329 { 5888 /* max_a.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10330 { 5896 /* max_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10331 { 5904 /* max_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10332 { 5912 /* max_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10333 { 5920 /* max_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10334 { 5928 /* max_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10335 { 5936 /* max_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10336 { 5944 /* max_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10337 { 5952 /* max_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10338 { 5960 /* max_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10339 { 5968 /* maxa.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 10340 { 5968 /* maxa.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 10341 { 5975 /* maxa.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 10342 { 5975 /* maxa.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 10343 { 5982 /* maxi_s.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10344 { 5991 /* maxi_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10345 { 6000 /* maxi_s.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10346 { 6009 /* maxi_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10347 { 6018 /* maxi_u.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10348 { 6027 /* maxi_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10349 { 6036 /* maxi_u.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10350 { 6045 /* maxi_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10351 { 6054 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10352 { 6054 /* mfc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10353 { 6054 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10354 { 6054 /* mfc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10355 { 6054 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10356 { 6054 /* mfc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10357 { 6054 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10358 { 6054 /* mfc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10359 { 6059 /* mfc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, 10360 { 6059 /* mfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, 10361 { 6059 /* mfc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 10362 { 6059 /* mfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 10363 { 6059 /* mfc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, 10364 { 6059 /* mfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, 10365 { 6059 /* mfc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, 10366 { 6059 /* mfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, 10367 { 6064 /* mfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10368 { 6064 /* mfc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10369 { 6064 /* mfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10370 { 6064 /* mfc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10371 { 6064 /* mfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10372 { 6064 /* mfc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10373 { 6069 /* mfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, 10374 { 6069 /* mfgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, 10375 { 6069 /* mfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, 10376 { 6069 /* mfgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, 10377 { 6069 /* mfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, 10378 { 6069 /* mfgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, 10379 { 6069 /* mfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, 10380 { 6069 /* mfgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, 10381 { 6075 /* mfhc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10382 { 6075 /* mfhc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10383 { 6075 /* mfhc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10384 { 6075 /* mfhc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10385 { 6081 /* mfhc1 */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips }, 10386 { 6081 /* mfhc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips }, 10387 { 6081 /* mfhc1 */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 10388 { 6081 /* mfhc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 10389 { 6081 /* mfhc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips }, 10390 { 6081 /* mfhc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips }, 10391 { 6081 /* mfhc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, 10392 { 6081 /* mfhc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, 10393 { 6087 /* mfhc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10394 { 6087 /* mfhc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10395 { 6093 /* mfhgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, 10396 { 6093 /* mfhgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, 10397 { 6093 /* mfhgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, 10398 { 6093 /* mfhgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, 10399 { 6093 /* mfhgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, 10400 { 6093 /* mfhgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, 10401 { 6093 /* mfhgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, 10402 { 6093 /* mfhgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, 10403 { 6100 /* mfhi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 10404 { 6100 /* mfhi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10405 { 6100 /* mfhi */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 10406 { 6100 /* mfhi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10407 { 6100 /* mfhi */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 10408 { 6100 /* mfhi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10409 { 6105 /* mfhi16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10410 { 6112 /* mflo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 10411 { 6112 /* mflo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10412 { 6112 /* mflo */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 10413 { 6112 /* mflo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10414 { 6112 /* mflo */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 10415 { 6112 /* mflo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10416 { 6117 /* mflo16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10417 { 6124 /* mftacx */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips }, 10418 { 6124 /* mftacx */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT }, 10419 { 6124 /* mftacx */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, 10420 { 6131 /* mftc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasMT_NotInMicroMips }, 10421 { 6131 /* mftc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips }, 10422 { 6131 /* mftc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasMT }, 10423 { 6131 /* mftc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, 10424 { 6137 /* mftc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT }, 10425 { 6137 /* mftc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, 10426 { 6143 /* mftdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, 10427 { 6150 /* mftgpr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasMT }, 10428 { 6157 /* mfthc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT }, 10429 { 6157 /* mfthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, 10430 { 6164 /* mfthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips }, 10431 { 6164 /* mfthi */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT }, 10432 { 6164 /* mfthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, 10433 { 6170 /* mftlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips }, 10434 { 6170 /* mftlo */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT }, 10435 { 6170 /* mftlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, 10436 { 6176 /* mftr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips }, 10437 { 6181 /* min.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 10438 { 6181 /* min.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 10439 { 6187 /* min.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 10440 { 6187 /* min.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 10441 { 6193 /* min_a.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10442 { 6201 /* min_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10443 { 6209 /* min_a.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10444 { 6217 /* min_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10445 { 6225 /* min_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10446 { 6233 /* min_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10447 { 6241 /* min_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10448 { 6249 /* min_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10449 { 6257 /* min_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10450 { 6265 /* min_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10451 { 6273 /* min_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10452 { 6281 /* min_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10453 { 6289 /* mina.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 10454 { 6289 /* mina.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 10455 { 6296 /* mina.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 10456 { 6296 /* mina.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 10457 { 6303 /* mini_s.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10458 { 6312 /* mini_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10459 { 6321 /* mini_s.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10460 { 6330 /* mini_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10461 { 6339 /* mini_u.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10462 { 6348 /* mini_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10463 { 6357 /* mini_u.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10464 { 6366 /* mini_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10465 { 6375 /* mod */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 10466 { 6375 /* mod */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10467 { 6379 /* mod_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10468 { 6387 /* mod_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10469 { 6395 /* mod_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10470 { 6403 /* mod_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10471 { 6411 /* mod_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10472 { 6419 /* mod_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10473 { 6427 /* mod_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10474 { 6435 /* mod_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10475 { 6443 /* modsub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10476 { 6443 /* modsub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10477 { 6450 /* modu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 10478 { 6450 /* modu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10479 { 6455 /* mov.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, 10480 { 6455 /* mov.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 10481 { 6455 /* mov.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, 10482 { 6455 /* mov.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, 10483 { 6455 /* mov.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 10484 { 6461 /* mov.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, 10485 { 6461 /* mov.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 10486 { 6461 /* mov.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, 10487 { 6467 /* move */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, 10488 { 6467 /* move */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, 10489 { 6467 /* move */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10490 { 6467 /* move */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit_NotInMicroMips }, 10491 { 6467 /* move */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit_NotInMicroMips }, 10492 { 6472 /* move.v */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10493 { 6479 /* move16 */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10494 { 6486 /* movep */, 12 /* 2, 3 */, MCK_GPRMM16AsmRegMoveP, AMFBS_InMicroMips_NotMips32r6 }, 10495 { 6486 /* movep */, 1 /* 0 */, MCK_GPRMM16AsmRegMovePPairFirst, AMFBS_InMicroMips_NotMips32r6 }, 10496 { 6486 /* movep */, 2 /* 1 */, MCK_GPRMM16AsmRegMovePPairSecond, AMFBS_InMicroMips_NotMips32r6 }, 10497 { 6486 /* movep */, 12 /* 2, 3 */, MCK_GPRMM16AsmRegMoveP, AMFBS_InMicroMips_HasMips32r6 }, 10498 { 6486 /* movep */, 1 /* 0 */, MCK_GPRMM16AsmRegMovePPairFirst, AMFBS_InMicroMips_HasMips32r6 }, 10499 { 6486 /* movep */, 2 /* 1 */, MCK_GPRMM16AsmRegMovePPairSecond, AMFBS_InMicroMips_HasMips32r6 }, 10500 { 6492 /* movf */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10501 { 6492 /* movf */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10502 { 6492 /* movf */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 10503 { 6492 /* movf */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 10504 { 6497 /* movf.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10505 { 6497 /* movf.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10506 { 6497 /* movf.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 10507 { 6497 /* movf.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 10508 { 6497 /* movf.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10509 { 6497 /* movf.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10510 { 6504 /* movf.s */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10511 { 6504 /* movf.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10512 { 6504 /* movf.s */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 10513 { 6504 /* movf.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 10514 { 6511 /* movn */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips }, 10515 { 6511 /* movn */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10516 { 6516 /* movn.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10517 { 6516 /* movn.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10518 { 6516 /* movn.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 10519 { 6516 /* movn.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 10520 { 6516 /* movn.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10521 { 6516 /* movn.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10522 { 6523 /* movn.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10523 { 6523 /* movn.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10524 { 6523 /* movn.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 10525 { 6523 /* movn.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 10526 { 6530 /* movt */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10527 { 6530 /* movt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10528 { 6530 /* movt */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 10529 { 6530 /* movt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 10530 { 6535 /* movt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10531 { 6535 /* movt.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10532 { 6535 /* movt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 10533 { 6535 /* movt.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 10534 { 6535 /* movt.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10535 { 6535 /* movt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10536 { 6542 /* movt.s */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10537 { 6542 /* movt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10538 { 6542 /* movt.s */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 10539 { 6542 /* movt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 10540 { 6549 /* movz */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips }, 10541 { 6549 /* movz */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10542 { 6554 /* movz.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10543 { 6554 /* movz.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10544 { 6554 /* movz.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 10545 { 6554 /* movz.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, 10546 { 6554 /* movz.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10547 { 6554 /* movz.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10548 { 6561 /* movz.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10549 { 6561 /* movz.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10550 { 6561 /* movz.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 10551 { 6561 /* movz.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 10552 { 6568 /* msub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips }, 10553 { 6568 /* msub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10554 { 6568 /* msub */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 10555 { 6568 /* msub */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10556 { 6568 /* msub */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 10557 { 6568 /* msub */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10558 { 6573 /* msub.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 }, 10559 { 6573 /* msub.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4 }, 10560 { 6573 /* msub.d */, 15 /* 0, 1, 2, 3 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 }, 10561 { 6580 /* msub.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 }, 10562 { 6580 /* msub.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4 }, 10563 { 6587 /* msub_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10564 { 6596 /* msub_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10565 { 6605 /* msubf.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 10566 { 6605 /* msubf.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 10567 { 6613 /* msubf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 10568 { 6613 /* msubf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 10569 { 6621 /* msubr_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10570 { 6631 /* msubr_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10571 { 6641 /* msubu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips }, 10572 { 6641 /* msubu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10573 { 6641 /* msubu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 10574 { 6641 /* msubu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10575 { 6641 /* msubu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 10576 { 6641 /* msubu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10577 { 6647 /* msubv.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10578 { 6655 /* msubv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10579 { 6663 /* msubv.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10580 { 6671 /* msubv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10581 { 6679 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10582 { 6679 /* mtc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10583 { 6679 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10584 { 6679 /* mtc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10585 { 6679 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10586 { 6679 /* mtc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10587 { 6679 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10588 { 6679 /* mtc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10589 { 6684 /* mtc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, 10590 { 6684 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, 10591 { 6684 /* mtc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 10592 { 6684 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 10593 { 6684 /* mtc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, 10594 { 6684 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, 10595 { 6684 /* mtc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, 10596 { 6684 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, 10597 { 6684 /* mtc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, 10598 { 6684 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, 10599 { 6689 /* mtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10600 { 6689 /* mtc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10601 { 6689 /* mtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10602 { 6689 /* mtc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10603 { 6689 /* mtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10604 { 6689 /* mtc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10605 { 6694 /* mtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, 10606 { 6694 /* mtgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, 10607 { 6694 /* mtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, 10608 { 6694 /* mtgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, 10609 { 6694 /* mtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, 10610 { 6694 /* mtgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, 10611 { 6694 /* mtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, 10612 { 6694 /* mtgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, 10613 { 6700 /* mthc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10614 { 6700 /* mthc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10615 { 6700 /* mthc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10616 { 6700 /* mthc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10617 { 6706 /* mthc1 */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips }, 10618 { 6706 /* mthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips }, 10619 { 6706 /* mthc1 */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 10620 { 6706 /* mthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 10621 { 6706 /* mthc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips }, 10622 { 6706 /* mthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips }, 10623 { 6706 /* mthc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, 10624 { 6706 /* mthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, 10625 { 6712 /* mthc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10626 { 6712 /* mthc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10627 { 6718 /* mthgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, 10628 { 6718 /* mthgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, 10629 { 6718 /* mthgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, 10630 { 6718 /* mthgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, 10631 { 6718 /* mthgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, 10632 { 6718 /* mthgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, 10633 { 6718 /* mthgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, 10634 { 6718 /* mthgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, 10635 { 6725 /* mthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 10636 { 6725 /* mthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10637 { 6725 /* mthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10638 { 6725 /* mthi */, 2 /* 1 */, MCK_HI32DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 10639 { 6725 /* mthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10640 { 6725 /* mthi */, 2 /* 1 */, MCK_HI32DSPAsmReg, AMFBS_HasDSP }, 10641 { 6730 /* mthlip */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 10642 { 6730 /* mthlip */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10643 { 6730 /* mthlip */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 10644 { 6730 /* mthlip */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10645 { 6737 /* mtlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 10646 { 6737 /* mtlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10647 { 6737 /* mtlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10648 { 6737 /* mtlo */, 2 /* 1 */, MCK_LO32DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 10649 { 6737 /* mtlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10650 { 6737 /* mtlo */, 2 /* 1 */, MCK_LO32DSPAsmReg, AMFBS_HasDSP }, 10651 { 6742 /* mtm0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 10652 { 6747 /* mtm1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 10653 { 6752 /* mtm2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 10654 { 6757 /* mtp0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 10655 { 6762 /* mtp1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 10656 { 6767 /* mtp2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 10657 { 6772 /* mttacx */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips }, 10658 { 6772 /* mttacx */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT }, 10659 { 6772 /* mttacx */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, 10660 { 6779 /* mttc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasMT_NotInMicroMips }, 10661 { 6779 /* mttc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips }, 10662 { 6779 /* mttc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasMT }, 10663 { 6779 /* mttc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, 10664 { 6785 /* mttc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT }, 10665 { 6785 /* mttc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, 10666 { 6791 /* mttdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, 10667 { 6798 /* mttgpr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasMT }, 10668 { 6805 /* mtthc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT }, 10669 { 6805 /* mtthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, 10670 { 6812 /* mtthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips }, 10671 { 6812 /* mtthi */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT }, 10672 { 6812 /* mtthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, 10673 { 6818 /* mttlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips }, 10674 { 6818 /* mttlo */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT }, 10675 { 6818 /* mttlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, 10676 { 6824 /* mttr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips }, 10677 { 6829 /* muh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10678 { 6829 /* muh */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 10679 { 6829 /* muh */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10680 { 6833 /* muhu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10681 { 6833 /* muhu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 10682 { 6833 /* muhu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10683 { 6838 /* mul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips }, 10684 { 6838 /* mul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10685 { 6838 /* mul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10686 { 6838 /* mul */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips }, 10687 { 6838 /* mul */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 10688 { 6838 /* mul */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10689 { 6838 /* mul */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10690 { 6838 /* mul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 10691 { 6842 /* mul.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, 10692 { 6842 /* mul.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 10693 { 6842 /* mul.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, 10694 { 6842 /* mul.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, 10695 { 6848 /* mul.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 10696 { 6848 /* mul.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 10697 { 6855 /* mul.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, 10698 { 6855 /* mul.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 10699 { 6855 /* mul.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, 10700 { 6861 /* mul_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10701 { 6869 /* mul_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10702 { 6877 /* mul_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 10703 { 6877 /* mul_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 10704 { 6886 /* muleq_s.w.phl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10705 { 6886 /* muleq_s.w.phl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10706 { 6900 /* muleq_s.w.phr */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10707 { 6900 /* muleq_s.w.phr */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10708 { 6914 /* muleu_s.ph.qbl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10709 { 6914 /* muleu_s.ph.qbl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10710 { 6929 /* muleu_s.ph.qbr */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10711 { 6929 /* muleu_s.ph.qbr */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10712 { 6944 /* mulo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 10713 { 6944 /* mulo */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 10714 { 6949 /* mulou */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 10715 { 6949 /* mulou */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 10716 { 6955 /* mulq_rs.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10717 { 6955 /* mulq_rs.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10718 { 6966 /* mulq_rs.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 10719 { 6966 /* mulq_rs.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 10720 { 6976 /* mulq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 10721 { 6976 /* mulq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 10722 { 6986 /* mulq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 10723 { 6986 /* mulq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 10724 { 6995 /* mulr_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10725 { 7004 /* mulr_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10726 { 7013 /* mulsa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 }, 10727 { 7013 /* mulsa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 10728 { 7013 /* mulsa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 }, 10729 { 7013 /* mulsa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 10730 { 7024 /* mulsaq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 10731 { 7024 /* mulsaq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10732 { 7024 /* mulsaq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 10733 { 7024 /* mulsaq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10734 { 7038 /* mult */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 10735 { 7038 /* mult */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10736 { 7038 /* mult */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 10737 { 7038 /* mult */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10738 { 7038 /* mult */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 10739 { 7038 /* mult */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10740 { 7043 /* multu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 10741 { 7043 /* multu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10742 { 7043 /* multu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 10743 { 7043 /* multu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10744 { 7043 /* multu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 10745 { 7043 /* multu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10746 { 7049 /* mulu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10747 { 7049 /* mulu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 10748 { 7049 /* mulu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10749 { 7054 /* mulv.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10750 { 7061 /* mulv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10751 { 7068 /* mulv.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10752 { 7075 /* mulv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10753 { 7082 /* neg */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10754 { 7082 /* neg */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10755 { 7082 /* neg */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10756 { 7082 /* neg */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10757 { 7082 /* neg */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10758 { 7082 /* neg */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10759 { 7086 /* neg.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, 10760 { 7086 /* neg.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 10761 { 7086 /* neg.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, 10762 { 7086 /* neg.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, 10763 { 7092 /* neg.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 10764 { 7092 /* neg.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat }, 10765 { 7092 /* neg.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, 10766 { 7098 /* negu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10767 { 7098 /* negu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10768 { 7098 /* negu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10769 { 7098 /* negu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10770 { 7098 /* negu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10771 { 7098 /* negu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10772 { 7103 /* nloc.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10773 { 7110 /* nloc.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10774 { 7117 /* nloc.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10775 { 7124 /* nloc.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10776 { 7131 /* nlzc.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10777 { 7138 /* nlzc.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10778 { 7145 /* nlzc.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10779 { 7152 /* nlzc.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10780 { 7159 /* nmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips }, 10781 { 7159 /* nmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4 }, 10782 { 7159 /* nmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips }, 10783 { 7167 /* nmadd.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips }, 10784 { 7167 /* nmadd.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4 }, 10785 { 7175 /* nmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips }, 10786 { 7175 /* nmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4 }, 10787 { 7175 /* nmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips }, 10788 { 7183 /* nmsub.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips }, 10789 { 7183 /* nmsub.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4 }, 10790 { 7195 /* nor */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit }, 10791 { 7195 /* nor */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, 10792 { 7195 /* nor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10793 { 7195 /* nor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10794 { 7195 /* nor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10795 { 7195 /* nor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit }, 10796 { 7195 /* nor */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, 10797 { 7199 /* nor.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10798 { 7205 /* nori.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10799 { 7212 /* not */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10800 { 7212 /* not */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10801 { 7212 /* not */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10802 { 7212 /* not */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10803 { 7212 /* not */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10804 { 7212 /* not */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10805 { 7216 /* not16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10806 { 7216 /* not16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10807 { 7222 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10808 { 7222 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10809 { 7222 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10810 { 7222 /* or */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10811 { 7222 /* or */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, 10812 { 7222 /* or */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 10813 { 7222 /* or */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips }, 10814 { 7222 /* or */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10815 { 7222 /* or */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10816 { 7222 /* or */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10817 { 7222 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10818 { 7222 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, 10819 { 7222 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 10820 { 7222 /* or */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips }, 10821 { 7225 /* or.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10822 { 7230 /* or16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10823 { 7230 /* or16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10824 { 7235 /* ori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10825 { 7235 /* ori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10826 { 7235 /* ori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10827 { 7235 /* ori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10828 { 7235 /* ori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10829 { 7235 /* ori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10830 { 7239 /* ori.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10831 { 7245 /* packrl.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10832 { 7245 /* packrl.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10833 { 7261 /* pckev.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10834 { 7269 /* pckev.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10835 { 7277 /* pckev.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10836 { 7285 /* pckev.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10837 { 7293 /* pckod.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10838 { 7301 /* pckod.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10839 { 7309 /* pckod.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10840 { 7317 /* pckod.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10841 { 7325 /* pcnt.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10842 { 7332 /* pcnt.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10843 { 7339 /* pcnt.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10844 { 7346 /* pcnt.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10845 { 7353 /* pick.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10846 { 7353 /* pick.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10847 { 7361 /* pick.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10848 { 7361 /* pick.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10849 { 7369 /* pll.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10850 { 7376 /* plu.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 10851 { 7383 /* pop */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasCnMips }, 10852 { 7383 /* pop */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasCnMips }, 10853 { 7387 /* preceq.w.phl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10854 { 7387 /* preceq.w.phl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10855 { 7400 /* preceq.w.phr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10856 { 7400 /* preceq.w.phr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10857 { 7413 /* precequ.ph.qbl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10858 { 7413 /* precequ.ph.qbl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10859 { 7428 /* precequ.ph.qbla */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10860 { 7428 /* precequ.ph.qbla */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10861 { 7444 /* precequ.ph.qbr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10862 { 7444 /* precequ.ph.qbr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10863 { 7459 /* precequ.ph.qbra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10864 { 7459 /* precequ.ph.qbra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10865 { 7475 /* preceu.ph.qbl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10866 { 7475 /* preceu.ph.qbl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10867 { 7489 /* preceu.ph.qbla */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10868 { 7489 /* preceu.ph.qbla */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10869 { 7504 /* preceu.ph.qbr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10870 { 7504 /* preceu.ph.qbr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10871 { 7518 /* preceu.ph.qbra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10872 { 7518 /* preceu.ph.qbra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10873 { 7533 /* precr.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 10874 { 7533 /* precr.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 10875 { 7545 /* precr_sra.ph.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 10876 { 7545 /* precr_sra.ph.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 10877 { 7560 /* precr_sra_r.ph.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 10878 { 7560 /* precr_sra_r.ph.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 10879 { 7577 /* precrq.ph.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10880 { 7577 /* precrq.ph.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10881 { 7589 /* precrq.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10882 { 7589 /* precrq.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10883 { 7602 /* precrq_rs.ph.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10884 { 7602 /* precrq_rs.ph.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10885 { 7617 /* precrqu_s.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10886 { 7617 /* precrqu_s.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10887 { 7633 /* pref */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 10888 { 7633 /* pref */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips }, 10889 { 7633 /* pref */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 }, 10890 { 7633 /* pref */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 }, 10891 { 7638 /* prefe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 10892 { 7638 /* prefe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA }, 10893 { 7644 /* prefx */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10894 { 7650 /* prepend */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 10895 { 7650 /* prepend */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 10896 { 7658 /* raddu.w.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10897 { 7658 /* raddu.w.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10898 { 7669 /* rddsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10899 { 7669 /* rddsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10900 { 7675 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10901 { 7675 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10902 { 7675 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10903 { 7675 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10904 { 7675 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10905 { 7675 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10906 { 7675 /* rdhwr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, 10907 { 7675 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_IsGP64bit }, 10908 { 7675 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10909 { 7675 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10910 { 7675 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10911 { 7675 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 10912 { 7675 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10913 { 7675 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_InMicroMips_NotMips32r6 }, 10914 { 7681 /* rdpgpr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10915 { 7688 /* recip.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips }, 10916 { 7688 /* recip.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 10917 { 7688 /* recip.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips }, 10918 { 7688 /* recip.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, 10919 { 7696 /* recip.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips }, 10920 { 7696 /* recip.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, 10921 { 7704 /* rem */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 10922 { 7704 /* rem */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 10923 { 7704 /* rem */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 10924 { 7704 /* rem */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 10925 { 7708 /* remu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 10926 { 7708 /* remu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 10927 { 7708 /* remu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 10928 { 7708 /* remu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 10929 { 7713 /* repl.ph */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10930 { 7713 /* repl.ph */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10931 { 7721 /* repl.qb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10932 { 7721 /* repl.qb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10933 { 7729 /* replv.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10934 { 7729 /* replv.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10935 { 7738 /* replv.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 10936 { 7738 /* replv.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 10937 { 7747 /* rint.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 10938 { 7747 /* rint.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10939 { 7754 /* rint.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 10940 { 7754 /* rint.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 10941 { 7761 /* rol */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, 10942 { 7761 /* rol */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, 10943 { 7761 /* rol */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_None }, 10944 { 7761 /* rol */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, 10945 { 7765 /* ror */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, 10946 { 7765 /* ror */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, 10947 { 7765 /* ror */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_None }, 10948 { 7765 /* ror */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, 10949 { 7769 /* rotr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, 10950 { 7769 /* rotr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 10951 { 7769 /* rotr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 10952 { 7769 /* rotr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, 10953 { 7769 /* rotr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 10954 { 7774 /* rotrv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, 10955 { 7774 /* rotrv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 10956 { 7780 /* round.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips }, 10957 { 7780 /* round.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 10958 { 7790 /* round.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 10959 { 7790 /* round.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 10960 { 7790 /* round.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 10961 { 7790 /* round.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 10962 { 7800 /* round.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 10963 { 7800 /* round.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 10964 { 7800 /* round.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 10965 { 7800 /* round.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 10966 { 7800 /* round.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 10967 { 7800 /* round.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 10968 { 7800 /* round.w.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 10969 { 7810 /* round.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips }, 10970 { 7810 /* round.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 10971 { 7810 /* round.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, 10972 { 7820 /* rsqrt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips }, 10973 { 7820 /* rsqrt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 10974 { 7820 /* rsqrt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips }, 10975 { 7820 /* rsqrt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, 10976 { 7828 /* rsqrt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips }, 10977 { 7828 /* rsqrt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, 10978 { 7836 /* s.d */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat }, 10979 { 7836 /* s.d */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat }, 10980 { 7836 /* s.d */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat }, 10981 { 7836 /* s.d */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat }, 10982 { 7836 /* s.d */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat }, 10983 { 7836 /* s.d */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat }, 10984 { 7836 /* s.d */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat }, 10985 { 7836 /* s.d */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat }, 10986 { 7840 /* s.s */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat }, 10987 { 7840 /* s.s */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat }, 10988 { 7844 /* saa */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMipsP }, 10989 { 7844 /* saa */, 2 /* 1 */, MCK_Mem, AMFBS_HasCnMipsP }, 10990 { 7844 /* saa */, 5 /* 0, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMipsP }, 10991 { 7848 /* saad */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMipsP }, 10992 { 7848 /* saad */, 2 /* 1 */, MCK_Mem, AMFBS_HasCnMipsP }, 10993 { 7848 /* saad */, 5 /* 0, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMipsP }, 10994 { 7853 /* sat_s.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10995 { 7861 /* sat_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10996 { 7869 /* sat_s.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10997 { 7877 /* sat_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10998 { 7885 /* sat_u.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 10999 { 7893 /* sat_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11000 { 7901 /* sat_u.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11001 { 7909 /* sat_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11002 { 7917 /* sb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11003 { 7917 /* sb */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotInMicroMips }, 11004 { 7917 /* sb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11005 { 7917 /* sb */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 }, 11006 { 7917 /* sb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11007 { 7917 /* sb */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips }, 11008 { 7920 /* sb16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_NotMips32r6 }, 11009 { 7920 /* sb16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_NotMips32r6 }, 11010 { 7920 /* sb16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_HasMips32r6 }, 11011 { 7920 /* sb16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_HasMips32r6 }, 11012 { 7925 /* sbe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 11013 { 7925 /* sbe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 11014 { 7925 /* sbe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA }, 11015 { 7925 /* sbe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA }, 11016 { 7929 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips }, 11017 { 7929 /* sc */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips }, 11018 { 7929 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips }, 11019 { 7929 /* sc */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips }, 11020 { 7929 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11021 { 7929 /* sc */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasMips32r6 }, 11022 { 7929 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 11023 { 7929 /* sc */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 11024 { 7929 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 11025 { 7929 /* sc */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 11026 { 7929 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 11027 { 7929 /* sc */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 }, 11028 { 7932 /* scd */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, 11029 { 7932 /* scd */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_HasMips32r6 }, 11030 { 7932 /* scd */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, 11031 { 7932 /* scd */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, 11032 { 7936 /* sce */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 11033 { 7936 /* sce */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 11034 { 7936 /* sce */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA }, 11035 { 7936 /* sce */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA }, 11036 { 7940 /* sd */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips3 }, 11037 { 7940 /* sd */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotMips3 }, 11038 { 7940 /* sd */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 11039 { 7940 /* sd */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 11040 { 7957 /* sdc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 11041 { 7957 /* sdc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 11042 { 7957 /* sdc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 11043 { 7957 /* sdc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 11044 { 7957 /* sdc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 11045 { 7957 /* sdc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 11046 { 7957 /* sdc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat }, 11047 { 7957 /* sdc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat }, 11048 { 7962 /* sdc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 11049 { 7962 /* sdc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 11050 { 7962 /* sdc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11051 { 7962 /* sdc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_InMicroMips_HasMips32r6 }, 11052 { 7962 /* sdc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 11053 { 7962 /* sdc2 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 11054 { 7967 /* sdc3 */, 1 /* 0 */, MCK_COP3AsmReg, AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips }, 11055 { 7967 /* sdc3 */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips }, 11056 { 7972 /* sdl */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, 11057 { 7972 /* sdl */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, 11058 { 7976 /* sdr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, 11059 { 7976 /* sdr */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, 11060 { 7980 /* sdxc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 11061 { 7980 /* sdxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 11062 { 7980 /* sdxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat }, 11063 { 7980 /* sdxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat }, 11064 { 7986 /* seb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, 11065 { 7986 /* seb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11066 { 7986 /* seb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, 11067 { 7986 /* seb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11068 { 7990 /* seh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, 11069 { 7990 /* seh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11070 { 7990 /* seh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, 11071 { 7990 /* seh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11072 { 7994 /* sel.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 11073 { 7994 /* sel.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11074 { 8000 /* sel.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 11075 { 8000 /* sel.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11076 { 8006 /* seleqz */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips }, 11077 { 8006 /* seleqz */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11078 { 8006 /* seleqz */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips32r6 }, 11079 { 8013 /* seleqz.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 11080 { 8013 /* seleqz.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11081 { 8022 /* seleqz.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 11082 { 8022 /* seleqz.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11083 { 8031 /* selnez */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips }, 11084 { 8031 /* selnez */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11085 { 8031 /* selnez */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips32r6 }, 11086 { 8038 /* selnez.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 11087 { 8038 /* selnez.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11088 { 8047 /* selnez.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, 11089 { 8047 /* selnez.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11090 { 8056 /* seq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotCnMips }, 11091 { 8056 /* seq */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_NotCnMips }, 11092 { 8056 /* seq */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 11093 { 8056 /* seq */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_NotCnMips }, 11094 { 8056 /* seq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotCnMips }, 11095 { 8056 /* seq */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 11096 { 8060 /* seqi */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 11097 { 8060 /* seqi */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 11098 { 8065 /* sge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11099 { 8065 /* sge */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips }, 11100 { 8065 /* sge */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, 11101 { 8065 /* sge */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11102 { 8065 /* sge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips }, 11103 { 8065 /* sge */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, 11104 { 8069 /* sgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11105 { 8069 /* sgeu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips }, 11106 { 8069 /* sgeu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, 11107 { 8069 /* sgeu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11108 { 8069 /* sgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips }, 11109 { 8069 /* sgeu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, 11110 { 8074 /* sgt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11111 { 8074 /* sgt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11112 { 8074 /* sgt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips }, 11113 { 8074 /* sgt */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, 11114 { 8074 /* sgt */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11115 { 8074 /* sgt */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11116 { 8074 /* sgt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips }, 11117 { 8074 /* sgt */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, 11118 { 8078 /* sgtu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11119 { 8078 /* sgtu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11120 { 8078 /* sgtu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips }, 11121 { 8078 /* sgtu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, 11122 { 8078 /* sgtu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11123 { 8078 /* sgtu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11124 { 8078 /* sgtu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips }, 11125 { 8078 /* sgtu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, 11126 { 8083 /* sh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11127 { 8083 /* sh */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotInMicroMips }, 11128 { 8083 /* sh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11129 { 8083 /* sh */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 }, 11130 { 8083 /* sh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11131 { 8083 /* sh */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips }, 11132 { 8086 /* sh16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_NotMips32r6 }, 11133 { 8086 /* sh16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_NotMips32r6 }, 11134 { 8086 /* sh16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_HasMips32r6 }, 11135 { 8086 /* sh16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_HasMips32r6 }, 11136 { 8091 /* she */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 11137 { 8091 /* she */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 11138 { 8091 /* she */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA }, 11139 { 8091 /* she */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA }, 11140 { 8095 /* shf.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11141 { 8101 /* shf.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11142 { 8107 /* shf.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11143 { 8113 /* shilo */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 11144 { 8113 /* shilo */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 11145 { 8119 /* shilov */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, 11146 { 8119 /* shilov */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 11147 { 8119 /* shilov */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, 11148 { 8119 /* shilov */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 11149 { 8126 /* shll.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 11150 { 8126 /* shll.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 11151 { 8134 /* shll.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 11152 { 8134 /* shll.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 11153 { 8142 /* shll_s.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 11154 { 8142 /* shll_s.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 11155 { 8152 /* shll_s.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 11156 { 8152 /* shll_s.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 11157 { 8161 /* shllv.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 11158 { 8161 /* shllv.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 11159 { 8170 /* shllv.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 11160 { 8170 /* shllv.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 11161 { 8179 /* shllv_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 11162 { 8179 /* shllv_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 11163 { 8190 /* shllv_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 11164 { 8190 /* shllv_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 11165 { 8200 /* shra.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 11166 { 8200 /* shra.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 11167 { 8208 /* shra.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 11168 { 8208 /* shra.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 11169 { 8216 /* shra_r.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 11170 { 8216 /* shra_r.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 11171 { 8226 /* shra_r.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 11172 { 8226 /* shra_r.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 11173 { 8236 /* shra_r.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 11174 { 8236 /* shra_r.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 11175 { 8245 /* shrav.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 11176 { 8245 /* shrav.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 11177 { 8254 /* shrav.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 11178 { 8254 /* shrav.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 11179 { 8263 /* shrav_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 11180 { 8263 /* shrav_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 11181 { 8274 /* shrav_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 11182 { 8274 /* shrav_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 11183 { 8285 /* shrav_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 11184 { 8285 /* shrav_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 11185 { 8295 /* shrl.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 11186 { 8295 /* shrl.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 11187 { 8303 /* shrl.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 11188 { 8303 /* shrl.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 11189 { 8311 /* shrlv.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 11190 { 8311 /* shrlv.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 11191 { 8320 /* shrlv.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 11192 { 8320 /* shrlv.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 11193 { 8336 /* sld.b */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, 11194 { 8336 /* sld.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11195 { 8342 /* sld.d */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, 11196 { 8342 /* sld.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11197 { 8348 /* sld.h */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, 11198 { 8348 /* sld.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11199 { 8354 /* sld.w */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, 11200 { 8354 /* sld.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11201 { 8360 /* sldi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11202 { 8367 /* sldi.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11203 { 8374 /* sldi.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11204 { 8381 /* sldi.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11205 { 8388 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips }, 11206 { 8388 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11207 { 8388 /* sll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11208 { 8388 /* sll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11209 { 8388 /* sll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11210 { 8388 /* sll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11211 { 8388 /* sll */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips }, 11212 { 8388 /* sll */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11213 { 8388 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11214 { 8388 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11215 { 8388 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11216 { 8392 /* sll.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11217 { 8398 /* sll.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11218 { 8404 /* sll.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11219 { 8410 /* sll.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11220 { 8416 /* sll16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 11221 { 8416 /* sll16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11222 { 8422 /* slli.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11223 { 8429 /* slli.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11224 { 8436 /* slli.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11225 { 8443 /* slli.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11226 { 8450 /* sllv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11227 { 8450 /* sllv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11228 { 8455 /* slt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, 11229 { 8455 /* slt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11230 { 8455 /* slt */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, 11231 { 8455 /* slt */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11232 { 8455 /* slt */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11233 { 8455 /* slt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, 11234 { 8455 /* slt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11235 { 8455 /* slt */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, 11236 { 8459 /* slti */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11237 { 8459 /* slti */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11238 { 8464 /* sltiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11239 { 8464 /* sltiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11240 { 8470 /* sltu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, 11241 { 8470 /* sltu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11242 { 8470 /* sltu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, 11243 { 8470 /* sltu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11244 { 8470 /* sltu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11245 { 8470 /* sltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, 11246 { 8470 /* sltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11247 { 8470 /* sltu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, 11248 { 8475 /* sne */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 11249 { 8475 /* sne */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 11250 { 8479 /* snei */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 11251 { 8479 /* snei */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 11252 { 8484 /* splat.b */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, 11253 { 8484 /* splat.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11254 { 8492 /* splat.d */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, 11255 { 8492 /* splat.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11256 { 8500 /* splat.h */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, 11257 { 8500 /* splat.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11258 { 8508 /* splat.w */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, 11259 { 8508 /* splat.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11260 { 8516 /* splati.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11261 { 8525 /* splati.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11262 { 8534 /* splati.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11263 { 8543 /* splati.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11264 { 8552 /* sqrt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 11265 { 8552 /* sqrt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 11266 { 8552 /* sqrt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 11267 { 8552 /* sqrt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, 11268 { 8559 /* sqrt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips }, 11269 { 8559 /* sqrt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, 11270 { 8566 /* sra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips }, 11271 { 8566 /* sra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11272 { 8566 /* sra */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11273 { 8566 /* sra */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11274 { 8566 /* sra */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11275 { 8566 /* sra */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips }, 11276 { 8566 /* sra */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11277 { 8566 /* sra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11278 { 8566 /* sra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11279 { 8570 /* sra.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11280 { 8576 /* sra.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11281 { 8582 /* sra.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11282 { 8588 /* sra.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11283 { 8594 /* srai.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11284 { 8601 /* srai.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11285 { 8608 /* srai.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11286 { 8615 /* srai.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11287 { 8622 /* srar.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11288 { 8629 /* srar.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11289 { 8636 /* srar.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11290 { 8643 /* srar.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11291 { 8650 /* srari.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11292 { 8658 /* srari.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11293 { 8666 /* srari.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11294 { 8674 /* srari.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11295 { 8682 /* srav */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11296 { 8682 /* srav */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11297 { 8687 /* srl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips }, 11298 { 8687 /* srl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11299 { 8687 /* srl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11300 { 8687 /* srl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11301 { 8687 /* srl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11302 { 8687 /* srl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips }, 11303 { 8687 /* srl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11304 { 8687 /* srl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11305 { 8687 /* srl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11306 { 8691 /* srl.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11307 { 8697 /* srl.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11308 { 8703 /* srl.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11309 { 8709 /* srl.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11310 { 8715 /* srl16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 11311 { 8715 /* srl16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11312 { 8721 /* srli.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11313 { 8728 /* srli.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11314 { 8735 /* srli.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11315 { 8742 /* srli.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11316 { 8749 /* srlr.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11317 { 8756 /* srlr.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11318 { 8763 /* srlr.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11319 { 8770 /* srlr.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11320 { 8777 /* srlri.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11321 { 8785 /* srlri.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11322 { 8793 /* srlri.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11323 { 8801 /* srlri.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11324 { 8809 /* srlv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11325 { 8809 /* srlv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11326 { 8820 /* st.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11327 { 8820 /* st.b */, 2 /* 1 */, MCK_MemOffsetSimm10_0, AMFBS_HasStdEnc_HasMSA }, 11328 { 8825 /* st.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11329 { 8825 /* st.d */, 2 /* 1 */, MCK_MemOffsetSimm10_3, AMFBS_HasStdEnc_HasMSA }, 11330 { 8830 /* st.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11331 { 8830 /* st.h */, 2 /* 1 */, MCK_MemOffsetSimm10_1, AMFBS_HasStdEnc_HasMSA }, 11332 { 8835 /* st.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11333 { 8835 /* st.w */, 2 /* 1 */, MCK_MemOffsetSimm10_2, AMFBS_HasStdEnc_HasMSA }, 11334 { 8840 /* sub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11335 { 8840 /* sub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 11336 { 8840 /* sub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11337 { 8840 /* sub */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 11338 { 8840 /* sub */, 2 /* 1 */, MCK_InvNum, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 11339 { 8840 /* sub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11340 { 8840 /* sub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 11341 { 8840 /* sub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11342 { 8840 /* sub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 11343 { 8840 /* sub */, 4 /* 2 */, MCK_InvNum, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, 11344 { 8844 /* sub.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, 11345 { 8844 /* sub.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 11346 { 8844 /* sub.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, 11347 { 8844 /* sub.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, 11348 { 8850 /* sub.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, 11349 { 8850 /* sub.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 11350 { 8850 /* sub.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, 11351 { 8856 /* subq.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 11352 { 8856 /* subq.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 11353 { 8864 /* subq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 11354 { 8864 /* subq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 11355 { 8874 /* subq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 11356 { 8874 /* subq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 11357 { 8883 /* subqh.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 11358 { 8883 /* subqh.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 11359 { 8892 /* subqh.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 11360 { 8892 /* subqh.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 11361 { 8900 /* subqh_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 11362 { 8900 /* subqh_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 11363 { 8911 /* subqh_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 11364 { 8911 /* subqh_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 11365 { 8921 /* subs_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11366 { 8930 /* subs_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11367 { 8939 /* subs_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11368 { 8948 /* subs_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11369 { 8957 /* subs_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11370 { 8966 /* subs_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11371 { 8975 /* subs_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11372 { 8984 /* subs_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11373 { 8993 /* subsus_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11374 { 9004 /* subsus_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11375 { 9015 /* subsus_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11376 { 9026 /* subsus_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11377 { 9037 /* subsuu_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11378 { 9048 /* subsuu_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11379 { 9059 /* subsuu_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11380 { 9070 /* subsuu_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11381 { 9081 /* subu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11382 { 9081 /* subu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11383 { 9081 /* subu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 11384 { 9081 /* subu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, 11385 { 9081 /* subu */, 2 /* 1 */, MCK_InvNum, AMFBS_None }, 11386 { 9081 /* subu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11387 { 9081 /* subu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11388 { 9081 /* subu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 11389 { 9081 /* subu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, 11390 { 9081 /* subu */, 4 /* 2 */, MCK_InvNum, AMFBS_None }, 11391 { 9086 /* subu.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 11392 { 9086 /* subu.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 11393 { 9094 /* subu.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 11394 { 9094 /* subu.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 11395 { 9102 /* subu16 */, 7 /* 0, 1, 2 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 11396 { 9102 /* subu16 */, 7 /* 0, 1, 2 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11397 { 9109 /* subu_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 11398 { 9109 /* subu_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 11399 { 9119 /* subu_s.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 11400 { 9119 /* subu_s.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, 11401 { 9129 /* subuh.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 11402 { 9129 /* subuh.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 11403 { 9138 /* subuh_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, 11404 { 9138 /* subuh_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, 11405 { 9149 /* subv.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11406 { 9156 /* subv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11407 { 9163 /* subv.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11408 { 9170 /* subv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11409 { 9177 /* subvi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11410 { 9185 /* subvi.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11411 { 9193 /* subvi.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11412 { 9201 /* subvi.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11413 { 9209 /* suxc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 11414 { 9209 /* suxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 11415 { 9209 /* suxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 11416 { 9209 /* suxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, 11417 { 9209 /* suxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 11418 { 9209 /* suxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, 11419 { 9215 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11420 { 9215 /* sw */, 2 /* 1 */, MCK_MicroMipsMemSP, AMFBS_InMicroMips_HasMips32r6 }, 11421 { 9215 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11422 { 9215 /* sw */, 2 /* 1 */, MCK_MicroMipsMemSP, AMFBS_InMicroMips }, 11423 { 9215 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11424 { 9215 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotInMicroMips }, 11425 { 9215 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_NotInMips16Mode_HasDSP }, 11426 { 9215 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_NotInMips16Mode_HasDSP }, 11427 { 9215 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 11428 { 9215 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasDSP }, 11429 { 9215 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11430 { 9215 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 }, 11431 { 9215 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11432 { 9215 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips }, 11433 { 9218 /* sw16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_NotMips32r6 }, 11434 { 9218 /* sw16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_NotMips32r6 }, 11435 { 9218 /* sw16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_HasMips32r6 }, 11436 { 9218 /* sw16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_HasMips32r6 }, 11437 { 9223 /* swc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, 11438 { 9223 /* swc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, 11439 { 9223 /* swc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, 11440 { 9223 /* swc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_IsNotSoftFloat }, 11441 { 9228 /* swc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 11442 { 9228 /* swc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, 11443 { 9228 /* swc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11444 { 9228 /* swc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_InMicroMips_HasMips32r6 }, 11445 { 9228 /* swc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 11446 { 9228 /* swc2 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 11447 { 9233 /* swc3 */, 1 /* 0 */, MCK_COP3AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips }, 11448 { 9233 /* swc3 */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips }, 11449 { 9238 /* swe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 11450 { 9238 /* swe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 11451 { 9238 /* swe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA }, 11452 { 9238 /* swe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA }, 11453 { 9242 /* swl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 11454 { 9242 /* swl */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 11455 { 9242 /* swl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 11456 { 9242 /* swl */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 }, 11457 { 9246 /* swle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips }, 11458 { 9246 /* swle */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips }, 11459 { 9246 /* swle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_HasEVA }, 11460 { 9246 /* swle */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_NotMips32r6_HasEVA }, 11461 { 9251 /* swm */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips }, 11462 { 9251 /* swm */, 1 /* 0 */, MCK_RegList, AMFBS_InMicroMips }, 11463 { 9255 /* swm16 */, 2 /* 1 */, MCK_MemOffsetUimm4, AMFBS_InMicroMips_NotMips32r6 }, 11464 { 9255 /* swm16 */, 1 /* 0 */, MCK_RegList16, AMFBS_InMicroMips_NotMips32r6 }, 11465 { 9255 /* swm16 */, 2 /* 1 */, MCK_MemOffsetUimm4, AMFBS_InMicroMips_HasMips32r6 }, 11466 { 9255 /* swm16 */, 1 /* 0 */, MCK_RegList16, AMFBS_InMicroMips_HasMips32r6 }, 11467 { 9261 /* swm32 */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips }, 11468 { 9261 /* swm32 */, 1 /* 0 */, MCK_RegList, AMFBS_InMicroMips }, 11469 { 9267 /* swp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11470 { 9267 /* swp */, 2 /* 1 */, MCK_MemOffsetSimm12_0, AMFBS_InMicroMips }, 11471 { 9271 /* swr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 11472 { 9271 /* swr */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 11473 { 9271 /* swr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 11474 { 9271 /* swr */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 }, 11475 { 9275 /* swre */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips }, 11476 { 9275 /* swre */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips }, 11477 { 9275 /* swre */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_HasEVA }, 11478 { 9275 /* swre */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_NotMips32r6_HasEVA }, 11479 { 9280 /* swsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 11480 { 9280 /* swsp */, 2 /* 1 */, MCK_MicroMipsMemSP, AMFBS_InMicroMips_NotMips32r6 }, 11481 { 9285 /* swxc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat }, 11482 { 9285 /* swxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat }, 11483 { 9285 /* swxc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 11484 { 9285 /* swxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, 11485 { 9296 /* synci */, 1 /* 0 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, 11486 { 9296 /* synci */, 1 /* 0 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_NotMips32r6 }, 11487 { 9296 /* synci */, 1 /* 0 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_HasMips32r6 }, 11488 { 9340 /* teq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, 11489 { 9340 /* teq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11490 { 9340 /* teq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11491 { 9340 /* teq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, 11492 { 9344 /* teqi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 11493 { 9344 /* teqi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 11494 { 9349 /* tge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, 11495 { 9349 /* tge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11496 { 9349 /* tge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11497 { 9349 /* tge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, 11498 { 9353 /* tgei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 11499 { 9353 /* tgei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 11500 { 9358 /* tgeiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 11501 { 9358 /* tgeiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 11502 { 9364 /* tgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, 11503 { 9364 /* tgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11504 { 9364 /* tgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11505 { 9364 /* tgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, 11506 { 9449 /* tlt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, 11507 { 9449 /* tlt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11508 { 9449 /* tlt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11509 { 9449 /* tlt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, 11510 { 9453 /* tlti */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 11511 { 9453 /* tlti */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 11512 { 9458 /* tltiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 11513 { 9458 /* tltiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 11514 { 9464 /* tltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, 11515 { 9464 /* tltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11516 { 9464 /* tltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11517 { 9464 /* tltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, 11518 { 9469 /* tne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, 11519 { 9469 /* tne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11520 { 9469 /* tne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11521 { 9469 /* tne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, 11522 { 9473 /* tnei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 11523 { 9473 /* tnei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 11524 { 9478 /* trunc.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips }, 11525 { 9478 /* trunc.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 11526 { 9488 /* trunc.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 11527 { 9488 /* trunc.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 11528 { 9488 /* trunc.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 11529 { 9488 /* trunc.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 11530 { 9498 /* trunc.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 11531 { 9498 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 11532 { 9498 /* trunc.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 11533 { 9498 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 11534 { 9498 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 11535 { 9498 /* trunc.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 11536 { 9498 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 11537 { 9498 /* trunc.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 11538 { 9498 /* trunc.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_NotFP64bit_IsNotSoftFloat }, 11539 { 9498 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_NotFP64bit_IsNotSoftFloat }, 11540 { 9498 /* trunc.w.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_NotFP64bit_IsNotSoftFloat }, 11541 { 9498 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_IsFP64bit_IsNotSoftFloat }, 11542 { 9498 /* trunc.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_IsFP64bit_IsNotSoftFloat }, 11543 { 9498 /* trunc.w.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_IsFP64bit_IsNotSoftFloat }, 11544 { 9508 /* trunc.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips }, 11545 { 9508 /* trunc.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, 11546 { 9508 /* trunc.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, 11547 { 9508 /* trunc.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_None }, 11548 { 9508 /* trunc.w.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_None }, 11549 { 9518 /* ulh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, 11550 { 9518 /* ulh */, 2 /* 1 */, MCK_Mem, AMFBS_None }, 11551 { 9522 /* ulhu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, 11552 { 9522 /* ulhu */, 2 /* 1 */, MCK_Mem, AMFBS_None }, 11553 { 9527 /* ulw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, 11554 { 9527 /* ulw */, 2 /* 1 */, MCK_Mem, AMFBS_None }, 11555 { 9531 /* ush */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, 11556 { 9531 /* ush */, 2 /* 1 */, MCK_Mem, AMFBS_None }, 11557 { 9535 /* usw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, 11558 { 9535 /* usw */, 2 /* 1 */, MCK_Mem, AMFBS_None }, 11559 { 9539 /* v3mulu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 11560 { 9539 /* v3mulu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 11561 { 9546 /* vmm0 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 11562 { 9546 /* vmm0 */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 11563 { 9551 /* vmulu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 11564 { 9551 /* vmulu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, 11565 { 9557 /* vshf.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11566 { 9564 /* vshf.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11567 { 9571 /* vshf.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11568 { 9578 /* vshf.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11569 { 9590 /* wrdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP_NotInMicroMips }, 11570 { 9590 /* wrdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP_InMicroMips }, 11571 { 9590 /* wrdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, 11572 { 9590 /* wrdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP_NotInMicroMips }, 11573 { 9596 /* wrpgpr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11574 { 9603 /* wsbh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, 11575 { 9603 /* wsbh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11576 { 9603 /* wsbh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11577 { 9608 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11578 { 9608 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 11579 { 9608 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11580 { 9608 /* xor */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11581 { 9608 /* xor */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, 11582 { 9608 /* xor */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11583 { 9608 /* xor */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips }, 11584 { 9608 /* xor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11585 { 9608 /* xor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 11586 { 9608 /* xor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11587 { 9608 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11588 { 9608 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, 11589 { 9608 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, 11590 { 9608 /* xor */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips }, 11591 { 9612 /* xor.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11592 { 9618 /* xor16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 11593 { 9618 /* xor16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11594 { 9624 /* xori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11595 { 9624 /* xori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11596 { 9624 /* xori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 11597 { 9624 /* xori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, 11598 { 9624 /* xori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, 11599 { 9624 /* xori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, 11600 { 9629 /* xori.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 11601 { 9636 /* yield */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips }, 11602 { 9636 /* yield */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips }, 11603}; 11604 11605OperandMatchResultTy MipsAsmParser:: 11606tryCustomParseOperand(OperandVector &Operands, 11607 unsigned MCK) { 11608 11609 switch(MCK) { 11610 case MCK_ACC64DSPAsmReg: 11611 return parseAnyRegister(Operands); 11612 case MCK_AFGR64AsmReg: 11613 return parseAnyRegister(Operands); 11614 case MCK_CCRAsmReg: 11615 return parseAnyRegister(Operands); 11616 case MCK_COP0AsmReg: 11617 return parseAnyRegister(Operands); 11618 case MCK_COP2AsmReg: 11619 return parseAnyRegister(Operands); 11620 case MCK_COP3AsmReg: 11621 return parseAnyRegister(Operands); 11622 case MCK_FCCAsmReg: 11623 return parseAnyRegister(Operands); 11624 case MCK_FGR32AsmReg: 11625 return parseAnyRegister(Operands); 11626 case MCK_FGR64AsmReg: 11627 return parseAnyRegister(Operands); 11628 case MCK_GPR32AsmReg: 11629 return parseAnyRegister(Operands); 11630 case MCK_GPR32NonZeroAsmReg: 11631 return parseAnyRegister(Operands); 11632 case MCK_GPR32ZeroAsmReg: 11633 return parseAnyRegister(Operands); 11634 case MCK_GPR64AsmReg: 11635 return parseAnyRegister(Operands); 11636 case MCK_GPRMM16AsmReg: 11637 return parseAnyRegister(Operands); 11638 case MCK_GPRMM16AsmRegMoveP: 11639 return parseAnyRegister(Operands); 11640 case MCK_GPRMM16AsmRegMovePPairFirst: 11641 return parseAnyRegister(Operands); 11642 case MCK_GPRMM16AsmRegMovePPairSecond: 11643 return parseAnyRegister(Operands); 11644 case MCK_GPRMM16AsmRegZero: 11645 return parseAnyRegister(Operands); 11646 case MCK_HI32DSPAsmReg: 11647 return parseAnyRegister(Operands); 11648 case MCK_HWRegsAsmReg: 11649 return parseAnyRegister(Operands); 11650 case MCK_LO32DSPAsmReg: 11651 return parseAnyRegister(Operands); 11652 case MCK_MSA128AsmReg: 11653 return parseAnyRegister(Operands); 11654 case MCK_MSACtrlAsmReg: 11655 return parseAnyRegister(Operands); 11656 case MCK_MicroMipsMemGP: 11657 return parseMemOperand(Operands); 11658 case MCK_MicroMipsMem: 11659 return parseMemOperand(Operands); 11660 case MCK_MicroMipsMemSP: 11661 return parseMemOperand(Operands); 11662 case MCK_InvNum: 11663 return parseInvNum(Operands); 11664 case MCK_JumpTarget: 11665 return parseJumpTarget(Operands); 11666 case MCK_MemOffsetSimmPtr: 11667 return parseMemOperand(Operands); 11668 case MCK_MemOffsetUimm4: 11669 return parseMemOperand(Operands); 11670 case MCK_MemOffsetSimm9_0: 11671 return parseMemOperand(Operands); 11672 case MCK_MemOffsetSimm10_0: 11673 return parseMemOperand(Operands); 11674 case MCK_MemOffsetSimm11_0: 11675 return parseMemOperand(Operands); 11676 case MCK_MemOffsetSimm12_0: 11677 return parseMemOperand(Operands); 11678 case MCK_MemOffsetSimm16_0: 11679 return parseMemOperand(Operands); 11680 case MCK_MemOffsetSimm10_1: 11681 return parseMemOperand(Operands); 11682 case MCK_MemOffsetSimm10_2: 11683 return parseMemOperand(Operands); 11684 case MCK_MemOffsetSimm10_3: 11685 return parseMemOperand(Operands); 11686 case MCK_Mem: 11687 return parseMemOperand(Operands); 11688 case MCK_RegList16: 11689 return parseRegisterList(Operands); 11690 case MCK_RegList: 11691 return parseRegisterList(Operands); 11692 case MCK_StrictlyAFGR64AsmReg: 11693 return parseAnyRegister(Operands); 11694 case MCK_StrictlyFGR32AsmReg: 11695 return parseAnyRegister(Operands); 11696 case MCK_StrictlyFGR64AsmReg: 11697 return parseAnyRegister(Operands); 11698 default: 11699 return MatchOperand_NoMatch; 11700 } 11701 return MatchOperand_NoMatch; 11702} 11703 11704OperandMatchResultTy MipsAsmParser:: 11705MatchOperandParserImpl(OperandVector &Operands, 11706 StringRef Mnemonic, 11707 bool ParseForAllFeatures) { 11708 // Get the current feature set. 11709 const FeatureBitset &AvailableFeatures = getAvailableFeatures(); 11710 11711 // Get the next operand index. 11712 unsigned NextOpNum = Operands.size() - 1; 11713 // Search the table. 11714 auto MnemonicRange = 11715 std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable), 11716 Mnemonic, LessOpcodeOperand()); 11717 11718 if (MnemonicRange.first == MnemonicRange.second) 11719 return MatchOperand_NoMatch; 11720 11721 for (const OperandMatchEntry *it = MnemonicRange.first, 11722 *ie = MnemonicRange.second; it != ie; ++it) { 11723 // equal_range guarantees that instruction mnemonic matches. 11724 assert(Mnemonic == it->getMnemonic()); 11725 11726 // check if the available features match 11727 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx]; 11728 if (!ParseForAllFeatures && (AvailableFeatures & RequiredFeatures) != RequiredFeatures) 11729 continue; 11730 11731 // check if the operand in question has a custom parser. 11732 if (!(it->OperandMask & (1 << NextOpNum))) 11733 continue; 11734 11735 // call custom parse method to handle the operand 11736 OperandMatchResultTy Result = tryCustomParseOperand(Operands, it->Class); 11737 if (Result != MatchOperand_NoMatch) 11738 return Result; 11739 } 11740 11741 // Okay, we had no match. 11742 return MatchOperand_NoMatch; 11743} 11744 11745#endif // GET_MATCHER_IMPLEMENTATION 11746 11747 11748#ifdef GET_MNEMONIC_SPELL_CHECKER 11749#undef GET_MNEMONIC_SPELL_CHECKER 11750 11751static std::string MipsMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID) { 11752 const unsigned MaxEditDist = 2; 11753 std::vector<StringRef> Candidates; 11754 StringRef Prev = ""; 11755 11756 // Find the appropriate table for this asm variant. 11757 const MatchEntry *Start, *End; 11758 switch (VariantID) { 11759 default: llvm_unreachable("invalid variant!"); 11760 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break; 11761 } 11762 11763 for (auto I = Start; I < End; I++) { 11764 // Ignore unsupported instructions. 11765 const FeatureBitset &RequiredFeatures = FeatureBitsets[I->RequiredFeaturesIdx]; 11766 if ((FBS & RequiredFeatures) != RequiredFeatures) 11767 continue; 11768 11769 StringRef T = I->getMnemonic(); 11770 // Avoid recomputing the edit distance for the same string. 11771 if (T.equals(Prev)) 11772 continue; 11773 11774 Prev = T; 11775 unsigned Dist = S.edit_distance(T, false, MaxEditDist); 11776 if (Dist <= MaxEditDist) 11777 Candidates.push_back(T); 11778 } 11779 11780 if (Candidates.empty()) 11781 return ""; 11782 11783 std::string Res = ", did you mean: "; 11784 unsigned i = 0; 11785 for( ; i < Candidates.size() - 1; i++) 11786 Res += Candidates[i].str() + ", "; 11787 return Res + Candidates[i].str() + "?"; 11788} 11789 11790#endif // GET_MNEMONIC_SPELL_CHECKER 11791 11792