1 //===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the SystemZ implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
14 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
15
16 #include "SystemZ.h"
17 #include "SystemZRegisterInfo.h"
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/TargetInstrInfo.h"
23 #include <cstdint>
24
25 #define GET_INSTRINFO_HEADER
26 #include "SystemZGenInstrInfo.inc"
27
28 namespace llvm {
29
30 class SystemZSubtarget;
31
32 namespace SystemZII {
33
34 enum {
35 // See comments in SystemZInstrFormats.td.
36 SimpleBDXLoad = (1 << 0),
37 SimpleBDXStore = (1 << 1),
38 Has20BitOffset = (1 << 2),
39 HasIndex = (1 << 3),
40 Is128Bit = (1 << 4),
41 AccessSizeMask = (31 << 5),
42 AccessSizeShift = 5,
43 CCValuesMask = (15 << 10),
44 CCValuesShift = 10,
45 CompareZeroCCMaskMask = (15 << 14),
46 CompareZeroCCMaskShift = 14,
47 CCMaskFirst = (1 << 18),
48 CCMaskLast = (1 << 19),
49 IsLogical = (1 << 20),
50 CCIfNoSignedWrap = (1 << 21)
51 };
52
getAccessSize(unsigned int Flags)53 static inline unsigned getAccessSize(unsigned int Flags) {
54 return (Flags & AccessSizeMask) >> AccessSizeShift;
55 }
56
getCCValues(unsigned int Flags)57 static inline unsigned getCCValues(unsigned int Flags) {
58 return (Flags & CCValuesMask) >> CCValuesShift;
59 }
60
getCompareZeroCCMask(unsigned int Flags)61 static inline unsigned getCompareZeroCCMask(unsigned int Flags) {
62 return (Flags & CompareZeroCCMaskMask) >> CompareZeroCCMaskShift;
63 }
64
65 // SystemZ MachineOperand target flags.
66 enum {
67 // Masks out the bits for the access model.
68 MO_SYMBOL_MODIFIER = (3 << 0),
69
70 // @GOT (aka @GOTENT)
71 MO_GOT = (1 << 0),
72
73 // @INDNTPOFF
74 MO_INDNTPOFF = (2 << 0)
75 };
76
77 // Classifies a branch.
78 enum BranchType {
79 // An instruction that branches on the current value of CC.
80 BranchNormal,
81
82 // An instruction that peforms a 32-bit signed comparison and branches
83 // on the result.
84 BranchC,
85
86 // An instruction that peforms a 32-bit unsigned comparison and branches
87 // on the result.
88 BranchCL,
89
90 // An instruction that peforms a 64-bit signed comparison and branches
91 // on the result.
92 BranchCG,
93
94 // An instruction that peforms a 64-bit unsigned comparison and branches
95 // on the result.
96 BranchCLG,
97
98 // An instruction that decrements a 32-bit register and branches if
99 // the result is nonzero.
100 BranchCT,
101
102 // An instruction that decrements a 64-bit register and branches if
103 // the result is nonzero.
104 BranchCTG,
105
106 // An instruction representing an asm goto statement.
107 AsmGoto
108 };
109
110 // Information about a branch instruction.
111 class Branch {
112 // The target of the branch. In case of INLINEASM_BR, this is nullptr.
113 const MachineOperand *Target;
114
115 public:
116 // The type of the branch.
117 BranchType Type;
118
119 // CCMASK_<N> is set if CC might be equal to N.
120 unsigned CCValid;
121
122 // CCMASK_<N> is set if the branch should be taken when CC == N.
123 unsigned CCMask;
124
Branch(BranchType type,unsigned ccValid,unsigned ccMask,const MachineOperand * target)125 Branch(BranchType type, unsigned ccValid, unsigned ccMask,
126 const MachineOperand *target)
127 : Target(target), Type(type), CCValid(ccValid), CCMask(ccMask) {}
128
isIndirect()129 bool isIndirect() { return Target != nullptr && Target->isReg(); }
hasMBBTarget()130 bool hasMBBTarget() { return Target != nullptr && Target->isMBB(); }
getMBBTarget()131 MachineBasicBlock *getMBBTarget() {
132 return hasMBBTarget() ? Target->getMBB() : nullptr;
133 }
134 };
135
136 // Kinds of fused compares in compare-and-* instructions. Together with type
137 // of the converted compare, this identifies the compare-and-*
138 // instruction.
139 enum FusedCompareType {
140 // Relative branch - CRJ etc.
141 CompareAndBranch,
142
143 // Indirect branch, used for return - CRBReturn etc.
144 CompareAndReturn,
145
146 // Indirect branch, used for sibcall - CRBCall etc.
147 CompareAndSibcall,
148
149 // Trap
150 CompareAndTrap
151 };
152
153 } // end namespace SystemZII
154
155 namespace SystemZ {
156 int getTwoOperandOpcode(uint16_t Opcode);
157 int getTargetMemOpcode(uint16_t Opcode);
158 }
159
160 class SystemZInstrInfo : public SystemZGenInstrInfo {
161 const SystemZRegisterInfo RI;
162 SystemZSubtarget &STI;
163
164 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
165 void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
166 void expandRIPseudo(MachineInstr &MI, unsigned LowOpcode, unsigned HighOpcode,
167 bool ConvertHigh) const;
168 void expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
169 unsigned LowOpcodeK, unsigned HighOpcode) const;
170 void expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
171 unsigned HighOpcode) const;
172 void expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
173 unsigned HighOpcode) const;
174 void expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
175 unsigned Size) const;
176 void expandLoadStackGuard(MachineInstr *MI) const;
177
178 MachineInstrBuilder
179 emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
180 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
181 unsigned LowLowOpcode, unsigned Size, bool KillSrc,
182 bool UndefSrc) const;
183
184 virtual void anchor();
185
186 protected:
187 /// Commutes the operands in the given instruction by changing the operands
188 /// order and/or changing the instruction's opcode and/or the immediate value
189 /// operand.
190 ///
191 /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
192 /// to be commuted.
193 ///
194 /// Do not call this method for a non-commutable instruction or
195 /// non-commutable operands.
196 /// Even though the instruction is commutable, the method may still
197 /// fail to commute the operands, null pointer is returned in such cases.
198 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
199 unsigned CommuteOpIdx1,
200 unsigned CommuteOpIdx2) const override;
201
202 public:
203 explicit SystemZInstrInfo(SystemZSubtarget &STI);
204
205 // Override TargetInstrInfo.
206 unsigned isLoadFromStackSlot(const MachineInstr &MI,
207 int &FrameIndex) const override;
208 unsigned isStoreToStackSlot(const MachineInstr &MI,
209 int &FrameIndex) const override;
210 bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
211 int &SrcFrameIndex) const override;
212 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
213 MachineBasicBlock *&FBB,
214 SmallVectorImpl<MachineOperand> &Cond,
215 bool AllowModify) const override;
216 unsigned removeBranch(MachineBasicBlock &MBB,
217 int *BytesRemoved = nullptr) const override;
218 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
219 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
220 const DebugLoc &DL,
221 int *BytesAdded = nullptr) const override;
222 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
223 unsigned &SrcReg2, int &Mask, int &Value) const override;
224 bool canInsertSelect(const MachineBasicBlock&, ArrayRef<MachineOperand> Cond,
225 unsigned, unsigned, int&, int&, int&) const override;
226 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
227 const DebugLoc &DL, unsigned DstReg,
228 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
229 unsigned FalseReg) const override;
230 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
231 MachineRegisterInfo *MRI) const override;
232 bool isPredicable(const MachineInstr &MI) const override;
233 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
234 unsigned ExtraPredCycles,
235 BranchProbability Probability) const override;
236 bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
237 unsigned NumCyclesT, unsigned ExtraPredCyclesT,
238 MachineBasicBlock &FMBB,
239 unsigned NumCyclesF, unsigned ExtraPredCyclesF,
240 BranchProbability Probability) const override;
241 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
242 BranchProbability Probability) const override;
243 bool PredicateInstruction(MachineInstr &MI,
244 ArrayRef<MachineOperand> Pred) const override;
245 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
246 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
247 bool KillSrc) const override;
248 void storeRegToStackSlot(MachineBasicBlock &MBB,
249 MachineBasicBlock::iterator MBBI,
250 unsigned SrcReg, bool isKill, int FrameIndex,
251 const TargetRegisterClass *RC,
252 const TargetRegisterInfo *TRI) const override;
253 void loadRegFromStackSlot(MachineBasicBlock &MBB,
254 MachineBasicBlock::iterator MBBI,
255 unsigned DestReg, int FrameIdx,
256 const TargetRegisterClass *RC,
257 const TargetRegisterInfo *TRI) const override;
258 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
259 MachineInstr &MI,
260 LiveVariables *LV) const override;
261 MachineInstr *
262 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
263 ArrayRef<unsigned> Ops,
264 MachineBasicBlock::iterator InsertPt, int FrameIndex,
265 LiveIntervals *LIS = nullptr,
266 VirtRegMap *VRM = nullptr) const override;
267 MachineInstr *foldMemoryOperandImpl(
268 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
269 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
270 LiveIntervals *LIS = nullptr) const override;
271 bool expandPostRAPseudo(MachineInstr &MBBI) const override;
272 bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
273 override;
274
275 // Return the SystemZRegisterInfo, which this class owns.
getRegisterInfo()276 const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
277
278 // Return the size in bytes of MI.
279 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
280
281 // Return true if MI is a conditional or unconditional branch.
282 // When returning true, set Cond to the mask of condition-code
283 // values on which the instruction will branch, and set Target
284 // to the operand that contains the branch target. This target
285 // can be a register or a basic block.
286 SystemZII::Branch getBranchInfo(const MachineInstr &MI) const;
287
288 // Get the load and store opcodes for a given register class.
289 void getLoadStoreOpcodes(const TargetRegisterClass *RC,
290 unsigned &LoadOpcode, unsigned &StoreOpcode) const;
291
292 // Opcode is the opcode of an instruction that has an address operand,
293 // and the caller wants to perform that instruction's operation on an
294 // address that has displacement Offset. Return the opcode of a suitable
295 // instruction (which might be Opcode itself) or 0 if no such instruction
296 // exists.
297 unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const;
298
299 // If Opcode is a load instruction that has a LOAD AND TEST form,
300 // return the opcode for the testing form, otherwise return 0.
301 unsigned getLoadAndTest(unsigned Opcode) const;
302
303 // Return true if ROTATE AND ... SELECTED BITS can be used to select bits
304 // Mask of the R2 operand, given that only the low BitSize bits of Mask are
305 // significant. Set Start and End to the I3 and I4 operands if so.
306 bool isRxSBGMask(uint64_t Mask, unsigned BitSize,
307 unsigned &Start, unsigned &End) const;
308
309 // If Opcode is a COMPARE opcode for which an associated fused COMPARE AND *
310 // operation exists, return the opcode for the latter, otherwise return 0.
311 // MI, if nonnull, is the compare instruction.
312 unsigned getFusedCompare(unsigned Opcode,
313 SystemZII::FusedCompareType Type,
314 const MachineInstr *MI = nullptr) const;
315
316 // If Opcode is a LOAD opcode for with an associated LOAD AND TRAP
317 // operation exists, returh the opcode for the latter, otherwise return 0.
318 unsigned getLoadAndTrap(unsigned Opcode) const;
319
320 // Emit code before MBBI in MI to move immediate value Value into
321 // physical register Reg.
322 void loadImmediate(MachineBasicBlock &MBB,
323 MachineBasicBlock::iterator MBBI,
324 unsigned Reg, uint64_t Value) const;
325
326 // Perform target specific instruction verification.
327 bool verifyInstruction(const MachineInstr &MI,
328 StringRef &ErrInfo) const override;
329
330 // Sometimes, it is possible for the target to tell, even without
331 // aliasing information, that two MIs access different memory
332 // addresses. This function returns true if two MIs access different
333 // memory addresses and false otherwise.
334 bool
335 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
336 const MachineInstr &MIb) const override;
337 };
338
339 } // end namespace llvm
340
341 #endif // LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
342