1 /* -*- Mode: C++; tab-width: 8; indent-tabs-mode: nil; c-basic-offset: 2 -*-
2 * vim: set ts=8 sts=2 et sw=2 tw=80:
3 */
4 // Copyright 2011 the V8 project authors. All rights reserved.
5 // Use of this source code is governed by a BSD-style license that can be
6 // found in the LICENSE file.
7
8 #ifndef jit_arm_disasm_Constants_arm_h
9 #define jit_arm_disasm_Constants_arm_h
10
11 #ifdef JS_DISASM_ARM
12
13 # include "mozilla/Assertions.h"
14 # include "mozilla/Types.h"
15
16 # include <string.h>
17
18 namespace js {
19 namespace jit {
20 namespace disasm {
21
22 // Constant pool marker.
23 // Use UDF, the permanently undefined instruction.
24 const int kConstantPoolMarkerMask = 0xfff000f0;
25 const int kConstantPoolMarker = 0xe7f000f0;
26 const int kConstantPoolLengthMaxMask = 0xffff;
27
EncodeConstantPoolLength(int length)28 inline int EncodeConstantPoolLength(int length) {
29 MOZ_ASSERT((length & kConstantPoolLengthMaxMask) == length);
30 return ((length & 0xfff0) << 4) | (length & 0xf);
31 }
32
DecodeConstantPoolLength(int instr)33 inline int DecodeConstantPoolLength(int instr) {
34 MOZ_ASSERT((instr & kConstantPoolMarkerMask) == kConstantPoolMarker);
35 return ((instr >> 4) & 0xfff0) | (instr & 0xf);
36 }
37
38 // Used in code age prologue - ldr(pc, MemOperand(pc, -4))
39 const int kCodeAgeJumpInstruction = 0xe51ff004;
40
41 // Number of registers in normal ARM mode.
42 const int kNumRegisters = 16;
43
44 // VFP support.
45 const int kNumVFPSingleRegisters = 32;
46 const int kNumVFPDoubleRegisters = 32;
47 const int kNumVFPRegisters = kNumVFPSingleRegisters + kNumVFPDoubleRegisters;
48
49 // PC is register 15.
50 const int kPCRegister = 15;
51 const int kNoRegister = -1;
52
53 // -----------------------------------------------------------------------------
54 // Conditions.
55
56 // Defines constants and accessor classes to assemble, disassemble and
57 // simulate ARM instructions.
58 //
59 // Section references in the code refer to the "ARM Architecture Reference
60 // Manual" from July 2005 (available at http://www.arm.com/miscPDFs/14128.pdf)
61 //
62 // Constants for specific fields are defined in their respective named enums.
63 // General constants are in an anonymous enum in class Instr.
64
65 // Values for the condition field as defined in section A3.2
66 enum Condition {
67 kNoCondition = -1,
68
69 eq = 0 << 28, // Z set Equal.
70 ne = 1 << 28, // Z clear Not equal.
71 cs = 2 << 28, // C set Unsigned higher or same.
72 cc = 3 << 28, // C clear Unsigned lower.
73 mi = 4 << 28, // N set Negative.
74 pl = 5 << 28, // N clear Positive or zero.
75 vs = 6 << 28, // V set Overflow.
76 vc = 7 << 28, // V clear No overflow.
77 hi = 8 << 28, // C set, Z clear Unsigned higher.
78 ls = 9 << 28, // C clear or Z set Unsigned lower or same.
79 ge = 10 << 28, // N == V Greater or equal.
80 lt = 11 << 28, // N != V Less than.
81 gt = 12 << 28, // Z clear, N == V Greater than.
82 le = 13 << 28, // Z set or N != V Less then or equal
83 al = 14 << 28, // Always.
84
85 kSpecialCondition = 15 << 28, // Special condition (refer to section A3.2.1).
86 kNumberOfConditions = 16,
87
88 // Aliases.
89 hs = cs, // C set Unsigned higher or same.
90 lo = cc // C clear Unsigned lower.
91 };
92
NegateCondition(Condition cond)93 inline Condition NegateCondition(Condition cond) {
94 MOZ_ASSERT(cond != al);
95 return static_cast<Condition>(cond ^ ne);
96 }
97
98 // Commute a condition such that {a cond b == b cond' a}.
CommuteCondition(Condition cond)99 inline Condition CommuteCondition(Condition cond) {
100 switch (cond) {
101 case lo:
102 return hi;
103 case hi:
104 return lo;
105 case hs:
106 return ls;
107 case ls:
108 return hs;
109 case lt:
110 return gt;
111 case gt:
112 return lt;
113 case ge:
114 return le;
115 case le:
116 return ge;
117 default:
118 return cond;
119 }
120 }
121
122 // -----------------------------------------------------------------------------
123 // Instructions encoding.
124
125 // Instr is merely used by the Assembler to distinguish 32bit integers
126 // representing instructions from usual 32 bit values.
127 // Instruction objects are pointers to 32bit values, and provide methods to
128 // access the various ISA fields.
129 typedef int32_t Instr;
130
131 // Opcodes for Data-processing instructions (instructions with a type 0 and 1)
132 // as defined in section A3.4
133 enum Opcode {
134 AND = 0 << 21, // Logical AND.
135 EOR = 1 << 21, // Logical Exclusive OR.
136 SUB = 2 << 21, // Subtract.
137 RSB = 3 << 21, // Reverse Subtract.
138 ADD = 4 << 21, // Add.
139 ADC = 5 << 21, // Add with Carry.
140 SBC = 6 << 21, // Subtract with Carry.
141 RSC = 7 << 21, // Reverse Subtract with Carry.
142 TST = 8 << 21, // Test.
143 TEQ = 9 << 21, // Test Equivalence.
144 CMP = 10 << 21, // Compare.
145 CMN = 11 << 21, // Compare Negated.
146 ORR = 12 << 21, // Logical (inclusive) OR.
147 MOV = 13 << 21, // Move.
148 BIC = 14 << 21, // Bit Clear.
149 MVN = 15 << 21 // Move Not.
150 };
151
152 // The bits for bit 7-4 for some type 0 miscellaneous instructions.
153 enum MiscInstructionsBits74 {
154 // With bits 22-21 01.
155 BX = 1 << 4,
156 BXJ = 2 << 4,
157 BLX = 3 << 4,
158 BKPT = 7 << 4,
159
160 // With bits 22-21 11.
161 CLZ = 1 << 4
162 };
163
164 // Load and store exclusive instructions.
165
166 // Bit positions.
167 enum {
168 ExclusiveOpHi = 24, // Hi bit of opcode field
169 ExclusiveOpLo = 23, // Lo bit of opcode field
170 ExclusiveSizeHi = 22, // Hi bit of operand size field
171 ExclusiveSizeLo = 21, // Lo bit of operand size field
172 ExclusiveLoad = 20 // Bit indicating load
173 };
174
175 // Opcode bits for exclusive instructions.
176 enum { ExclusiveOpcode = 3 };
177
178 // Operand size, Bits(ExclusiveSizeHi,ExclusiveSizeLo).
179 enum {
180 ExclusiveWord = 0,
181 ExclusiveDouble = 1,
182 ExclusiveByte = 2,
183 ExclusiveHalf = 3
184 };
185
186 // Instruction encoding bits and masks.
187 enum {
188 H = 1 << 5, // Halfword (or byte).
189 S6 = 1 << 6, // Signed (or unsigned).
190 L = 1 << 20, // Load (or store).
191 S = 1 << 20, // Set condition code (or leave unchanged).
192 W = 1 << 21, // Writeback base register (or leave unchanged).
193 A = 1 << 21, // Accumulate in multiply instruction (or not).
194 B = 1 << 22, // Unsigned byte (or word).
195 N = 1 << 22, // Long (or short).
196 U = 1 << 23, // Positive (or negative) offset/index.
197 P = 1 << 24, // Offset/pre-indexed addressing (or post-indexed addressing).
198 I = 1 << 25, // Immediate shifter operand (or not).
199 B0 = 1 << 0,
200 B4 = 1 << 4,
201 B5 = 1 << 5,
202 B6 = 1 << 6,
203 B7 = 1 << 7,
204 B8 = 1 << 8,
205 B9 = 1 << 9,
206 B12 = 1 << 12,
207 B16 = 1 << 16,
208 B17 = 1 << 17,
209 B18 = 1 << 18,
210 B19 = 1 << 19,
211 B20 = 1 << 20,
212 B21 = 1 << 21,
213 B22 = 1 << 22,
214 B23 = 1 << 23,
215 B24 = 1 << 24,
216 B25 = 1 << 25,
217 B26 = 1 << 26,
218 B27 = 1 << 27,
219 B28 = 1 << 28,
220
221 // Instruction bit masks.
222 kCondMask = 15 << 28,
223 kALUMask = 0x6f << 21,
224 kRdMask = 15 << 12, // In str instruction.
225 kCoprocessorMask = 15 << 8,
226 kOpCodeMask = 15 << 21, // In data-processing instructions.
227 kImm24Mask = (1 << 24) - 1,
228 kImm16Mask = (1 << 16) - 1,
229 kImm8Mask = (1 << 8) - 1,
230 kOff12Mask = (1 << 12) - 1,
231 kOff8Mask = (1 << 8) - 1
232 };
233
234 // -----------------------------------------------------------------------------
235 // Addressing modes and instruction variants.
236
237 // Condition code updating mode.
238 enum SBit {
239 SetCC = 1 << 20, // Set condition code.
240 LeaveCC = 0 << 20 // Leave condition code unchanged.
241 };
242
243 // Status register selection.
244 enum SRegister { CPSR = 0 << 22, SPSR = 1 << 22 };
245
246 // Shifter types for Data-processing operands as defined in section A5.1.2.
247 enum ShiftOp {
248 LSL = 0 << 5, // Logical shift left.
249 LSR = 1 << 5, // Logical shift right.
250 ASR = 2 << 5, // Arithmetic shift right.
251 ROR = 3 << 5, // Rotate right.
252
253 // RRX is encoded as ROR with shift_imm == 0.
254 // Use a special code to make the distinction. The RRX ShiftOp is only used
255 // as an argument, and will never actually be encoded. The Assembler will
256 // detect it and emit the correct ROR shift operand with shift_imm == 0.
257 RRX = -1,
258 kNumberOfShifts = 4
259 };
260
261 // Status register fields.
262 enum SRegisterField {
263 CPSR_c = CPSR | 1 << 16,
264 CPSR_x = CPSR | 1 << 17,
265 CPSR_s = CPSR | 1 << 18,
266 CPSR_f = CPSR | 1 << 19,
267 SPSR_c = SPSR | 1 << 16,
268 SPSR_x = SPSR | 1 << 17,
269 SPSR_s = SPSR | 1 << 18,
270 SPSR_f = SPSR | 1 << 19
271 };
272
273 // Status register field mask (or'ed SRegisterField enum values).
274 typedef uint32_t SRegisterFieldMask;
275
276 // Memory operand addressing mode.
277 enum AddrMode {
278 // Bit encoding P U W.
279 Offset = (8 | 4 | 0) << 21, // Offset (without writeback to base).
280 PreIndex = (8 | 4 | 1) << 21, // Pre-indexed addressing with writeback.
281 PostIndex = (0 | 4 | 0) << 21, // Post-indexed addressing with writeback.
282 NegOffset =
283 (8 | 0 | 0) << 21, // Negative offset (without writeback to base).
284 NegPreIndex = (8 | 0 | 1) << 21, // Negative pre-indexed with writeback.
285 NegPostIndex = (0 | 0 | 0) << 21 // Negative post-indexed with writeback.
286 };
287
288 // Load/store multiple addressing mode.
289 enum BlockAddrMode {
290 // Bit encoding P U W .
291 da = (0 | 0 | 0) << 21, // Decrement after.
292 ia = (0 | 4 | 0) << 21, // Increment after.
293 db = (8 | 0 | 0) << 21, // Decrement before.
294 ib = (8 | 4 | 0) << 21, // Increment before.
295 da_w = (0 | 0 | 1) << 21, // Decrement after with writeback to base.
296 ia_w = (0 | 4 | 1) << 21, // Increment after with writeback to base.
297 db_w = (8 | 0 | 1) << 21, // Decrement before with writeback to base.
298 ib_w = (8 | 4 | 1) << 21, // Increment before with writeback to base.
299
300 // Alias modes for comparison when writeback does not matter.
301 da_x = (0 | 0 | 0) << 21, // Decrement after.
302 ia_x = (0 | 4 | 0) << 21, // Increment after.
303 db_x = (8 | 0 | 0) << 21, // Decrement before.
304 ib_x = (8 | 4 | 0) << 21, // Increment before.
305
306 kBlockAddrModeMask = (8 | 4 | 1) << 21
307 };
308
309 // Coprocessor load/store operand size.
310 enum LFlag {
311 Long = 1 << 22, // Long load/store coprocessor.
312 Short = 0 << 22 // Short load/store coprocessor.
313 };
314
315 // NEON data type
316 enum NeonDataType {
317 NeonS8 = 0x1, // U = 0, imm3 = 0b001
318 NeonS16 = 0x2, // U = 0, imm3 = 0b010
319 NeonS32 = 0x4, // U = 0, imm3 = 0b100
320 NeonU8 = 1 << 24 | 0x1, // U = 1, imm3 = 0b001
321 NeonU16 = 1 << 24 | 0x2, // U = 1, imm3 = 0b010
322 NeonU32 = 1 << 24 | 0x4, // U = 1, imm3 = 0b100
323 NeonDataTypeSizeMask = 0x7,
324 NeonDataTypeUMask = 1 << 24
325 };
326
327 enum NeonListType { nlt_1 = 0x7, nlt_2 = 0xA, nlt_3 = 0x6, nlt_4 = 0x2 };
328
329 enum NeonSize { Neon8 = 0x0, Neon16 = 0x1, Neon32 = 0x2, Neon64 = 0x3 };
330
331 // -----------------------------------------------------------------------------
332 // Supervisor Call (svc) specific support.
333
334 // Special Software Interrupt codes when used in the presence of the ARM
335 // simulator.
336 // svc (formerly swi) provides a 24bit immediate value. Use bits 22:0 for
337 // standard SoftwareInterrupCode. Bit 23 is reserved for the stop feature.
338 enum SoftwareInterruptCodes {
339 // transition to C code
340 kCallRtRedirected = 0x10,
341 // break point
342 kBreakpoint = 0x20,
343 // stop
344 kStopCode = 1 << 23
345 };
346 const uint32_t kStopCodeMask = kStopCode - 1;
347 const uint32_t kMaxStopCode = kStopCode - 1;
348 const int32_t kDefaultStopCode = -1;
349
350 // Type of VFP register. Determines register encoding.
351 enum VFPRegPrecision { kSinglePrecision = 0, kDoublePrecision = 1 };
352
353 // VFP FPSCR constants.
354 enum VFPConversionMode { kFPSCRRounding = 0, kDefaultRoundToZero = 1 };
355
356 // This mask does not include the "inexact" or "input denormal" cumulative
357 // exceptions flags, because we usually don't want to check for it.
358 const uint32_t kVFPExceptionMask = 0xf;
359 const uint32_t kVFPInvalidOpExceptionBit = 1 << 0;
360 const uint32_t kVFPOverflowExceptionBit = 1 << 2;
361 const uint32_t kVFPUnderflowExceptionBit = 1 << 3;
362 const uint32_t kVFPInexactExceptionBit = 1 << 4;
363 const uint32_t kVFPFlushToZeroMask = 1 << 24;
364 const uint32_t kVFPDefaultNaNModeControlBit = 1 << 25;
365
366 const uint32_t kVFPNConditionFlagBit = 1 << 31;
367 const uint32_t kVFPZConditionFlagBit = 1 << 30;
368 const uint32_t kVFPCConditionFlagBit = 1 << 29;
369 const uint32_t kVFPVConditionFlagBit = 1 << 28;
370
371 // VFP rounding modes. See ARM DDI 0406B Page A2-29.
372 enum VFPRoundingMode {
373 RN = 0 << 22, // Round to Nearest.
374 RP = 1 << 22, // Round towards Plus Infinity.
375 RM = 2 << 22, // Round towards Minus Infinity.
376 RZ = 3 << 22, // Round towards zero.
377
378 // Aliases.
379 kRoundToNearest = RN,
380 kRoundToPlusInf = RP,
381 kRoundToMinusInf = RM,
382 kRoundToZero = RZ
383 };
384
385 const uint32_t kVFPRoundingModeMask = 3 << 22;
386
387 enum CheckForInexactConversion {
388 kCheckForInexactConversion,
389 kDontCheckForInexactConversion
390 };
391
392 // -----------------------------------------------------------------------------
393 // Hints.
394
395 // Branch hints are not used on the ARM. They are defined so that they can
396 // appear in shared function signatures, but will be ignored in ARM
397 // implementations.
398 enum Hint { no_hint };
399
400 // Hints are not used on the arm. Negating is trivial.
NegateHint(Hint ignored)401 inline Hint NegateHint(Hint ignored) { return no_hint; }
402
403 // -----------------------------------------------------------------------------
404 // Instruction abstraction.
405
406 // The class Instruction enables access to individual fields defined in the ARM
407 // architecture instruction set encoding as described in figure A3-1.
408 // Note that the Assembler uses typedef int32_t Instr.
409 //
410 // Example: Test whether the instruction at ptr does set the condition code
411 // bits.
412 //
413 // bool InstructionSetsConditionCodes(byte* ptr) {
414 // Instruction* instr = Instruction::At(ptr);
415 // int type = instr->TypeValue();
416 // return ((type == 0) || (type == 1)) && instr->HasS();
417 // }
418 //
419 class Instruction {
420 public:
421 enum { kInstrSize = 4, kInstrSizeLog2 = 2, kPCReadOffset = 8 };
422
423 // Helper macro to define static accessors.
424 // We use the cast to char* trick to bypass the strict anti-aliasing rules.
425 # define DECLARE_STATIC_TYPED_ACCESSOR(return_type, Name) \
426 static inline return_type Name(Instr instr) { \
427 char* temp = reinterpret_cast<char*>(&instr); \
428 return reinterpret_cast<Instruction*>(temp)->Name(); \
429 }
430
431 # define DECLARE_STATIC_ACCESSOR(Name) DECLARE_STATIC_TYPED_ACCESSOR(int, Name)
432
433 // Get the raw instruction bits.
InstructionBits()434 inline Instr InstructionBits() const {
435 return *reinterpret_cast<const Instr*>(this);
436 }
437
438 // Set the raw instruction bits to value.
SetInstructionBits(Instr value)439 inline void SetInstructionBits(Instr value) {
440 *reinterpret_cast<Instr*>(this) = value;
441 }
442
443 // Read one particular bit out of the instruction bits.
Bit(int nr)444 inline int Bit(int nr) const { return (InstructionBits() >> nr) & 1; }
445
446 // Read a bit field's value out of the instruction bits.
Bits(int hi,int lo)447 inline int Bits(int hi, int lo) const {
448 return (InstructionBits() >> lo) & ((2 << (hi - lo)) - 1);
449 }
450
451 // Read a bit field out of the instruction bits.
BitField(int hi,int lo)452 inline int BitField(int hi, int lo) const {
453 return InstructionBits() & (((2 << (hi - lo)) - 1) << lo);
454 }
455
456 // Static support.
457
458 // Read one particular bit out of the instruction bits.
Bit(Instr instr,int nr)459 static inline int Bit(Instr instr, int nr) { return (instr >> nr) & 1; }
460
461 // Read the value of a bit field out of the instruction bits.
Bits(Instr instr,int hi,int lo)462 static inline int Bits(Instr instr, int hi, int lo) {
463 return (instr >> lo) & ((2 << (hi - lo)) - 1);
464 }
465
466 // Read a bit field out of the instruction bits.
BitField(Instr instr,int hi,int lo)467 static inline int BitField(Instr instr, int hi, int lo) {
468 return instr & (((2 << (hi - lo)) - 1) << lo);
469 }
470
471 // Accessors for the different named fields used in the ARM encoding.
472 // The naming of these accessor corresponds to figure A3-1.
473 //
474 // Two kind of accessors are declared:
475 // - <Name>Field() will return the raw field, i.e. the field's bits at their
476 // original place in the instruction encoding.
477 // e.g. if instr is the 'addgt r0, r1, r2' instruction, encoded as
478 // 0xC0810002 ConditionField(instr) will return 0xC0000000.
479 // - <Name>Value() will return the field value, shifted back to bit 0.
480 // e.g. if instr is the 'addgt r0, r1, r2' instruction, encoded as
481 // 0xC0810002 ConditionField(instr) will return 0xC.
482
483 // Generally applicable fields
ConditionValue()484 inline Condition ConditionValue() const {
485 return static_cast<Condition>(Bits(31, 28));
486 }
ConditionField()487 inline Condition ConditionField() const {
488 return static_cast<Condition>(BitField(31, 28));
489 }
490 DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionValue);
491 DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionField);
492
TypeValue()493 inline int TypeValue() const { return Bits(27, 25); }
SpecialValue()494 inline int SpecialValue() const { return Bits(27, 23); }
495
RnValue()496 inline int RnValue() const { return Bits(19, 16); }
497 DECLARE_STATIC_ACCESSOR(RnValue);
RdValue()498 inline int RdValue() const { return Bits(15, 12); }
499 DECLARE_STATIC_ACCESSOR(RdValue);
500
CoprocessorValue()501 inline int CoprocessorValue() const { return Bits(11, 8); }
502 // Support for VFP.
503 // Vn(19-16) | Vd(15-12) | Vm(3-0)
VnValue()504 inline int VnValue() const { return Bits(19, 16); }
VmValue()505 inline int VmValue() const { return Bits(3, 0); }
VdValue()506 inline int VdValue() const { return Bits(15, 12); }
NValue()507 inline int NValue() const { return Bit(7); }
MValue()508 inline int MValue() const { return Bit(5); }
DValue()509 inline int DValue() const { return Bit(22); }
RtValue()510 inline int RtValue() const { return Bits(15, 12); }
PValue()511 inline int PValue() const { return Bit(24); }
UValue()512 inline int UValue() const { return Bit(23); }
Opc1Value()513 inline int Opc1Value() const { return (Bit(23) << 2) | Bits(21, 20); }
Opc2Value()514 inline int Opc2Value() const { return Bits(19, 16); }
Opc3Value()515 inline int Opc3Value() const { return Bits(7, 6); }
SzValue()516 inline int SzValue() const { return Bit(8); }
VLValue()517 inline int VLValue() const { return Bit(20); }
VCValue()518 inline int VCValue() const { return Bit(8); }
VAValue()519 inline int VAValue() const { return Bits(23, 21); }
VBValue()520 inline int VBValue() const { return Bits(6, 5); }
VFPNRegValue(VFPRegPrecision pre)521 inline int VFPNRegValue(VFPRegPrecision pre) {
522 return VFPGlueRegValue(pre, 16, 7);
523 }
VFPMRegValue(VFPRegPrecision pre)524 inline int VFPMRegValue(VFPRegPrecision pre) {
525 return VFPGlueRegValue(pre, 0, 5);
526 }
VFPDRegValue(VFPRegPrecision pre)527 inline int VFPDRegValue(VFPRegPrecision pre) {
528 return VFPGlueRegValue(pre, 12, 22);
529 }
530
531 // Fields used in Data processing instructions
OpcodeValue()532 inline int OpcodeValue() const { return static_cast<Opcode>(Bits(24, 21)); }
OpcodeField()533 inline Opcode OpcodeField() const {
534 return static_cast<Opcode>(BitField(24, 21));
535 }
SValue()536 inline int SValue() const { return Bit(20); }
537 // with register
RmValue()538 inline int RmValue() const { return Bits(3, 0); }
539 DECLARE_STATIC_ACCESSOR(RmValue);
ShiftValue()540 inline int ShiftValue() const { return static_cast<ShiftOp>(Bits(6, 5)); }
ShiftField()541 inline ShiftOp ShiftField() const {
542 return static_cast<ShiftOp>(BitField(6, 5));
543 }
RegShiftValue()544 inline int RegShiftValue() const { return Bit(4); }
RsValue()545 inline int RsValue() const { return Bits(11, 8); }
ShiftAmountValue()546 inline int ShiftAmountValue() const { return Bits(11, 7); }
547 // with immediate
RotateValue()548 inline int RotateValue() const { return Bits(11, 8); }
549 DECLARE_STATIC_ACCESSOR(RotateValue);
Immed8Value()550 inline int Immed8Value() const { return Bits(7, 0); }
551 DECLARE_STATIC_ACCESSOR(Immed8Value);
Immed4Value()552 inline int Immed4Value() const { return Bits(19, 16); }
ImmedMovwMovtValue()553 inline int ImmedMovwMovtValue() const {
554 return Immed4Value() << 12 | Offset12Value();
555 }
556 DECLARE_STATIC_ACCESSOR(ImmedMovwMovtValue);
557
558 // Fields used in Load/Store instructions
PUValue()559 inline int PUValue() const { return Bits(24, 23); }
PUField()560 inline int PUField() const { return BitField(24, 23); }
BValue()561 inline int BValue() const { return Bit(22); }
WValue()562 inline int WValue() const { return Bit(21); }
LValue()563 inline int LValue() const { return Bit(20); }
564 // with register uses same fields as Data processing instructions above
565 // with immediate
Offset12Value()566 inline int Offset12Value() const { return Bits(11, 0); }
567 // multiple
RlistValue()568 inline int RlistValue() const { return Bits(15, 0); }
569 // extra loads and stores
SignValue()570 inline int SignValue() const { return Bit(6); }
HValue()571 inline int HValue() const { return Bit(5); }
ImmedHValue()572 inline int ImmedHValue() const { return Bits(11, 8); }
ImmedLValue()573 inline int ImmedLValue() const { return Bits(3, 0); }
574
575 // Fields used in Branch instructions
LinkValue()576 inline int LinkValue() const { return Bit(24); }
SImmed24Value()577 inline int SImmed24Value() const { return ((InstructionBits() << 8) >> 8); }
578
579 // Fields used in Software interrupt instructions
SvcValue()580 inline SoftwareInterruptCodes SvcValue() const {
581 return static_cast<SoftwareInterruptCodes>(Bits(23, 0));
582 }
583
584 // Test for special encodings of type 0 instructions (extra loads and stores,
585 // as well as multiplications).
IsSpecialType0()586 inline bool IsSpecialType0() const { return (Bit(7) == 1) && (Bit(4) == 1); }
587
588 // Test for miscellaneous instructions encodings of type 0 instructions.
IsMiscType0()589 inline bool IsMiscType0() const {
590 return (Bit(24) == 1) && (Bit(23) == 0) && (Bit(20) == 0) &&
591 ((Bit(7) == 0));
592 }
593
594 // Test for a nop instruction, which falls under type 1.
IsNopType1()595 inline bool IsNopType1() const { return Bits(24, 0) == 0x0120F000; }
596
597 // Test for a nop instruction, which falls under type 1.
IsCsdbType1()598 inline bool IsCsdbType1() const { return Bits(24, 0) == 0x0120F014; }
599
600 // Test for a stop instruction.
IsStop()601 inline bool IsStop() const {
602 return (TypeValue() == 7) && (Bit(24) == 1) && (SvcValue() >= kStopCode);
603 }
604
605 // Special accessors that test for existence of a value.
HasS()606 inline bool HasS() const { return SValue() == 1; }
HasB()607 inline bool HasB() const { return BValue() == 1; }
HasW()608 inline bool HasW() const { return WValue() == 1; }
HasL()609 inline bool HasL() const { return LValue() == 1; }
HasU()610 inline bool HasU() const { return UValue() == 1; }
HasSign()611 inline bool HasSign() const { return SignValue() == 1; }
HasH()612 inline bool HasH() const { return HValue() == 1; }
HasLink()613 inline bool HasLink() const { return LinkValue() == 1; }
614
615 // Decoding the double immediate in the vmov instruction.
616 double DoubleImmedVmov() const;
617
618 // Instructions are read of out a code stream. The only way to get a
619 // reference to an instruction is to convert a pointer. There is no way
620 // to allocate or create instances of class Instruction.
621 // Use the At(pc) function to create references to Instruction.
At(uint8_t * pc)622 static Instruction* At(uint8_t* pc) {
623 return reinterpret_cast<Instruction*>(pc);
624 }
625
626 private:
627 // Join split register codes, depending on single or double precision.
628 // four_bit is the position of the least-significant bit of the four
629 // bit specifier. one_bit is the position of the additional single bit
630 // specifier.
VFPGlueRegValue(VFPRegPrecision pre,int four_bit,int one_bit)631 inline int VFPGlueRegValue(VFPRegPrecision pre, int four_bit, int one_bit) {
632 if (pre == kSinglePrecision) {
633 return (Bits(four_bit + 3, four_bit) << 1) | Bit(one_bit);
634 }
635 return (Bit(one_bit) << 4) | Bits(four_bit + 3, four_bit);
636 }
637
638 // We need to prevent the creation of instances of class Instruction.
639 Instruction() = delete;
640 Instruction(const Instruction&) = delete;
641 void operator=(const Instruction&) = delete;
642 };
643
644 // Helper functions for converting between register numbers and names.
645 class Registers {
646 public:
647 // Return the name of the register.
648 static const char* Name(int reg);
649
650 // Lookup the register number for the name provided.
651 static int Number(const char* name);
652
653 struct RegisterAlias {
654 int reg;
655 const char* name;
656 };
657
658 private:
659 static const char* names_[kNumRegisters];
660 static const RegisterAlias aliases_[];
661 };
662
663 // Helper functions for converting between VFP register numbers and names.
664 class VFPRegisters {
665 public:
666 // Return the name of the register.
667 static const char* Name(int reg, bool is_double);
668
669 // Lookup the register number for the name provided.
670 // Set flag pointed by is_double to true if register
671 // is double-precision.
672 static int Number(const char* name, bool* is_double);
673
674 private:
675 static const char* names_[kNumVFPRegisters];
676 };
677
678 } // namespace disasm
679 } // namespace jit
680 } // namespace js
681
682 #endif // JS_DISASM_ARM
683
684 #endif // jit_arm_disasm_Constants_arm_h
685