1 /*
2 * Copyright (c) 2017 The WebM project authors. All Rights Reserved.
3 *
4 * Use of this source code is governed by a BSD-style license
5 * that can be found in the LICENSE file in the root of the source
6 * tree. An additional intellectual property rights grant can be found
7 * in the file PATENTS. All contributing project authors may
8 * be found in the AUTHORS file in the root of the source tree.
9 */
10
11 #include <arm_neon.h>
12
13 #include "./vpx_config.h"
14 #include "./vpx_dsp_rtcd.h"
15 #include "vpx_dsp/txfm_common.h"
16 #include "vpx_dsp/vpx_dsp_common.h"
17 #include "vpx_dsp/arm/idct_neon.h"
18 #include "vpx_dsp/arm/mem_neon.h"
19 #include "vpx_dsp/arm/transpose_neon.h"
20
vpx_fdct4x4_neon(const int16_t * input,tran_low_t * final_output,int stride)21 void vpx_fdct4x4_neon(const int16_t *input, tran_low_t *final_output,
22 int stride) {
23 int i;
24 // input[M * stride] * 16
25 int16x4_t input_0 = vshl_n_s16(vld1_s16(input + 0 * stride), 4);
26 int16x4_t input_1 = vshl_n_s16(vld1_s16(input + 1 * stride), 4);
27 int16x4_t input_2 = vshl_n_s16(vld1_s16(input + 2 * stride), 4);
28 int16x4_t input_3 = vshl_n_s16(vld1_s16(input + 3 * stride), 4);
29
30 // If the very first value != 0, then add 1.
31 if (input[0] != 0) {
32 const int16x4_t one = vreinterpret_s16_s64(vdup_n_s64(1));
33 input_0 = vadd_s16(input_0, one);
34 }
35
36 for (i = 0; i < 2; ++i) {
37 const int16x8_t input_01 = vcombine_s16(input_0, input_1);
38 const int16x8_t input_32 = vcombine_s16(input_3, input_2);
39
40 // in_0 +/- in_3, in_1 +/- in_2
41 const int16x8_t s_01 = vaddq_s16(input_01, input_32);
42 const int16x8_t s_32 = vsubq_s16(input_01, input_32);
43
44 // step_0 +/- step_1, step_2 +/- step_3
45 const int16x4_t s_0 = vget_low_s16(s_01);
46 const int16x4_t s_1 = vget_high_s16(s_01);
47 const int16x4_t s_2 = vget_high_s16(s_32);
48 const int16x4_t s_3 = vget_low_s16(s_32);
49
50 // (s_0 +/- s_1) * cospi_16_64
51 // Must expand all elements to s32. See 'needs32' comment in fwd_txfm.c.
52 const int32x4_t s_0_p_s_1 = vaddl_s16(s_0, s_1);
53 const int32x4_t s_0_m_s_1 = vsubl_s16(s_0, s_1);
54 const int32x4_t temp1 = vmulq_n_s32(s_0_p_s_1, cospi_16_64);
55 const int32x4_t temp2 = vmulq_n_s32(s_0_m_s_1, cospi_16_64);
56
57 // fdct_round_shift
58 int16x4_t out_0 = vrshrn_n_s32(temp1, DCT_CONST_BITS);
59 int16x4_t out_2 = vrshrn_n_s32(temp2, DCT_CONST_BITS);
60
61 // s_3 * cospi_8_64 + s_2 * cospi_24_64
62 // s_3 * cospi_24_64 - s_2 * cospi_8_64
63 const int32x4_t s_3_cospi_8_64 = vmull_n_s16(s_3, cospi_8_64);
64 const int32x4_t s_3_cospi_24_64 = vmull_n_s16(s_3, cospi_24_64);
65
66 const int32x4_t temp3 = vmlal_n_s16(s_3_cospi_8_64, s_2, cospi_24_64);
67 const int32x4_t temp4 = vmlsl_n_s16(s_3_cospi_24_64, s_2, cospi_8_64);
68
69 // fdct_round_shift
70 int16x4_t out_1 = vrshrn_n_s32(temp3, DCT_CONST_BITS);
71 int16x4_t out_3 = vrshrn_n_s32(temp4, DCT_CONST_BITS);
72
73 transpose_s16_4x4d(&out_0, &out_1, &out_2, &out_3);
74
75 input_0 = out_0;
76 input_1 = out_1;
77 input_2 = out_2;
78 input_3 = out_3;
79 }
80
81 {
82 // Not quite a rounding shift. Only add 1 despite shifting by 2.
83 const int16x8_t one = vdupq_n_s16(1);
84 int16x8_t out_01 = vcombine_s16(input_0, input_1);
85 int16x8_t out_23 = vcombine_s16(input_2, input_3);
86 out_01 = vshrq_n_s16(vaddq_s16(out_01, one), 2);
87 out_23 = vshrq_n_s16(vaddq_s16(out_23, one), 2);
88 store_s16q_to_tran_low(final_output + 0 * 8, out_01);
89 store_s16q_to_tran_low(final_output + 1 * 8, out_23);
90 }
91 }
92