1 /*
2 * Copyright (c) 2015 The WebM project authors. All Rights Reserved.
3 *
4 * Use of this source code is governed by a BSD-style license
5 * that can be found in the LICENSE file in the root of the source
6 * tree. An additional intellectual property rights grant can be found
7 * in the file PATENTS. All contributing project authors may
8 * be found in the AUTHORS file in the root of the source tree.
9 */
10
11 #include <arm_neon.h>
12
13 #include "./vpx_config.h"
14 #include "./vpx_dsp_rtcd.h"
15 #include "vpx_dsp/txfm_common.h"
16 #include "vpx_dsp/vpx_dsp_common.h"
17 #include "vpx_dsp/arm/idct_neon.h"
18 #include "vpx_dsp/arm/mem_neon.h"
19
vpx_fdct8x8_neon(const int16_t * input,tran_low_t * final_output,int stride)20 void vpx_fdct8x8_neon(const int16_t *input, tran_low_t *final_output,
21 int stride) {
22 int i;
23 // stage 1
24 int16x8_t input_0 = vshlq_n_s16(vld1q_s16(&input[0 * stride]), 2);
25 int16x8_t input_1 = vshlq_n_s16(vld1q_s16(&input[1 * stride]), 2);
26 int16x8_t input_2 = vshlq_n_s16(vld1q_s16(&input[2 * stride]), 2);
27 int16x8_t input_3 = vshlq_n_s16(vld1q_s16(&input[3 * stride]), 2);
28 int16x8_t input_4 = vshlq_n_s16(vld1q_s16(&input[4 * stride]), 2);
29 int16x8_t input_5 = vshlq_n_s16(vld1q_s16(&input[5 * stride]), 2);
30 int16x8_t input_6 = vshlq_n_s16(vld1q_s16(&input[6 * stride]), 2);
31 int16x8_t input_7 = vshlq_n_s16(vld1q_s16(&input[7 * stride]), 2);
32 for (i = 0; i < 2; ++i) {
33 int16x8_t out_0, out_1, out_2, out_3, out_4, out_5, out_6, out_7;
34 const int16x8_t v_s0 = vaddq_s16(input_0, input_7);
35 const int16x8_t v_s1 = vaddq_s16(input_1, input_6);
36 const int16x8_t v_s2 = vaddq_s16(input_2, input_5);
37 const int16x8_t v_s3 = vaddq_s16(input_3, input_4);
38 const int16x8_t v_s4 = vsubq_s16(input_3, input_4);
39 const int16x8_t v_s5 = vsubq_s16(input_2, input_5);
40 const int16x8_t v_s6 = vsubq_s16(input_1, input_6);
41 const int16x8_t v_s7 = vsubq_s16(input_0, input_7);
42 // fdct4(step, step);
43 int16x8_t v_x0 = vaddq_s16(v_s0, v_s3);
44 int16x8_t v_x1 = vaddq_s16(v_s1, v_s2);
45 int16x8_t v_x2 = vsubq_s16(v_s1, v_s2);
46 int16x8_t v_x3 = vsubq_s16(v_s0, v_s3);
47 // fdct4(step, step);
48 int32x4_t v_t0_lo = vaddl_s16(vget_low_s16(v_x0), vget_low_s16(v_x1));
49 int32x4_t v_t0_hi = vaddl_s16(vget_high_s16(v_x0), vget_high_s16(v_x1));
50 int32x4_t v_t1_lo = vsubl_s16(vget_low_s16(v_x0), vget_low_s16(v_x1));
51 int32x4_t v_t1_hi = vsubl_s16(vget_high_s16(v_x0), vget_high_s16(v_x1));
52 int32x4_t v_t2_lo = vmull_n_s16(vget_low_s16(v_x2), cospi_24_64);
53 int32x4_t v_t2_hi = vmull_n_s16(vget_high_s16(v_x2), cospi_24_64);
54 int32x4_t v_t3_lo = vmull_n_s16(vget_low_s16(v_x3), cospi_24_64);
55 int32x4_t v_t3_hi = vmull_n_s16(vget_high_s16(v_x3), cospi_24_64);
56 v_t2_lo = vmlal_n_s16(v_t2_lo, vget_low_s16(v_x3), cospi_8_64);
57 v_t2_hi = vmlal_n_s16(v_t2_hi, vget_high_s16(v_x3), cospi_8_64);
58 v_t3_lo = vmlsl_n_s16(v_t3_lo, vget_low_s16(v_x2), cospi_8_64);
59 v_t3_hi = vmlsl_n_s16(v_t3_hi, vget_high_s16(v_x2), cospi_8_64);
60 v_t0_lo = vmulq_n_s32(v_t0_lo, cospi_16_64);
61 v_t0_hi = vmulq_n_s32(v_t0_hi, cospi_16_64);
62 v_t1_lo = vmulq_n_s32(v_t1_lo, cospi_16_64);
63 v_t1_hi = vmulq_n_s32(v_t1_hi, cospi_16_64);
64 {
65 const int16x4_t a = vrshrn_n_s32(v_t0_lo, DCT_CONST_BITS);
66 const int16x4_t b = vrshrn_n_s32(v_t0_hi, DCT_CONST_BITS);
67 const int16x4_t c = vrshrn_n_s32(v_t1_lo, DCT_CONST_BITS);
68 const int16x4_t d = vrshrn_n_s32(v_t1_hi, DCT_CONST_BITS);
69 const int16x4_t e = vrshrn_n_s32(v_t2_lo, DCT_CONST_BITS);
70 const int16x4_t f = vrshrn_n_s32(v_t2_hi, DCT_CONST_BITS);
71 const int16x4_t g = vrshrn_n_s32(v_t3_lo, DCT_CONST_BITS);
72 const int16x4_t h = vrshrn_n_s32(v_t3_hi, DCT_CONST_BITS);
73 out_0 = vcombine_s16(a, c); // 00 01 02 03 40 41 42 43
74 out_2 = vcombine_s16(e, g); // 20 21 22 23 60 61 62 63
75 out_4 = vcombine_s16(b, d); // 04 05 06 07 44 45 46 47
76 out_6 = vcombine_s16(f, h); // 24 25 26 27 64 65 66 67
77 }
78 // Stage 2
79 v_x0 = vsubq_s16(v_s6, v_s5);
80 v_x1 = vaddq_s16(v_s6, v_s5);
81 v_t0_lo = vmull_n_s16(vget_low_s16(v_x0), cospi_16_64);
82 v_t0_hi = vmull_n_s16(vget_high_s16(v_x0), cospi_16_64);
83 v_t1_lo = vmull_n_s16(vget_low_s16(v_x1), cospi_16_64);
84 v_t1_hi = vmull_n_s16(vget_high_s16(v_x1), cospi_16_64);
85 {
86 const int16x4_t a = vrshrn_n_s32(v_t0_lo, DCT_CONST_BITS);
87 const int16x4_t b = vrshrn_n_s32(v_t0_hi, DCT_CONST_BITS);
88 const int16x4_t c = vrshrn_n_s32(v_t1_lo, DCT_CONST_BITS);
89 const int16x4_t d = vrshrn_n_s32(v_t1_hi, DCT_CONST_BITS);
90 const int16x8_t ab = vcombine_s16(a, b);
91 const int16x8_t cd = vcombine_s16(c, d);
92 // Stage 3
93 v_x0 = vaddq_s16(v_s4, ab);
94 v_x1 = vsubq_s16(v_s4, ab);
95 v_x2 = vsubq_s16(v_s7, cd);
96 v_x3 = vaddq_s16(v_s7, cd);
97 }
98 // Stage 4
99 v_t0_lo = vmull_n_s16(vget_low_s16(v_x3), cospi_4_64);
100 v_t0_hi = vmull_n_s16(vget_high_s16(v_x3), cospi_4_64);
101 v_t0_lo = vmlal_n_s16(v_t0_lo, vget_low_s16(v_x0), cospi_28_64);
102 v_t0_hi = vmlal_n_s16(v_t0_hi, vget_high_s16(v_x0), cospi_28_64);
103 v_t1_lo = vmull_n_s16(vget_low_s16(v_x1), cospi_12_64);
104 v_t1_hi = vmull_n_s16(vget_high_s16(v_x1), cospi_12_64);
105 v_t1_lo = vmlal_n_s16(v_t1_lo, vget_low_s16(v_x2), cospi_20_64);
106 v_t1_hi = vmlal_n_s16(v_t1_hi, vget_high_s16(v_x2), cospi_20_64);
107 v_t2_lo = vmull_n_s16(vget_low_s16(v_x2), cospi_12_64);
108 v_t2_hi = vmull_n_s16(vget_high_s16(v_x2), cospi_12_64);
109 v_t2_lo = vmlsl_n_s16(v_t2_lo, vget_low_s16(v_x1), cospi_20_64);
110 v_t2_hi = vmlsl_n_s16(v_t2_hi, vget_high_s16(v_x1), cospi_20_64);
111 v_t3_lo = vmull_n_s16(vget_low_s16(v_x3), cospi_28_64);
112 v_t3_hi = vmull_n_s16(vget_high_s16(v_x3), cospi_28_64);
113 v_t3_lo = vmlsl_n_s16(v_t3_lo, vget_low_s16(v_x0), cospi_4_64);
114 v_t3_hi = vmlsl_n_s16(v_t3_hi, vget_high_s16(v_x0), cospi_4_64);
115 {
116 const int16x4_t a = vrshrn_n_s32(v_t0_lo, DCT_CONST_BITS);
117 const int16x4_t b = vrshrn_n_s32(v_t0_hi, DCT_CONST_BITS);
118 const int16x4_t c = vrshrn_n_s32(v_t1_lo, DCT_CONST_BITS);
119 const int16x4_t d = vrshrn_n_s32(v_t1_hi, DCT_CONST_BITS);
120 const int16x4_t e = vrshrn_n_s32(v_t2_lo, DCT_CONST_BITS);
121 const int16x4_t f = vrshrn_n_s32(v_t2_hi, DCT_CONST_BITS);
122 const int16x4_t g = vrshrn_n_s32(v_t3_lo, DCT_CONST_BITS);
123 const int16x4_t h = vrshrn_n_s32(v_t3_hi, DCT_CONST_BITS);
124 out_1 = vcombine_s16(a, c); // 10 11 12 13 50 51 52 53
125 out_3 = vcombine_s16(e, g); // 30 31 32 33 70 71 72 73
126 out_5 = vcombine_s16(b, d); // 14 15 16 17 54 55 56 57
127 out_7 = vcombine_s16(f, h); // 34 35 36 37 74 75 76 77
128 }
129 // transpose 8x8
130 // Can't use transpose_s16_8x8() because the values are arranged in two 4x8
131 // columns.
132 {
133 // 00 01 02 03 40 41 42 43
134 // 10 11 12 13 50 51 52 53
135 // 20 21 22 23 60 61 62 63
136 // 30 31 32 33 70 71 72 73
137 // 04 05 06 07 44 45 46 47
138 // 14 15 16 17 54 55 56 57
139 // 24 25 26 27 64 65 66 67
140 // 34 35 36 37 74 75 76 77
141 const int32x4x2_t r02_s32 =
142 vtrnq_s32(vreinterpretq_s32_s16(out_0), vreinterpretq_s32_s16(out_2));
143 const int32x4x2_t r13_s32 =
144 vtrnq_s32(vreinterpretq_s32_s16(out_1), vreinterpretq_s32_s16(out_3));
145 const int32x4x2_t r46_s32 =
146 vtrnq_s32(vreinterpretq_s32_s16(out_4), vreinterpretq_s32_s16(out_6));
147 const int32x4x2_t r57_s32 =
148 vtrnq_s32(vreinterpretq_s32_s16(out_5), vreinterpretq_s32_s16(out_7));
149 const int16x8x2_t r01_s16 =
150 vtrnq_s16(vreinterpretq_s16_s32(r02_s32.val[0]),
151 vreinterpretq_s16_s32(r13_s32.val[0]));
152 const int16x8x2_t r23_s16 =
153 vtrnq_s16(vreinterpretq_s16_s32(r02_s32.val[1]),
154 vreinterpretq_s16_s32(r13_s32.val[1]));
155 const int16x8x2_t r45_s16 =
156 vtrnq_s16(vreinterpretq_s16_s32(r46_s32.val[0]),
157 vreinterpretq_s16_s32(r57_s32.val[0]));
158 const int16x8x2_t r67_s16 =
159 vtrnq_s16(vreinterpretq_s16_s32(r46_s32.val[1]),
160 vreinterpretq_s16_s32(r57_s32.val[1]));
161 input_0 = r01_s16.val[0];
162 input_1 = r01_s16.val[1];
163 input_2 = r23_s16.val[0];
164 input_3 = r23_s16.val[1];
165 input_4 = r45_s16.val[0];
166 input_5 = r45_s16.val[1];
167 input_6 = r67_s16.val[0];
168 input_7 = r67_s16.val[1];
169 // 00 10 20 30 40 50 60 70
170 // 01 11 21 31 41 51 61 71
171 // 02 12 22 32 42 52 62 72
172 // 03 13 23 33 43 53 63 73
173 // 04 14 24 34 44 54 64 74
174 // 05 15 25 35 45 55 65 75
175 // 06 16 26 36 46 56 66 76
176 // 07 17 27 37 47 57 67 77
177 }
178 } // for
179 {
180 // from vpx_dct_sse2.c
181 // Post-condition (division by two)
182 // division of two 16 bits signed numbers using shifts
183 // n / 2 = (n - (n >> 15)) >> 1
184 const int16x8_t sign_in0 = vshrq_n_s16(input_0, 15);
185 const int16x8_t sign_in1 = vshrq_n_s16(input_1, 15);
186 const int16x8_t sign_in2 = vshrq_n_s16(input_2, 15);
187 const int16x8_t sign_in3 = vshrq_n_s16(input_3, 15);
188 const int16x8_t sign_in4 = vshrq_n_s16(input_4, 15);
189 const int16x8_t sign_in5 = vshrq_n_s16(input_5, 15);
190 const int16x8_t sign_in6 = vshrq_n_s16(input_6, 15);
191 const int16x8_t sign_in7 = vshrq_n_s16(input_7, 15);
192 input_0 = vhsubq_s16(input_0, sign_in0);
193 input_1 = vhsubq_s16(input_1, sign_in1);
194 input_2 = vhsubq_s16(input_2, sign_in2);
195 input_3 = vhsubq_s16(input_3, sign_in3);
196 input_4 = vhsubq_s16(input_4, sign_in4);
197 input_5 = vhsubq_s16(input_5, sign_in5);
198 input_6 = vhsubq_s16(input_6, sign_in6);
199 input_7 = vhsubq_s16(input_7, sign_in7);
200 // store results
201 store_s16q_to_tran_low(final_output + 0 * 8, input_0);
202 store_s16q_to_tran_low(final_output + 1 * 8, input_1);
203 store_s16q_to_tran_low(final_output + 2 * 8, input_2);
204 store_s16q_to_tran_low(final_output + 3 * 8, input_3);
205 store_s16q_to_tran_low(final_output + 4 * 8, input_4);
206 store_s16q_to_tran_low(final_output + 5 * 8, input_5);
207 store_s16q_to_tran_low(final_output + 6 * 8, input_6);
208 store_s16q_to_tran_low(final_output + 7 * 8, input_7);
209 }
210 }
211