1 /*
2 * Copyright (c) 2016, Alliance for Open Media. All rights reserved
3 *
4 * This source code is subject to the terms of the BSD 2 Clause License and
5 * the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
6 * was not distributed with this source code in the LICENSE file, you can
7 * obtain it at www.aomedia.org/license/software. If the Alliance for Open
8 * Media Patent License 1.0 was not distributed with this source code in the
9 * PATENTS file, you can obtain it at www.aomedia.org/license/patent.
10 */
11
12 #include <arm_neon.h>
13
14 #include "config/aom_config.h"
15
16 #include "aom_dsp/txfm_common.h"
17
aom_fdct8x8_neon(const int16_t * input,int16_t * final_output,int stride)18 void aom_fdct8x8_neon(const int16_t *input, int16_t *final_output, int stride) {
19 int i;
20 // stage 1
21 int16x8_t input_0 = vshlq_n_s16(vld1q_s16(&input[0 * stride]), 2);
22 int16x8_t input_1 = vshlq_n_s16(vld1q_s16(&input[1 * stride]), 2);
23 int16x8_t input_2 = vshlq_n_s16(vld1q_s16(&input[2 * stride]), 2);
24 int16x8_t input_3 = vshlq_n_s16(vld1q_s16(&input[3 * stride]), 2);
25 int16x8_t input_4 = vshlq_n_s16(vld1q_s16(&input[4 * stride]), 2);
26 int16x8_t input_5 = vshlq_n_s16(vld1q_s16(&input[5 * stride]), 2);
27 int16x8_t input_6 = vshlq_n_s16(vld1q_s16(&input[6 * stride]), 2);
28 int16x8_t input_7 = vshlq_n_s16(vld1q_s16(&input[7 * stride]), 2);
29 for (i = 0; i < 2; ++i) {
30 int16x8_t out_0, out_1, out_2, out_3, out_4, out_5, out_6, out_7;
31 const int16x8_t v_s0 = vaddq_s16(input_0, input_7);
32 const int16x8_t v_s1 = vaddq_s16(input_1, input_6);
33 const int16x8_t v_s2 = vaddq_s16(input_2, input_5);
34 const int16x8_t v_s3 = vaddq_s16(input_3, input_4);
35 const int16x8_t v_s4 = vsubq_s16(input_3, input_4);
36 const int16x8_t v_s5 = vsubq_s16(input_2, input_5);
37 const int16x8_t v_s6 = vsubq_s16(input_1, input_6);
38 const int16x8_t v_s7 = vsubq_s16(input_0, input_7);
39 // fdct4(step, step);
40 int16x8_t v_x0 = vaddq_s16(v_s0, v_s3);
41 int16x8_t v_x1 = vaddq_s16(v_s1, v_s2);
42 int16x8_t v_x2 = vsubq_s16(v_s1, v_s2);
43 int16x8_t v_x3 = vsubq_s16(v_s0, v_s3);
44 // fdct4(step, step);
45 int32x4_t v_t0_lo = vaddl_s16(vget_low_s16(v_x0), vget_low_s16(v_x1));
46 int32x4_t v_t0_hi = vaddl_s16(vget_high_s16(v_x0), vget_high_s16(v_x1));
47 int32x4_t v_t1_lo = vsubl_s16(vget_low_s16(v_x0), vget_low_s16(v_x1));
48 int32x4_t v_t1_hi = vsubl_s16(vget_high_s16(v_x0), vget_high_s16(v_x1));
49 int32x4_t v_t2_lo = vmull_n_s16(vget_low_s16(v_x2), (int16_t)cospi_24_64);
50 int32x4_t v_t2_hi = vmull_n_s16(vget_high_s16(v_x2), (int16_t)cospi_24_64);
51 int32x4_t v_t3_lo = vmull_n_s16(vget_low_s16(v_x3), (int16_t)cospi_24_64);
52 int32x4_t v_t3_hi = vmull_n_s16(vget_high_s16(v_x3), (int16_t)cospi_24_64);
53 v_t2_lo = vmlal_n_s16(v_t2_lo, vget_low_s16(v_x3), (int16_t)cospi_8_64);
54 v_t2_hi = vmlal_n_s16(v_t2_hi, vget_high_s16(v_x3), (int16_t)cospi_8_64);
55 v_t3_lo = vmlsl_n_s16(v_t3_lo, vget_low_s16(v_x2), (int16_t)cospi_8_64);
56 v_t3_hi = vmlsl_n_s16(v_t3_hi, vget_high_s16(v_x2), (int16_t)cospi_8_64);
57 v_t0_lo = vmulq_n_s32(v_t0_lo, (int32_t)cospi_16_64);
58 v_t0_hi = vmulq_n_s32(v_t0_hi, (int32_t)cospi_16_64);
59 v_t1_lo = vmulq_n_s32(v_t1_lo, (int32_t)cospi_16_64);
60 v_t1_hi = vmulq_n_s32(v_t1_hi, (int32_t)cospi_16_64);
61 {
62 const int16x4_t a = vrshrn_n_s32(v_t0_lo, DCT_CONST_BITS);
63 const int16x4_t b = vrshrn_n_s32(v_t0_hi, DCT_CONST_BITS);
64 const int16x4_t c = vrshrn_n_s32(v_t1_lo, DCT_CONST_BITS);
65 const int16x4_t d = vrshrn_n_s32(v_t1_hi, DCT_CONST_BITS);
66 const int16x4_t e = vrshrn_n_s32(v_t2_lo, DCT_CONST_BITS);
67 const int16x4_t f = vrshrn_n_s32(v_t2_hi, DCT_CONST_BITS);
68 const int16x4_t g = vrshrn_n_s32(v_t3_lo, DCT_CONST_BITS);
69 const int16x4_t h = vrshrn_n_s32(v_t3_hi, DCT_CONST_BITS);
70 out_0 = vcombine_s16(a, c); // 00 01 02 03 40 41 42 43
71 out_2 = vcombine_s16(e, g); // 20 21 22 23 60 61 62 63
72 out_4 = vcombine_s16(b, d); // 04 05 06 07 44 45 46 47
73 out_6 = vcombine_s16(f, h); // 24 25 26 27 64 65 66 67
74 }
75 // Stage 2
76 v_x0 = vsubq_s16(v_s6, v_s5);
77 v_x1 = vaddq_s16(v_s6, v_s5);
78 v_t0_lo = vmull_n_s16(vget_low_s16(v_x0), (int16_t)cospi_16_64);
79 v_t0_hi = vmull_n_s16(vget_high_s16(v_x0), (int16_t)cospi_16_64);
80 v_t1_lo = vmull_n_s16(vget_low_s16(v_x1), (int16_t)cospi_16_64);
81 v_t1_hi = vmull_n_s16(vget_high_s16(v_x1), (int16_t)cospi_16_64);
82 {
83 const int16x4_t a = vrshrn_n_s32(v_t0_lo, DCT_CONST_BITS);
84 const int16x4_t b = vrshrn_n_s32(v_t0_hi, DCT_CONST_BITS);
85 const int16x4_t c = vrshrn_n_s32(v_t1_lo, DCT_CONST_BITS);
86 const int16x4_t d = vrshrn_n_s32(v_t1_hi, DCT_CONST_BITS);
87 const int16x8_t ab = vcombine_s16(a, b);
88 const int16x8_t cd = vcombine_s16(c, d);
89 // Stage 3
90 v_x0 = vaddq_s16(v_s4, ab);
91 v_x1 = vsubq_s16(v_s4, ab);
92 v_x2 = vsubq_s16(v_s7, cd);
93 v_x3 = vaddq_s16(v_s7, cd);
94 }
95 // Stage 4
96 v_t0_lo = vmull_n_s16(vget_low_s16(v_x3), (int16_t)cospi_4_64);
97 v_t0_hi = vmull_n_s16(vget_high_s16(v_x3), (int16_t)cospi_4_64);
98 v_t0_lo = vmlal_n_s16(v_t0_lo, vget_low_s16(v_x0), (int16_t)cospi_28_64);
99 v_t0_hi = vmlal_n_s16(v_t0_hi, vget_high_s16(v_x0), (int16_t)cospi_28_64);
100 v_t1_lo = vmull_n_s16(vget_low_s16(v_x1), (int16_t)cospi_12_64);
101 v_t1_hi = vmull_n_s16(vget_high_s16(v_x1), (int16_t)cospi_12_64);
102 v_t1_lo = vmlal_n_s16(v_t1_lo, vget_low_s16(v_x2), (int16_t)cospi_20_64);
103 v_t1_hi = vmlal_n_s16(v_t1_hi, vget_high_s16(v_x2), (int16_t)cospi_20_64);
104 v_t2_lo = vmull_n_s16(vget_low_s16(v_x2), (int16_t)cospi_12_64);
105 v_t2_hi = vmull_n_s16(vget_high_s16(v_x2), (int16_t)cospi_12_64);
106 v_t2_lo = vmlsl_n_s16(v_t2_lo, vget_low_s16(v_x1), (int16_t)cospi_20_64);
107 v_t2_hi = vmlsl_n_s16(v_t2_hi, vget_high_s16(v_x1), (int16_t)cospi_20_64);
108 v_t3_lo = vmull_n_s16(vget_low_s16(v_x3), (int16_t)cospi_28_64);
109 v_t3_hi = vmull_n_s16(vget_high_s16(v_x3), (int16_t)cospi_28_64);
110 v_t3_lo = vmlsl_n_s16(v_t3_lo, vget_low_s16(v_x0), (int16_t)cospi_4_64);
111 v_t3_hi = vmlsl_n_s16(v_t3_hi, vget_high_s16(v_x0), (int16_t)cospi_4_64);
112 {
113 const int16x4_t a = vrshrn_n_s32(v_t0_lo, DCT_CONST_BITS);
114 const int16x4_t b = vrshrn_n_s32(v_t0_hi, DCT_CONST_BITS);
115 const int16x4_t c = vrshrn_n_s32(v_t1_lo, DCT_CONST_BITS);
116 const int16x4_t d = vrshrn_n_s32(v_t1_hi, DCT_CONST_BITS);
117 const int16x4_t e = vrshrn_n_s32(v_t2_lo, DCT_CONST_BITS);
118 const int16x4_t f = vrshrn_n_s32(v_t2_hi, DCT_CONST_BITS);
119 const int16x4_t g = vrshrn_n_s32(v_t3_lo, DCT_CONST_BITS);
120 const int16x4_t h = vrshrn_n_s32(v_t3_hi, DCT_CONST_BITS);
121 out_1 = vcombine_s16(a, c); // 10 11 12 13 50 51 52 53
122 out_3 = vcombine_s16(e, g); // 30 31 32 33 70 71 72 73
123 out_5 = vcombine_s16(b, d); // 14 15 16 17 54 55 56 57
124 out_7 = vcombine_s16(f, h); // 34 35 36 37 74 75 76 77
125 }
126 // transpose 8x8
127 {
128 // 00 01 02 03 40 41 42 43
129 // 10 11 12 13 50 51 52 53
130 // 20 21 22 23 60 61 62 63
131 // 30 31 32 33 70 71 72 73
132 // 04 05 06 07 44 45 46 47
133 // 14 15 16 17 54 55 56 57
134 // 24 25 26 27 64 65 66 67
135 // 34 35 36 37 74 75 76 77
136 const int32x4x2_t r02_s32 =
137 vtrnq_s32(vreinterpretq_s32_s16(out_0), vreinterpretq_s32_s16(out_2));
138 const int32x4x2_t r13_s32 =
139 vtrnq_s32(vreinterpretq_s32_s16(out_1), vreinterpretq_s32_s16(out_3));
140 const int32x4x2_t r46_s32 =
141 vtrnq_s32(vreinterpretq_s32_s16(out_4), vreinterpretq_s32_s16(out_6));
142 const int32x4x2_t r57_s32 =
143 vtrnq_s32(vreinterpretq_s32_s16(out_5), vreinterpretq_s32_s16(out_7));
144 const int16x8x2_t r01_s16 =
145 vtrnq_s16(vreinterpretq_s16_s32(r02_s32.val[0]),
146 vreinterpretq_s16_s32(r13_s32.val[0]));
147 const int16x8x2_t r23_s16 =
148 vtrnq_s16(vreinterpretq_s16_s32(r02_s32.val[1]),
149 vreinterpretq_s16_s32(r13_s32.val[1]));
150 const int16x8x2_t r45_s16 =
151 vtrnq_s16(vreinterpretq_s16_s32(r46_s32.val[0]),
152 vreinterpretq_s16_s32(r57_s32.val[0]));
153 const int16x8x2_t r67_s16 =
154 vtrnq_s16(vreinterpretq_s16_s32(r46_s32.val[1]),
155 vreinterpretq_s16_s32(r57_s32.val[1]));
156 input_0 = r01_s16.val[0];
157 input_1 = r01_s16.val[1];
158 input_2 = r23_s16.val[0];
159 input_3 = r23_s16.val[1];
160 input_4 = r45_s16.val[0];
161 input_5 = r45_s16.val[1];
162 input_6 = r67_s16.val[0];
163 input_7 = r67_s16.val[1];
164 // 00 10 20 30 40 50 60 70
165 // 01 11 21 31 41 51 61 71
166 // 02 12 22 32 42 52 62 72
167 // 03 13 23 33 43 53 63 73
168 // 04 14 24 34 44 54 64 74
169 // 05 15 25 35 45 55 65 75
170 // 06 16 26 36 46 56 66 76
171 // 07 17 27 37 47 57 67 77
172 }
173 } // for
174 {
175 // from aom_dct_sse2.c
176 // Post-condition (division by two)
177 // division of two 16 bits signed numbers using shifts
178 // n / 2 = (n - (n >> 15)) >> 1
179 const int16x8_t sign_in0 = vshrq_n_s16(input_0, 15);
180 const int16x8_t sign_in1 = vshrq_n_s16(input_1, 15);
181 const int16x8_t sign_in2 = vshrq_n_s16(input_2, 15);
182 const int16x8_t sign_in3 = vshrq_n_s16(input_3, 15);
183 const int16x8_t sign_in4 = vshrq_n_s16(input_4, 15);
184 const int16x8_t sign_in5 = vshrq_n_s16(input_5, 15);
185 const int16x8_t sign_in6 = vshrq_n_s16(input_6, 15);
186 const int16x8_t sign_in7 = vshrq_n_s16(input_7, 15);
187 input_0 = vhsubq_s16(input_0, sign_in0);
188 input_1 = vhsubq_s16(input_1, sign_in1);
189 input_2 = vhsubq_s16(input_2, sign_in2);
190 input_3 = vhsubq_s16(input_3, sign_in3);
191 input_4 = vhsubq_s16(input_4, sign_in4);
192 input_5 = vhsubq_s16(input_5, sign_in5);
193 input_6 = vhsubq_s16(input_6, sign_in6);
194 input_7 = vhsubq_s16(input_7, sign_in7);
195 // store results
196 vst1q_s16(&final_output[0 * 8], input_0);
197 vst1q_s16(&final_output[1 * 8], input_1);
198 vst1q_s16(&final_output[2 * 8], input_2);
199 vst1q_s16(&final_output[3 * 8], input_3);
200 vst1q_s16(&final_output[4 * 8], input_4);
201 vst1q_s16(&final_output[5 * 8], input_5);
202 vst1q_s16(&final_output[6 * 8], input_6);
203 vst1q_s16(&final_output[7 * 8], input_7);
204 }
205 }
206
aom_fdct8x8_1_neon(const int16_t * input,int16_t * output,int stride)207 void aom_fdct8x8_1_neon(const int16_t *input, int16_t *output, int stride) {
208 int r;
209 int16x8_t sum = vld1q_s16(&input[0]);
210 for (r = 1; r < 8; ++r) {
211 const int16x8_t input_00 = vld1q_s16(&input[r * stride]);
212 sum = vaddq_s16(sum, input_00);
213 }
214 {
215 const int32x4_t a = vpaddlq_s16(sum);
216 const int64x2_t b = vpaddlq_s32(a);
217 const int32x2_t c = vadd_s32(vreinterpret_s32_s64(vget_low_s64(b)),
218 vreinterpret_s32_s64(vget_high_s64(b)));
219 output[0] = vget_lane_s16(vreinterpret_s16_s32(c), 0);
220 output[1] = 0;
221 }
222 }
223