1 /*
2 * Copyright 2012 The LibYuv Project Authors. All rights reserved.
3 *
4 * Use of this source code is governed by a BSD-style license
5 * that can be found in the LICENSE file in the root of the source
6 * tree. An additional intellectual property rights grant can be found
7 * in the file PATENTS. All contributing project authors may
8 * be found in the AUTHORS file in the root of the source tree.
9 */
10
11 #include <stdio.h>
12 #include <stdlib.h>
13 #include <string.h>
14
15 #define INCLUDE_LIBYUV_COMPARE_H_
16 #include "libyuv.h"
17 #include "./psnr.h"
18 #include "./ssim.h"
19
main(int argc,const char * argv[])20 int main(int argc, const char* argv[]) {
21 int cpu_flags = TestCpuFlag(-1);
22 int has_arm = TestCpuFlag(kCpuHasARM);
23 int has_mips = TestCpuFlag(kCpuHasMIPS);
24 int has_x86 = TestCpuFlag(kCpuHasX86);
25 (void)argc;
26 (void)argv;
27
28 #if defined(__i386__) || defined(__x86_64__) || \
29 defined(_M_IX86) || defined(_M_X64)
30 if (has_x86) {
31 int family, model, cpu_info[4];
32 // Vendor ID:
33 // AuthenticAMD AMD processor
34 // CentaurHauls Centaur processor
35 // CyrixInstead Cyrix processor
36 // GenuineIntel Intel processor
37 // GenuineTMx86 Transmeta processor
38 // Geode by NSC National Semiconductor processor
39 // NexGenDriven NexGen processor
40 // RiseRiseRise Rise Technology processor
41 // SiS SiS SiS SiS processor
42 // UMC UMC UMC UMC processor
43 CpuId(0, 0, &cpu_info[0]);
44 cpu_info[0] = cpu_info[1]; // Reorder output
45 cpu_info[1] = cpu_info[3];
46 cpu_info[3] = 0;
47 printf("Cpu Vendor: %s\n", (char*)(&cpu_info[0]));
48
49 // CPU Family and Model
50 // 3:0 - Stepping
51 // 7:4 - Model
52 // 11:8 - Family
53 // 13:12 - Processor Type
54 // 19:16 - Extended Model
55 // 27:20 - Extended Family
56 CpuId(1, 0, &cpu_info[0]);
57 family = ((cpu_info[0] >> 8) & 0x0f) | ((cpu_info[0] >> 16) & 0xff0);
58 model = ((cpu_info[0] >> 4) & 0x0f) | ((cpu_info[0] >> 12) & 0xf0);
59 printf("Cpu Family %d (0x%x), Model %d (0x%x)\n", family, family,
60 model, model);
61 }
62 #endif
63 printf("Cpu Flags %x\n", cpu_flags);
64 printf("Has ARM %x\n", has_arm);
65 printf("Has MIPS %x\n", has_mips);
66 printf("Has X86 %x\n", has_x86);
67 if (has_arm) {
68 int has_neon = TestCpuFlag(kCpuHasNEON);
69 printf("Has NEON %x\n", has_neon);
70 }
71 if (has_mips) {
72 int has_msa = TestCpuFlag(kCpuHasMSA);
73 printf("Has MSA %x\n", has_msa);
74 }
75 if (has_x86) {
76 int has_sse2 = TestCpuFlag(kCpuHasSSE2);
77 int has_ssse3 = TestCpuFlag(kCpuHasSSSE3);
78 int has_sse41 = TestCpuFlag(kCpuHasSSE41);
79 int has_sse42 = TestCpuFlag(kCpuHasSSE42);
80 int has_avx = TestCpuFlag(kCpuHasAVX);
81 int has_avx2 = TestCpuFlag(kCpuHasAVX2);
82 int has_erms = TestCpuFlag(kCpuHasERMS);
83 int has_fma3 = TestCpuFlag(kCpuHasFMA3);
84 int has_f16c = TestCpuFlag(kCpuHasF16C);
85 int has_gfni = TestCpuFlag(kCpuHasGFNI);
86 int has_avx512bw = TestCpuFlag(kCpuHasAVX512BW);
87 int has_avx512vl = TestCpuFlag(kCpuHasAVX512VL);
88 int has_avx512vbmi = TestCpuFlag(kCpuHasAVX512VBMI);
89 int has_avx512vbmi2 = TestCpuFlag(kCpuHasAVX512VBMI2);
90 int has_avx512vbitalg = TestCpuFlag(kCpuHasAVX512VBITALG);
91 int has_avx512vpopcntdq = TestCpuFlag(kCpuHasAVX512VPOPCNTDQ);
92 printf("Has SSE2 %x\n", has_sse2);
93 printf("Has SSSE3 %x\n", has_ssse3);
94 printf("Has SSE4.1 %x\n", has_sse41);
95 printf("Has SSE4.2 %x\n", has_sse42);
96 printf("Has AVX %x\n", has_avx);
97 printf("Has AVX2 %x\n", has_avx2);
98 printf("Has ERMS %x\n", has_erms);
99 printf("Has FMA3 %x\n", has_fma3);
100 printf("Has F16C %x\n", has_f16c);
101 printf("Has GFNI %x\n", has_gfni);
102 printf("Has AVX512BW %x\n", has_avx512bw);
103 printf("Has AVX512VL %x\n", has_avx512vl);
104 printf("Has AVX512VBMI %x\n", has_avx512vbmi);
105 printf("Has AVX512VBMI2 %x\n", has_avx512vbmi2);
106 printf("Has AVX512VBITALG %x\n", has_avx512vbitalg);
107 printf("Has AVX512VPOPCNTDQ %x\n", has_avx512vpopcntdq);
108 }
109 return 0;
110 }
111
112